A new instruction extension method based on instruction-level data flow analysis

Abstract

The application discloses a new instruction extension method based on instruction-level data flow analysis, comprising the following steps: firstly, constructing an instruction-level data flow graph based on static analysis; then, dividing the instruction-level data flow graph based on instruction constraint conditions to obtain a subgraph set; then, performing equivalence class division on the subgraph set based on the definition of subgraph equivalence relation, and screening high-frequency subgraphs conforming to characteristics based on instruction sequence characteristics and frequency; finally, describing the new instruction semantics corresponding to each high-frequency subgraph based on an abstract instruction sequence. Then, the new instruction can be implemented according to the abstract instruction sequence, and the performance optimization effect can be achieved by using the new instruction during code generation. The method makes the user only need to provide a small amount of information such as instruction constraint conditions and instruction sequence characteristics, so that the instruction segments that can be optimized in the program can be automatically explored, thereby effectively reducing the manual cost and improving the accuracy and efficiency of instruction mining.

Description

Technical Field

[0001] This invention relates to the field of software engineering, and more specifically to a new instruction extension method based on instruction-level dataflow analysis. Background Technology

[0002] Software performance has always been a core indicator for evaluating software quality. Some performance problems stem from insufficient optimization of critical time-consuming code in the system. Currently, the software engineering field has been working on finding critical performance parts from the source code based on performance-related code characteristics and optimizing the code performance. In recent years, with the continuous development of hardware architecture and instruction sets, it is possible to support custom instruction set extensions. Therefore, by leveraging domain requirements, we can find frequently occurring performance-critical program characteristics in the program and its execution trajectory and build new instructions for them. By extending the program's specific instruction set, we can further improve program performance.

[0003] Currently, the common method for instruction extension relies on manual analysis of performance-critical code segments in a program, based on top-down program modeling and performance metrics during dynamic execution, and then transforms these segments into new instructions. This approach is labor-intensive, and in practice, few optimization points can be found. With the continuous increase in program size, a new, automated method for instruction extension is needed. Summary of the Invention

[0004] This invention provides a novel instruction extension method based on instruction-level dataflow analysis, which can solve the problems of current general methods for instruction extension requiring a large amount of human resources and having low instruction mining efficiency.

[0005] To solve the above problems, the present invention is achieved through the following technical solution:

[0006] A novel instruction extension method based on instruction-level dataflow analysis is characterized by the following steps:

[0007] Step 1: Construct an instruction-level data flow graph based on static analysis. Perform static analysis on the input program and its variants to construct an instruction-level data flow graph at the basic block granularity.

[0008] Step 2: Based on the instruction constraints, the instruction-level data flow graph is divided into subgraph sets. By exhaustively searching all possible subgraph partitions of the instruction-level data flow graph, each subgraph is traversed during the search process to collect information such as the number of nodes and the number of incoming and outgoing edges in the subgraph. Through constraint solving, it is determined whether the subgraph satisfies the instruction constraints, and finally the set of subgraphs in the instruction-level data flow graph that satisfy the instruction constraints is obtained.

[0009] Step 3: Based on the definition of subgraph equivalence relations, the subgraph set is partitioned into equivalence classes, and subgraphs are filtered based on instruction sequence features and frequency. First, according to the definition of equivalence relations, the subgraph set is traversed to perform equivalence class partitioning. Then, the instruction sequence features are converted into template instruction-level data flow graphs. By traversing the subgraph equivalence classes, subgraph equivalence classes that are equivalent to the template instruction-level data flow graphs are filtered out and their frequency is counted. Finally, high-frequency subgraphs that appear more than a user-defined threshold are retained.

[0010] Step four: Describe the new instruction semantics corresponding to each high-frequency subgraph based on the abstract instruction sequence. By traversing the subgraph, the subgraph is converted into an instruction sequence, and virtual registers are used to represent the operands and output values ​​of the instructions.

[0011] The aforementioned new instruction extension method based on instruction-level dataflow analysis is characterized in that step one, constructing the instruction-level dataflow graph based on static analysis, includes:

[0012] The input program and its variants mainly include assembly representation, intermediate code representation (IR), and program dynamic execution trace;

[0013] The instruction-level data flow graph is a directed acyclic graph (DAG), where nodes represent instructions and values, including four types: a) instruction nodes represent actual instructions; b) instruction output value nodes represent instruction output values; c) constant value nodes represent immediate values; and d) sign value nodes represent external input values. Edges represent the data dependencies between instructions and values, and edge labels represent the semantics of data in instruction operations, mainly including three categories: general values, addresses, and shift-extended values.

[0014] • By using static analysis techniques such as alias analysis and value flow analysis, an instruction-level data flow graph corresponding to the intermediate representation (IR) of the program is constructed at the basic block granularity;

[0015] • By using abstract interpretation techniques, an instruction-level data flow graph corresponding to the program's dynamic execution trajectory (Trace) is constructed at the basic block granularity;

[0016] • Reduce the nodes representing intermediate values ​​in the instruction-level dataflow graph, and unify the nodes representing values ​​in the instruction-level dataflow graph into symbolic value nodes;

[0017] • Divide the instruction-level dataflow graph according to its connected components to obtain the corresponding instruction-level dataflow graph set.

[0018] The aforementioned novel instruction extension method based on instruction-level dataflow analysis is characterized in that step two, which involves partitioning the instruction-level dataflow graph based on instruction constraints to obtain a set of subgraphs, includes:

[0019] The instruction constraints mainly include the number of instructions, the range of inputs, the range of outputs, and convexity, which are set by the user.

[0020] • Perform topological sorting on the instruction nodes of the instruction-level data flow graph;

[0021] • A recursive algorithm is used to search in the reverse topological order of the instruction nodes in the instruction-level data flow graph, exhaustively enumerating all possible subgraph partitions;

[0022] • Traverse each subgraph obtained during the search process to obtain the number of instruction nodes, the number of edges entering and leaving the subgraph, the number of nodes connected by the edges entering and leaving the subgraph, and whether there are cases where the outgoing edges of the subgraph connect to external nodes and then the incoming edges connect to internal nodes. Solve the constraints to determine whether the subgraph satisfies the instruction constraints, and remove subgraphs that do not meet the constraints. During the algorithm's operation, if a subgraph partition cannot satisfy the constraints, and the subgraph partitions obtained by subsequent searches based on this subgraph partition cannot satisfy the constraints either, then pruning is performed.

[0023] • Collect all subgraphs that satisfy the constraints during the search process to obtain the set of subgraphs corresponding to the instruction-level data flow graph.

[0024] The aforementioned new instruction extension method based on instruction-level dataflow analysis is characterized in that step three, which involves dividing the subgraph set into equivalence classes based on the definition of subgraph equivalence relations and filtering subgraphs based on instruction sequence characteristics and frequency, includes:

[0025] • The instruction sequence characteristics are user-defined and are instruction sequences containing a specific pattern;

[0026] The graph equivalence relation is defined as follows: two subgraphs are equivalent if and only if both nodes are instruction nodes and the instructions are the same, or both nodes are value nodes; two subgraphs are equivalent if and only if the output-related nodes of the subgraphs are equivalent, and for any two equivalent instruction nodes, if their instructions satisfy the commutative law, then there exists an equivalent one-to-one correspondence between their input nodes; if their instructions do not satisfy the commutative law, then their input nodes are equivalent according to the input order.

[0027] • Based on the definition of graph equivalence relations, perform equivalence class partitioning on the set of subgraphs;

[0028] • Using the instruction-level data flow graph construction method in step one, user-defined instruction sequence features are converted into template instruction-level data flow graphs, and the equivalence classes of the subgraphs are traversed to remove equivalence classes that do not match the instruction sequence features;

[0029] • Perform frequency statistics on equivalence classes and retain those equivalence classes whose frequency exceeds a custom threshold. The subgraphs contained in these classes are the high-frequency subgraphs.

[0030] The aforementioned new instruction extension method based on instruction-level dataflow analysis is characterized in that step four, describing the new instruction semantics corresponding to each high-frequency subgraph based on abstract instruction sequences, includes:

[0031] • Perform topological sorting on the instruction nodes in the high-frequency subgraph and construct the instruction sequence according to the topological order;

[0032] Based on the data dependencies between instruction nodes in the high-frequency subgraph, generate virtual input / output registers corresponding to the instructions.

[0033] By adopting the above technical solutions, the following beneficial effects can be achieved:

[0034] This invention proposes a novel instruction expansion method based on instruction-level dataflow analysis. By using instruction-level dataflow graphs, it performs bottom-up program modeling, automatically modeling the entire program. Then, through configurable instruction constraints and instruction sequence features, users only need to provide a small amount of information such as instruction constraints and instruction sequence features to automatically discover instruction sequences in the program suitable for forming new instructions. This effectively reduces manual costs and improves the accuracy and efficiency of instruction mining. Attached Figure Description

[0035] Figure 1 This is a framework diagram of a new instruction extension method based on instruction-level dataflow analysis according to an embodiment of the present invention.

[0036] Figure 2 This is an example diagram of the dynamic running trajectory (Trace) of the input program in an embodiment of the present invention.

[0037] Figure 3 This is a representation diagram of the instruction-level data flow diagram of an input example in an embodiment of the present invention. Detailed Implementation

[0038] To enable those skilled in the art to better understand the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0039] like Figure 1 As shown, this embodiment provides a new instruction extension method based on instruction-level dataflow analysis, which includes the following steps:

[0040] Step 1: Construct an instruction-level data flow graph based on static analysis. Perform static analysis on the input program and its variants to construct an instruction-level data flow graph at the basic block granularity. Its beneficial effect is that the instruction-level data flow graph at the basic block granularity of the program, constructed by using static analysis techniques such as alias analysis, value flow analysis, and abstract interpretation, can express the dependencies between program instructions and data with high precision.

[0041] Step two involves partitioning the instruction-level dataflow graph based on instruction constraints to obtain a set of subgraphs. This is achieved by exhaustively searching all possible subgraph partitions of the instruction-level dataflow graph, traversing each subgraph during the search process, and collecting information such as the number of nodes and incoming / outgoing edges. Constraint solving is then used to determine whether the subgraphs satisfy the instruction constraints, ultimately yielding a set of subgraphs in the instruction-level dataflow graph that meet the instruction constraints. The beneficial effect is that the proposed use of inverse topological order-based dataflow subgraph search makes the search and pruning after constraint solving of the subgraphs more efficient, effectively reducing the search space and improving algorithm efficiency.

[0042] Step 3 involves partitioning the subgraph set into equivalence classes based on the definition of subgraph equivalence relations and filtering subgraphs based on instruction sequence features and frequency. First, according to the definition of equivalence relations, the subgraph set is traversed to perform equivalence class partitioning. Then, the instruction sequence features are converted into a template instruction-level data flow graph. The subgraph equivalence classes are traversed again, and subgraph equivalence classes equivalent to the template instruction-level data flow graph are selected and their frequency is statistically analyzed. Finally, high-frequency subgraphs whose frequency exceeds a user-defined threshold are retained. The beneficial effects are: defining a subgraph equivalence relation that considers algebraic patterns, improving the accuracy of equivalence subgraph determination; and proposing a conversion from instruction sequence features to template data flow graphs, transforming the instruction sequence feature matching problem into a graph matching problem, thus improving the flexibility of user configuration.

[0043] Step four involves describing the new instruction semantics corresponding to each high-frequency subgraph based on an abstract instruction sequence. By traversing the subgraph, the subgraph is converted into an instruction sequence, and virtual registers are used to represent the operands and output values ​​of the instructions. The beneficial effect is that an abstract instruction sequence is defined, which uses an infinite number of virtual registers to represent the instruction operands and output values, avoiding the additional memory access instructions introduced by the limitation of the number of registers. It specifically and accurately expresses the actual operation semantics of the instruction sequence corresponding to the high-frequency subgraph, making it convenient to implement new instructions based on the semantics in the future.

[0044] The specific steps of constructing the instruction-level data flow graph based on static analysis in step one include:

[0045] The input program and its variants mainly include assembly representation, intermediate code representation (IR), and program dynamic execution trace, etc.; the program dynamic execution trace is as follows: Figure 2 As shown, this records the instructions executed by the central processing unit at each step during the actual operation of the program, as well as the internal state during instruction execution.

[0046] The instruction-level data flow graph is a directed acyclic graph, such as... Figure 3 As shown, Figure 3This is a representation of the instruction-level data flow graph of the input example in this embodiment of the invention. Nodes represent instructions and values, including four types: a) Instruction nodes represent actual instructions; b) Instruction output value nodes represent instruction output values; c) Constant value nodes represent immediate values; d) Signed value nodes represent external input values. Edges represent the data dependencies between instructions and values, and edge labels represent the semantics of data in instruction operations, as shown in Table 1.

[0047] Table 1. Edge Labels and Their Semantics

[0048]

[0049] • By using static analysis techniques such as alias analysis and value flow analysis, an instruction-level data flow graph corresponding to the intermediate representation (IR) of the program is constructed at the basic block granularity;

[0050] • By using abstract interpretation techniques, an instruction-level data flow graph corresponding to the program's dynamic execution trajectory (Trace) is constructed at the basic block granularity;

[0051] • Reduce the nodes representing intermediate values ​​in the instruction-level dataflow graph, and unify the nodes representing values ​​in the instruction-level dataflow graph into symbolic value nodes;

[0052] • Divide the instruction-level dataflow graph according to its connected components to obtain the corresponding instruction-level dataflow graph set.

[0053] Step two, which involves partitioning the instruction-level data flow graph based on instruction constraints to obtain a set of subgraphs, specifically includes the following steps:

[0054] The instruction constraints mainly include the number of instructions, the range of inputs, the range of outputs, convexity, etc., which are set by the user.

[0055] • A recursive algorithm is used to search in the reverse topological order of the instruction nodes in the instruction-level data flow graph, exhaustively enumerating all possible subgraph partitions;

[0056] • Traverse each subgraph obtained during the search process to obtain the number of instruction nodes, the number of edges entering and leaving the subgraph, the number of nodes connected by the edges entering and leaving the subgraph, and whether there are cases where the outgoing edges of the subgraph connect to external nodes and then the incoming edges connect to internal nodes. Solve the constraints to determine whether the subgraph satisfies the instruction constraints, and remove subgraphs that do not meet the constraints. During the algorithm's operation, if a subgraph partition cannot satisfy the constraints, and the subgraph partitions obtained by subsequent searches based on this subgraph partition cannot satisfy the constraints either, then pruning is performed. For example, since subgraphs are required to be connected, no subgraph can be formed into a new subgraph by adding instruction nodes that are not connected to the current subgraph. Since instruction nodes are added in reverse topological order, adding new instruction nodes will not reduce the number of outgoing parameters of the subgraph, nor can it restore the broken convexity.

[0057] • Collect all subgraphs that satisfy the constraints during the search process to obtain the set of subgraphs corresponding to the instruction-level data flow graph.

[0058] Step three, which involves dividing the subgraph set into equivalence classes based on the definition of subgraph equivalence relations and filtering subgraphs based on instruction sequence features and frequency, specifically includes the following steps:

[0059] • The instruction sequence characteristics are user-defined and are instruction sequences containing a specific pattern (such as a read-modify-write pattern);

[0060] The graph equivalence relation is defined as follows: two subgraphs are equivalent if and only if both nodes are instruction nodes and the instructions are the same, or both nodes are value nodes; two subgraphs are equivalent if and only if the output-related nodes of the subgraphs are equivalent, and for any two equivalent instruction nodes, if their instructions satisfy the commutative law, then there exists an equivalent one-to-one correspondence between their input nodes; if their instructions do not satisfy the commutative law, then their input nodes are equivalent according to the input order.

[0061] • Based on the definition of graph equivalence relations, perform equivalence class partitioning on the set of subgraphs;

[0062] • Using the instruction-level data flow graph construction method in step one, user-defined instruction sequence features are converted into template instruction-level data flow graphs, and the equivalence classes of the subgraphs are traversed to remove equivalence classes that do not match the instruction sequence features;

[0063] • Perform frequency statistics on equivalence classes and retain those equivalence classes whose frequency exceeds a custom threshold. The subgraphs contained in these classes are the high-frequency subgraphs.

[0064] The fourth step, describing the new instruction semantics corresponding to each high-frequency subgraph based on the abstract instruction sequence, includes:

[0065] • Perform topological sorting on the instruction nodes in the high-frequency subgraph and construct the instruction sequence according to the topological order;

[0066] Based on the data dependencies between instruction nodes in the high-frequency subgraph, generate virtual input / output registers corresponding to the instructions.

[0067] The above descriptions are embodiments of the present invention, but the specific embodiments described herein are merely illustrative and not intended to limit the invention. Any omissions, modifications, or equivalent substitutions made within the scope of the claims of this invention without departing from the principles and spirit of the invention should be included within the protection scope of this disclosure.

Claims

1. A novel instruction extension method based on instruction-level dataflow analysis, characterized in that, Includes the following steps: Step 1: Construct an instruction-level data flow graph based on static analysis. Perform static analysis on the input program and its variants to construct an instruction-level data flow graph at the basic block granularity. Step two involves partitioning the instruction-level dataflow graph based on instruction constraints to obtain a set of subgraphs. This is achieved by exhaustively searching all possible subgraph partitions of the instruction-level dataflow graph, traversing each subgraph during the search, and collecting information on the number of nodes and inbound / outbound edges. Constraint solving is then used to determine whether the subgraphs satisfy the instruction constraints, ultimately yielding a set of subgraphs in the instruction-level dataflow graph that meet the instruction constraints. Specifically, step two includes: The instruction constraints include the number of instructions, the range of the number of inputs, the range of the number of outputs, and convexity, which are set by the user. Perform topological sorting on the instruction nodes of the instruction-level data flow graph; A recursive algorithm is used to search in the reverse topological order of the instruction nodes in the instruction-level data flow graph, exhaustively enumerating all possible subgraph partitions; Each subgraph obtained during the search process is traversed to obtain the number of instruction nodes, the number of edges entering and leaving the subgraph, the number of nodes connected by the edges entering and leaving the subgraph, and whether there are cases where an outgoing edge of the subgraph connects to an external node and then an incoming edge connects to an internal node. By solving the constraints, it is determined whether the subgraph satisfies the instruction constraints, and subgraphs that do not satisfy the constraints are removed. During the algorithm's operation, if a subgraph partition cannot satisfy the constraints, and subsequent subgraph partitions obtained based on this partition cannot satisfy the constraints either, then pruning is performed. Collect all subgraphs that satisfy the constraints during the search process to obtain the set of subgraphs corresponding to the instruction-level data flow graph; Step 3: Based on the definition of subgraph equivalence relations, the subgraph set is partitioned into equivalence classes, and subgraphs are filtered based on instruction sequence features and frequency. First, according to the definition of equivalence relations, the subgraph set is traversed to perform equivalence class partitioning. Then, the instruction sequence features are converted into template instruction-level data flow graphs. By traversing the subgraph equivalence classes, subgraph equivalence classes that are equivalent to the template instruction-level data flow graphs are filtered out and their frequency is counted. Finally, high-frequency subgraphs that appear more than a user-defined threshold are retained. Step four: Describe the new instruction semantics corresponding to each high-frequency subgraph based on the abstract instruction sequence. By traversing the subgraph, the subgraph is converted into an instruction sequence, and virtual registers are used to represent the operands and output values ​​of the instructions.

2. The novel instruction extension method based on instruction-level dataflow analysis according to claim 1, characterized in that, Step one, constructing the instruction-level dataflow graph based on static analysis, includes: The input program and its variants include assembly representation, intermediate code representation (IR), and program dynamic execution trajectory (Trace). The instruction-level data flow graph is a directed acyclic graph (DAG), where nodes represent instructions and values, including four types: a) instruction nodes represent actual instructions; b) instruction output value nodes represent instruction output values; c) constant value nodes represent immediate values; and d) sign value nodes represent external input values. Edges represent the data dependencies between instructions and values, and edge labels represent the semantics of data in instruction operations, including three categories: general values, addresses, and shift-extended values. By using alias analysis, value flow analysis, and static analysis techniques, an instruction-level data flow graph corresponding to the intermediate representation (IR) of the program is constructed at the basic block granularity. By using abstract interpretation techniques, an instruction-level data flow graph corresponding to the program's dynamic execution trajectory Trace is constructed at the basic block granularity. The nodes representing intermediate values ​​in the instruction-level dataflow graph are simplified, and the nodes representing values ​​in the instruction-level dataflow graph are uniformly abstracted into symbolic value nodes. The instruction-level data flow graph is divided into connected components to obtain the corresponding instruction-level data flow graph set.

3. The novel instruction extension method based on instruction-level dataflow analysis according to claim 1, characterized in that, Step three, which involves dividing the subgraph set into equivalence classes based on the definition of subgraph equivalence relations and filtering subgraphs based on instruction sequence features and frequency, includes: The instruction sequence features are user-defined and are instruction sequences containing a specific pattern; The graph equivalence relation is defined as follows: two subgraphs are equivalent if and only if both nodes are instruction nodes and the instructions are the same, or both nodes are value nodes; two subgraphs are equivalent if and only if the output-related nodes of the subgraphs are equivalent, and for any two equivalent instruction nodes, if their instructions satisfy the commutative law, then there exists an equivalent one-to-one correspondence between their input nodes; if their instructions do not satisfy the commutative law, then their input nodes are equivalent according to the input order. Based on the definition of graph equivalence relations, the set of subgraphs is divided into equivalence classes. Using the instruction-level data flow graph construction method in step one, user-defined instruction sequence features are converted into template instruction-level data flow graphs. The equivalence classes of the subgraphs are traversed, and equivalence classes that do not match the instruction sequence features are removed. Frequency statistics are performed on equivalence classes, and equivalence classes that appear more frequently than a custom threshold are retained. The subgraphs contained in these classes are the high-frequency subgraphs.

4. The novel instruction extension method based on instruction-level dataflow analysis according to claim 1, characterized in that, The fourth step, describing the new instruction semantics corresponding to each high-frequency subgraph based on the abstract instruction sequence, includes: Perform topological sorting on the instruction nodes in the high-frequency subgraph and construct the instruction sequence according to the topological order; Based on the data dependencies between instruction nodes in the high-frequency subgraph, virtual input / output registers corresponding to the instructions are generated.

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