A charge pump circuit

Abstract

The present application discloses a charge pump circuit, comprising a first switch, whose control terminal receives a driving voltage when a clock signal is at a first level, and whose substrate terminal receives one of a power supply voltage and an output voltage; a second switch, whose control terminal receives a driving voltage when a clock signal is at a second level, and whose substrate terminal receives a power supply voltage; and a flying capacitor, whose first terminal receives the power supply voltage via the first switch, and whose second terminal receives the power supply voltage via the second switch. When the first switch is on, the second switch is off, and the power supply voltage charges the flying capacitor. When the second switch is on, the first switch is off, and the flying capacitor discharges to generate an output voltage. When the power supply voltage is less than a preset output voltage, the driving voltage provided to the first switch is less than the driving voltage provided to the second switch. The present application adaptively adjusts the overcurrent capacity of the first and second switches according to the magnitude of the power supply voltage to ensure that the voltage difference across the flying capacitor varies minimally with the power supply voltage, thereby improving circuit stability.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and more particularly, to a charge pump circuit. Background Art

[0002] A charge pump, also known as a switched-load capacitor voltage converter, is a type of converter that uses so-called "fast" or "pumping" load capacitors to store energy. It can step up or down the input voltage and can also be used to generate negative voltages. It is widely used in power supplies, memory devices, and radio frequency chips.

[0003] The charge pump circuit in the prior art has the following problem: due to the different working states of the charging switch element and the discharging switch element in the charge pump circuit, the voltage difference of the flying capacitor in the charge pump circuit is greatly affected by the change of the power supply voltage. Summary of the Invention

[0004] In view of the above problems, an object of the present invention is to provide a charge pump circuit to solve the problem that the voltage difference of the flying capacitor in the charge pump circuit is greatly affected by the change of the power supply voltage.

[0005] According to an embodiment of the present invention, a charge pump circuit is provided, comprising:

[0006] a first switch, wherein the control terminal receives a driving voltage when the clock signal is in a first level state, and the substrate terminal receives one of a power supply voltage and an output voltage;

[0007] a second switch, wherein a control terminal receives the driving voltage when the clock signal is in a second level state, and a substrate terminal receives the power supply voltage;

[0008] a flying capacitor, a first end receiving the power supply voltage via the first switch, and a second end receiving the power supply voltage via the second switch,

[0009] When the first switch receives a driving voltage and is turned on, the second switch is turned off, and the power supply voltage charges the flying capacitor; when the second switch receives a driving voltage and is turned on, the first switch is turned off, and the flying capacitor discharges to generate the output voltage.

[0010] When the power supply voltage is lower than a preset output voltage, the driving voltage provided to the first switch is lower than the driving voltage provided to the second switch during at least one cycle of the clock signal.

[0011] Optionally, when the power supply voltage is lower than a preset output voltage, the substrate end of the first switch receives the output voltage; when the power supply voltage is higher than the preset output voltage, the substrate end of the first switch receives the power supply voltage.

[0012] Optionally, when the power supply voltage is greater than a preset output voltage, the driving voltage provided to the first switch is equal to the driving voltage provided to the second switch in at least one cycle of the clock signal.

[0013] Optionally, it also includes:

[0014] an adjustment circuit that provides an offset voltage when the power supply voltage is less than a preset output voltage and the first switch is turned on, generates a feedback amplified signal based on the output voltage and a reference voltage, and outputs the feedback amplified signal or the feedback amplified signal superimposed with the offset voltage as the driving voltage.

[0015] Optionally, when the power supply voltage is less than a preset output voltage, the driving voltage provided to the first switch is a feedback amplified signal superimposed with the offset voltage, and the driving voltage provided to the second switch is a feedback amplified signal; when the power supply voltage is greater than the preset output voltage, the driving voltages are both the feedback amplified signal.

[0016] Optionally, the adjustment circuit includes:

[0017] an offset module, configured to provide an offset voltage when the power supply voltage is less than a preset output voltage and the first switch is turned on; and

[0018] a feedback module that generates a feedback amplified signal according to the output voltage and a reference voltage, and outputs the feedback amplified signal or the feedback amplified signal superimposed with the offset voltage as the driving voltage;

[0019] The feedback module includes:

[0020] a voltage dividing unit, collecting the output voltage to obtain a divided voltage;

[0021] an error amplifier connected to the voltage divider unit, and generating the feedback amplified signal according to the divided voltage and the reference voltage; and

[0022] A buffer has a first input terminal receiving the feedback amplified signal, a second input terminal connected to an output terminal of the buffer, and the output terminal further receiving the offset voltage.

[0023] Optionally, the imbalance module includes:

[0024] a current source, a first terminal of which receives the power supply voltage; and

[0025] A third switch and a fourth switch are connected in series between the second end of the current source and the output end of the buffer, wherein the third switch is turned on when the substrate end of the first switch receives the output voltage, and the fourth switch is turned on when the clock signal is in a first level state.

[0026] Optionally, the preset output voltage is positively correlated with the reference voltage.

[0027] Optionally, it also includes:

[0028] a fifth switch, a first end of which is connected to the second end of the flying capacitor and a second end of which is grounded;

[0029] a sixth switch, a first end of which is connected to the first end of the flying capacitor, and a second end of which provides the output voltage; and

[0030] The output capacitor is connected between the output voltage and ground.

[0031] The fifth switch is turned on when the first switch is turned on, and the sixth switch is turned on when the second switch is turned on.

[0032] The charge pump circuit of an embodiment of the present application includes a flying capacitor, an output capacitor, a first switch, and a second switch, wherein the substrate terminal of the first switch receives one of a power supply voltage and an output voltage, and the substrate terminal of the second switch receives the power supply voltage. When the substrate terminal of the first switch receives the output voltage, the overcurrent capacity of the first switch and the second switch will be different. When the substrate terminal of the first switch receives the output voltage, the present application adjusts the overcurrent capacity of the first switch and the second switch adaptively according to the magnitude of the power supply voltage by making the driving voltage provided to the first switch lower than the driving voltage provided to the second switch. The first switch and the second switch are constantly operated in the saturation region to ensure that the voltage difference of the flying capacitor changes less with the power supply voltage, thereby making the state switching of the entire charge pump circuit more gentle during the change of the power supply voltage, thereby improving the circuit stability.

[0033] Furthermore, by providing an adjustment circuit within the charge pump circuit, when the power supply voltage is less than the preset output voltage and the drive voltage is supplied to the first switch, an offset voltage is generated and superimposed on the feedback amplified signal, thereby increasing the gate-source voltage of the first switch and improving its current capacity. This allows the first and second switches to operate in a constant saturation region, ensuring that the voltage difference across the flying capacitor varies minimally with power supply voltage. This, in turn, allows the entire charge pump circuit to switch states more smoothly during power supply voltage changes, thereby improving circuit stability. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and other objects, features and advantages of the present invention will become more apparent through the following description of the embodiments of the present invention with reference to the accompanying drawings, in which:

[0035] Figure 1a A schematic structural diagram of a charge pump circuit provided according to an embodiment of the present application is shown;

[0036] Figure 1b Show Figure 1a A schematic diagram of the waveform of the driving voltage of the charge pump circuit when the power supply voltage is lower than the preset output voltage;

[0037] Figure 2 A schematic structural diagram of another charge pump circuit provided according to an embodiment of the present invention is shown. DETAILED DESCRIPTION

[0038] Various embodiments of the present invention will be described in more detail below with reference to the accompanying drawings. In each of the accompanying drawings, identical elements are represented by identical or similar reference numerals. For the sake of clarity, the various parts in the accompanying drawings are not drawn to scale.

[0039] It should be understood that in the following description, a "circuit" may include a single or multiple combined hardware circuits, programmable circuits, state machine circuits, and / or elements capable of storing instructions executed by programmable circuits. When an element or circuit is said to be "connected to" another element or an element / circuit is said to be "connected" between two nodes, it may be directly coupled or connected to the other element or there may be an intermediate element, and the connection between the elements may be physical, logical, or a combination thereof. Conversely, when an element is said to be "directly coupled to" or "directly connected to" another element, it means that there are no intermediate elements between the two.

[0040] The present invention will be further described below with reference to the accompanying drawings and examples.

[0041] Figure 1a A schematic structural diagram of a charge pump circuit provided according to an embodiment of the present application is shown. Figure 1b Show Figure 1a Schematic diagram of the driving voltage waveform of the charge pump circuit when the power supply voltage is lower than the preset output voltage.

[0042] like Figure 1a As shown, the charge pump circuit 100 includes a flying capacitor Cfly, a switch SW1 , and a switch SW2 .

[0043] When the clock signal CLK is at a first level, the control terminal of the switch SW1 receives the driving voltage Vg. The first terminal of the switch SW1 receives the power supply voltage VDD. The second terminal of the switch SW1 is connected to the first terminal of the flying capacitor Cfly. The substrate terminal of the switch SW1 receives one of the power supply voltage VDD and the output voltage VOUT. When the switch SW1 is turned on, the flying capacitor Cfly is charged by the power supply voltage VDD.

[0044] The control terminal of switch SW2 receives the driving voltage Vg when the clock signal CLK is at a second level. The first terminal of switch SW2 receives the power supply voltage VDD. The second terminal of switch SW2 is connected to the second terminal of fly capacitor Cfly. The substrate terminal of switch SW2 is connected to the first terminal of switch SW2 and receives the power supply voltage VDD. When switch SW2 is turned on, fly capacitor Cfly is discharged and output voltage VOUT is provided. The control terminals of switches SW1 and SW2 alternately receive the driving voltage Vg and are thus turned on alternately, depending on the level of clock signal CLK.

[0045] In other embodiments, the charge pump circuit 100 further includes a switch SW5 , a switch SW6 , and an output capacitor Cout.

[0046] The first end of switch SW5 is connected to the second end of flying capacitor Cfly, and the second end of switch SW5 is grounded. The first end of switch SW6 is connected to the first end of flying capacitor Cfly, and the second end of switch SW6 provides output voltage VOUT and is connected to one end of output capacitor Cout. The other end of output capacitor Cout is grounded. Furthermore, when the clock signal CLK is at a first level, switch SW1, serving as the charging switch element, receives the driving voltage Vg and turns on, and switch SW5 turns on. At this time, switches SW2 and SW6, serving as the discharging switch elements, are disconnected. In other words, the charge pump circuit 100 is in the charging phase, with the power supply voltage VDD charging flying capacitor Cfly. Next, when the clock signal CLK is at a second level, switches SW1 and SW5, serving as the charging switch elements, are disconnected. At this time, switch SW2, serving as the discharging switch element, receives the driving voltage Vg and turns on, and switch SW6 turns on. In other words, the charge pump circuit 100 is in the discharging phase, with the power supply voltage VDD superimposed on the charging voltage of flying capacitor Cfly. The charging and discharging stages are repeated alternately to make the voltage Vout of the output capacitor Cout higher than the power supply voltage VDD. The control terminals of the switches SW5 and SW6 receive a logic high level or a logic low level to turn on or off.

[0047] For example, in this embodiment, switches SW1, SW2, and SW6 are selected from P-type MOSFETs (N-Channel-Metal-Oxide-Semiconductors), and switch SW5 is selected from N-type MOSFETs (N-Channel-Metal-Oxide-Semiconductors). Furthermore, the first terminals of switches SW1 and SW2 are the sources of the PMOS transistors, the second terminals of switches SW1 and SW2 are the drains of the PMOS transistors, and the control terminals of switches SW1 and SW2 are the gates of the PMOS transistors.

[0048] The second terminal of switch SW1 is connected to the output voltage Vout via a switch. To prevent conduction of the PN junction between the substrate terminal and the second terminal of switch SW1, charge pump circuit 100 further includes a selection circuit 110, adapted to select one of the output voltage VOUT and the power supply voltage VDD based on the power supply voltage VDD and a preset output voltage, and to provide it to the substrate terminal of switch SW1. Furthermore, selection circuit 100 includes switches SW7 and SW8. A first terminal of switch SW7 receives the power supply voltage VDD, and a second terminal of switch SW7 is connected to the substrate terminal of switch SW1. A first terminal of switch SW8 receives the output voltage VOUT, and a second terminal of switch SW8 is connected to the substrate terminal of switch SW1. Control terminals (not shown) of switches SW7 and SW8 both receive, for example, a comparison result between the power supply voltage VDD and the preset output voltage. Furthermore, when the power supply voltage VDD is lower than the preset output voltage, switch SW7 is turned off, switch SW8 is turned on, and the substrate terminal of switch SW1 receives the output voltage VOUT. When the power supply voltage VDD is greater than the preset output voltage, switch SW7 is turned on and switch SW8 is turned off, and the substrate terminal of switch SW1 receives the power supply voltage VDD. In this embodiment, switches SW7 and SW8 may have different transistor types. It should be noted that switches SW7 and SW8 may also have the same transistor type. Correspondingly, the control terminal of one of switches SW7 and SW8 receives the comparison result between the power supply voltage VDD and the preset output voltage, while the control terminal of the other receives the negation of the comparison result.

[0049] Furthermore, when the power supply voltage VDD is greater than the preset output voltage, the voltage difference between the substrate terminal and the first terminal of switch SW1 is zero, and the voltage difference between the substrate terminal and the first terminal of switch SW2 is zero. Switches SW1 and SW2 remain in the saturation region to charge and discharge the fly capacitor Cfly. Ideally, the charge and discharge capabilities of switches SW1 and SW2 are consistent. In this case, within at least one cycle of the clock signal CLK, the voltage value of the drive voltage Vg when the clock signal CLK is at the first level is equal to the voltage value when the clock signal CLK is at the second level.

[0050] Furthermore, when the power supply voltage VDD is lower than the preset output voltage, the voltage difference between the substrate terminal and the first terminal of the switch SW1 is greater than 0, and the voltage difference between the substrate terminal and the first terminal of the switch SW2 is 0. At this time, the switch SW1 experiences a bias effect, which increases the threshold voltage VTH of the switch SW1 and weakens the overcurrent capability. This makes the charging capability of the charge pump circuit 100 for the flying capacitor Cfly weaker than its discharging capability. Figure 1bWhen the power supply voltage VDD is lower than the preset output voltage, and for at least one cycle of the clock signal CLK, the driving voltage Vg is lower (Vg1) when the clock signal CLK is at the first level than (Vg2) when the clock signal CLK is at the second level. Because the voltage at the first terminals of both switches SW1 and SW2 is the power supply voltage VDD, the gate-source voltage amplitude of switch SW1 when it is on (low level) is greater than the gate-source voltage amplitude of switch SW2 when it is on (low level). That is, when the power supply voltage VDD is lower than the preset output voltage, this embodiment reduces the driving voltage Vg supplied to switch SW1 (the voltage Vg1 when the clock signal CLK is at the first level) so that the gate-source voltage amplitude of switch SW1 is greater than the gate-source voltage amplitude of switch SW2. This improves the charging capability of the charge pump circuit 100 and maintains charge balance on the fly capacitor Cfly. This prevents voltage steps across the fly capacitor Cfly when the power supply voltage VDD varies, thereby improving the stability of the charge pump circuit 100.

[0051] Figure 2 A schematic structural diagram of another charge pump circuit provided according to an embodiment of the present invention is shown.

[0052] like Figure 2 As shown, the charge pump circuit 200 further includes an adjustment circuit 220 based on the charge pump circuit 100 .

[0053] The adjustment circuit 220 is adapted to provide an offset voltage when the substrate terminal of the switch SW1 receives the output voltage VOUT and the clock signal CLK is at a first level, generate an amplified feedback signal based on the output voltage VOUT and a reference voltage VBG, and output the amplified feedback signal or the amplified feedback signal superimposed with the offset voltage as the drive voltage Vg. Furthermore, when the substrate terminal of the switch SW1 receives the output voltage VOUT and the clock signal CLK is at a first level, the drive voltage Vg is the amplified feedback signal superimposed with the offset voltage. When the substrate terminal of the switch SW1 receives the output voltage VOUT and the clock signal CLK is at a second level, and when the substrate terminal of the switch SW1 receives the power supply voltage VDD, the drive voltage Vg is the amplified feedback signal.

[0054] Furthermore, the adjustment circuit 220 includes a feedback module 221 and an offset module 222 .

[0055] The feedback module 221 is configured to generate an amplified feedback signal based on the output voltage VOUT and the reference voltage VBG, and output the amplified feedback signal or the amplified feedback signal superimposed with an offset voltage as the driving voltage Vg. The feedback module includes a voltage divider unit, an error amplifier U1, and a buffer U2. The voltage divider unit is configured to collect the output voltage VOUT to obtain a divided voltage. The voltage divider unit includes resistors R1 and R2 connected in parallel between the two ends of the output capacitor Cout. The first end of resistor R1 receives the output voltage VOUT, the second end of resistor R1 is connected to the first end of resistor R2 and outputs the divided voltage, and the second end of resistor R2 is grounded. The error amplifier (EA) U1 generates the amplified feedback signal based on the divided voltage and the reference voltage VBG. Furthermore, the first input of the error amplifier U1 receives the reference voltage VBG, the second input of the error amplifier U1 receives the divided voltage, and the output of the error amplifier U1 outputs the amplified feedback signal. The first input of the buffer U2 is connected to the output of the error amplifier U1 to receive the amplified feedback signal, and the second input of the buffer U2 is connected to the output of the buffer U2. The output of the buffer U2 is also configured to receive the offset voltage. The preset output voltage is positively correlated with the reference voltage VBG.

[0056] The offset module 222 is adapted to provide an offset voltage when the substrate terminal of switch SW1 receives the output voltage VOUT and the clock signal CLK is at a first level. The offset module 222 includes a current source I1, a switch SW3, and a switch SW4. The first terminal of current source I1 receives the power supply voltage VDD. Switches SW3 and SW4 are connected in series between the second terminal of current source I1 and the output terminal of buffer U2. Switch SW3 is turned on when the substrate terminal voltage VMAX of switch SW1 reaches the output voltage VOUT and is turned off otherwise. Switch SW4 is turned on when the clock signal CLK is at a first level and turned off when the clock signal CLK is at a second level. Specifically, the first terminal of switch SW3 is connected to the second terminal of current source I1, the second terminal of switch SW3 is connected to the first terminal of switch SW4, the second terminal of switch SW4 is connected to the output terminal of buffer U2, and the control terminal of switch SW4 receives the clock signal CLK. Furthermore, the offset module 2222 also includes a comparison unit 2221, which controls the conduction of switch SW3 when switch SW8 in the selection circuit 110 is turned on. Exemplarily, the comparison unit 2221 includes, for example, a comparison circuit (not shown). A first input of the comparison circuit is connected to, for example, the first terminals of the switches SW7 and SW8 to receive the substrate voltage VMAX of the switch SW1. A second input of the comparison circuit receives, for example, the power supply voltage VDD. An output of the comparison circuit outputs a comparison result. For example, when the substrate voltage VMAX is greater than the power supply voltage VDD, the comparison result is in a valid level state, thereby controlling the switch SW3 to be turned on. When the substrate voltage VMAX is less than the power supply voltage VDD, the comparison result is in an invalid level state, thereby controlling the switch SW3 to be turned off.

[0057] When the substrate voltage VMAX of switch SW1 is greater than the power supply voltage and the drive voltage Vg is supplied to switch SW1, the charge pump circuit 200 generates an offset voltage that is superimposed on the feedback amplified signal. This increases the amplitude of the gate-source voltage of switch SW1 and thus improves its current handling capability. This ensures that at least switches SW1 and SW2 in the charge pump circuit 200 remain in the saturation region, thereby charging and discharging the flying capacitor Cfly.

[0058] Drain-source voltage of switch SW1 , the drain-source voltage of switch SW2 in, is the voltage difference across the flying capacitor Cfly. When the charge and discharge capabilities of switch SW1 and switch SW2 are exactly the same, the drain-source voltage of switch SW1 The drain-source voltage of switch SW2 If they are equal, the steady-state value of the voltage difference of the flying capacitor Cfly is That is, the embodiment of the present application adaptively adjusts the overcurrent capacity between the switch SW1 and the switch SW2 by the size of the power supply voltage VDD, so that the switch SW1 and the switch SW2 operate in the saturation region, and the voltage difference of the flying capacitor Cfly is stabilized at The change of the power supply voltage VDD is small, so that the state switching of the entire system is smoother and more stable during the change of the power supply voltage.

[0059] It should be noted that although devices are described herein as certain N-channel or P-channel devices, or certain N-type or P-type doped regions, those skilled in the art will appreciate that complementary devices are also achievable according to the present invention. Those skilled in the art will appreciate that conductivity type refers to the mechanism by which conduction occurs, such as conduction by holes or electrons. Therefore, conductivity type does not refer to doping concentration but rather to doping type, such as P-type or N-type. Those skilled in the art will appreciate that the terms "during," "when," and "when" used herein with respect to circuit operation are not strict terms indicating that an action occurs immediately upon the start of a startup action. Rather, there may be some small but reasonable delay or delays between the start of a startup action and the reaction initiated by the startup action, such as various transmission delays. The terms "approximately" or "substantially" are used herein to indicate that an element has a parameter that is expected to be close to the stated value or position. However, as is well known in the art, slight variations exist that make it difficult to accurately define a value or position as stated. It is well established in the art that a deviation of at least ten percent (10%) (or at least twenty percent (20%) for semiconductor doping concentrations) is a reasonable deviation from the desired goal of accuracy as described. When used in conjunction with a signal state, the actual voltage value or logic state (e.g., "1" or "0") of the signal depends on whether positive or negative logic is used.

[0060] In addition, it should be noted that relational terms such as first and second, etc., in this article are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "comprises", "comprising" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device that includes a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements that are inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprising a ..." does not exclude the presence of other identical elements in the process, method, article or device that includes the element.

[0061] The embodiments of the present invention are described above, but these embodiments do not describe all details in detail, nor do they limit the invention to specific embodiments. Obviously, many modifications and variations can be made based on the above description. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can make good use of the present invention and modify and use it based on the present invention. The scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A charge pump circuit, wherein: include: a first switch, wherein the control terminal receives a driving voltage when the clock signal is in a first level state, and the substrate terminal receives one of a power supply voltage and an output voltage; a second switch, wherein a control terminal receives the driving voltage when the clock signal is in a second level state, and a substrate terminal receives the power supply voltage; a flying capacitor, a first end of which receives the power supply voltage via the first switch, and a second end of which receives the power supply voltage via the second switch; a fifth switch, a first end of which is connected to the second end of the flying capacitor and a second end of which is grounded; a sixth switch, a first end of which is connected to the first end of the flying capacitor, and a second end of which provides the output voltage; as well as The output capacitor is connected between the output voltage and ground. Wherein, when the first switch is turned on, the fifth switch is turned on, and when the second switch is turned on, the sixth switch is turned on; When the first switch receives a driving voltage and is turned on, the second switch is turned off, and the power supply voltage charges the flying capacitor; when the second switch receives a driving voltage and is turned on, the first switch is turned off, and the flying capacitor discharges to generate the output voltage. When the power supply voltage is lower than the preset output voltage, the driving voltage provided to the first switch is lower than the driving voltage provided to the second switch during at least one cycle of the clock signal. When the power supply voltage is lower than the preset output voltage, the substrate end of the first switch receives the output voltage; when the power supply voltage is higher than the preset output voltage, the substrate end of the first switch receives the power supply voltage.

2. The charge pump circuit according to claim 1, wherein: When the power supply voltage is greater than a preset output voltage, the driving voltage provided to the first switch is equal to the driving voltage provided to the second switch during at least one cycle of the clock signal.

3. The charge pump circuit according to claim 2, wherein: Also includes: an adjustment circuit that provides an offset voltage when the power supply voltage is less than a preset output voltage and the first switch is turned on, generates a feedback amplified signal based on the output voltage and a reference voltage, and outputs the feedback amplified signal or the feedback amplified signal superimposed with the offset voltage as the drive voltage.

4. The charge pump circuit according to claim 3, wherein: When the power supply voltage is lower than the preset output voltage, the driving voltage provided to the first switch is a feedback amplified signal superimposed with the offset voltage, and the driving voltage provided to the second switch is a feedback amplified signal; when the power supply voltage is higher than the preset output voltage, the driving voltages are both the feedback amplified signal.

5. The charge pump circuit according to claim 3, wherein: The adjustment circuit includes: an offset module, configured to provide an offset voltage when the power supply voltage is less than a preset output voltage and the first switch is turned on; and a feedback module that generates a feedback amplified signal according to the output voltage and a reference voltage, and outputs the feedback amplified signal or the feedback amplified signal superimposed with the offset voltage as the driving voltage; The feedback module includes: a voltage dividing unit, collecting the output voltage to obtain a divided voltage; an error amplifier connected to the voltage divider unit, and generating the feedback amplified signal according to the divided voltage and the reference voltage; and A buffer has a first input terminal receiving the feedback amplified signal, a second input terminal connected to an output terminal of the buffer, and the output terminal further receiving the offset voltage.

6. The charge pump circuit according to claim 5, wherein: The imbalance module includes: a current source, a first terminal of which receives the power supply voltage; and A third switch and a fourth switch are connected in series between the second end of the current source and the output end of the buffer, wherein the third switch is turned on when the substrate end of the first switch receives the output voltage, and the fourth switch is turned on when the clock signal is in a first level state.

7. The charge pump circuit according to claim 1 , wherein: The preset output voltage is positively correlated with the reference voltage.

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