A pulse generation circuit applied to a gated time domain ADC

Abstract

The application discloses a pulse generation circuit applied to a gated time domain ADC, and comprises a first short time delay circuit, a second short time delay circuit, a first long time delay circuit, a second long time delay circuit, a first logic gate circuit and a second logic gate circuit. The first short time delay circuit is used for generating a first short time delay signal according to a first input signal; the second short time delay circuit is used for generating a second short time delay signal according to a second input signal; the first long time delay circuit is used for generating a first long time delay signal according to the first input signal; the second long time delay circuit is used for generating a second long time delay signal according to the second input signal; the first logic gate circuit is used for generating a first pulse signal according to the first short time delay signal and the second long time delay signal; the second logic gate circuit is used for generating a second pulse signal according to the second short time delay signal and the first long time delay signal; and a wide pulse selection circuit is used for selecting a final output pulse signal from the first pulse signal and the second pulse signal. The application greatly improves the linearity of the pulse generation circuit.

Description

Technical Field

[0001] This invention belongs to the field of mixed-signal integrated circuit processing technology, specifically relating to a pulse generation circuit applied to a gated time-domain ADC. Background Technology

[0002] A gated time-domain analog-to-digital converter (ADC) is a novel structure for achieving ultra-high energy efficiency ADCs. It boasts fast conversion speeds and low power consumption. The pulse generation circuit, as a key component, directly determines the overall performance of the gated ADC due to its linearity. Because of propagation delays, traditional pulse generation circuits suffer from a generation dead zone when the input signal time difference is small, failing to generate an effective pulse width. This severely impacts the linearity of the output pulse width. Summary of the Invention

[0003] To address the aforementioned problems in the prior art, this invention provides a pulse generation circuit for a gated time-domain ADC. The technical problem to be solved by this invention is achieved through the following technical solution:

[0004] This invention provides a pulse generation circuit for a gated time-domain ADC, comprising:

[0005] A first short-delay circuit is used to generate a first short-delay signal based on a first input signal;

[0006] The second short-delay circuit is used to generate a second short-delay signal based on the second input signal;

[0007] A first long delay circuit is used to generate a first long delay signal based on the first input signal;

[0008] The second long delay circuit is used to generate a second long delay signal based on the second input signal;

[0009] A first logic gate circuit is used to generate a first pulse signal based on the first short-delay signal and the second long-delay signal;

[0010] The second logic gate circuit is used to generate a second pulse signal based on the second short-delay signal and the first long-delay signal;

[0011] A wide pulse selection circuit is used to select the final output pulse signal from the first pulse signal and the second pulse signal.

[0012] In one embodiment of the present invention, the first short delay circuit and the second short delay circuit adopt the same circuit structure; the first short delay circuit includes M1 inverters connected in sequence, M1 being an even number greater than 1, and a switch connected to the control terminal of the last inverter; wherein the switching on and off is controlled by a synchronous clock signal.

[0013] In one embodiment of the present invention, the first long delay circuit and the second long delay circuit adopt the same circuit structure; the second long delay circuit includes N1 inverters connected in sequence, where N1 is an even number greater than 1 and N1>M1, and a switch connected to the last inverter; wherein the switching on and off is controlled by the synchronous clock signal.

[0014] In one embodiment of the present invention, the first logic gate circuit implements a logical XOR operation between the first short-delay signal and the second long-delay signal; the second logic gate circuit implements a logical XOR operation between the second short-delay signal and the first long-delay signal.

[0015] In one embodiment of the present invention, the first logic gate circuit and the second logic gate circuit adopt the same circuit structure; the first logic gate circuit includes a transistor P. 11 ~P 14 Transistor M 11 ~M 14 Inverters INT1 to INT2, where,

[0016] The input terminal of the inverter INT1 is connected to the first short-delay circuit and the transistor P. 11 The gate of the transistor M 12 The gate of the inverter INT1 is connected to the gate of the transistor P. 14 The gate of the transistor M 11 The gate of the inverter INT2 is connected to the second long delay circuit and the transistor P. 12 The gate of the transistor M 14 The gate of the inverter INT2 is connected to the gate of the transistor P. 13 The gate of the transistor M 13 The gate connection of the transistor P 11 The source of the transistor P 12 The source of the transistor is connected to VDD, and the transistor P 11 The drain of the transistor P 13 The source connection of the transistor P 12 The drain of the transistor P 14 The source connection of the transistor P13 The drain of the transistor M 11 The drain of the transistor P 14 The drain of the transistor M 12 The drain of the transistor M is connected to the first logic gate circuit. 11 The source of the transistor M 13 The drain connection of the transistor M 12 The source of the transistor M 14 The drain connection of the transistor M 13 The source of the transistor M 14 The source electrode is grounded.

[0017] In one embodiment of the present invention, the first short delay circuit and the second short delay circuit adopt the same circuit structure; the first short delay circuit includes M2 inverters connected in sequence, where M2 is an even number greater than 1.

[0018] In one embodiment of the present invention, the first long delay circuit and the second long delay circuit adopt the same circuit structure; the second long delay circuit includes N2 inverters connected in sequence, where N2 is an odd number greater than 1 and N2>M2.

[0019] In one embodiment of the present invention, the first logic gate circuit implements a logical AND operation between the first short-delay signal and the second long-delay signal; the second logic gate circuit implements a logical AND operation between the second short-delay signal and the first long-delay signal.

[0020] In one embodiment of the present invention, the first logic gate circuit and the second logic gate circuit adopt the same circuit structure; the first logic gate circuit includes a transistor P. 21 ~P 23 Transistor M 21 ~M 23 ,in,

[0021] The transistor P 21 The gate of the transistor M 21 The gate of transistor P is connected to the second long delay circuit. 21 The source of the transistor P 22 The source of the transistor P 23 The source of the transistor is connected to VDD, and the transistor P 21 The drain of the transistor P 22 The drain of the transistor M 21 The drain of the transistor P 23 The gate of the transistor M 23 The gate connection of the transistor P 22The gate of the transistor M 22 The gate of the transistor P is connected to the first short-delay circuit. 23 The drain of the transistor M 23 The drain of the transistor M is connected to the first logic gate circuit. 21 The source of the transistor M 22 The drain connection of the transistor M 22 The source of the transistor M 23 The source electrode is grounded.

[0022] In one embodiment of the present invention, the wide pulse selection circuit includes transistor P. 31 ~P 33 Transistor M 31 ~M 33 ,in,

[0023] The transistor P 31 The gate of the transistor M 31 The gate of the transistor P is connected to the first logic gate circuit. 31 The source of the transistor P 33 The source of the transistor is connected to VDD, and the transistor P 31 The drain of the transistor P 32 The source connection of the transistor P 32 The gate of the transistor M 32 The gate of transistor P is connected to the second logic gate circuit. 32 The drain of the transistor M 31 The drain of the transistor M 32 The drain of the transistor M 33 The gate of the transistor P 33 The gate connection of the transistor P 33 The drain of the transistor M 33 The drain and signal output terminals are connected, and the transistor M... 31 The source of the transistor M 32 The source of the transistor M 33 The source electrode is grounded.

[0024] The beneficial effects of this invention are:

[0025] The pulse generation circuit proposed in this invention for a gated time-domain ADC employs a novel dead-zone elimination technique. The insertion of short-delay and long-delay circuits ensures that even with a zero input time difference, the generated pulse has a defined minimum width (the delay difference between the long and short delay circuits). This effectively avoids the pulse generation dead zone when converting the input time difference to pulse width, thus achieving high linearity pulse generation. Furthermore, considering the nonlinear transition region between the pulse generation dead zone and the linear region, adjusting the delay difference between the short and long delay circuits allows the minimum pulse width to cover this nonlinear region, achieving a completely linear conversion from input time difference to pulse width. Additionally, since this delay difference is a fixed value in the design, the minimum pulse width with zero input time difference is also fixed, manifesting as a defined digital code offset in subsequent gated quantization. This offset can be easily eliminated in the digital domain without affecting the overall quantization performance of the gated time-domain ADC.

[0026] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. Attached Figure Description

[0027] Figure 1 This is a schematic diagram of a pulse generation circuit applied to a gated time-domain ADC provided in an embodiment of the present invention;

[0028] Figure 2 This is a schematic diagram of the structure of a first short delay circuit applied in a pulse generation circuit of a gated time-domain ADC provided in an embodiment of the present invention;

[0029] Figure 3 This is a schematic diagram of the structure of a second long delay circuit applied in a pulse generation circuit of a gated time-domain ADC provided in an embodiment of the present invention;

[0030] Figure 4 This is a schematic diagram of the structure of a first logic gate circuit applied in a pulse generation circuit of a gated time-domain ADC provided in an embodiment of the present invention;

[0031] Figure 5 This is a schematic diagram of another first short delay circuit provided in the pulse generation circuit of a gated time-domain ADC according to an embodiment of the present invention;

[0032] Figure 6 This is a schematic diagram of another second long delay circuit provided in the pulse generation circuit of a gated time-domain ADC according to an embodiment of the present invention;

[0033] Figure 7 This is a schematic diagram of another first logic gate circuit provided in the pulse generation circuit of a gated time-domain ADC according to an embodiment of the present invention;

[0034] Figure 8 This is a schematic diagram of the wide pulse selection circuit in the pulse generation circuit of a gated time-domain ADC provided in an embodiment of the present invention;

[0035] Figure 9 (a)~ Figure 9 (b) is a schematic diagram showing the comparison of the transmission characteristic curves of the conventional pulse generation circuit, the pulse generation circuit of the present invention, and the ideal pulse generation circuit provided in the embodiments of the present invention.

[0036] Figure 10 This is a schematic diagram showing the comparison of the transmission characteristic curves of a first logic gate circuit, a second logic gate circuit, and a wide pulse selection circuit provided in an embodiment of the present invention.

[0037] Figure 11 This is a schematic diagram of the timing output of each circuit stage in a pulse generation circuit provided by an embodiment of the present invention;

[0038] Figure 12 This is a schematic diagram showing the comparison of the transmission characteristic curves of another first logic gate circuit, a second logic gate circuit, and a wide pulse selection circuit provided in an embodiment of the present invention.

[0039] Figure 13 This is a schematic diagram of the timing output of each circuit stage in another pulse generation circuit provided in an embodiment of the present invention. Detailed Implementation

[0040] The present invention will be further described in detail below with reference to specific embodiments, but the implementation of the present invention is not limited thereto.

[0041] To effectively improve the linearity of the pulse generation circuit, please refer to [link / reference needed]. Figure 1 This invention provides a pulse generation circuit for a gated time-domain ADC, comprising:

[0042] The first short-delay circuit is used to determine the input signal T based on the first input signal T. in_p Generate the first short-delay signal T p_q ;

[0043] The second short-delay circuit is used to determine the input signal T based on the second input signal T. in_n Generate the second short-delay signal T n_q ;

[0044] The first long-delay circuit is used to determine the input signal T based on the first input signal T. in_p Generate the first long-delay signal T p_s ;

[0045] The second long delay circuit is used to determine the second input signal T.in_n Generate a second long-delay signal T n_s ;

[0046] The first logic gate circuit is used to determine the first short-delay signal T. p_q Second long delay signal T n_s Generate the first pulse signal CLK1;

[0047] The second logic gate circuit is used to determine the second short-delay signal T. n_q and the first long-delay signal T p_s Generate the second pulse signal CLK2;

[0048] A wide pulse selection circuit is used to select the final output pulse signal CLK from the first pulse signal CLK1 and the second pulse signal CLK2.

[0049] The pulse generation circuit for a gated time-domain ADC provided in this invention employs a novel dead-zone elimination technique. The insertion of short-delay and long-delay circuits ensures that even with a zero input time difference, the generated pulse has a defined minimum width (the delay difference between the long and short delay circuits). This effectively avoids the pulse generation dead zone when converting the input time difference to pulse width, thus achieving high-linearity pulse generation. Furthermore, considering the nonlinear transition region between the pulse generation dead zone and the linear region, adjusting the delay difference between the short and long delay circuits allows the minimum pulse width to cover this nonlinear region, achieving a completely linear conversion from input time difference to pulse width. Additionally, since this delay difference is a fixed value in the design, the minimum pulse width with zero input time difference is also defined. In subsequent gated quantization, this manifests as a defined digital code offset, which can be easily eliminated in the digital domain without affecting the overall quantization performance of the gated time-domain ADC.

[0050] Next, the implementation of the first short delay circuit, the second short delay circuit, the first long delay circuit, the second long delay circuit, the first logic gate circuit, the second logic gate circuit, and the wide pulse selection circuit will be described in detail in the embodiments of the present invention.

[0051] This invention provides an optional solution where the first short-delay circuit and the second short-delay circuit employ the same circuit structure; the input terminal of the first short-delay circuit is connected to the first input signal T. in_p The input terminal is connected to the output terminal (T) of the first short-delay circuit. p_q The second short-delay circuit is connected to the first logic gate, and its input is connected to the second input signal T. in_n The input terminal is connected to the output terminal of the second short-delay circuit (T). n_q ) is connected to the second logic gate. For example... Figure 2The first short-delay circuit shown includes M1 inverters connected in sequence, where M1 is an even number greater than 1, for example... Figure 2 The diagram illustrates two inverters connected in sequence, and a switch K1 connected to the control terminal of the last inverter. The other end of switch K1 is grounded. The switching on and off of switch K1 is controlled by a synchronous clock signal SYNC. Switch K1 can be a MOS transistor or other switching structures. The specific structure is not limited here, as long as the switching effect is achieved.

[0052] Correspondingly, the first long delay circuit and the second long delay circuit adopt the same circuit structure; the input terminal of the first long delay circuit is connected to the first input signal T. in_p The input terminal is connected to the output terminal (T) of the first long delay circuit. p_s The second logic gate is connected to the second long delay circuit, and the input of the second long delay circuit is connected to the second input signal T. in_n The input terminal is connected to the output terminal of the second long delay circuit (T). n_s ) is connected to the first logic gate circuit; such as Figure 3 The second long delay circuit shown includes N1 inverters connected in sequence, where N1 is an even number greater than 1, and N1 > M1, for example... Figure 2 The diagram shows four inverters connected in sequence, and a switch K2 connected to the last inverter. The other end of switch K2 is grounded. The switching on and off of switch K2 is controlled by the synchronization clock signal SYNC. Switch K2 and switch K1 can both have the same switching effect, and the specific structure is not limited.

[0053] Here, the first input signal T in_p Second input signal T in_n In the time domain, this can be represented as two input signals with different rising edges.

[0054] Correspondingly, the first logic gate circuit implements the first short-delay signal T. p_q Second long delay signal T n_s The first logic gate performs a logical XOR operation; the second logic gate implements the second short-delay signal T. n_q and the first long-delay signal T p_s The logical XOR operation. An embodiment of the present invention provides an optional solution where the first logic gate circuit and the second logic gate circuit adopt the same circuit structure; such as... Figure 4 The first logic gate circuit shown includes transistor P 11 ~P 14 Transistor M 11 ~M 14 Inverters INT1 to INT2, where,

[0055] The input of inverter INT1 is connected to the first short delay circuit (Tp_q ), transistor P 11 Gate, transistor M 12 The gate is connected, and the output of inverter INT1 is connected to transistor P. 14 Gate, transistor M 11 The gate is connected, and the input of inverter INT2 is connected to the second long delay circuit (T). n_s ), transistor P 12 Gate, transistor M 14 The gate is connected, and the output of inverter INT2 is connected to transistor P. 13 Gate, transistor M 13 Gate connection, transistor P 11 The source of the transistor P 12 The source of transistor P is connected to VDD. 11 The drain and transistor P 13 The source connection, transistor P 12 The drain and transistor P 14 The source connection, transistor P 13 The drain and transistor M 11 drain, transistor P 14 The drain of the transistor M 12 The drain and the first logic gate are connected, transistor M 11 The source and transistor M 13 The drain connection of transistor M 12 The source and transistor M 14 The drain connection of transistor M 13 The source of the transistor M 14 The source electrode is grounded.

[0056] Similarly, for the second logic gate circuit including transistor P 11 ~P 14 Transistor M 11 ~M 14 Inverters INT1 to INT2, the input of inverter INT1 is connected to the second short-delay circuit (T... n_q ), transistor P 11 Gate, transistor M 12 The gate is connected, and the input of inverter INT2 is connected to the first long delay circuit (T). p_s ), transistor P 12 Gate, transistor M 14 The gate connection is the same as that of the first logic gate circuit, and other connection methods are the same, so they will not be described again here.

[0057] This invention provides another optional solution, in which the first short-delay circuit and the second short-delay circuit adopt the same circuit structure; such as... Figure 5The first short-delay circuit shown includes M2 inverters connected in sequence, where M2 is an even number greater than 1, for example... Figure 5 The diagram shows two inverters connected in sequence.

[0058] Correspondingly, the first long delay circuit and the second long delay circuit adopt the same circuit structure; such as Figure 6 The second long delay circuit shown includes N2 inverters connected in sequence, where N2 is an odd number greater than 1, and N2 > M2, for example... Figure 6 The diagram shows five inverters connected in sequence.

[0059] Correspondingly, the first logic gate circuit implements the first short-delay signal T. p_q Second long delay signal T n_s The first logic gate performs AND operations; the second logic gate implements the second short-delay signal T. n_q and the first long-delay signal T p_s The logic and operations. An embodiment of the present invention provides an optional solution where the first logic gate circuit and the second logic gate circuit adopt the same circuit structure; such as... Figure 7 The first logic gate circuit shown includes transistor P 21 ~P 23 Transistor M 21 ~M 23 ,in,

[0060] transistor P 21 Gate, transistor M 21 The gate and the second long delay circuit (T) n_s ) connection, transistor P 21 The source of the transistor P 22 The source of the transistor P 23 The source of transistor P is connected to VDD. 21 The drain and transistor P 22 The drain of the transistor M 21 drain, transistor P 23 Gate, transistor M 23 Gate connection, transistor P 22 Gate and transistor M 22 The gate, the first short delay circuit (T) p_q ) connection, transistor P 23 The drain and transistor M 23 The drain and the first logic gate are connected, transistor M 21 The source and transistor M 22 The drain connection of transistor M 22 The source of the transistor M 23 The source electrode is grounded.

[0061] Similarly, for the second logic gate circuit including transistor P 21 ~P 23 Transistor M 21 ~M 23 transistor P 21 Gate, transistor M 21 The gate and the first long delay circuit (T) p_s ) connection, transistor P 22 Gate and transistor M 22 The gate, the second short delay circuit (T) n_q The connection is the same as the first logic gate circuit, and other connection methods are the same, so they will not be described again here.

[0062] Regardless of whether it is based on Figure 2 , Figure 3 , Figure 4 The circuit is still based on Figure 5 , Figure 6 , Figure 7 The circuit is composed of two logic gates, the first and second logic gates, which are ultimately connected to a wide pulse selection circuit. This embodiment of the invention provides an alternative solution for the wide pulse selection circuit, such as... Figure 8 The wide pulse selection circuit shown includes transistor P 31 ~P 33 Transistor M 31 ~M 33 ,in,

[0063] transistor P 31 Gate, transistor M 31 The gate of transistor P is connected to the first logic gate (CLK1). 31 The source of the transistor P 33 The source of transistor P is connected to VDD. 31 The drain and transistor P 32 The source connection, transistor P 32 Gate, transistor M 32 The gate of transistor P is connected to the second logic gate (CLK2). 32 The drain and transistor M 31 The drain of the transistor M 32 The drain of the transistor M 33 Gate, transistor P 33 Gate connection, transistor P 33 The drain and transistor M 33 The drain and signal output terminal (CLK) are connected, and transistor M... 31 The source of the transistor M 32 The source of the transistor M 33 The source electrode is grounded.

[0064] As can be seen, the first input signal T in this embodiment of the invention in_p The first long-delay signal T is generated by the first long-delay circuit and the first short-delay circuit respectively. p_s and the first short-delay signal T p_q The second input signal T in_n The second long-delay circuit and the second short-delay circuit generate the second long-delay signal T respectively. n_s Second short delay signal T n_q After that, the first short-delay signal T p_q With the second long-delay signal T n_s A first pulse signal CLK1 is generated through the first logic gate circuit (the pulse width of the first pulse signal CLK1 is equal to that of the first short-delay signal T). p_q With the second long-delay signal T n_s (Time difference), similarly, the first long-delay signal T p_s With the second short-delay signal T n_q The second pulse signal CLK2 is generated through the second logic gate circuit (the pulse width of the second pulse signal CLK2 is equal to that of the first long-delay signal T). p_s With the second short-delay signal T n_q (Time difference), and finally, the first pulse signal CLK1 and the second pulse signal CLK2 are used to generate the output pulse signal CLK through the wide pulse selection circuit (the width of the output pulse signal CLK is equal to the larger pulse width of the first pulse signal CLK1 and the second pulse signal CLK2).

[0065] Assume the first input signal T in_p With the second input signal T in_n The rising / falling times are T and T, respectively. p and T n The delay of the first long delay circuit and the second long delay circuit is T. s The delay of the first short-delay circuit and the second short-delay circuit is T. q The first short-delay signal T generated by the first short-delay circuit p_q The first long-delay signal T generated by the first long-delay circuit p_s The second short-delay signal T generated by the second short-delay circuit n_q The second long delay signal T generated by the second long delay circuit n_s The rising / falling times are T and T, respectively. p +T q T p +T s T n +T q T n +T sThen the widths of the first pulse signal CLK1 generated by the first logic gate circuit and the second pulse signal CLK2 generated by the second logic gate circuit are |T p +T q -T n -T s | and | T p +T s -T n -T q The final output pulse signal CLK width is |T p -T n |+T s -T q As can be seen, even the first input signal T in_p With the second input signal T in_n Input time difference |T p -T n When | is zero, the output pulse signal CLK still has a fixed minimum pulse width (T). s -T q Let the fixed pulse width be T. os .

[0066] The input-output transfer characteristic curves of the conventional pulse generation circuit, the pulse generation circuit of this invention, and the ideal pulse generation circuit are shown below. Figure 9 (a)~ Figure 9 As shown in (b), it can be seen that the input-output transmission characteristic curve of the traditional pulse generation circuit exhibits severe nonlinearity when the input time difference is small due to the existence of a pulse generation dead zone. However, the pulse generation circuit proposed in this embodiment of the invention, by introducing a minimum fixed pulse width and designing it to be sufficiently large, can effectively fill the input dead zone and nonlinear region, thereby achieving a highly linear conversion (approximately the linearity of an ideal curve) from the input time difference to the output pulse signal CLK. The difference between its transmission characteristic curve and the ideal transmission characteristic curve lies only in the introduction of an initial fixed output pulse width, the width of which is equal to the delay difference between the long-delay circuit and the short-delay circuit, i.e., the delay T of the first long-delay circuit. s The delay T of the first short delay circuit q The time difference between them, and the time delay T of the second long delay circuit. s The delay T of the first short delay circuit q The delay difference between them can be designed to be a fixed value, so the effect of the initial fixed pulse width can be easily eliminated in subsequent processing.

[0067] based on Figure 1 The embodiments of the present invention propose implementation methods for the above two specific circuits, by Figure 2 , Figure 3 , Figure 4 , Figure 8The formed pulse generation circuit, and Figure 5 , Figure 6 , Figure 7 , Figure 8 Another pulse generation circuit is formed, specifically:

[0068] Figure 2 , Figure 3 Examples of a first short delay circuit and a second long delay circuit are given in the embodiments of the present invention. The second long delay circuit and the first short delay circuit are composed of an inverter chain. Similarly, the first long delay circuit and the second short delay circuit are composed of an inverter chain. Their output falling edges are synchronized by a unified synchronization clock SYNC. Figure 4 An example of a first logic gate circuit is given in an embodiment of the present invention. Similarly, a second logic gate circuit is adopted as follows: Figure 4 The circuit structures shown all implement the XOR function, the purpose of which is: the first logic gate circuit will input the first short-delay signal T. p_q With the second long-delay signal T n_s The time difference between them is converted into the first pulse signal CLK1. Similarly, the second logic gate circuit will input its second short-delay signal T. n_q With the first long-delay signal T p_s The time difference between them is converted into a second pulse signal CLK2; Figure 8 An example of a wide pulse selection circuit in this invention is provided. It implements an OR function, aiming to make the output pulse width CLK equal to the larger of the two input pulse signals CLK1 and CLK2. This embodiment considers that in practical applications, usually only the time difference of one input edge (rising edge or falling edge) needs to be converted. Therefore, in the second long delay circuit and the first short delay circuit, as well as in the first long delay circuit and the second short delay circuit, a dynamic delay method can be used to synchronize the edges that do not need to be converted with an additional synchronization signal SYNC, to avoid generating additional output pulse width. Taking the case of converting the time difference of the input rising edge as an example... Figure 10 The following is given by Figure 2 , Figure 3 , Figure 4 , Figure 8 The input-output transmission characteristic curves of the specific first pulse signal CLK1, second pulse signal CLK2 and output pulse CLK corresponding to the formed pulse generation circuit show that although the first pulse signal CLK1 and the second pulse signal CLK2 still have pulse generation dead zones, the width of the output pulse CLK is determined by the larger pulse width in the first pulse signal CLK1 and the second pulse signal CLK2, thus effectively eliminating dead zones and nonlinearity. Figure 11 The following is given by Figure 2 , Figure 3 , Figure 4 , Figure 8 The input signal time of the formed pulse generation circuit is respectively at T p <T n T p =T n T p >T n The specific timing sequence of the signals in the three cases.

[0069] Figure 5 , Figure 6 Examples of another first short delay circuit and a second long delay circuit in the embodiments of the present invention are given respectively. The second long delay circuit and the first short delay circuit are composed of an inverter chain. Similarly, the first long delay circuit and the second short delay circuit are composed of an inverter chain. Figure 7 Another example of a first logic gate circuit is given in the embodiments of the present invention. Similarly, the second logic gate circuit adopts the following... Figure 7 The circuit structures shown all implement a logical AND operation. Their inputs are inverted, and the time difference is then converted into a first pulse signal CLK1 and a second pulse signal CLK2. Finally, through... Figure 8 The given example of a wide pulse selection circuit selects the larger pulse width from two inputs: a first pulse signal CLK1 and a second pulse signal CLK2. (This is an embodiment of the invention.) Figure 12 The following is given by Figure 5 , Figure 6 , Figure 7 , Figure 8 The input-output transfer characteristic curves of the specific first pulse signal CLK1, second pulse signal CLK2, and output pulse CLK corresponding to the formed pulse generation circuit are shown below. Figure 13 The following is given by Figure 5 , Figure 6 , Figure 7 , Figure 8 The input signal time of the formed pulse generation circuit is respectively at T p <T n T p =T n T p >T n The specific timing sequence of the signals in the three cases, and Figure 10 , Figure 11 In comparison, by Figure 5 , Figure 6 , Figure 7 , Figure 8 The resulting pulse generation circuit structure is compared to that of... Figure 2 , Figure 3 , Figure 4 , Figure 8 The advantage of the formed pulse generation circuit is that... Figure 7The example's first and second logic gates operate for almost half of the input time, thus effectively reducing conversion power consumption and eliminating the need for additional SYNC clock control.

[0070] In the description of this invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified.

[0071] Although the invention has been described herein in conjunction with various embodiments, those skilled in the art, by reviewing the specification and accompanying drawings, will understand and implement other variations of the disclosed embodiments in carrying out the claimed invention. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality. While certain measures are described in different embodiments, this does not mean that these measures cannot be combined to produce good results.

[0072] The above description, in conjunction with specific preferred embodiments, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions. For those skilled in the art, various simple deductions or substitutions can be made without departing from the concept of the present invention, and all such modifications and substitutions should be considered within the scope of protection of the present invention.

Claims

1. A pulse generation circuit for a gated time-domain ADC, characterized in that, include: A first short-delay circuit is used to generate a first short-delay signal based on a first input signal; The second short-delay circuit is used to generate a second short-delay signal based on the second input signal; A first long delay circuit is used to generate a first long delay signal based on the first input signal; The second long delay circuit is used to generate a second long delay signal based on the second input signal; A first logic gate circuit is used to generate a first pulse signal based on the first short-delay signal and the second long-delay signal; the pulse width of the first pulse signal is equal to the time difference between the first short-delay signal and the second long-delay signal. The second logic gate circuit is used to generate a second pulse signal based on the second short-delay signal and the first long-delay signal; The pulse width of the second pulse signal is equal to the time difference between the second short-delay signal and the first long-delay signal; A wide pulse selection circuit is used to select the pulse signal with the larger pulse width from the first pulse signal and the second pulse signal as the final output pulse signal; Specifically, by designing the delay difference between the delay of the first long delay circuit and the delay of the second short delay circuit, as well as the delay difference between the delay of the second long delay circuit and the delay of the first short delay circuit, to a fixed value, the generated pulse has a fixed minimum width even when the input time difference is zero, so as to avoid the pulse generation dead zone and achieve high linearity pulse generation.

2. The pulse generation circuit applied to a gated time-domain ADC according to claim 1, characterized in that, The first short delay circuit and the second short delay circuit adopt the same circuit structure; the first short delay circuit includes M1 inverters connected in sequence, M1 being an even number greater than 1, and a switch connected to the control terminal of the last inverter; wherein, the switching on and off is controlled by a synchronous clock signal.

3. The pulse generation circuit applied to a gated time-domain ADC according to claim 2, characterized in that, The first long delay circuit and the second long delay circuit adopt the same circuit structure; the second long delay circuit includes N1 inverters connected in sequence, where N1 is an even number greater than 1, N1>M1, and a switch connected to the last inverter; wherein the switching on and off is controlled by the synchronous clock signal.

4. The pulse generation circuit applied to a gated time-domain ADC according to claim 3, characterized in that, The first logic gate circuit implements the logical XOR operation of the first short-delay signal and the second long-delay signal; the second logic gate circuit implements the logical XOR operation of the second short-delay signal and the first long-delay signal.

5. The pulse generation circuit applied to a gated time-domain ADC according to claim 4, characterized in that, The first logic gate circuit and the second logic gate circuit adopt the same circuit structure; the first logic gate circuit includes transistor P. 11 ~P 14 Transistor M 11 ~M 14 Inverters INT1~INT2, where, The input terminal of the inverter INT1 is connected to the first short-delay circuit and the transistor P. 11 The gate of the transistor M 12 The gate of the inverter INT1 is connected to the gate of the transistor P. 14 The gate of the transistor M 11 The gate of the inverter INT2 is connected to the second long delay circuit and the transistor P. 12 The gate of the transistor M 14 The gate of the inverter INT2 is connected to the gate of the transistor P. 13 The gate of the transistor M 13 The gate connection of the transistor P 11 The source of the transistor P 12 The source of the transistor is connected to VDD, and the transistor P 11 The drain of the transistor P 13 The source connection of the transistor P 12 The drain of the transistor P 14 The source connection of the transistor P 13 The drain of the transistor M 11 The drain of the transistor P 14 The drain of the transistor M 12 The drain of the transistor M is connected to the first logic gate circuit. 11 The source of the transistor M 13 The drain connection of the transistor M 12 The source of the transistor M 14 The drain connection of the transistor M 13 The source of the transistor M 14 The source electrode is grounded.

6. The pulse generation circuit applied to a gated time-domain ADC according to claim 1, characterized in that, The first short delay circuit and the second short delay circuit adopt the same circuit structure; the first short delay circuit includes M2 inverters connected in sequence, where M2 is an even number greater than 1.

7. The pulse generation circuit for a gated time-domain ADC according to claim 6, characterized in that, The first long delay circuit and the second long delay circuit adopt the same circuit structure; the second long delay circuit includes N2 inverters connected in sequence, where N2 is an odd number greater than 1 and N2 > M2.

8. The pulse generation circuit applied to a gated time-domain ADC according to claim 7, characterized in that, The first logic gate circuit implements a logical AND operation between the first short-delay signal and the second long-delay signal; the second logic gate circuit implements a logical AND operation between the second short-delay signal and the first long-delay signal.

9. The pulse generation circuit applied to a gated time-domain ADC according to claim 8, characterized in that, The first logic gate circuit and the second logic gate circuit adopt the same circuit structure; the first logic gate circuit includes transistor P. 21 ~P 23 Transistor M 21 ~M 23 ,in, The transistor P 21 The gate of the transistor M 21 The gate of transistor P is connected to the second long delay circuit. 21 The source of the transistor P 22 The source of the transistor P 23 The source of the transistor is connected to VDD, and the transistor P 21 The drain of the transistor P 22 The drain of the transistor M 21 The drain of the transistor P 23 The gate of the transistor M 23 The gate connection of the transistor P 22 The gate of the transistor M 22 The gate of the transistor P is connected to the first short-delay circuit. 23 The drain of the transistor M 23 The drain of the transistor M is connected to the first logic gate circuit. 21 The source of the transistor M 22 The drain connection of the transistor M 22 The source of the transistor M 23 The source electrode is grounded.

10. The pulse generation circuit applied to a gated time-domain ADC according to claim 5 or 9, characterized in that, The wide pulse selection circuit includes transistor P. 31 ~P 33 Transistor M 31 ~M 33 ,in, The transistor P 31 The gate of the transistor M 31 The gate of the transistor P is connected to the first logic gate circuit. 31 The source of the transistor P 33 The source of the transistor is connected to VDD, and the transistor P 31 The drain of the transistor P 32 The source connection of the transistor P 32 The gate of the transistor M 32 The gate of transistor P is connected to the second logic gate circuit. 32 The drain of the transistor M 31 The drain of the transistor M 32 The drain of the transistor M 33 The gate of the transistor P 33 The gate connection of the transistor P 33 The drain of the transistor M 33 The drain and signal output terminals are connected, and the transistor M... 31 The source of the transistor M 32 The source of the transistor M 33 The source electrode is grounded.

Images