Counter-based multiplication using in-memory processing

Abstract

The present disclosure relates to systems and methods for, for example, memory devices such as in-memory processing devices configured to perform multiplication operations in memory using a population count operation. A multiplication operation can include a sum of a multiplicand multiplied by a corresponding multiplicand. Inputs can be arranged in a particular configuration within a memory array. Sense amplifiers can be used to perform the population count by counting significant bits along a bit line. One or more registers can accumulate results for performing the multiplication operation.

Description

[0001] Related applications

[0002] This application claims priority to U.S. Patent Application No. 16 / 836,773, filed March 31, 2020, entitled "Counter-based Multiplication Using Processing in Memory," the entire disclosure of which is hereby incorporated herein by reference. Background Technology

[0003] General-purpose processors can interface with memory components and caches to perform repetitive computations on stored data. Data can be loaded into a cache, the processor can then access the data, the processor can compute the result, and the result can then be stored in memory. Processors can perform repetitive or intensive linear algebra operations by manipulating matrix elements. For example, a processor can perform read / write operations to retrieve data, process the data, and store it in memory. These general-purpose processors can be used to perform multiplication operations as part of more complex algorithms, such as convolution operations. In addition to general-purpose processors, dedicated devices, such as in-memory processing devices, can include memory arrays and logic to perform operations on the contents of the memory array. Attached Figure Description

[0004] Many aspects of this disclosure can be better understood with reference to the accompanying drawings. Components in the drawings are not necessarily drawn to scale, but are intended to clearly illustrate the principles of this disclosure. Furthermore, in the drawings, similar reference numerals refer to corresponding portions throughout several views.

[0005] Figure 1 These are diagrams of memory devices according to various embodiments.

[0006] Figures 2A to 2B This is a diagram of a memory device that performs in-memory multiplication using a common multiplier with a total count (popcount) operation according to various embodiments.

[0007] Figure 3 This is a flowchart illustrating the functionality of a memory device that performs in-memory multiplication using a total counting operation according to various embodiments.

[0008] Figures 4A to 4E This is a diagram of a memory device that performs in-memory multiplication with different multipliers using total counting operations according to various embodiments.

[0009] Figure 5 This is a flowchart illustrating the functionality of a memory device that performs in-memory multiplication with different multipliers using a total counting operation according to various embodiments.

[0010] Figure 6 This is a schematic diagram illustrating a system including a memory device according to various embodiments. Detailed Implementation

[0011] This disclosure relates to systems and methods for performing multiplication in a memory device using total counting operations. By performing multiplication in the memory device (e.g., performing an "in-memory" operation), at least some operands of the multiplication operation can be stored in memory, loaded separately in system memory, cache, some other fast memory, or the like. By performing the multiplication operation, the memory device of this disclosure can include components such as registers, controllers, and sense amplifiers to perform the multiplication operation directly in the memory device.

[0012] This disclosure describes embodiments using total counting operations. Total counting operations are operations performed in a memory device, wherein a series of memory cells are provided as input, and the number of high (“hi”) bits (e.g., significant bits or “1”) is counted. For example, if the series of memory cells contains binary values ​​[1,0,1,1,0,1], then the total counting operation will produce the number 4 because four bits have the value “1” (e.g., significant bits or hi bits).

[0013] This disclosure describes various ways in which structured memory devices perform total counting operations as part of multiplication operations. Basic multiplication involves a multiplier (A) and a multiplicand (B), producing a product expressed as "A x B". More complex multiplication operations may involve one multiplier (A) and multiple multiplicands (B and C), where the product is expressed as "A x B + A x C" or alternatively as "A x (B + C)". In this case, the multiplicands are added together and then multiplied by the multiplier. The multiplicand may be referred to as the "addend," which is the operand to be added together. Thus, in this example, the multiplier (A) is the common multiplier. More complex multiplication operations may involve different multipliers corresponding to different multiplicands. For example, the multipliers (A and B) may correspond to multiplicands (C and D), such that the resulting product is expressed as "A x C + B x D". In this context, the operation can be referred to as the "dot product" of two vectors or sequences [A,B] multiplied by [C,D], or more broadly, the sum of element-wise products of more than one vector or sequence.

[0014] In some embodiments, the memory device is a dedicated means for performing multiplication operations, typically as part of a convolution operation (e.g., in a convolutional neural network). The memory device can be used to implement one or more layers in a convolutional neural network. Convolutional neural networks can be designed to detect: image features in image data, motion features in video streams, text patterns in text data, statistical features in multidimensional complex data, scientific features in scientific processes and simulations, astronomical features in astronomical data from space, weather conditions and forecasts based thereon in world weather data, and text in speech audio data. Convolutional neural networks can be used to detect features or characteristics in computer-generated graphics, virtual reality data, and augmented reality data. Features can be detected in satellite imagery, long-exposure graphics, time-lapse video, and slow-motion video. Convolutional neural networks can be configured to perform feature detection on graphical or visual representations of data collected from various sources, such as data repositories or databases. Data undergoing feature detection can be structured, semi-structured, unstructured, machine-generated data objects, data logs, real-time data generated from remote sources, data aggregated from multiple sources, data received over a network, data preprocessed by an external system, data visually filtered, or at least partially generated by an external computing system. Features searched within the data include visual patterns, horizontal lines, edges, vertical lines, various shapes, curves, angles, specific colors, and orientation. Furthermore, simple features can be combined to form more complex features, such as complex objects.

[0015] In addition to implementing convolutional neural networks, the memory device can be configured as an in-memory linear algebra accelerator, an in-memory neuromorphic processor, a compute-capable dual in-memory memory module (DIMM), an in-memory graphics processor, and a compute-capable smart solid-state drive (SSD). Furthermore, the memory device can include NAND flash memory arrays, X-dot arrays, or other compute-capable memory arrays. The memory device can be configured to perform matrix-matrix multiplication and neural network inference and training.

[0016] The following discussion refers to the figures to illustrate various embodiments of a memory device that uses total counting operations to perform multiplication.

[0017] Figure 1 This is a diagram of a memory device 100 according to various embodiments. (See diagram for example.) Figure 1The memory device 100 shown may be embodied as a part-memory processing (PIM) device. However, this disclosure is not limited to PIM devices. A PIM device is a semiconductor device comprising one or more memory arrays and a PIM processor coupled to these memory arrays. The PIM processor is configured to perform operations using data stored in cells of the memory arrays without needing to perform time-intensive input / output operations, fetch operations, or load / store operations via a memory bus. In this respect, the PIM processor can access at least some data to perform data and computational operations without buffer memory or cache or bus. In contrast, a host processor is coupled to one or more memory devices via a memory bus or other links. The host processor may be a central processing unit (CPU), digital signal processor, graphics processing unit (GPU), dedicated processor, or general-purpose processor in a device or system installed outside the memory devices. The host processor may be installed in a computing device, laptop computer, mobile device, server, dedicated computer, or general-purpose computer.

[0018] Memory device 100 is an integrated circuit. Memory device 100 may be a semiconductor chip, die, or stack of dies. Memory device 100 may include one or more memory arrays 103. Memory array 103 includes multiple rows and columns, and may be defined according to row-column size. Figure 1 An example is shown: a memory array 103 having rows labeled r1 to rn and columns labeled c1 to cn. At each intersection of rows and columns is a memory cell configured to store at least a portion of the operands in a multiplication operation. The operands can be multipliers or multiplicands. In this respect, for example, the operand of the decimal number "9" can be stored across multiple memory cells as a series of binary bits "1001".

[0019] A memory cell can be a single-level cell storing one binary bit (e.g., a bit that may have two values ​​or states, such as "0" or "1" encoded as the low or high value of the memory cell), or a multi-level cell containing multiple bits or levels (e.g., a cell that can store multiple bits). An example of a multi-level cell is a QCL NAND flash memory, which may have 16 values ​​or states encoded as Vt (threshold voltage) of a floating-gate transistor, thus storing 4 bits or 4 levels of data per memory cell. To illustrate a memory array composed of multi-level cells (e.g., a two-level cell encoding 2 binary bits), the decimal number "9" (expressed as the binary number "1001") can be stored in a multi-level cell with the left part (two most significant bits) of the four binary bits as the binary number "10", and the right part (two least significant bits) as the binary number "01" in another two-level cell. In a memory device with single-level memory cells, the decimal number "9" can occupy at least four separate cells to represent the binary number "1001".

[0020] Therefore, memory array 103 is a hardware component for storing data as multiple array elements addressable by rows and columns. Memory device 100 may include several memory arrays 103 organized throughout memory device 100. Memory array 103 may be implemented using various types of technologies, organizations, or aspects. A memory array may be defined as containing volatile memory and non-volatile memory. Volatile components may be components that do not retain data values ​​when power is lost. Non-volatile components may be components that retain data when power is lost. Memory array 103 may include random access memory (RAM), read-only memory (ROM), and solid-state memory arrays. RAM may include static random access memory (SRAM) and dynamic random access memory (DRAM). Memory array 103 may include solid-state memory, such as flash memory, NOR flash memory (e.g., flash memory in a NOR configuration), or NAND flash memory (e.g., flash memory in a NAND configuration). Memory arrays may be resistive RAM (ReRAM), crosspoint memory, or cross-switch 3D memory. Rows, columns, or other memory addresses can be used to access each type of memory technology used to implement memory arrays. A row may be called a word line. A word line may include a terminal of the gate of a transistor corresponding to a memory cell. Alternatively, word lines may be directly connected to the memory cell material, such as for resistive or diode-based memory cells. A column may be called a bit line. A bit line may include the source and / or drain of a transistor constituting a memory cell, a capacitor terminal of a capacitor constituting a memory cell, a resistor terminal of a resistor constituting a memory cell, a diode terminal of a diode constituting a memory cell, or a combination thereof.

[0021] The memory array 103 includes peripheral circuitry that may be located outside or as part of the memory array 103. The peripheral circuitry may include an accumulator 106, a controller 109, a buffer memory 112, a system link 115, and potentially other integrated components, such as a sense amplifier for sensing data from the memory array 103 and a driver for storing data back to the memory array 103.

[0022] Accumulator 106 may be, for example, a fused multiply-accumulate (FMA) unit 106. Accumulator 106 may be configured to perform dot product multiplication on a data array (or matrix) including, for example, multipliers or multiplicands. Operands for the multiplication operation may be supplied directly from memory array 103 and from controller 109. In some embodiments, accumulator 106 may be dedicated to performing only dot product matrix calculations. Accumulator 106 may be configured to perform a multiply-accumulate operation that calculates the product of the input operands and adds the product to an accumulated value. Accumulator 106 may include one or more registers for storing intermediate values ​​as part of the multiplication operation.

[0023] Controller 109 is part of the processor of memory device 100. Controller 109 may include an integrated circuit system or logic embodied in hardware for storing data into memory array 103. Additionally, controller 109 may be received from a location outside memory array 103. Controller 109 may be implemented to select bit lines and word lines in a specific pattern according to logic, microcode, or other algorithms.

[0024] Memory device 100 may also include buffer memory 112. Buffer memory may be included as part of controller 109 and / or accumulator 106, or it may be external to controller 109 and / or accumulator 106, or it may be connected to these components 109 and 106 via an internal bus (e.g., system link 115). Alternatively, buffer memory 112 may be part of memory array 103 specifically allocated for the buffering purposes described herein. Specifically, a portion of memory array 103 allocated to buffer memory may be a portion of the array with faster access (e.g., a shorter path to accumulator 106). Buffer memory 112 may include buffers to temporarily store data while controller 109 and accumulator 106 perform multiplication operations. Controller 109 and / or accumulator 106 may write to or read from buffer memory 112. For example, buffer memory 112 may be used to store intermediate results as part of a multiplication operation. The buffer memory 112 may also store portions of the operands of the multiplication operation, for example, one or more multipliers, which are stored in the memory array 103 at the same time.

[0025] System link 115 of memory device 100 provides data and / or control signals between memory device 100 and external systems. System link 115 may be coupled to various components of memory device 100, such as memory array 103, accumulator 106, controller 109, buffer memory 112, and other components. Therefore, system link 115 may include internal links between various components of memory device 100, allowing these components to exchange data and / or control signals with each other. System link 115 may include input / output ports to couple to external systems outside memory device 100. System link 115 may be an input / output (I / O) bus, such as a DDR4 bus or PCIe bus. In this respect, external systems can read or write data to memory array 103, accumulator 106, and buffer memory 112. Additionally, external systems can transmit control signals to controller 109 to program or otherwise control controller 109.

[0026] The external system may include a host processor with a PCB motherboard, wherein memory devices 100 are connected to the host processor via a bus such as DDR4, DDR5, or PCIe or similar. The external system may execute an operating system, applications, libraries, scripts, or programming languages. The external system may include one or more server racks or computers or other arrangements. Servers may be a single installation or may be distributed across many different geographical locations. The external system may include multiple computing devices, which together may include managed computing resources, grid computing resources, and / or any other distributed computing arrangements. In some cases, the external system may correspond to elastic computing resources, where the capacity of allocated processing, networking, storage, or other computing-related resources may vary over time. The external system may implement one or more virtual machines that utilize the resources of the computing system. Various software components may be executed on one or more virtual machines. The external system may also include additional memory devices 100. In this regard, examples of memory devices 100 may allow querying, controlling, or accessing data in any additional memory devices 100 installed in the system.

[0027] System link 115 allows memory device 100 to be coupled to external systems that implement convolutional neural networks together or separately. For example, memory device 100 may implement one or more layers within a neural network. For instance, memory device 100 may be used to implement convolutional layers. System link 115 can extract the output of memory device 100 and input it to different layers of the neural network located in other memory devices or other parts of external systems. Pooling layers in the neural network can obtain output from system link 115 of memory device 100, perform pooling operations, and pass the results as input to memory device 100. For example, output data generated by accumulator 106 can be accessed by system link 115 and processed externally by pooling layers, wherein the results are supplied via system link 115 to memory array 103 of memory device 100 for further processing. The following figures provide examples of... Figure 1 Examples of configuration and computation occurring within the memory device of the memory device 100.

[0028] Figures 2A to 2B This is a diagram of a memory device 100 that performs in-memory multiplication using a common multiplier with a total counting operation according to various embodiments. Figure 2A In this context, memory device 100 is configured to perform a multiplication operation, wherein multiplier 203 is applied to the sum of first multiplicand 206a and second multiplicand 206b. Figure 2A In the example shown, the multiplier 203 has the value of decimal "6", the first multiplicand 206a has the value of decimal "7", and the second multiplicand 206b has the value of decimal "10". Alternatively, according to the distributive law of multiplication, this can be interpreted as 6 x 7 + 6 x 10, rather than 6 x (7 + 10). In this respect, A x (B + C) can be expressed as the dot product of the following two vectors: [A,A] x [B,C]. Therefore, Figure 2A An embodiment is depicted in which the common multiplier 203 is applied to the multiplicands 206a and 206b. However, any number of multiplicands may be included as... Figure 2A The multiplication operation shown in the image.

[0029] The memory device 100 may store a first multiplicand 206a in the first bit line (e.g., BL 1) of the memory array and a second multiplicand 206b in the second bit line (e.g., BL 2) of the memory array. In some embodiments, the first and second bit lines are in the same memory array. In other embodiments, the first and second bit lines are in different arrays. When the multiplicands 206a and 206b are stored in the bit lines, the value of the multiplicand may occupy multiple memory cells, such that it spans multiple word lines. For example, the first multiplicand 206a having the instance decimal number "7" is represented as "0111" in binary. The least significant bit "1" may be stored at the first word line (e.g., WL 1). The second bit "1" may be stored at the second word line (e.g., WL 2). Then, the third bit "1" may be stored at the third word line (e.g., WL 3). And the most significant bit "0" may be stored at the fourth word line (e.g., WL 4). The second multiplicand 206b, having the instance decimal number "10", is represented in binary as "1010". The least significant bit "0" can be stored at the first word line (e.g., WL 1). The second bit "1" can be stored at the second word line (e.g., WL 2). Then, the third bit "0" can be stored at the third word line (e.g., WL 3). And the most significant bit "1" can be stored at the fourth word line (e.g., WL 4). Therefore, the multiplicands 206a and 206b are stored in a bit-serial configuration.

[0030] The multiplier 203 may be stored in the memory array 103 of the memory device 100, the buffer memory 112 of the memory device, or some other source. Figure 2A The controller 109 demonstrates the application of multiplication 203, which has the instance decimal number "6" (represented as the binary number "0110"), to the sum of the multiplicands 206a and 206b.

[0031] Memory device 100 may include a sense amplifier (SA) array 212. The sense amplifier array 212 may include multiple sense amplifiers (e.g., SA 1, SA 2). In some embodiments, each sense amplifier is dedicated to a corresponding bit line. For example, each sense amplifier may access only one bit line. Figure 2A In this example, the first sense amplifier (SA1) accesses the first bit line (BL1), and the second sense amplifier (SA2) accesses the second bit line (BL2). Each sense amplifier receives input when the controller 109 activates the bit line coupled to the sense amplifier.

[0032] The sense amplifiers in sense amplifier array 212 are configured to perform a total counting operation when a bit line for the sense amplifier is activated and when one or more word lines are activated. The sense amplifiers are configured to count the number of valid bits (e.g., bits represented as "1" or having a "hi" value) in all memory cells selected by controller 109. For example, the counting can be implemented as a long shift register or chain that matches the size of the sense amplifier array and is integrated therein. In this case, the controller will shift out all bits. Another alternative implementation includes a rolling ripple carry adder. In this embodiment, the rightmost sense amplifier sends its value to the sense amplifier positioned to the left. The current sense amplifier adds the result from the right to the value sensed on the bit line and sends it to the next left sense amplifier. This continues until the final value is transmitted to the controller. In this embodiment, gradually increasing the bus width towards the controller will provide more bandwidth for the rolling value. Another embodiment includes using a logarithmically reduced tree counter / adder. This embodiment performs relatively fast calculations; however, it may require relatively more wiring to connect various components. In another embodiment, the sense amplifier array may include a thermometer-to-binary converter with bypass capability. In this embodiment, the sense amplifier with a current value of zero (sensed from the bit line) is bypassed. This may also include the use of a lookup table. In yet another embodiment, the sense amplifier array 212 includes a flash analog-to-digital converter (ADC).

[0033] Figure 2A An example is depicted where the bit positions of multiplicands 206a and 206b are stored along the same word line. That is, the least significant bit of each multiplicand 206a and 206b is stored on the same word line, the most significant bit of each multiplicand 206a and 206b is stored on the same word line, and this also applies to the bits in between. In other embodiments, multiplicands 206a and 206b may be stored along different word line ranges or partially overlapping word line ranges.

[0034] Figure 2B This means using the multiplicands 206a and 206b, which are added together and multiplied by the multiplier 203, to perform the operation. Figure 2A Examples of multiplication operations. Specifically, Figure 2B The diagram illustrates four sequences of multiplication performed using a total counting operation by sorting the bits of multiplier 203. Memory device 100 may include one or more registers, such as a result register 215 and an operand register 224. The result register 215 may store a sum value 221, which is updated at each sequence until the multiplication operation is complete. The sum value 221, after sorting all the bits of the multiplier, represents the multiplication result 233 upon completion. The bit positions of the sum value are incremented at each sequence, where the controller selectively performs an accumulation operation based on the bit positions of multiplier 203. This is explained in more detail below.

[0035] In the first sequence 250, the bit positions of the multiplier start from position 1, which is the least significant bit of the multiplier 203. For example... Figure 2B As shown, arrows are used to illustrate the tracking of the bit position of multiplier 203. Controller 109 is configured to activate the word line and send control signals to accumulator 106 and sense amplifier array 212. Controller 109 reads the value of multiplier 203 at position 1, which is a binary bit "0" (e.g., the least significant bit of binary number "0110" or decimal number "6"). When the value is a predetermined value, such as binary "0" or "low", controller 109 records "0" at the current bit position (position 1 of the first sequence 250) in result register 215. The bit position is then incremented to position 2.

[0036] In the second sequence 251, the bit position of the multiplier 203 is at position 2, which is a binary bit "1" (e.g., the second bit from the least significant bit of the binary number "0110" or the decimal number "6"). If the value is a predetermined value, such as a binary "0" or "low", then the controller 109 records "0" at the current bit position in the result register 215, as in the case of the first sequence 250. However, since the bit value of the multiplier 203 at position 2 is a binary "1", the controller performs an initialization operation on the operand register 224 to store the overall count results 227, 230. For example, the initialization operation occurs the first time a binary "1" appears. The initialization operation includes performing an overall count operation on the multiplicands 206a, 206b to generate an overall count result 227, where each number in the overall count result represents the number of "hi" or "1" bits in each memory row or a portion of its stored multiplicands (alternatively, this can be any predetermined selected value). The overall count result can be stored as a flattened binary number 230 in the operand register 224. The overall count results 227 and 230 can be retained in the operand register 224 until the multiplication operation is completed. In response to the presence of a binary "1" at the bit position of the multiplier 203, the overall count operation can be performed only once.

[0037] To perform the overall counting operation, the controller 109 sequentially activates the word lines of the memory array 103 storing the multiplicands 206a and 206b to count the number of binary "1"s present at each location in the multiplicands 206a and 206b. For example, refer to Figure 2AController 109 activates BL 1 and BL 2 to perform a total counting operation on the multiplicands 206a and 206b stored along these bit lines. Controller 109 activates WL 1 to perform a first total counting operation. With BL 1, BL 2, and WL 1 activated, the sense amplifier array 212 counts the total number of binary "1"s. Specifically, (BL 1, WL 1) has binary "1"s, while (BL 2, WL 1) does not have binary "1"s. Therefore, the total counting operation on the least significant bit of the multiplicand will produce a binary "1".

[0038] Next, WL 2 is activated for the next bit position of the multiplicands 206a and 206b. The overall counting operation produces two binary "1s". Next, WL 3 is activated for the next bit position of the multiplicands 206a and 206b. The overall counting operation produces one binary "1". Finally, WL 4 is activated for the next bit position of the multiplicands 206a and 206b. The overall counting operation produces one binary "1". After sorting all word lines of the multiplicands 206a and 206b, the overall count result 227 is [1,1,2,1] ranging from the most significant bit to the least significant bit. Therefore, the overall count result counts the number of binary "1s" (e.g., a predetermined value) at each bit position across one or more multiplicands 206a and 206b. The overall count result 227 can be flattened into the binary number 230, where MSB => [1,1,2,1] <= LSB equals the binary number "10001". To flatten the result, the flattening operation involves right-to-left binary summation and carry propagation. For example, starting from LSB to MSB (right-to-left), the flattening of the array [1,1,2,1] is performed as follows: the value "1" produces a result of "1" in the first position, and the value "0" is carried over to the next position. Next, the value "2" with a carry-in "0" produces a result of "0" in the second position, and the value "1" is carried over to the next position. Next, the value "1" with a carry-in "1" produces a result of "0" in the third position, and the value "1" is carried over to the next position. The value "1" with a carry-in "1" produces a result of "0" in the fourth position, and the value "1" is carried over to the next position. The value "0" with a carry-in "1" produces a result of "1" in the fifth position, and the value "0" is carried over. Each step in this calculation sequence can be performed immediately as the overall count result is generated from each row. In some embodiments, the flattening operation can be performed entirely in the context of memory accesses that occur during the overall counting operation of each memory line. Therefore, this flattening operation may have no latency overhead.

[0039] After generating the overall count results 227 and 230, the operand register 224 is initialized. A flag can be set to indicate that the overall count operation does not need to be performed again for immediate multiplication operations. In addition to detecting a binary "1" at position 2 of the multiplier 203, the controller 109 also performs an accumulation operation at position 2, where the current sum 221 is added to the overall count results 227 and 230 at the current bit position. This produces the current sum "100010". For example, if a binary "0" is recorded at position 1, the accumulation operation will start from position 2 (i.e., the current position) and add the overall count result "10001".

[0040] In the third sequence 252, the bit position of the multiplier 203 is at position 3, which is a binary bit "1" (e.g., the third bit from the least significant bit of the binary number "0110" or the decimal number "6"). In response to the detection of the binary "1", the controller performs an accumulation operation starting from position 3 using the current sum value 221 (i.e., "100010"). Specifically, the result register 215 is updated such that the new sum value is the sum of "100010" and the overall count result 230, i.e., "10001", but the sum occurs at position 3 of the result register 215. In other words, the accumulation operation can be expressed as the binary sum of "100010" and "1000100". This produces the result of the current sum value 221 as "1100110". After the operand register is initialized, it is not necessary to recalculate the overall count result 230.

[0041] In the fourth sequence 253, the bit position of the multiplier 203 is at position 4, which is a binary bit "0" (e.g., the most significant bit of the binary number "0110" or the decimal number "6"). In response to the detection of a binary "0" (e.g., a predetermined binary value), the controller 109 bypasses the accumulation operation. Because all bit positions are sorted, the current sum 233 is the result of multiplying "1100110", which is expressed as the decimal number "102", and is also the result of multiplying 6 x (7 + 10).

[0042] about Figure 2A and 2BThe described multiplication process example demonstrates how multiple total counting operations can be used to apply a common multiplier 203 to the sum of multiplicands 206a and 206b. For example, total counting operations are performed on multiplicands 206a and 206b to generate a total count result 230 representing the sum of multiplicands 206a and 206b. This sum of multiplicands 206a and 206b is stored in operand register 224. When controller 109 sorts the bit positions of common multiplier 203 (from least significant bit to most significant bit), the total count result 230 is selectively accumulated based on the current bit position and whether the bit value at the current bit position is a predetermined value (e.g., binary "1"). In other words, when the multiplier bit positions are sorted and accumulation is performed at the current bit position of the current sum value 221, controller 109 may selectively accumulate the current sum value 221 in result register 215 when a binary "1" is detected.

[0043] To further explain Figure 2A and 2B An example is shown where at least one augend is stored in the memory array 103 of the memory device 100. The augend may be multiplicands 206a, 206b that are added together and then multiplied by multiplier 203. Accumulator 106 may perform a fused multiplication accumulation operation to multiply multiplier 203 by an overall count result 230 determined using (some) augends as input. The fused multiplication accumulation operation may involve selectively accumulating the current sum 221 and the overall count result 230 by sorting at least one bit of multiplier 203. The fused multiplication accumulation result is generated when the bits of multiplier 203 are sorted.

[0044] Selective accumulation may involve accumulating when a first predetermined value (e.g., binary "1") is detected at the current bit position of multiplier 203, and not accumulating (e.g., bypassing the accumulation operation) when a second predetermined value (e.g., binary "0") is detected at the current bit position of multiplier 203. Selective accumulation latency can be smaller compared to the time spent performing overall counting calculations via a sense amplifier, since the latter can be performed in a local fast register, while the former can be performed as part of a memory array access, which typically has a longer latency. Therefore, to speed up multiple operations in memory, embodiments may involve performing overall counting operations on rows of other memory arrays and storing other multipliers while performing selective accumulation on the current overall counting result. In this regard, additional operand registers may be included for storing and / or flattening the next overall counting result when it arrives from the SA array. In another embodiment, a selective accumulator with multiple operand registers may act as multiple arrays such that their operations are completely hidden from memory accesses of the memory array performing the overall counting operation.

[0045] Figure 3This is a flowchart illustrating the functionality of a memory device that performs in-memory multiplication using a total counting operation according to various embodiments. The blocks in the flowchart may represent microcode, machine code, firmware, or other software executable by the controller of memory device 100. The blocks in the flowchart may alternatively represent steps in method 300, which may be executed by memory device 100.

[0046] In item 303, memory device 100 may store one or more multiplicands 206a, 206b in one or more memory arrays. The multiplicands 206a, 206b may be stored in a bit-serial configuration along separate bit lines. The bit positions of each multiplicand 206a, 206b may be located on the same word line or on different word lines.

[0047] In item 306, memory device 100 identifies the current bit position of multiplier 203. The memory device may start from the least significant bit of multiplier 203 (e.g., bit 1). The current bit position may be tracked and stored in memory such as buffer memory 112. When a multiplication operation begins, the bit position starts from bit 1 and then increments through each bit position of multiplier 203 until the most significant bit of the multiplier is disposed of.

[0048] In item 309, memory device 100 checks the value of multiplier 203 at the current bit position to determine if it is a first predetermined value (e.g., binary "1" or "hi") or a second predetermined value (e.g., binary "0" or "low"). If the value is the second predetermined value (e.g., binary "0" or "low"), then in item 312, memory device 100 records a binary "0" at the current bit position in result register 215. Result register 215 stores the current sum value 221, which is updated until the multiplication operation is complete. Afterward, in item 315, memory device 100 moves to the next bit position of multiplier 203. This completes the processing of a sequence of bit positions.

[0049] If the current bit of multiplier 203 is a first predetermined value (e.g., binary "1" or "hi"), then memory device 100 checks at 318 whether to calculate the overall count result 330. If not, then at 321, memory device 100 performs an overall count operation on multiplicands 206a, 206b. For example, memory device 100 may activate the bit lines and word lines of the memory cells storing multiplicands 206a, 206b, and then use sense amplifier array 212 to count the number of binary "1"s.

[0050] The total count result 227 can be flattened into a binary number representing the total count result 230. Mathematically, the total count result 230 represents the sum of the multiplicands (e.g., treated as an addend).

[0051] In item 324, the overall count result 230 is stored in operand register 224. A flag indicating that operand register 224 contains the overall count result 230 can be set.

[0052] In item 327, the memory device accumulates the current sum based on the overall count 230 result and the current bit position of the multiplier 203. Since the accumulation operation is performed based on whether the value corresponds to the current bit of the multiplier 203, the accumulation operation is selective. For example, when sorting the bit positions of the multiplier 203, the accumulation operation is selectively performed in response to the detection of a binary "1". Additionally, the overall count result 230 is added to the current sum at the current bit position. The memory device 100 then proceeds to item 315. If all bit positions of the multiplier have been processed, the multiplication process ends, and the current sum is the multiplication result.

[0053] Figures 4A to 4E This is a diagram of a memory device that performs in-memory multiplication with different multipliers using total counting operations according to various embodiments. Figure 4A This section describes an example of performing a multiplication operation using multiple multipliers 402a and 402b and their corresponding multiplicands 405a and 405b. For example, Figure 4A The memory device 100 describes multiplying a first multiplier 402a by a first multiplicand 405a, and adding the result to a multiplication of a second multiplier 402b and a second multiplicand 405b. Figure 4A In the example described, the first multiplier 402a has the value of decimal "6", the first multiplicand 405a has the value of decimal "9", the second multiplier 402b has the value of decimal "10", and the second multiplicand 405b has the value of decimal "13". Therefore, Figure 4A Examples are described in which different multipliers 402a and 402b are applied to corresponding multiplicands 405a and 405b. However, any number of multipliers and multiplicands may be included as... Figure 4A The multiplication operation is shown in the diagram. Depending on the context, the terms "multiplier" and "multiplicand" are interchangeable. For example, the multiplicand 405 can be used as the multiplier, and the multiplier 402 can be used as the multiplicand.

[0054] Figure 4AThe different operands of a multiplication operation are shown (e.g., multipliers 402a and 402b, and multiplicands 405a and 405b), where the operands are stored in a bit-serial configuration, and the bit positions of each operand share the same word line. For example, starting from the least significant bit of the operand, the bits of the operand are stored along the first word line (WL 1) and extend to the fourth word line (WL 4). The first multiplier 402a is stored along the first bit line (BL 1), the first multiplicand 405a is stored along the second bit line (BL 2), the second multiplier 402b is stored along the third bit line (BL 3), and the second multiplicand 405b is stored along the fourth bit line (BL 4).

[0055] Figure 4A An example is depicted in which multipliers 402a and 402b are stored along odd-numbered bit lines, and multiplicands 405a and 405b are stored along even-numbered bit lines. In this respect, the bit lines may alternate between storing multipliers 402a and 402b and storing multiplicands 405a and 405b.

[0056] Additionally, the memory device 100 can be configured such that consecutive bit line pairs are coupled to the same sense amplifier. For example, BL 1 and BL 2 are coupled to a first sense amplifier SA 1, and BL 3 and BL 4 are coupled to a second sense amplifier SA 2. In this respect, the bit lines storing the multiplier and the corresponding multiplicand are coupled to the same sense amplifier.

[0057] Figure 4A The multiplication operation illustrated in the example can represent a dot product calculation that produces a dot product result. For example, the multiplier may come from a first matrix, and the multiplicand may come from a second matrix. The dot product calculation is used to multiply the first matrix and the second matrix to produce a dot product result. The dot product calculation can be used as the median of a feature map used in a convolutional neural network. For example, one matrix may include a convolutional filter, while another matrix may include a portion of the data undergoing feature detection using the convolutional filter.

[0058] although Figure 4A Some embodiments are described for configuring memory devices to perform multiplication operations using multiple multipliers 402a, 402b and multiplicands 405a, 405b, but other arrangements are within the scope of this disclosure. For example, in Figure 4AThe operands used in the multiplication operation can be stored on different bit lines of the same memory array 103 or on bit lines of different memory arrays 103. For example, the first multiplier 402a and the second multiplier 402b can be stored in the first memory array 103, while the second multiplicand 405a and the second multiplicand 405b can be stored in the second memory array 103. The bit lines from the first and second memory arrays can be coupled to the same sense amplifier. As another example, the multipliers 402a and 402b can be stored along the first bit line, while the multiplicands 405a and 405b can be stored along the second bit line. As another example, the multipliers 402a and 405a can be stored along the first bit line, while the multipliers 402a and 405b can be stored along the second bit line. In addition, in some embodiments, the multipliers 402a and 402b can be received by the controller 109 from a memory outside the memory array 103. For example, multipliers 402a and 402b may be stored in buffer memory 112 or received from an external source via system link 115. In another embodiment, each sense amplifier may have its own local register to store its multiplier (or multiplicand), and the corresponding multiplicand (or multiplier) may be accessed from a memory array.

[0059] Figures 4B to 4E This is established by demonstrating the multiplication operation when sorting each bit position of the multipliers 402a and 402b. Figure 4A On the example of. Figure 4B The multiplication operation is demonstrated at bit positions 1 of multipliers 402a and 402b. Controller 109 activates the bit lines storing multipliers 402a and 402b. In this case, the first multiplier 402a is stored along BL 1, and the second multiplier 402b is stored along BL 3. Figure 4B The activation of these bit lines is illustrated by arrows along BL 1 and BL 3. Controller 109 also selects a word line corresponding to position 1 of multipliers 402a and 402b; in this example, the word line is WL 1. Activation of WL 1 is shown by an arrow at this word line. The first sense amplifier SA 1 detects binary "0", and the second sense amplifier SA 2 also detects binary "0". When only binary "0" is detected at its current bit position for all multipliers, controller 109 records binary "0" at current bit position 429 as the current sum value 426 of result register 423. Based on the presence of only binary "0" at a specific bit position, the controller bypasses the overall counting and accumulation operations. Thereafter, the current bit position is incremented by 1 to the next bit position of multipliers 402a and 402b.

[0060] Figure 4C The multiplication operation at bit position 2 of multipliers 402a and 402b is demonstrated. Controller 109 activates the bit lines storing multipliers 402a and 402b, namely bit lines BL1 and BL3. Figure 4C The activation of these bit lines is illustrated by presenting arrows (with the digit 1) along BL 1 and BL 3. The controller 109 then selects the word line corresponding to position 2 of the multipliers 402a, 402b; in this example, the word line is WL 2. Activation of WL 2 is shown by presenting an arrow at this word line. The first sensing amplifier SA 1 detects a binary "1," and the second sensing amplifier SA 2 also detects a binary "1." For each multiplier 402a, 402b having a binary "1" at the current position, the corresponding multiplicand 405a, 405b is identified, and a total counting operation is performed on the identified multiplicands 405a, 405b. For example, since the first multiplier 402a produces a binary "1" at position 2, the bit line of its corresponding multiplicand (e.g., the first multiplicand 405a) is selected. Similarly, since the second multiplier 402b also produces a binary "1" at position 2, the bit line of its corresponding multiplicand (e.g., the second multiplicand 405b) is selected. Figure 4C The activation of these bit lines is illustrated by showing arrows (with the number 2) along BL 2 and BL 4.

[0061] Then, a total count operation is performed on the selected multiplicands 405a and 405b by activating the word lines associated with the selected multiplicands. In this case, the total count operation involves activating WL 1 (which produces a count of two "1"s), activating WL 2 (which produces a count of zero "1"s), activating WL 3 (which produces a count of one "1"), and activating WL 4 (which produces a count of two "1"s). Therefore, the total count result 436 is MSB => [2,1,0,2] <= LSB. Flattening the total count result 436 into a binary number "10110" is the binary version of the total count result stored in the operand register 433. The total count result 439 represents the sum of the selected multiplicands 405a and 405b.

[0062] After generating the overall count result, the controller 109 adds the overall count result 439 to the current sum value 426 stored in the result register 423 to update the current value 426 in the result register 423. Furthermore, the accumulation operation occurs at bit position 2. This produces the current sum value 426 "101100". Thereafter, the current bit position is incremented by 1 to the next bit position of the multipliers 402a and 402b.

[0063] Figure 4D The multiplication operation at bit position 3 of multipliers 402a and 402b is demonstrated. Controller 109 reactivates the bit lines storing multipliers 402a and 402b, namely bit lines BL1 and BL3. Figure 4DThe activation of these bit lines is illustrated by presenting arrows (with the digit 1) along BL 1 and BL 3. The controller 109 then selects the word line corresponding to position 3 of the multipliers 402a and 402b; in this example, the word line is WL 3. Activation of WL 3 is shown by presenting an arrow at this word line. The first sense amplifier SA 1 detects a binary "1," and the second sense amplifier SA 2 also detects a binary "0." For each multiplier 402a having a binary "1" at the current position, the corresponding multiplicand 405a is identified, and a total counting operation is performed on the identified multiplicand 405a. For example, since the first multiplier 402a produces a binary "1" at position 3, the bit line of its corresponding multiplicand (e.g., the first multiplicand 405a) is selected. However, since the second multiplier 402b produces a binary "0" at position 3, the bit line of its corresponding multiplicand (e.g., the second multiplicand 405b) is deactivated. Figure 4D The activation of this bit line is illustrated by showing an arrow (with the number 2) along BL 2.

[0064] Then, a total count operation is performed on the selected multiplicand 405a by activating the word lines associated with the selected multiplicand. In this case, the total count operation involves activating WL 1 (which produces a count of one "1"), activating WL 2 (which produces a count of zero "1"), activating WL 3 (which produces a count of zero "1"), and activating WL 4 (which produces a count of one "1"). Therefore, the total count result 436 is [1,0,0,1]. Flattening the total count result 436 into binary produces the number "1001", which is the binary version of the total count result stored in the operand register 433. The total count result 439 represents the sum of the selected multiplicand 405a. When only one multiplicand 405a is selected, the sum equals the value of the multiplicand 405a.

[0065] After generating the overall count result, the controller 109 adds the overall count result 439 to the current sum value 426 stored in the result register 423 to update the current value 426 in the result register 423. Furthermore, the accumulation operation occurs at bit position 3. This produces the current sum value 426 "1010000". Thereafter, the current bit position is incremented by 1 to the next bit position of the multipliers 402a and 402b.

[0066] Figure 4E The multiplication operation at bit position 4 of multipliers 402a and 402b is demonstrated. Controller 109 reactivates the bit lines storing multipliers 402a and 402b, namely bit lines BL1 and BL3. Figure 4EThe activation of these bit lines is illustrated by presenting arrows (with the digit 1) along BL 1 and BL 3. The controller 109 then selects the word line corresponding to position 4 of the multipliers 402a and 402b; in this example, the word line is WL 4. Activation of WL 4 is shown by presenting an arrow at this word line. The first sensing amplifier SA 1 detects a binary "0", and the second sensing amplifier SA 2 also detects a binary "1". For each multiplier 402b having a binary "1" at the current position, the corresponding multiplicand 405b is identified, and a total counting operation is performed on the identified multiplicand 405b. For example, since the first multiplier 402a produces a binary "0" at position 4, the bit line of its corresponding multiplicand (e.g., the first multiplicand 405a) is deactivated. Furthermore, since the second multiplier 402b produces a binary "1" at position 4, the bit line of its corresponding multiplicand (e.g., the second multiplicand 405b) is selected. Figure 4D The activation of this bitline is illustrated by showing an arrow (with the number 2) along BL 4.

[0067] Then, a total count operation is performed on the selected multiplicand 405b by activating the word lines associated with the selected multiplicand. In this case, the total count operation involves activating WL 1 (which produces a count of one "1"), activating WL 2 (which produces a count of zero "1"), activating WL 3 (which produces a count of one "1"), and activating WL 4 (which produces a count of one "1"). Therefore, the total count result 436 is [1,0,1,1]MSB => [1,1,0,1] <= LSB. Flattening the total count result 436 into binary produces the number "1101", which is the binary version of the total count result stored in the operand register 433. The total count result 439 represents the sum of the selected multiplicand 405b.

[0068] After generating the overall count result, the controller 109 adds the overall count result 439 to the current sum value 426 stored in the result register 423 to update the current value 426 in the result register 423. Furthermore, the accumulation operation occurs at bit position 4. This produces the current sum value 426 "10111000" (decimal 184). Since the controller sorts all the bit positions of the multiplier from the least significant bit to the most significant bit, the multiplication operation is complete: 184 = 6 x 9 + 10 x 13. The value in the result register 423 represents the multiplication result 445, which can also be a dot product result when the operands represent matrix elements.

[0069] Figure 5This is a flowchart illustrating the functionality of a memory device that performs in-memory multiplication with different multipliers using total counting operations according to various embodiments. The blocks in the flowchart may represent microcode, machine code, firmware, or other software executable by the controller of memory device 100. The blocks in the flowchart may alternatively represent steps in method 500, which may be executed by memory device 100.

[0070] In item 501, memory device 100 may store one or more multiplicands 405a, 405b in one or more memory arrays. In some embodiments, memory device 100 may store multipliers. Multiplicands 405a, 406b may be stored in a bit-serial configuration along separate bit lines. The bit positions of each multiplicand 405a, 406b may be located on the same word line or on different word lines.

[0071] In item 504, memory device 100 identifies the current bit position of multipliers 402a and 402b. Memory device 100 may start from the least significant bit (e.g., bit 1) of multipliers 402a and 402b. The current bit position may be tracked and stored in memory such as buffer memory 112. When a multiplication operation begins, the bit position starts from bit 1 and then increments through each bit position of multipliers 402a and 402b until the most significant bit of the multiplier is disposed of.

[0072] In item 507, memory device 100 checks the value of multipliers 402a and 402b at the current bit position to determine if it is a first predetermined value (e.g., binary "1" or "hi") or a second predetermined value (e.g., binary "0" or "low"). If the value is the second predetermined value (e.g., binary "0" or "low") for all multipliers 402a and 402b, then in item 510, memory device 100 records a binary "0" at the current bit position in result register 423. Result register 423 stores the current sum value 426, which is updated until the multiplication operation is complete. Afterward, in item 513, memory device 100 moves to the next bit position of multipliers 402a and 402b. This completes the disposal of a sequence of bit positions.

[0073] If any current bit of multipliers 402a, 402b is equal to a first predetermined value (e.g., binary "1" or "hi"), then at 516, memory device 100 selects multiplicands 405a, 405b corresponding to multipliers having a binary "1" or "hi" value at the current bit position. Controller 109 may select the bit line associated with the cell storing the selected multiplicands 405a, 405b.

[0074] In item 519, memory device 100 performs a total counting operation on the selected multiplicands 405a, 405b. For example, memory device 100 may activate the bit lines and word lines of the memory cells storing the multiplicands 405a, 406b, and then use sense amplifier array 212 to count the number of binary "1"s.

[0075] The total count result 227 can be flattened into a binary number representing the total count result 439. Mathematically, the total count result 439 represents the sum of the selected multiplicands (e.g., treated as an addend).

[0076] In item 522, the total count result 439 is stored in operand register 433.

[0077] In item 525, memory device 100 accumulates the current sum based on the overall count result 439 and the current bit positions of multipliers 405a and 405b. Since the accumulation operation is performed based on whether any value corresponds to the current bit of multipliers 402a and 402b, the accumulation operation is selective. For example, when sorting the bit positions of either multiplier 402a or 402b, the accumulation operation is selectively performed in response to the detection of a binary "1". Additionally, the overall count result 439 is added to the current sum at the current bit position. Memory device 100 then proceeds to item 513. If all bit positions of the multipliers have been processed, the multiplication process ends, and the current sum is the multiplication result. The accumulation operation can be performed simultaneously with the current bit position when accessing the next multiplier and / or performing the overall count operation.

[0078] Figure 6 This describes an example networking system 600 including a memory device 100 according to some embodiments of the present disclosure. Figure 6 This section describes an example of a computing device 602, which is part of a networking system 600. Figure 6 This demonstrates how such computing devices can be integrated into various machines, devices, and systems, such as IoT (Internet of Things) devices, mobile devices, communication network devices and equipment (e.g., see base station 630), appliances (e.g., see appliance 640), and vehicles (e.g., see vehicle 650).

[0079] The computing device 602 and other computing devices (e.g., see computing devices 622a, 622b, 622c, and 622d) of the networking system 600 are communicatively coupled to one or more communication networks 620. The computing device 602 includes, for example, a bus 606, a controller 608 (e.g., a CPU), other memory 610, a network interface 612, a storage system 614, other components 616 (e.g., any type of component found in mobile or computing devices, GPS components, input / output (I / O) components, various types of user interface components, sensors, cameras, etc.), and memory device 100. Other components 616 may also include one or more user interfaces (e.g., GUI, auditory user interface, haptic user interface, etc.), a display, different types of sensors, haptic, audio, and / or visual input / output devices, additional dedicated memory, one or more additional controllers (e.g., a GPU), or any combination thereof. Bus 606 communicatively couples controller 608, other memory 610, network interface 612, data storage system 614, and other components 616, and in some embodiments, such components may be coupled to memory device 100. For example, system link 115 of memory device 100 may be coupled to bus 606.

[0080] The computing device 602 includes a computer system that includes at least a controller 608, other memories 610 (e.g., random access memory (RAM), read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (e.g., synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM)), static random access memory (SRAM), crosspoint or cross-switch memory, cross-switch memory, etc.), a memory device 100, and a data storage system 614, which can communicate with each other via a bus 606 (which may include multiple buses). In some embodiments, the memory device 100 may not communicate via the bus 606.

[0081] in other words, Figure 6 The block diagram includes a computing device 602 having a computer system operable therein according to embodiments of the present disclosure. In some embodiments, the computer system may include a set of instructions for causing the machine to perform the methods discussed herein when executed. In such embodiments, the machine may be connected (e.g., networked via network interface 612) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet (e.g., see network 620). The machine may operate as a server or client machine in a client-server network environment, as a peer-to-peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0082] Controller 608 represents one or more general-purpose processing devices, such as microprocessors, central processing units, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a single instruction multiple data (SIMD) microprocessor, a multiple instruction multiple data (MIMD) microprocessor, or a processor implementing other instruction sets, or multiple processors implementing combinations of instruction sets. Controller 608 may also be one or more special-purpose processing devices, such as ASICs, programmable logic (e.g., FPGAs), digital signal processors (DSPs), network processors, or the like. Controller 608 is configured to execute instructions for performing the operations and steps discussed herein. Controller 608 may further include network interface means, such as network interface 612, for communication via one or more communication networks (e.g., network 620).

[0083] Data storage system 614 may include a machine-readable storage medium (also referred to as computer-readable medium) on which one or more sets of instructions or software embodying any or more of the methods or functions described herein are stored. Data storage system 614 may have executable capability, for example, it is capable of at least partially executing instructions residing in the data storage system. Instructions may also reside wholly or at least partially in at least one of another memory 610 and memory device 100 and / or in controller 608 during execution by a computer system, the other memory 610 and at least one of memory device 100 and controller 608 also constituting machine-readable storage medium. Another memory 610 may be or include the main memory or system memory of computing device 602. Another memory 610 and memory device 100 may have executable capability, for example, it is capable of at least partially executing instructions residing in any memory of computing device 602.

[0084] As mentioned, the networking system 600 includes computing devices, and each computing device may include one or more buses, controllers, memory, network interfaces, storage systems, and other components. Furthermore, Figure 6Each of the computing devices shown and described herein may include or be part of a mobile device, such as a smartphone, tablet computer, IoT device, smart TV, smartwatch, glasses or other smart home appliance, in-vehicle infotainment system, wearable smart device, game console, PC, digital camera, or any combination thereof. As shown, the computing device may connect to network 620, which may include, for example, a local device network such as Bluetooth or the like, a wide area network (WAN), a local area network (LAN), an intranet, a mobile wireless network such as 4G or 5G, an extranet, the Internet, and / or any combination thereof. In some embodiments, as shown with connection 619, memory device 100 may include at least one network interface so that it can communicate independently with other devices via communication network 620. For example, system link 115 may be coupled to communication network 620. In this respect, a memory module or memory module system of memory device 100 may have its own network interface, allowing this component to communicate independently with other devices via communication network 620.

[0085] Each of the computing devices described herein may be or be replaced by: a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network appliance, a server, a network router, a switch or bridge, or any machine capable of (sequentially or otherwise) executing a set of instructions specifying actions to be taken by the machine.

[0086] Moreover, although targeting Figure 6 The computing device 602 shown herein illustrates a single machine; however, the term "machine" should also be considered to include any collection of machines that individually or jointly execute a set (or more sets) of instructions to perform one or more of the methods or operations discussed herein. Furthermore, each of the illustrated computing devices and computing systems may each include at least a bus and / or motherboard, one or more controllers (e.g., one or more CPUs), main memory that may include temporary data storage devices, at least one type of network interface, a storage system that may include permanent data storage devices, and / or any combination thereof. In some multi-device embodiments, one device may perform some parts of the methods described herein and then send the completed results via a network to another device, allowing the other device to continue performing other steps of the methods described herein.

[0087] Although the memory, controller, and data storage sections are shown as single sections, each section should contain one or more sections capable of storing instructions and performing their respective operations. The term "machine-readable storage medium" should also be considered to include any medium capable of storing or encoding a set of instructions for machine execution and causing the machine to perform any or more of the methods of this disclosure. Therefore, the term "machine-readable storage medium" should be considered to include (but is not limited to) solid-state memory, optical media, and magnetic media.

[0088] Unless otherwise specifically stated, disjunctive language such as the phrase “at least one of X, Y, or Z” is understood in the context to generally represent items, terms, etc., that can be X, Y, or Z or any combination thereof (e.g., X, Y, and / or Z). Therefore, this disjunctive language generally does not intend and should not imply that some embodiments require the existence of at least one X, at least one Y, or at least one Z.

[0089] Certain portions of the foregoing detailed description have been presented based on algorithms and symbolic representations of operations on data bits within computer memory. These algorithmic descriptions and representations are the most effective way for those skilled in the art of data processing to communicate the essence of their work to others skilled in the art. Here, an algorithm is generally considered as a self-consistent sequence of operations that leads to a desired result. These operations are those that require physical manipulation of physical quantities. Typically, but not necessarily, these quantities take the form of electrical or magnetic signals that can be stored, combined, compared, and otherwise manipulated. It has proven convenient, primarily for general reasons, to sometimes refer to these signals as bits, values, elements, symbols, characters, items, numbers, or the like.

[0090] However, it should be remembered that all these and similar terms should be associated with appropriate physical quantities and are merely convenient labels for application to those quantities. This disclosure may relate to the operation and processes of a computer system or similar electronic computing device that manipulate and transform data representing physical (electronic) quantities in the registers and memories of the computer system into physical quantities similarly represented in the memory or registers of the computer system or other such information storage systems.

[0091] This disclosure also relates to apparatus for performing the operations described herein. Such apparatus may be specifically configured for its intended purpose, or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. This computer program may be stored in a computer-readable storage medium, such as any type of disk, including floppy disks, optical disks, CD-ROMs and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic cards or optical cards, or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0092] The algorithms and displays presented herein are not inherently associated with any particular computer or other device. Various general-purpose systems may be used with the programs taught herein, or it may prove convenient to construct more specialized devices to perform the methods. Structures for various such systems will appear as described below. Furthermore, this disclosure is not intended to refer to any particular programming language. It will be understood that various programming languages ​​can be used to implement the teachings of this disclosure as described herein.

[0093] This disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, the instructions being usable to program a computer system (or other electronic device) to perform processes according to this disclosure. Machine-readable media includes any mechanism (e.g., a computer) for storing information in a machine-readable form. In some embodiments, machine-readable (e.g., computer-readable) media includes machine (e.g., computer) readable storage media, such as read-only memory (“ROM”), random access memory (“RAM”), disk storage media, optical storage media, flash memory components, etc.

[0094] It should be emphasized that the above embodiments of this disclosure are merely possible examples of implementations described to clearly understand the principles of this disclosure. Many variations and modifications can be made to the above embodiments without departing substantially from the spirit and principles of this disclosure. All such modifications and variations are intended to be included within the scope of this disclosure and protected by the appended claims.

Claims

1. A system comprising: At least one memory device; At least one memory array of the memory device; The at least one memory array has a plurality of memory cells, which can be accessed via a plurality of bit lines and a plurality of word lines, wherein at least one is multiplied and stored in the memory array, and the multiplier is stored in the memory device; The at least one memory device is configured to: The sum of the at least one multiplier is generated based on a plurality of total counting operations performed on the at least one multiplier, wherein each of the plurality of total counting operations is configured to determine the total number of high bits in a single word line present in the plurality of word lines; and The multiplication result is generated based on the sum and by sorting the bits of the multiplier.

2. The system according to claim 1, wherein, In response to the multiplier having a first predefined value at the corresponding position, the sum is generated based on the sum of the current sum and the overall count result.

3. The system according to claim 2, wherein, In response to the multiplier having a second predefined value at the corresponding position, the sum is generated based on sorting the positions without accumulation.

4. The system of claim 1, wherein at least one multiplicand is stored along the corresponding bit line.

5. The system of claim 4, wherein the plurality of total counting operations comprises counting the number of bits having a first predefined value for each bit position of the at least one multiplicand.

6. The system of claim 5, wherein the bit positions of the at least one multiplied are stored along the same word line.

7. The system of claim 4, further comprising a plurality of sense amplifiers, wherein each sense amplifier is coupled to a corresponding bit line, wherein the plurality of sense amplifiers are used to perform the plurality of overall counting operations.

8. A system comprising: At least one memory device; At least one memory array of the memory device; The at least one memory array has a plurality of memory cells, which can be accessed via a plurality of bit lines and a plurality of word lines, wherein at least one multiplicand is stored in the memory array, and at least one multiplier corresponding to the at least one multiplicand is stored in at least one bit line among the plurality of bit lines in the memory array. and The memory device is further configured to generate a dot product of the at least one multiplicand and the at least one multiplier based on a plurality of total counting operations performed on the at least one multiplicand, wherein the plurality of total counting operations are performed selectively by sorting the bits of the at least one multiplier.

9. The system according to claim 8, wherein, A set of overall counting operations generates an overall counting result for each bit position of the at least one multiplier.

10. The system of claim 9, wherein each total count result is generated by selectively applying the plurality of total count operations to the at least one multiplicand, and each total count operation includes counting the number of bits having a first value for each bit position of the at least one multiplicand.

11. The system of claim 10, wherein each overall counting result is generated in response to a bit of the at least one multiplier having a first predefined value at a corresponding bit position, and is bypassed in response to a bit of the at least one multiplier having a second predefined value at a corresponding bit position.

12. The system of claim 10, wherein the at least one multiplier is stored along odd-numbered bit lines, and wherein the at least one multiplicand is stored along even-numbered bit lines.

13. The system of claim 10, wherein each pair of consecutive bit lines is coupled to a corresponding sensing amplifier.

14. The system of claim 10, wherein each dot product calculation in the plurality of dot product calculations is generated from a group of multipliers having a corresponding multiplicand.

15. A method comprising: Multiple multiplicands and their corresponding multipliers are stored in a memory device, the memory device comprising multiple memory cells accessible via multiple bit lines and multiple word lines; The dot product is generated by summing the multiplications of each multiplicand and its corresponding multiplier, wherein the dot product is generated by: Sort the positions of the bits in the multiplier; Based on the bit value of the current bit position of the corresponding multiplier, a plurality of total counting operations are selectively applied to the multiplicand to produce at least one total counting result, wherein each of the plurality of total counting operations is performed on a bit of a single word line of the memory device; and Selectively accumulate the at least one overall count result; The dot product result is generated when the sorting is completed.

16. The method of claim 15, wherein the dot product result is generated as a value in a feature map used in a convolutional neural network.

17. The method of claim 15, wherein the multiplier is stored in a first memory array, and wherein the multiplicand is stored in a second memory array different from the first memory array.

18. The method of claim 15, wherein the multiplier is stored along odd-numbered bit lines and the multiplicand is stored along even-numbered bit lines.

19. The method of claim 15, wherein each pair of consecutive bit lines is coupled to a corresponding sensing amplifier.

20. The method of claim 19, wherein the sensing amplifier is used to perform the plurality of total counting operations.

21. A method comprising: At least one addend is stored in a memory array of a memory device, the memory array comprising a plurality of memory cells accessible via a plurality of bit lines and a plurality of word lines; A fused multiplication sum is generated by multiplying the multiplier by the total count of the at least one addend and summing the results. A total count result is generated by applying a plurality of total count operations to the at least one addend, wherein each of the plurality of total count operations is performed only on one bit of each of the at least one addend; and The current sum is selectively accumulated with the overall count result by sorting at least one bit of the multiplier; The fused multiplication accumulation result is generated when at least one bit of the multiplier completes the sorting.

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