Display device

Abstract

A display device according to one embodiment of the present application can include a substrate including a plurality of pixel areas, and a pixel provided for each of the plurality of pixel areas. The pixel can include first and second electrodes extending in a first direction on the substrate and spaced apart from each other in a second direction different from the first direction, a bank pattern disposed between the substrate and the first electrode and between the substrate and the second electrode, located in the same column, and including at least two sub-bank patterns spaced apart from each other, and a plurality of light emitting elements disposed between the first and second electrodes. Here, each of the first and second electrodes can have at least two widths in the second direction along the extending direction.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a display device. BACKGROUND

[0002] As interest in information display and demand for use of portable information media increase, demand for and commercialization of display devices have become the focus. SUMMARY

[0003] TECHNICAL PROBLEM

[0004] An aspect and a feature of an embodiment of the disclosure is to provide a display device having improved light output efficiency by improving the degree of alignment of light emitting elements.

[0005] TECHNICAL SOLUTION

[0006] A display device according to an embodiment of the disclosure can include a substrate including a plurality of pixel regions, and a pixel disposed in each of the plurality of pixel regions. The pixel can include first and second electrodes extending in a first direction on the substrate and spaced apart from each other in a second direction different from the first direction, a bank pattern disposed between the substrate and the first electrode and between the substrate and the second electrode and including at least two sub-bank patterns located in the same column and spaced apart from each other, and a plurality of light emitting elements disposed between the first and second electrodes.

[0007] In an embodiment of the disclosure, each of the first and second electrodes can have at least two widths in the second direction along the extension direction.

[0008] In an embodiment of the disclosure, each of the first and second electrodes can include a first region corresponding to an area between the sub-bank patterns and a second region superimposed with the sub-bank patterns.

[0009] In an embodiment of the disclosure, the first region of each of the first and second electrodes can have at least two widths in the second direction along the extension direction of the first and second electrodes, and the second region of each of the first and second electrodes can have a constant width in the second direction along the extension direction of the first and second electrodes.

[0010] In an embodiment of the disclosure, the first region of each of the first and second electrodes can have a width in the second direction that is less than or equal to a width of the second region of the corresponding electrode.

[0011] In an embodiment of the disclosure, the width of the first region of the first electrode in the second direction and the width of the first region of the second electrode in the second direction can be equal to each other. Also, the width of the second region of the first electrode in the second direction and the width of the second region of the second electrode in the second direction can be equal to each other.

[0012] In an embodiment of the disclosure, the first region of each of the first electrode and the second electrode can include a recessed portion recessed in the second direction such that the width of the first region in the second direction decreases along the extension direction of the corresponding electrode.

[0013] In an embodiment of the disclosure, the recessed portion can include a non-square boundary.

[0014] In an embodiment of the disclosure, the recessed portion can have a polygonal shape or a circular curved surface shape.

[0015] In an embodiment of the disclosure, when viewed in a plan view, the distance between the first electrode and the second electrode in the second direction can have at least two widths along the extension direction of the first electrode and the second electrode.

[0016] In an embodiment of the disclosure, the recessed portion of the first electrode and the recessed portion of the second electrode can face each other.

[0017] In an embodiment of the disclosure, the distance between the first region of the first electrode and the first region of the second electrode in the second direction can be greater than the distance between the second region of the first electrode and the second region of the second electrode in the second direction.

[0018] In an embodiment of the disclosure, two sub-dike patterns adjacent in the first direction can be spaced apart from each other by a distance equal to or greater than the length of each of the light emitting elements in the extension direction of each of the light emitting elements disposed between the first electrode and the second electrode.

[0019] In an embodiment of the disclosure, the sub-dike patterns can be identical to each other.

[0020] In an embodiment of the disclosure, when viewed in a cross-section, the first region and the second region of each of the first electrode and the second electrode can have different surface profiles.

[0021] In an embodiment of the disclosure, the pixel can further include a first contact electrode electrically connecting the first electrode and one of both ends of each of the plurality of light emitting elements, and a second contact electrode electrically connecting the second electrode and the other of both ends of each of the plurality of light emitting elements.

[0022] A display device according to another embodiment of the disclosure can include a substrate including a display area including a plurality of pixel areas and a non-display area surrounding at least one side of the display area, and a pixel disposed in each of the plurality of pixel areas. The pixel can include a pixel circuit layer disposed on the substrate and a display element layer disposed on the pixel circuit layer. Here, the pixel circuit layer can include at least one transistor disposed on the substrate, a power line electrically connected to the transistor, and a protection layer disposed on the power line.

[0023] In an embodiment of the disclosure, the display element layer can include a first electrode and a second electrode extending in a first direction on the protection layer and spaced apart from each other in a second direction different from the first direction, a bank pattern disposed between the protection layer and the first electrode and between the protection layer and the second electrode and including first to third sub-bank patterns arranged along the first direction and located in the same column, a plurality of light emitting elements disposed between the first electrode and the second electrode, a first contact electrode electrically connecting one of both ends of the first electrode and each of the plurality of light emitting elements, and a second contact electrode electrically connecting the other of both ends of the second electrode and each of the plurality of light emitting elements.

[0024] In an embodiment of the disclosure, the first to third sub-bank patterns can be spaced apart from each other, and each of the first and second electrodes can have at least two widths in the second direction along the extension direction.

[0025] Advantageous Effects

[0026] According to an embodiment of the disclosure, a display device having an excellent degree of alignment of light emitting elements can be provided.

[0027] According to an embodiment of the disclosure, by designing the width of a first region of an alignment electrode corresponding to a region in which a sub-bank pattern is spaced apart and the width of a second region of the alignment electrode other than the first region differently, light emitting elements can be densely aligned only in a desired region.

[0028] Effects according to an embodiment of the disclosure are not limited by what is exemplified above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1a is a perspective cross-sectional view schematically showing a light emitting element according to an embodiment of the disclosure.

[0030] Figure 1b is Figure 1a a cross-sectional view of the light emitting element of

[0031] Figure 2ais a perspective cross-sectional view schematically showing a light-emitting element according to another embodiment of the present disclosure.

[0032] Figure 2b is Figure 2a a cross-sectional view of the light-emitting element.

[0033] Figure 3a is a perspective view schematically showing a light-emitting element according to still another embodiment of the present disclosure.

[0034] Figure 3b is Figure 3a a cross-sectional view of the light-emitting element.

[0035] Figure 4a is a perspective view schematically showing a light-emitting element according to still another embodiment of the present disclosure.

[0036] Figure 4b is Figure 4a a cross-sectional view of the light-emitting element.

[0037] Figure 1a is a diagram showing a display device according to an embodiment of the present disclosure, and is a schematic plan view of a display device using any one of the light-emitting elements shown in Figure 1b , Figure 2a , Figure 2b , Figure 3a , Figure 3b , Figure 4a , Figure 4b and Figure 6a to Figure 6e as light-emitting sources.

[0038] Figure 5 is a circuit diagram showing an electrical connection relationship between components included in one pixel shown in Figure 7a .

[0039] Figure 7b and Figure 5 are circuit diagrams showing an electrical connection relationship of components included in one pixel shown in Figure 8 .

[0040] Figure 5 is a plan view schematically showing one pixel from among the pixels shown in Figure 9a .

[0041] Figure 8 is a plan view showing only the first bank pattern and the first to third electrodes of Figure 9b .

[0042] Figure 8 is a plan view of Figure 10a plan view of the first to third sub-dike patterns of the first dike pattern.

[0043] Figure 8 is a cross-sectional view taken along the line I-I' of Figure 11

[0044] Figure 8 is a cross-sectional view taken along the line II-II' of Figure 12

[0045] Figure 8 is a cross-sectional view taken along the line III-III' of Figure 13

[0046] Figure 8 is a cross-sectional view taken along the line IV-IV' of Figure 14

[0047] Figure 13 is a cross-sectional view corresponding to the line IV-IV' of Figure 8 Figure 8

[0048] Figure 6a to Figure 6e is a schematic plan view sequentially showing a method of manufacturing the pixel shown in Figure 7a

[0049] Figure 7b is a schematic cross-sectional view sequentially showing a method of manufacturing the pixel shown in Figure 8

[0050] Figure 6a shows a pixel of Figure 8 according to another embodiment and is a schematic plan view of a partial configuration including only a display element layer. DETAILED DESCRIPTION

[0051] Since the present disclosure can be modified in various ways and has various forms, specific embodiments will be shown in the drawings and will be described in detail in the specification. However, it should be understood that the present disclosure is not intended to be limited to the disclosed specific forms, and the present disclosure includes all modifications, equivalents, and alternatives within the spirit and technical scope of the present disclosure.

[0052] ​​​​​​​​In describing the drawings, like reference numerals are used to describe like components throughout the several views. In the drawings, the sizes of structures are shown exaggerated for clarity of presentation. Terminology of the type, "first" and "second," etc., can be used to describe various components, but the components should not be limited to the terminology. The terminology is only used for the purpose of distinguishing between one component and another component. For example, a first component could be termed a second component, and, similarly, a second component could be termed a first component, without departing from the scope of the present disclosure.

[0053] It is to be understood that the terms "including", "comprising", "having" and the like are used herein to mean that existence of stated features, integers, steps, operations, components, parts, and / or the combination thereof but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, and / or the combination thereof. In addition, in the case where a portion of a layer, film, region, or plate, etc. is referred to as "on" another portion, it not only includes the case where the portion is "directly on" the other portion, but also includes the case where another portion is present between the portion and the other portion. In addition, in the present specification, when a portion of a layer, film, region, or plate, etc. is formed on another portion, the direction of formation is not limited to the upward direction, but includes the case where the portion is formed on a side surface or in the downward direction. Conversely, when a portion of a layer, film, region, or plate, etc. is formed "under" another portion, it not only includes the case where the portion is "directly under" the other portion, but also includes the case where another portion is present between the portion and the other portion.

[0054] In the present application, in the case where a "component" (e.g., "a first component") is operatively or communicatively coupled / bonded to or "connected to" another component (e.g., "a second component"), the case is understood that the component can be directly connected to the other component, or can be connected to the other component through yet another component (e.g., "a third component"). In addition, in the present application, "connected" or "bonded" can include physically and / or electrically connected or bonded.

[0055] Hereinafter, embodiments of the present disclosure and other matters necessary for those skilled in the art to understand the content of the present disclosure will be described in detail with reference to the accompanying drawings. In the following description, singular expressions include plural expressions unless the context clearly indicates otherwise.

[0056] Figure 8 to Figure 14 is a perspective cross-sectional view schematically showing a light emitting element according to an embodiment of the present disclosure, Figure 8 to Figure 14 is Figure 1a to Figure 5 a cross-sectional view of the light emitting element of Figure 6ais a perspective cross-sectional view schematically showing a light emitting element according to another embodiment of the present disclosure, Figure 8 to Figure 14 is Figure 6a to Figure 7b a cross-sectional view of the light emitting element, Figure 6a to Figure 7b is a perspective view schematically showing a light emitting element according to still another embodiment of the present disclosure, Figure 6a to Figure 7b is Figure 6a to Figure 7b a cross-sectional view of the light emitting element, Figure 9b is a perspective view schematically showing a light emitting element according to still another embodiment of the present disclosure, Figure 14 is Figure 12 a cross-sectional view of the light emitting element.

[0057] For convenience, in describing the light emitting element shown in Figure 15a to Figure 15f , Figure 8 , Figure 16a to Figure 16h , Figure 10 , Figure 15a to Figure 15f and Figure 16a to Figure 16h , the light emitting element is shown as being manufactured by an etching method. Figure 8 and Figure 10 , the light emitting element is shown as being manufactured by a growth method. In embodiments of the present disclosure, the type and / or shape of the light emitting element is not limited to the embodiments shown in Figure 15a to Figure 15f , Figure 16a to Figure 16h , Figure 1a to Figure 5 , Figure 8 to Figure 15a , Figure 16a , Figure 1a to Figure 5 , Figure 8 to Figure 14 and Figure 15b .

[0058] First, referring to Figure 16a , Figure 16b , Figure 1a to Figure 5 , Figure 8 to Figure 14 , Figure 15c and Figure 16a to Figure 16c , the light emitting element LD can include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 interposed between the first semiconductor layer 11 and the second semiconductor layer 13. For example, the light emitting element LD can be implemented as a light emitting stack in which the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 are sequentially stacked.

[0059] According to embodiments of the present disclosure, the light emitting element LD can be provided in a shape extending in one direction. When the extending direction of the light emitting element LD is referred to as a length direction, the light emitting element LD can have one end and the other end along the length direction. Any one of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at one end of the light emitting element LD, and the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be provided at the other end of the light emitting element LD.

[0060] The light emitting element LD can be provided in various shapes. For example, the light emitting element LD can have a rod shape, a bar shape, a column shape, or the like that is long in a length direction (i.e., an aspect ratio is greater than 1). In an embodiment of the disclosure, the length L of the light emitting element LD in the length direction can be greater than the diameter D (or the width of a cross section) of the light emitting element LD. The light emitting element LD can include, for example, a light emitting diode (LED) that is manufactured to be extremely small to have a diameter D and / or a length L of about a nanometer to a micrometer. In an embodiment of the disclosure, the size of the light emitting element LD can be changed to comply with a requirement condition (or a design condition) of an illumination device or a self-emission display device.

[0061] The first semiconductor layer 11 can include, for example, at least one n-type semiconductor layer. For example, the first semiconductor layer 11 can include any one semiconductor material from among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and can include an n-type semiconductor layer doped with a first conductive dopant such as Si, Ge, or Sn. However, the material configuring the first semiconductor layer 11 is not limited thereto, and various other materials can configure the first semiconductor layer 11.

[0062] The active layer 12 can be disposed on the first semiconductor layer 11, and can be formed in a single quantum well structure or a multiple quantum well structure. The position of the active layer 12 can be variously changed depending on the type of the light emitting element LD. The active layer 12 can emit light having a wavelength of 400 nm to 900 nm, and can use a double hetero structure. In an embodiment of the disclosure, a cap layer (not shown) doped with a conductive dopant can be formed on and / or under the active layer 12. For example, the cap layer can be formed of an AlGaN layer or an InAlGaN layer. According to an embodiment, a material of AlGaN, InAlGaN, or the like can be used to form the active layer 12, and various other materials can configure the active layer 12.

[0063] When an electric field of a predetermined voltage or higher is applied to both ends of the light emitting element LD, the light emitting element LD emits light while an electron-hole pair recombines in the active layer 12. By controlling the light emission by the light emitting element LD using such a principle, the light emitting element LD can be used as a light source of various light emitting devices such as pixels of a display device.

[0064] The second semiconductor layer 13 can be provided on the active layer 12, and can include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 can include at least one p-type semiconductor layer. For example, the second semiconductor layer 13 can include at least one semiconductor material from among InAlGaN, GaN, AlGaN, InGaN, AlN, and InN, and can include a p-type semiconductor layer doped with a second conductive dopant such as Mg. However, the material configuring the second semiconductor layer 13 is not limited thereto, and various other materials can configure the second semiconductor layer 13.

[0065] In an embodiment of the disclosure, the first semiconductor layer 11 and the second semiconductor layer 13 can have different widths (or thicknesses) from each other in a length direction of the light emitting element LD. For example, along the length direction of the light emitting element LD, the first semiconductor layer 11 can have a relatively wider width (or thicker thickness) than the width (or thickness) of the second semiconductor layer 13. Thus, as shown in FIG. 1A, the active layer 12 of the light emitting element LD can be positioned closer to the upper surface of the second semiconductor layer 13 than to the lower surface of the first semiconductor layer 11. Figure 1a to Figure 5

[0066] According to an embodiment, in addition to the above-described first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13, the light emitting element LD can further include an additional electrode 15 provided on the second semiconductor layer 13. Also, according to another embodiment, as shown in FIG. 1B, the light emitting element LD can further include another additional electrode 16 provided at one end of the first semiconductor layer 11. Figure 8 to Figure 14 Figure 16a to Figure 16d

[0067] The additional electrodes 15 and 16 can be ohmic contact electrodes, but are not limited thereto, and can be Schottky contact electrodes according to an embodiment. The additional electrodes 15 and 16 can include a metal or a metal oxide, for example, chromium (Cr), titanium (Ti), aluminum (Al), gold (Au), nickel (Ni), an oxide or an alloy thereof, and indium tin oxide (ITO), etc. can be used alone or in combination, but the disclosure is not limited thereto.

[0068] The materials included in each of the additional electrodes 15 and 16 can be the same as or different from each other. The additional electrodes 15 and 16 can be substantially transparent or translucent. Thus, light generated by the light emitting element LD can pass through the additional electrodes 15 and 16, and can be emitted to the outside of the light emitting element LD. According to an embodiment, when light generated by the light emitting element LD does not pass through the additional electrodes 15 and 16 and is emitted to the outside of the light emitting element LD through an area other than the two ends of the light emitting element LD, the additional electrodes 15 and 16 can include an opaque metal.

[0069] ​​​In embodiments of the present disclosure, the light emitting element LD can further include an insulating film 14 (or an insulating thin film). However, according to embodiments, the insulating film 14 can be omitted, and the insulating film 14 can be provided to cover only a portion of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13.

[0070] The insulating film 14 can prevent an electrical short that can occur when the active layer 12 comes into contact with a conductive material other than the first semiconductor layer 11 and the second semiconductor layer 13. In addition, by forming the insulating film 14, the lifespan and efficiency of the light emitting element LD can be improved by minimizing surface defects of the light emitting element LD. In addition, when a plurality of light emitting elements LD are closely disposed, the insulating film 14 can prevent an unwanted short that can occur between the light emitting elements LD. When the active layer 12 can prevent a short with an external conductive material, the presence or absence of the insulating film 14 is not limited.

[0071] As shown in Figure 1a to Figure 5 and Figure 8 to Figure 14 , the insulating film 14 can be provided in a form of completely surrounding an outer circumferential surface of a light emitting stack including the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15. For ease of description, a portion of the insulating film 14 is removed in Figure 15d , and the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15 included in the actual light emitting element LD can be surrounded by the insulating film 14.

[0072] In the above-described embodiments, the insulating film 14 completely surrounds the outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, the second semiconductor layer 13, and the additional electrode 15, but the present disclosure is not limited thereto.

[0073] According to embodiments, as shown in Figure 16a to Figure 16e and Figure 1a to Figure 5 , the insulating film 14 can surround the outer circumferential surface of each of the first semiconductor layer 11, the active layer 12, and the second semiconductor layer 13 and can not surround the outer circumferential surface of the additional electrode 15 provided on the second semiconductor layer 13, or can surround only a portion of the outer circumferential surface of the additional electrode 15 and can not surround the remaining portion of the outer circumferential surface of the additional electrode 15. However, the insulating film 14 can expose at least two ends of the light emitting element LD, for example, the insulating film 14 can expose one end of the first semiconductor layer 11 together with the additional electrode 15 provided at one end of the second semiconductor layer 13. In addition, according to embodiments, as shown in Figure 8 to Figure 14 and Figure 15e , when the additional electrodes 15 and 16 are provided at both ends of the light emitting element LD, the insulating film 14 can expose at least one region of each of the additional electrodes 15 and 16. Alternatively, in still another embodiment, the insulating film 14 can not be provided.

[0074] According to an embodiment of the disclosure, the insulating film 14 can include a transparent insulating material. For example, the insulating film 14 can include at least one insulating material selected from the group consisting of silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), aluminum oxide (AlO x ), titanium oxide (TiO x ), etc., but is not limited thereto, and various materials having insulating properties can be used.

[0075] When the insulating film 14 is provided with respect to the light emitting element LD, a short circuit between the active layer 12 and a driving electrode not shown can be prevented. In addition, by forming the insulating film 14, the lifetime and efficiency of the light emitting element LD can be improved by minimizing surface defects of the light emitting element LD. In addition, when a plurality of light emitting elements LD are closely provided, the insulating film 14 can prevent an unwanted short circuit that can occur between the light emitting elements LD.

[0076] The light emitting element LD described above can be used as a light emitting source of various display devices. The light emitting element LD can be manufactured through a surface treatment process. For example, when a plurality of light emitting elements LD are mixed in a fluid solution (or solvent) and are supplied to each pixel area (e.g., an emission area of each pixel or an emission area of each sub-pixel), surface treatment can be performed on each of the light emitting elements LD so that the light emitting elements LD can be uniformly dispersed without being unevenly aggregated in the solution.

[0077] A light emitting device including the light emitting element LD described above can be used in various types of devices such as display devices that require a light source. For example, when a plurality of light emitting elements LD are provided in a pixel area of each pixel of a display panel, the light emitting element LD can be used as a light source of each pixel. However, the application field of the light emitting element LD is not limited to the above-described example. For example, the light emitting element LD can be used in another type of device (such as an illumination device) that requires a light source.

[0078] Next, the light emitting element LD manufactured by a growth method is described with reference to Figure 16a to Figure 16f and Figure 1a to Figure 5 .

[0079] In describing the light emitting element LD manufactured by a growth method, the disclosure is described based on points different from the above-described embodiment, and portions not specifically described in the light emitting element LD manufactured by a growth method follow the above-described embodiment, and the same reference numerals are assigned to components similar and / or identical to those of the above-described embodiment.

[0080] Reference is made to Figure 8 to Figure 14 andFigure 15f A light emitting element LD according to an embodiment of the disclosure can include a first semiconductor layer 11, a second semiconductor layer 13, and an active layer 12 disposed between the first semiconductor layer 11 and the second semiconductor layer 13. According to an embodiment, the light emitting element LD can include a light emitting pattern 10 of a core-shell structure including the first semiconductor layer 11 at the center, the active layer 12 surrounding at least one side of the first semiconductor layer 11, the second semiconductor layer 13 surrounding at least one side of the active layer 12, and the additional electrode 15 surrounding at least one side of the second semiconductor layer 13.

[0081] The light emitting element LD can be disposed in a polygonal horn shape extending in one direction. For example, the light emitting element LD can be disposed in a hexagonal horn shape. When the extending direction of the light emitting element LD is referred to as a length direction, the light emitting element LD can have one end (or a lower end) and the other end (or an upper end) along the length direction. A portion of one of the first semiconductor layer 11 and the second semiconductor layer 13 can be exposed at one end (or a lower end) of the light emitting element LD, and a portion of the other of the first semiconductor layer 11 and the second semiconductor layer 13 can be exposed at the other end (or an upper end) of the light emitting element LD. For example, a portion of the first semiconductor layer 11 can be exposed at one end (or a lower end) of the light emitting element LD, and a portion of the second semiconductor layer 13 can be exposed at the other end (or an upper end) of the light emitting element LD. In this case, when the light emitting element LD is used as a light source of a display device, the exposed portion of the first semiconductor layer 11 can be in contact with one of the driving electrodes driving the light emitting element LD, and the exposed portion of the second semiconductor layer 13 can be in contact with the other driving electrode.

[0082] According to an embodiment, when the light emitting element LD includes the additional electrode 15, a portion of the additional electrode 15 surrounding at least one side of the second semiconductor layer 13 can be exposed at the other end (or an upper end) of the light emitting element LD. In this case, when the light emitting element LD is used as a light source of a display device, the exposed portion of the additional electrode 15 can be in contact with the other driving electrode, and can be electrically connected to the other driving electrode.

[0083] In an embodiment of the disclosure, the first semiconductor layer 11 can be located at the core (i.e., the center (or the middle) of the light emitting element LD). The light emitting element LD can be disposed in a shape corresponding to the shape of the first semiconductor layer 11. For example, when the first semiconductor layer 11 has a hexagonal horn shape, the light emitting element LD and the light emitting pattern 10 can also have a hexagonal horn shape.

[0084] The active layer 12 can be disposed and / or formed in a shape surrounding an outer circumferential surface of the first semiconductor layer 11 in the length direction of the light emitting element LD. Specifically, the active layer 12 can be disposed and / or formed in a shape surrounding a remaining region except for one of the both ends of the first semiconductor layer 11 disposed at the lower side in the length direction of the light emitting element LD.

[0085] The second semiconductor layer 13 can be disposed and / or formed in a shape surrounding the active layer 12 in the length direction of the light emitting element LD, and can include a semiconductor layer of a type different from that of the first semiconductor layer 11. For example, the second semiconductor layer 13 can include at least one p-type semiconductor layer.

[0086] In an embodiment of the disclosure, the light emitting element LD can include an additional electrode 15 surrounding at least one side of the second semiconductor layer 13. The additional electrode 15 can be an ohmic contact electrode or a Schottky contact electrode electrically connected to the second semiconductor layer 13, but is not limited thereto.

[0087] As described above, the light emitting element LD can be configured in a hexagonal horn shape having a shape in which both ends protrude, and can be implemented as a core-shell structure light emitting pattern 10 including the first semiconductor layer 11 disposed at the center thereof, the active layer 12 surrounding the first semiconductor layer 11, the second semiconductor layer 13 surrounding the active layer 12, and the additional electrode 15 surrounding the second semiconductor layer 13. The first semiconductor layer 11 can be disposed at one end (or a lower end) of the light emitting element LD having a hexagonal horn shape, and the additional electrode 15 can be disposed at the other end (or an upper end) of the light emitting element LD.

[0088] In addition, according to an embodiment, the light emitting element LD can further include an insulating film 14 disposed on an outer circumferential surface of the core-shell structure light emitting pattern 10. The insulating film 14 can include a transparent insulating material.

[0089] Figure 16a to Figure 16g is a diagram showing a display device according to an embodiment of the disclosure, and is a schematic plan view of a display device particularly using any one of the light emitting elements shown in Figure 1a to Figure 5 、 Figure 8 to Figure 14 、 Figure 16a to Figure 16h 、 Figure 17a to Figure 17c 、 Figure 8 、 Figure 17a to Figure 17c 、 Figure 1a to Figure 5 and Figure 8 as a light emitting source.

[0090] In Figure 17a to Figure 17cIn the drawings, for convenience, the structure of the display device is briefly shown based on a display area DA in which an image is displayed. However, according to an embodiment, at least one driver (e.g., a scan driver, a data driver, etc.) and / or a plurality of signal lines not shown can also be provided in the display device.

[0091] Referring to Figure 17a , ​ , ​ , ​ , ​ , ​ , ​ , ​ and ​ , the display device according to an embodiment of the disclosure can include a substrate SUB, a plurality of pixels PXL disposed on the substrate SUB and including at least one light emitting element LD, a driver disposed on the substrate SUB and driving the pixels PXL, a line unit connecting the pixels PXL and the driver to each other.

[0092] The display device can be classified into a passive matrix type display device and an active matrix type display device according to a method of driving the light emitting element LD. For example, when the display device is implemented as an active matrix type, each of the pixels PXL can include a driving transistor controlling an amount of current supplied to the light emitting element LD, a switching transistor transmitting a data signal to the driving transistor, etc.

[0093] Recently, an active matrix type display device in which each pixel PXL is selected and lightened in resolution, contrast, and operation speed has become mainstream, but the disclosure is not limited thereto, in which a passive matrix type display device in which lightening is performed for each pixel PXL group can also use components (e.g., a first electrode and a second electrode, etc.) for driving the light emitting element LD.

[0094] The substrate SUB can include a display area DA and a non-display area NDA.

[0095] According to an embodiment, the display area DA can be disposed in a central area of the display device, and the non-display area NDA can be disposed in an edge area of the display device to surround the display area DA. However, the positions of the display area DA and the non-display area NDA are not limited thereto, and the positions of the display area DA and the non-display area NDA can be changed.

[0096] The display area DA can be an area in which the pixels PXL in which an image is displayed are disposed. The non-display area NDA can be an area in which a portion of the driver for driving the pixels PXL and the line unit connecting the pixels PXL and the driver to each other are disposed.

[0097] The display area DA can have various shapes. For example, the display area DA can be set to a polygonal shape of a closed shape including sides formed of straight lines. Also, the display area DA can be set in a circular shape and / or an elliptical shape including sides formed of curved lines. Also, the display area DA can be set in various shapes including sides formed of straight lines and curved lines, such as a semi-circular shape, a semi-elliptical shape, etc.

[0098] The non-display area NDA can be disposed at least one side of the display area DA. In an embodiment of the disclosure, the non-display area NDA can surround a periphery (or an edge) of the display area DA.

[0099] The non-display area NDA can be provided with a line unit connected to the pixel PXL and a driver connected to the line unit and driving the pixel PXL.

[0100] The line unit can electrically connect the driver and the pixel PXL to each other. The line unit can provide a signal to each pixel PXL, and can be a signal line connected to each pixel PXL, for example, a fan-out line connected to a scan line, a data line, an emission control line, etc. Also, the line unit can be a signal line connected to each pixel PXL (for example, a fan-out line connected to a control line, a sensing line, etc.) to compensate for a change in electrical characteristics of each pixel PXL in real time.

[0101] The substrate SUB can include a transparent insulating material, and can transmit light. The substrate SUB can be a rigid substrate or a flexible substrate.

[0102] One area on the substrate SUB can be set as the display area DA in which the pixel PXL is disposed, and the remaining area on the substrate SUB can be set as the non-display area NDA. For example, the substrate SUB can include the display area DA including a pixel area in which each pixel PXL is disposed, and the non-display area NDA disposed around the display area DA.

[0103] Each of the pixels PXL can be disposed in the display area DA on the substrate SUB. In an embodiment of the disclosure, the pixels PXL can be disposed in a stripe or The array structure is arranged in the display area DA, but the disclosure is not limited thereto.

[0104] Each pixel PXL can include at least one light emitting element LD driven by a corresponding scan signal and a data signal. The light emitting element LD can have a size as small as micrometers or nanometers, and can be connected in parallel with an adjacent light emitting element, but the disclosure is not limited thereto. The light emitting element LD can constitute a light source of each pixel PXL.

[0105] Each pixel PXL can include at least one light source driven by a predetermined signal (e.g., a scan signal and a data signal) and / or a predetermined power (e.g., a first driving power source and a second driving power source). For example, each pixel PXL can include at least one ultra-small light emitting element LD having a small size of about a nanometer to a micrometer as shown in each of the embodiments of ​ However, in the embodiments of the disclosure, the type of the light emitting element LD that can be used as the light source of each pixel PXL is not limited thereto.

[0106] In the embodiments of the disclosure, the color, type, number, etc. of the pixel PXL are not particularly limited, for example, the color of light emitted from each pixel PXL can be changed differently.

[0107] The driver can provide the predetermined signal and the predetermined power to each pixel PXL through the line unit, thereby controlling the driving of the pixel PXL.

[0108] The driver can include a scan driver that provides a scan signal to the pixel PXL through a scan line, an emission driver that provides an emission control signal to the pixel PXL through an emission control line, a data driver that provides a data signal to the pixel PXL through a data line, and a timing controller. The timing controller can control the scan driver, the emission driver, and the data driver.

[0109] ​ is a circuit diagram showing an electrical connection relationship between components included in one pixel shown in ​ .

[0110] For example, ​ An electrical connection relationship between components included in a pixel PXL that can be applied to an active type display device is shown according to different embodiments. However, the type of components included in the pixel PXL to which the embodiments of the disclosure can be applied is not limited thereto.

[0111] In ​ , not only the components included in each of the pixels shown in ​ , but also a region in which the components are disposed is referred to as a pixel PXL. According to embodiments, ​ Each pixel PXL shown in ​ may be any one of the pixels PXL included in the display device of , and the pixels PXL can have substantially the same or similar structures to each other.

[0112] ​ Referring to ​ , ​As described above, each light emitting element LD connected in parallel between the first electrode EL1 and the second electrode EL2 to which voltages of different potentials are supplied can constitute an individual effective light source. Such effective light sources can be aggregated to constitute the emission unit EMU of the pixel PXL.

[0113] According to an embodiment, the emission unit EMU can include a plurality of light emitting elements LD connected in parallel between a first power line PL1 to which a voltage of the first driving power source VDD is applied and a second power line PL2 to which a voltage of the second driving power source VSS is applied. For example, the emission unit EMU can include a first electrode EL1 (or "first alignment electrode") connected to the first driving power source VDD via the pixel circuit 144 and the first power line PL1, a second electrode EL2 (or "second alignment electrode") connected to the second driving power source VSS via the second power line PL2, and a plurality of light emitting elements LD connected in parallel in the same direction between the first electrode EL1 and the second electrode EL2. In an embodiment of the disclosure, the first electrode EL1 can be an anode electrode, and the second electrode EL2 can be a cathode electrode.

[0114] In an embodiment of the disclosure, each of the light emitting elements LD included in the emission unit EMU can include a first end connected to the first driving power source VDD through the first electrode EL1 and a second end connected to the second driving power source VSS through the second electrode EL2. The first driving power source VDD and the second driving power source VSS can have different potentials. For example, the first driving power source VDD can be set to a high potential power, and the second driving power source VSS can be set to a low potential power. At this time, during an emission period of the pixel PXL, a potential difference between the first driving power source VDD and the second driving power source VSS can be set to a threshold voltage or higher of the light emitting element LD.

[0115] As described above, each light emitting element LD connected in parallel between the first electrode EL1 and the second electrode EL2 to which voltages of different potentials are supplied in the same direction (e.g., a forward direction) can constitute an individual effective light source. Such effective light sources can be aggregated to constitute the emission unit EMU of the pixel PXL.

[0116] The light emitting elements LD of the emission unit EMU can emit light having a luminance corresponding to a driving current supplied through the corresponding pixel circuit 144. For example, the pixel circuit 144 can supply a driving current corresponding to a gray value of corresponding frame data to the emission unit EMU during each frame period. The driving current supplied to the emission unit EMU can be shunted and flow to the light emitting elements LD. Accordingly, each of the light emitting elements LD can emit light having a luminance corresponding to a current flowing therethrough, and thus the emission unit EMU can emit light having a luminance corresponding to the driving current.

[0117] Meanwhile, ​ An embodiment in which both ends of the light emitting element LD are connected in the same direction between the first driving power source VDD and the second driving power source VSS is shown, but the present disclosure is not limited thereto. According to an embodiment, the emission unit EMU can include at least one inactive light source in addition to the light emitting element LD configuring each active light source. For example, as shown in ​ and ​ At least a reverse light emitting element LDr can also be connected between the first electrode EL1 and the second electrode EL2 of the emission unit EMU, as shown in

[0118] The pixel circuit 144 can be connected to the scan line Si and the data line Dj of the corresponding pixel PXL. For example, when the pixel PXL is disposed in the ith (i is a positive integer) row and the jth (j is a positive integer) column of the display area DA, the pixel circuit 144 of the pixel PXL can be connected to the ith scan line Si and the jth data line Dj of the display area DA. According to an embodiment, as shown in ​ and ​ The pixel circuit 144 can include the first transistor T1 and the second transistor T2 and the storage capacitor Cst, as shown in ​ and ​ The structure of the pixel circuit 144 is not limited to the embodiment shown in

[0119] First, referring to ​ , the pixel circuit 144 can include the first transistor T1 and the second transistor T2 and the storage capacitor Cst.

[0120] The first terminal of the second transistor T2 (or the switching transistor) can be connected to the data line Dj, and the second terminal can be connected to the first node N1. Here, the first terminal and the second terminal of the second transistor T2 can be different terminals, for example, when the first terminal is a source electrode, the second terminal can be a drain electrode. In addition, the gate electrode of the second transistor T2 can be connected to the ith scan line Si.

[0121] The second transistor T2 can be turned on when a scan signal supplying a voltage (e.g., a low voltage) at which the second transistor T2 can be turned on is supplied from the i-th scan line Si, to electrically connect the j-th data line Dj and the first node N1 to each other. At this time, a data signal of a corresponding frame is supplied to the j-th data line Dj, and thus the data signal is transmitted to the first node N1. The data signal transmitted to the first node N1 is charged in the storage capacitor Cst.

[0122] A first terminal of the first transistor T1 (or a driving transistor) can be connected to a first driving power source VDD, and a second terminal can be electrically connected to the first electrode EL1 of the emission unit EMU. A gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls an amount of a driving current supplied to the light emitting element LD in response to a voltage of the first node N1.

[0123] One electrode of the storage capacitor Cst can be connected to the first driving power source VDD, and the other electrode can be connected to the first node N1. The storage capacitor Cst is charged with a voltage corresponding to a data signal supplied to the first node N1 and maintains the charged voltage until a data signal of a next frame is supplied.

[0124] ​ and ​ Each of

[0125] However, the present disclosure is not limited thereto, and the structure of the pixel circuit 144 can be variously modified and implemented. For example, it goes without saying that the pixel circuit 144 can further include other circuit elements such as at least one transistor element (such as a transistor element for compensating for a threshold voltage of the first transistor T1, a transistor element for initializing the first node N1, and / or a transistor element for controlling an emission time of the light emitting element LD) or a boost capacitor for boosting a voltage of the first node N1.

[0126] In addition, in ​ , the transistors (e.g., the first transistor T1 and the second transistor T2) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. That is, at least one of the first transistor T1 and the second transistor T2 included in the pixel circuit 144 can be changed to an N-type transistor.

[0127] Next, with reference to ​ , ​ and ​According to an embodiment of the present disclosure, the first transistor T1 and the second transistor T2 can be implemented as N-type transistors. Except for the change in connection positions of some components due to the change in transistor type, ​ The configuration or operation of the pixel circuit 144 shown in ​ is similar to that of the pixel circuit 144 shown in

[0128] In an embodiment of the present disclosure, ​ The pixel circuit 144 shown in ​ may include the first transistor T1 and the second transistor T2 formed of N-type transistors and the storage capacitor Cst. When the first transistor T1 and the second transistor T2 are formed of N-type transistors, in order to stabilize the storage capacitor Cst charged with a voltage corresponding to a data signal supplied to the first node N1, the emission unit EMU can be connected between the first drive power source VDD and the pixel circuit 144. However, the present disclosure is not limited thereto, and according to an embodiment, ​ The emission unit EMU shown in ​ may be connected between the pixel circuit 144 and the second drive power source VSS. In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to ​ and ​ embodiments shown in

[0129] According to an embodiment, as shown in ​ and ​ The pixel circuit 144 connected to the pixel PXL located in the i-th row and the j-th column can also be connected to at least another scan line. For example, the pixel PXL provided in the i-th row of the display area DA can also be connected to the i-1-th scan line Si-1 and / or the i+1-th scan line Si+1. In addition, according to an embodiment, the pixel circuit 144 can also be connected to a third power source in addition to the first drive power source VDD and the second drive power source VSS. For example, the pixel circuit 144 can also be connected to an initialization power source Vint.

[0130] The pixel circuit 144 can include the first transistor T1 to the seventh transistor T7 and the storage capacitor Cst.

[0131] One electrode (e.g., a source electrode of the first transistor T1 (a driver transistor)) can be connected to the first driving power source VDD via the fifth transistor T5, and the other electrode (e.g., a drain electrode) can be connected to one end of the light emitting element LD via the sixth transistor T6. In addition, a gate electrode of the first transistor T1 can be connected to the first node N1. The first transistor T1 controls a driving current flowing between the first driving power source VDD and the second driving power source VSS via the light emitting element LD in response to a voltage of the first node N1.

[0132] The second transistor T2 (a switching transistor) can be connected between the jth data line Dj connected to the pixel PXL and the source electrode of the first transistor T1. In addition, a gate electrode of the second transistor T2 can be connected to the ith scan line Si connected to the pixel PXL. The second transistor T2 can be turned on when a gate-on voltage (e.g., a low voltage) of a scan signal is supplied from the ith scan line Si, to electrically connect the jth data line Dj to the source electrode of the first transistor T1. Thus, when the second transistor T2 is turned on, a data signal supplied from the jth data line Dj is transmitted to the first transistor T1.

[0133] The third transistor T3 can be connected between the drain electrode of the first transistor T1 and the first node N1. In addition, a gate electrode of the third transistor T3 can be connected to the ith scan line Si. The third transistor T3 can be turned on when a gate-on voltage of a scan signal is supplied from the ith scan line Si, to electrically connect the drain electrode of the first transistor T1 and the first node N1 to each other.

[0134] The fourth transistor T4 can be connected between the first node N1 and an initialization power source line to which a voltage of the initialization power source Vint is applied. In addition, a gate electrode of the fourth transistor T4 can be connected to a previous scan line, e.g., the (i-1)th scan line Si-1. The fourth transistor T4 can be turned on when a gate-on voltage of a scan signal is supplied to the (i-1)th scan line Si-1, to transmit the voltage of the initialization power source Vint to the first node N1. Here, the initialization power source Vint can have a voltage less than or equal to a lowest voltage of the data signal.

[0135] The fifth transistor T5 can be connected between the first driving power source VDD and the first transistor T1. In addition, a gate electrode of the fifth transistor T5 can be connected to a corresponding emission control line, e.g., the ith emission control line Ei. The fifth transistor T5 can be turned off when a gate-off voltage of an emission control signal is supplied to the ith emission control line Ei, and can be turned on in other cases.

[0136] The sixth transistor T6 can be connected between the first transistor T1 and a second node N2 electrically connected to one end of the light emitting element LD. Also, a gate electrode of the sixth transistor T6 can be connected to the i-th emission control line Ei. The sixth transistor T6 can be turned off when the emission control signal of the gate-off voltage is supplied to the i-th emission control line Ei, and can be turned on in other cases.

[0137] The seventh transistor T7 can be connected between one end of the light emitting element LD and the initialization power supply line. Also, a gate electrode of the seventh transistor T7 can be connected to any one of the next scan lines, for example, the i+1-th scan line Si+1. The seventh transistor T7 can be turned on when the scan signal of the gate-on voltage is supplied to the i+1-th scan line Si+1, to supply the voltage of the initialization power supply Vint to one end of the light emitting element LD.

[0138] The storage capacitor Cst can be connected between the first drive power supply VDD and the first node N1. The storage capacitor Cst can store the data signal supplied to the first node N1 and the voltage corresponding to the threshold voltage of the first transistor T1 during each frame period.

[0139] In ​ and ​ , the transistors (for example, the first transistor T1 to the seventh transistor T7) included in the pixel circuit 144 are P-type transistors, but the present disclosure is not limited thereto. For example, at least one of the first transistor T1 to the seventh transistor T7 can be changed to an N-type transistor.

[0140] In an embodiment of the present disclosure, the configuration of the pixel circuit 144 is not limited to the embodiment shown in ​ . For example, the pixel circuit 144 can be configured as in the embodiment shown in ​

[0141] As shown in ​ , the pixel circuit 144 can also be connected to the control line CLi and the sensing line SENj. For example, the pixel circuit 144 of the pixel PXL disposed in the i-th row and the j-th column of the display area DA can be connected to the i-th control line CLi and the j-th sensing line SENj of the display area DA. In addition to the first transistor T1 and the second transistor T2 shown in ​ and ​ , the above-described pixel circuit 144 can further include a third transistor T3.

[0142] ​The third transistor T3 is connected between the first transistor T1 and the jth sensing line SENj. For example, one electrode of the third transistor T3 can be connected to one terminal (e.g., a source electrode) of the first transistor T1 connected to the first electrode EL1, and the other electrode of the third transistor T3 can be connected to the jth sensing line SENj.

[0143] According to an embodiment, the gate electrode of the third transistor T3 is connected to the ith control line CLi. The third transistor T3 can be turned on by a control signal of a gate-on voltage (e.g., a high level) supplied to the ith control line CLi during a predetermined sensing period, to electrically connect the jth sensing line SENj and the first transistor T1 to each other.

[0144] According to an embodiment, the sensing period can be a period for extracting characteristic information (e.g., a threshold voltage of the first transistor T1, etc.) of each of the pixels PXL disposed in the display area DA. During the above-described sensing period, the first transistor T1 can be turned on by supplying a predetermined reference voltage that can turn on the first transistor T1 or connecting each pixel PXL to a current source, etc. to the first node N1 via the jth data line Dj and the second transistor T2. Also, the first transistor T1 can be connected to the jth sensing line SENj by supplying a control signal of a gate-on voltage to the third transistor T3 to turn on the third transistor T3. Accordingly, the characteristic information including the threshold voltage of the first transistor T1, etc. of each pixel PXL can be extracted through the jth sensing line SENj. The extracted characteristic information can be used to convert image data, thereby compensating for characteristic deviation between the pixels PXL.

[0145] Meanwhile, ​ Embodiments in which all of the first transistor T1 to the third transistor T3 are N-type transistors are disclosed, but the present disclosure is not limited thereto. For example, at least one of the above-described first transistor T1 to the third transistor T3 can be changed to a P-type transistor. Also, ​ Embodiments in which the emission unit EMU is connected between the pixel circuit 144 and the second driving power source VSS are disclosed, but the emission unit EMU can also be connected between the first driving power source VDD and the pixel circuit 144.

[0146] Also, ​ Embodiments in which all of the light emitting elements LD configuring each emission unit EMU are connected in parallel are shown, but the present disclosure is not limited thereto. According to an embodiment, the emission unit EMU can be configured to include at least one series stage including a plurality of light emitting elements LD connected in parallel to each other. That is, the emission unit EMU can be configured in a series / parallel hybrid structure. This will be described later with reference to FIG. 6. ​ and ​ This will be described.

[0147] The structure of the pixel PXL that can be applied to the present disclosure is not limited to ​ the embodiment shown in FIG. 1, and a corresponding pixel can have various structures. In addition, in another embodiment of the present disclosure, each pixel PXL can be configured inside a passive type light emitting display device or the like. In this case, the pixel circuit 144 can be omitted, and each of both ends of the light emitting element LD included in the emission unit EMU can be directly connected to each of the scan lines Si-1, Si, and Si+1, the jth data line Dj, the first power supply line PL1 to which a voltage of the first drive power supply VDD is applied, the second power supply line PL2 to which a voltage of the second drive power supply VSS is applied, each of predetermined control lines, and the like.

[0148] ​ and ​ is a circuit diagram showing an electrical connection relationship of components included in one pixel shown in ​

[0149] In ​ and ​ , the emission unit EMU of each pixel PXL can be configured to include a plurality of series stages connected to each other in series. In describing the embodiment of FIGS. 7A and 7B, detailed descriptions of configurations (for example, the pixel circuit 144) similar or identical to those of the embodiment of FIG. 1 are omitted in order to avoid overlapping descriptions. ​

[0150] First, referring to ​ , the emission unit EMU can include a plurality of light emitting elements LD connected to each other in series. For example, the emission unit EMU can include a first light emitting element LD1, a second light emitting element LD2, a third light emitting element LD3, and a fourth light emitting element LD4 connected in series in a forward direction to configure an effective light source between the first drive power supply VDD and the second drive power supply VSS. In the following embodiments, at least one random light emitting element LD from among the first light emitting element LD1 to the fourth light emitting element LD4 or all of the first light emitting element LD1 to the fourth light emitting element LD4 can be referred to as a light emitting element LD or a plurality of light emitting elements LD.

[0151] One end (for example, a second semiconductor layer) of the first light emitting element LD1 can be connected to the first drive power supply VDD through a first electrode EL1, and the other end (for example, a first semiconductor layer) of the first light emitting element LD1 can be connected to one end (for example, a second semiconductor layer) of the second light emitting element LD2 through a first intermediate electrode CTE1 connected between the first series stage and the second series stage.

[0152] ​​One end (e.g., the second semiconductor layer) of the second light emitting element LD2 can be connected to the first intermediate electrode CTE1, and the other end (e.g., the first semiconductor layer) of the second light emitting element LD2 can be connected to one end (e.g., the second semiconductor layer) of the third light emitting element LD3 through the second intermediate electrode CTE2 connected between the second series stage and the third series stage.

[0153] One end of the third light emitting element LD3 can be connected to the second intermediate electrode CTE2, and the other end (e.g., the first semiconductor layer) of the third light emitting element LD3 can be connected to one end (e.g., the second semiconductor layer) of the fourth light emitting element LD4 through the third intermediate electrode CTE3 connected between the third series stage and the fourth series stage.

[0154] One end of the fourth light emitting element LD4 can be connected to the third intermediate electrode CTE3, and the other end (e.g., the first semiconductor layer) of the fourth light emitting element LD4 can be connected to the second driving power source VSS through the second electrode EL2.

[0155] As described above, the first to fourth light emitting elements LD1 to LD4 can be connected in series between the first electrode EL1 and the second electrode EL2 of the emission unit EMU of the pixel PXL.

[0156] In the case of the emission unit EMU of the structure in which the light emitting elements LD are connected in series, the voltage applied between the first electrode EL1 and the second electrode EL2 can increase, and the size of the driving current flowing through the emission unit EMU can decrease, compared to the emission unit EMU of the structure in which the light emitting elements LD are connected in parallel. Accordingly, when the emission unit EMU of each pixel PXL is configured in a series structure, the power consumption of the display device can be reduced.

[0157] According to an embodiment, at least one series stage can be provided in the form including a plurality of light emitting elements LD connected in parallel to each other. In this case, the emission unit EMU of each pixel PXL can be configured in a series / parallel hybrid structure. For example, the emission unit EMU can be configured as shown in FIG. 11. ​

[0158] Next, referring to FIG. 12, a description will be made of an emission unit EMU of a structure in which light emitting elements LD are connected in parallel. ​ ​The emission unit EMU of the pixel PXL can include a plurality of series stages sequentially connected between the first driving power source VDD and the second driving power source VSS. In addition, each series stage can include one or more light emitting elements LD connected in a forward direction between two electrodes of an electrode pair configuring the corresponding series stage. For example, the emission unit EMU can include a first series stage SET1 to a third series stage SET3 sequentially connected between the first driving power source VDD and the second driving power source VSS. The first series stage SET1 to the third series stage SET3 can respectively include two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 of an electrode pair configuring the corresponding series stage, and a plurality of light emitting elements LD connected in parallel between each pair of the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 in a forward direction (e.g., in the same direction).

[0159] The first series stage SET1 can include a first electrode EL1 and a second electrode EL2a from among the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 forming the electrode pair included in the emission unit EMU, and can include at least one first light emitting element LD1 connected between the first electrode EL1 and the second electrode EL2a. For example, the first series stage SET1 can include the first electrode EL1 connected to the first driving power source VDD via the pixel circuit 144, the second electrode connected to the second driving power source VSS, and a plurality of first light emitting elements LD1 connected between the first electrode EL1 and the second electrode EL2a. One end (e.g., a second semiconductor layer) of each first light emitting element LD1 is electrically connected to the first electrode EL1 of the first series stage SET1, and the other end (e.g., a first semiconductor layer) thereof is electrically connected to the second electrode EL2a of the first series stage SET1. The first light emitting elements LD1 can be connected in parallel between the first electrode EL1 and the second electrode EL2a of the first series stage SET1, and can be connected in the same direction (e.g., a forward direction) between the first electrode EL1 and the second electrode EL2a. According to an embodiment, at least one reverse light emitting element (refer to LDr of FIG. 1) can also be connected to the first series stage SET1. The reverse light emitting element LDr can be connected in parallel between the first electrode EL1 and the second electrode EL2a with the first light emitting elements LD1 configuring the effective light source, and can be connected between the first electrode EL1 and the second electrode EL2a in a direction opposite to that of the first light emitting elements LD1. Even if a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode EL1 and the second electrode EL2a, the reverse light emitting element LDr remains in a non-activated state, and thus substantially no current flows through the reverse light emitting element LDr. ​ The first series stage SET1 can include a first electrode EL1 and a second electrode EL2a from among the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 forming the electrode pair included in the emission unit EMU, and can include at least one first light emitting element LD1 connected between the first electrode EL1 and the second electrode EL2a. For example, the first series stage SET1 can include the first electrode EL1 connected to the first driving power source VDD via the pixel circuit 144, the second electrode connected to the second driving power source VSS, and a plurality of first light emitting elements LD1 connected between the first electrode EL1 and the second electrode EL2a. One end (e.g., a second semiconductor layer) of each first light emitting element LD1 is electrically connected to the first electrode EL1 of the first series stage SET1, and the other end (e.g., a first semiconductor layer) thereof is electrically connected to the second electrode EL2a of the first series stage SET1. The first light emitting elements LD1 can be connected in parallel between the first electrode EL1 and the second electrode EL2a of the first series stage SET1, and can be connected in the same direction (e.g., a forward direction) between the first electrode EL1 and the second electrode EL2a. According to an embodiment, at least one reverse light emitting element (refer to LDr of FIG. 1) can also be connected to the first series stage SET1. The reverse light emitting element LDr can be connected in parallel between the first electrode EL1 and the second electrode EL2a with the first light emitting elements LD1 configuring the effective light source, and can be connected between the first electrode EL1 and the second electrode EL2a in a direction opposite to that of the first light emitting elements LD1. Even if a predetermined driving voltage (e.g., a driving voltage in the forward direction) is applied between the first electrode EL1 and the second electrode EL2a, the reverse light emitting element LDr remains in a non-activated state, and thus substantially no current flows through the reverse light emitting element LDr.

[0160] The second series stage SET2 can include the 2bth electrode EL2b and the 3ath electrode EL3a from among the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 forming the electrode pair included in the emission unit EMU, and can include at least one second light emitting element LD2 connected between the 2bth electrode EL2b and the 3ath electrode EL3a. For example, the second series stage SET2 can include the 2bth electrode EL2b connected to the first driving power source VDD via the pixel circuit 144 and the first series stage SET1, the 3ath electrode EL3a connected to the second driving power source VSS, and a plurality of second light emitting elements LD2 connected between the 2bth electrode EL2b and the 3ath electrode EL3a. One end (e.g., a second semiconductor layer) of each of the second light emitting elements LD2 is electrically connected to the 2bth electrode EL2b of the second series stage SET2, and the other end (e.g., a first semiconductor layer) thereof is electrically connected to the 3ath electrode EL3a of the second series stage SET2. The second light emitting elements LD2 can be connected in parallel between the 2bth electrode EL2b and the 3ath electrode EL3a of the second series stage SET2, and can be connected in the same direction (e.g., a forward direction) between the first driving power source VDD and the second driving power source VSS through the 2bth electrode EL2b and the 3ath electrode EL3a. According to an embodiment, at least one reverse light emitting element (refer to LDr of FIG. 1) can also be connected between the 2bth electrode EL2b and the 3ath electrode EL3a. The reverse light emitting element LDr can be connected in parallel with the second light emitting elements LD2 configuring the effective light source between the 2bth electrode EL2b and the 3ath electrode EL3a, and can be connected between the 2bth electrode EL2b and the 3ath electrode EL3a in a direction opposite to that of the second light emitting elements LD2. ​

[0161] In an embodiment of the disclosure, the 2ath electrode EL2a of the first series stage SET1 and the 2bth electrode EL2b of the second series stage SET2 can be integrally provided and connected to each other. That is, the 2ath electrode EL2a of the first series stage SET1 and the 2bth electrode EL2b of the second series stage SET2 can configure the second electrode EL2 electrically connecting the first series stage SET1 and the second series stage SET2 to each other. As described above, when the 2ath electrode EL2a of the first series stage SET1 and the 2bth electrode EL2b of the second series stage SET2 are integrally provided, the 2ath electrode EL2a and the 2bth electrode EL2b can be different regions of the second electrode EL2.

[0162] ​The third series stage SET3 can include the 3rd electrode EL3b and the fourth electrode EL4 from among the two electrodes EL1 and EL2a, EL2b and EL3a, and EL3b and EL4 forming the electrode pair included in the emission unit EMU, and can include at least one third light emitting element LD3 connected between the 3rd electrode EL3b and the fourth electrode EL4. For example, the third series stage SET3 can include the 3rd electrode EL3b connected to the first driving power source VDD, the fourth electrode EL4 connected to the second driving power source VSS, and a plurality of third light emitting elements LD3 connected between the 3rd electrode EL3b and the fourth electrode EL4 via the pixel circuit 144 and the previous series stages (e.g., the first series stage SET1 and the second series stage SET2). One end (e.g., the second semiconductor layer) of each of the third light emitting elements LD3 is electrically connected to the 3rd electrode EL3b of the third series stage SET3, and the other end (e.g., the first semiconductor layer) thereof is electrically connected to the fourth electrode EL4 of the third series stage SET3. The third light emitting elements LD3 can be connected in parallel between the 3rd electrode EL3b and the fourth electrode EL4 of the third series stage SET3, and can be connected in the same direction (e.g., the forward direction) between the first driving power source VDD and the second driving power source VSS through the 3rd electrode EL3b and the fourth electrode EL4. According to an embodiment, at least one reverse light emitting element (refer to LDr of FIG. 1) can also be connected between the 3rd electrode EL3b and the fourth electrode EL4. The reverse light emitting element LDr can be connected in parallel between the 3rd electrode EL3b and the fourth electrode EL4 together with the third light emitting elements LD3 configuring the effective light source, and can be connected between the 3rd electrode EL3b and the fourth electrode EL4 in a direction opposite to that of the third light emitting elements LD3. ​

[0163] In an embodiment of the disclosure, the 3rd electrode EL3b of the second series stage SET2 and the 3rd electrode EL3b of the third series stage SET3 can be integrally provided and connected to each other. That is, the 3rd electrode EL3b of the second series stage SET2 and the 3rd electrode EL3b of the third series stage SET3 can configure the third electrode EL3 electrically connecting the second series stage SET2 and the third series stage SET3 to each other. As described above, when the 3rd electrode EL3b of the second series stage SET2 and the 3rd electrode EL3b of the third series stage SET3 are integrally provided, the 3rd electrode EL3b and the 3rd electrode EL3b can be different regions of the third electrode EL3.

[0164] In the above-described embodiment, the first electrode EL1 of the first series stage SET1 can be an anode electrode of the emission unit EMU of each of the pixels PXL, and the fourth electrode EL4 of the third series stage SET3 can be a cathode electrode of the emission unit EMU.​

[0165] As described above, the emission unit EMU including the pixels PXL of the light emitting elements LD connected in the series / parallel hybrid structure can easily adjust the driving current / voltage conditions according to the product specifications of applications.

[0166] In particular, the emission unit EMU including the pixels PXL of the light emitting elements LD connected in the series / parallel hybrid structure can reduce the driving current compared to the emission unit EMU of the structure in which all of the light emitting elements LD are connected in parallel. In addition, the emission unit EMU including the pixels PXL of the light emitting elements LD connected in the series / parallel hybrid structure can reduce the driving voltage applied across the emission unit EMU compared to the emission unit EMU of the structure in which all of the light emitting elements LD are connected in series. In addition, in the case where all of the light emitting elements LD are connected only in series, when at least one of the series-connected light emitting elements LD is not fully connected in the forward direction (or includes a reverse light emitting element LDr), the driving current can be blocked by the path through which it flows in the pixel PXL, thus possibly causing a dark spot defect. On the other hand, in the case where the light emitting elements LD are connected in the series / parallel hybrid structure, even if some of the light emitting elements LD are not connected in the forward direction (or include a reverse light emitting element LDr) or a defect occurs in some of the light emitting elements LD in each series stage, the driving current can flow through another light emitting element LD of the corresponding series stage. Accordingly, a defect of the pixel PXL can be prevented or reduced.

[0167] ​ is a plan view schematically showing a pixel among the pixels shown in ​ , ​ is a plan view showing only the first bank pattern and the first to third electrodes of ​ , ​ is a plan view according to another embodiment in which the first to third sub-bank patterns of ​ are implemented, ​ is a cross-sectional view taken along line I-I' of ​ , ​ is a cross-sectional view taken along line II-II' of ​ . ​ is a cross-sectional view taken along line III-III' of ​ , ​ is a cross-sectional view taken along line IV-IV' of ​ , ​ is a cross-sectional view corresponding to line IV-IV' of ​ according to another embodiment as an implementation of the first bank pattern shown in ​ .

[0168] ​ The pixel shown in ​ and ​ and ​ The pixel shown in ​ may be the pixel shown in ​ .

[0169] In ​ , for convenience, the illustration of the transistor connected to the light-emitting element and some signal lines connected to the transistor is omitted.

[0170] ​ The structure of one pixel PXL is simplified and illustrated (such as each electrode is illustrated as a single electrode and each insulating layer is illustrated as a single insulating layer), but the present disclosure is not limited thereto.

[0171] In addition, in embodiments of the present disclosure, "formed and / or disposed in the same layer" can mean formed in the same process, and "formed and / or disposed in different layers" can mean formed in different processes.

[0172] In addition, in embodiments of the present disclosure, "connection" between two configurations can mean inclusively using both electrical connection and physical connection.

[0173] In addition, in ​ , for convenience of description, the width direction (or horizontal direction) is indicated as a first direction DR1, the height direction (or vertical direction) is indicated as a second direction DR2, and the thickness direction of the substrate SUB is indicated as a third direction DR3. The first direction DR1, the second direction DR2, and the third direction DR3 can respectively indicate the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3.

[0174] Referring to ​ , ​ and ​ , the display device according to embodiments of the present disclosure can include a substrate SUB, a line unit, and a plurality of pixels PXL.

[0175] The substrate SUB can include a transparent insulating material and can transmit light. The substrate SUB can be a rigid substrate or a flexible substrate.

[0176] For example, the rigid substrate can be one of a glass substrate, a quartz substrate, a glass-ceramic substrate, and a crystallized glass substrate.

[0177] The flexible substrate can be one of a film substrate and a plastic substrate including a polymeric organic material. For example, the flexible substrate can include at least one of polystyrene, polyvinyl alcohol, polymethyl methacrylate, polyether sulfone, polyacrylate, polyetherimide, polyethylene naphthalate, polyethylene terephthalate, polyphenylene sulfide, polyarylate, polyimide, polycarbonate, cellulose triacetate, and cellulose acetate propionate.

[0178] However, the material configuring the substrate SUB can be variously changed, and can include a fiber-reinforced plastic (FRP) or the like. In a manufacturing process of the display device, the material applied to the substrate SUB can preferably have resistance (or heat resistance) to a high process temperature.

[0179] The substrate SUB can include a display area DA including at least one pixel area PXA in which the pixels PXL are disposed, and a non-display area NDA disposed around the display area DA.

[0180] The pixels PXL can be arranged in a matrix form and / or a strip form in the display area DA on the substrate SUB according to a plurality of pixel rows extending in a first direction DR1 and a plurality of pixel columns extending in a second direction DR2 different from (e.g., crossing) the first direction DR1, but the disclosure is not limited thereto. According to an embodiment, the pixels PXL can be disposed in various arrangement forms in the display area DA on the substrate SUB.

[0181] The pixel area PXA in which each of the pixels PXL is disposed (or arranged) can include an emission area in which light is emitted, and a peripheral area surrounding a periphery of the emission area. In an embodiment of the disclosure, the peripheral area can include a non-emission area in which light is not emitted.

[0182] The wire unit can include a plurality of signal lines that transmit a signal (or a voltage) to each of the pixels PXL. The signal lines can include, for example, a scan line Si that transmits a scan signal to each of the pixels PXL, a data line Dj that transmits a data signal to each of the pixels PXL, an emission control line Ei that transmits an emission control signal to each of the pixels PXL, and a power line PL1 and PL2 that transmit a voltage of a driving power source to each of the pixels PXL.

[0183] Each of the pixels PXL can include a pixel circuit layer PCL disposed on the substrate SUB and including a pixel circuit 144, and a display element layer DPL including a plurality of light emitting elements LD. The light emitting elements LD can be located in the emission area included in the pixel area PXA of each of the pixels PXL.

[0184] For convenience, the pixel circuit layer PCL is first described, and then the display element layer DPL is described.

[0185] The pixel circuit layer PCL may include a buffer layer BFL, a pixel circuit 144 disposed on the buffer layer BFL, and a protective layer PSV disposed on the pixel circuit 144.

[0186] The buffer layer BFL prevents impurities from diffusing into the transistor T included in the pixel circuit 144. The buffer layer BFL may include an inorganic insulating layer comprising an inorganic material. The buffer layer BFL may include materials such as silicon nitride (SiN). x ), silicon dioxide (SiO) x ), silicon oxynitride (SiON) and aluminum oxide (AlO) x The buffer layer BFL can be a single layer or a multilayer structure with at least two layers. When the buffer layer BFL is multilayered, each layer can be formed of the same material or different materials. The buffer layer BFL can be omitted depending on the material of the substrate SUB, the process conditions, etc.

[0187] Pixel circuit 144 may include at least one transistor T and a storage capacitor Cst. Transistor T may include a driving transistor Tdr for controlling the drive current of the light-emitting element LD and a switching transistor Tsw connected to the driving transistor Tdr. However, this disclosure is not limited thereto; in addition to the driving transistor Tdr and the switching transistor Tsw, pixel circuit 144 may also include circuit elements performing other functions. In the following embodiments, when referring to the driving transistor Tdr and the switching transistor Tsw together, the driving transistor Tdr and the switching transistor Tsw may be referred to as one transistor T or multiple transistors T. The driving transistor Tdr may have the same characteristics as referenced... ​ The first transistor T1 described has the same construction, and the switching transistor Tsw can have the same construction as the reference. ​ The second transistor T2 described has the same construction.

[0188] Each of the driving transistor Tdr and the switching transistor Tsw may include a transistor semiconductor pattern SCL, a gate electrode GE, a first terminal SE, and a second terminal DE. The first terminal SE may be either the source electrode or the drain electrode, and the second terminal DE may be the other of the source electrode and the drain electrode. For example, when the first terminal SE is the source electrode, the second terminal DE may be the drain electrode.

[0189] The transistor semiconductor pattern SCL can be provided and / or formed on the buffer layer BFL. The transistor semiconductor pattern SCL can include a first contact region contacting the first terminal SE and a second contact region contacting the second terminal DE. A region between the first contact region and the second contact region can be a channel region. The transistor semiconductor pattern SCL can be a semiconductor pattern formed of polysilicon, amorphous silicon, oxide semiconductor, or the like. The channel region can be a semiconductor pattern not doped with impurities, and can be an intrinsic semiconductor. The first contact region and the second contact region can be semiconductor patterns doped with impurities.

[0190] The gate electrode GE can be provided and / or formed on the transistor semiconductor pattern SCL with the gate insulating layer GI interposed between the gate electrode GE and the transistor semiconductor pattern SCL. For example, the gate electrode GE can be provided on the gate insulating layer GI to be superposed with the channel region of the transistor semiconductor pattern SCL. The gate electrode GE can be formed of a single layer of a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, alone or in combination, or can be formed in a double-layer or multi-layer structure of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or silver (Ag) as a low-resistance material to reduce line resistance.

[0191] The gate insulating layer GI can be an inorganic insulating layer including an inorganic material. For example, the gate insulating layer GI can include at least one of inorganic materials such as silicon nitride (SiN x ), silicon oxide (SiO x ), silicon oxynitride (SiON), and aluminum oxide (AlO x ). However, the material of the gate insulating layer GI is not limited to the above-described embodiments. According to an embodiment, the gate insulating layer GI can be formed of an organic insulating layer including an organic material. The gate insulating layer GI can be provided as a single layer, or can also be provided as a multi-layer of at least a double layer.

[0192] The respective first terminal SE and the second terminal DE can contact the first contact region and the second contact region of the transistor semiconductor pattern SCL through a contact hole passing through the first interlayer insulating layer ILD1 and the gate insulating layer GI. For example, the first terminal SE can contact one of the first contact region and the second contact region of the transistor semiconductor pattern SCL, and the second terminal DE can contact the other of the first contact region and the second contact region of the transistor semiconductor pattern SCL.

[0193] Each of the first terminal SE and the second terminal DE can include the same material as that of the gate electrode GE, or can include one or more materials selected from among the materials exemplified as the material of the gate electrode GE.

[0194] The first interlayer insulating layer ILD1 can be provided on the gate electrode GE, and can be an inorganic insulating layer including an inorganic material. For example, the first interlayer insulating layer ILD1 can include at least one of inorganic materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). The first interlayer insulating layer ILD1 can be formed of a single layer or multiple layers. According to an embodiment, the first interlayer insulating layer ILD1 can be an organic insulating layer including an organic material.

[0195] In the above-described embodiment, the first terminal SE and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw are described as being electrically connected to the separate electrode of the transistor semiconductor pattern SCL through the respective contact holes passing through the gate insulating layer GI and the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. According to an embodiment, the first terminal SE of each of the driving transistor Tdr and the switching transistor Tsw can be one of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL, and the second terminal DE of each of the driving transistor Tdr and the switching transistor Tsw can be the other of the first contact region and the second contact region adjacent to the channel region of the corresponding transistor semiconductor pattern SCL. In this case, the second terminal DE of the driving transistor Tdr can be electrically connected to the light emitting element LD of the corresponding pixel PXL through a separate connection device including a bridge electrode, a contact electrode, or the like.

[0196] In an embodiment of the present disclosure, the transistor T included in the pixel circuit 144 can be configured of an LTPS (low temperature polysilicon) thin film transistor, but the present disclosure is not limited thereto, and can be configured of an oxide semiconductor thin film transistor according to an embodiment. In addition, a case where the transistor T is a thin film transistor of a top gate structure is described by way of example, but the present disclosure is not limited thereto. According to an embodiment, the transistor T can be a thin film transistor of a bottom gate structure.

[0197] The second interlayer insulating layer ILD2 can be provided and / or formed on the transistor T. The second interlayer insulating layer ILD2 can cover the transistor T. The second interlayer insulating layer ILD2 can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the second interlayer insulating layer ILD2 can include the same material as that of the first interlayer insulating layer ILD1, but the present disclosure is not limited thereto. The second interlayer insulating layer ILD2 can be provided as a single layer, or can be provided as a multiple layer of at least a double layer. The second interlayer insulating layer ILD2 can include a first contact hole CH1 exposing a portion of the driving transistor Tdr.

[0198] The pixel circuit layer PCL can include a first power line PL1 and a second power line PL2 disposed and / or formed on the second interlayer insulating layer ILD2. The first power line PL1 and the second power line PL2 can extend in the second direction DR2 and can be commonly disposed for each pixel PXL and an adjacent pixel PXL located in the same pixel column as the each pixel PXL. A first driving power source VDD can be applied to the first power line PL1, and a second driving power source VSS can be applied to the second power line PL2. In an embodiment of the disclosure, the first power line PL1 can have the same configuration as the configuration of the first power line PL1 described with reference to FIG. 6, and the second power line PL2 can have the same configuration as the configuration of the second power line PL2 described with reference to FIG. 6. ​ The first power line PL1 can have the same configuration as the configuration of the first power line PL1 described with reference to FIG. 6, and the second power line PL2 can have the same configuration as the configuration of the second power line PL2 described with reference to FIG. 6. ​ The first power line PL1 can have the same configuration as the configuration of the first power line PL1 described with reference to FIG. 6, and the second power line PL2 can have the same configuration as the configuration of the second power line PL2 described with reference to FIG. 6.

[0199] The first power line PL1 can be electrically connected to a partial configuration (e.g., the first electrode EL1) of the display element layer DPL, and the second power line PL2 can be electrically connected to a partial configuration (e.g., the third electrode EL3) of the display element layer DPL. The first power line PL1 and the second power line PL2 can transmit an alignment signal (or an alignment voltage) to each of the first electrode EL1 to the third electrode EL3 to align the light emitting element LD in the pixel area PXA of each pixel PXL. In addition, after the light emitting element LD is aligned, the first power line PL1 and the second power line PL2 can transmit a voltage of a corresponding driving power source to each pixel PXL to drive the light emitting element LD.

[0200] Each of the first power line PL1 and the second power line PL2 can include a conductive material. For example, each of the first power line PL1 and the second power line PL2 can be formed in a single layer with a material selected from the group consisting of copper (Cu), molybdenum (Mo), tungsten (W), neodymium (Nd), titanium (Ti), aluminum (Al), silver (Ag), and alloys thereof, alone or in combination, or can be formed in a double-layer or multi-layer structure of molybdenum (Mo), copper (Cu), titanium (Ti), aluminum (Al), or silver (Ag) as a low-resistance material to reduce line resistance. For example, each of the first power line PL1 and the second power line PL2 can be formed in a double-layer configuration sequentially stacked in the order of titanium (Ti) / copper (Cu).

[0201] In the above-described embodiment, it has been described that the first power line PL1 and the second power line PL2 are disposed on the second interlayer insulating layer ILD2, but the present disclosure is not limited thereto. According to an embodiment, the first power line PL1 and the second power line PL2 can be disposed and / or formed on any one of the insulating layers (e.g., the first interlayer insulating layer ILD1) disposed on the substrate SUB. In addition, in the above-described embodiment, it has been described that the first power line PL1 and the second power line PL2 are disposed on the same layer, but the present disclosure is not limited thereto. According to an embodiment, the first power line PL1 and the second power line PL2 can be disposed on different layers.

[0202] The protective layer PSV can be disposed and / or formed on the first power line PL1 and the second power line PL2.

[0203] The protective layer PSV can be disposed in a form including an organic insulating layer, an inorganic insulating layer, or an organic insulating layer disposed on an inorganic insulating layer. For example, the inorganic insulating layer can include at least one of inorganic materials such as silicon oxide (SiO x ), silicon nitride (SiN x ), silicon oxynitride (SiO x N y ), and aluminum oxide (AlO x ). The organic insulating layer can include at least one of acrylic resin (polyacrylate resin), epoxy resin, phenol resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, and benzocyclobutene resin.

[0204] The protective layer PSV can include a first contact hole CH1 corresponding to the first contact hole CH1 of the second interlayer insulating layer ILD2 and a second contact hole CH2 exposing a region of the second power line PL2.

[0205] The display element layer DPL can be disposed on the protective layer PSV.

[0206] The display element layer DPL can include the first bank pattern BNK1 and the second bank pattern BNK2, the first electrode EL1 to the third electrode EL3, the light emitting element LD, and the contact electrode CNE.

[0207] The first bank pattern BNK1 can be located in an emission region in which light is emitted from the pixel area PXA of each pixel PXL. The first bank pattern BNK1 can be a support member that supports each of the first to third electrodes EL1 to EL3 to change a surface profile (or shape) of each of the first to third electrodes EL1 to EL3 in the third direction DR3 to guide light emitted from the light emitting element LD in an image display direction of the display device. That is, the first bank pattern BNK1 can change the surface profile (or shape) of each of the first to third electrodes EL1 to EL3 in the third direction DR3.

[0208] The first bank pattern BNK1 can be disposed and / or formed in the emission region of the corresponding pixel PXL between the protective layer PSV and the corresponding electrode. For example, the first bank pattern BNK1 can be disposed and / or formed between the protective layer PSV and the first electrode EL1, between the protective layer PSV and the second electrode EL2, and between the protective layer PSV and the third electrode EL3, respectively.

[0209] The first bank pattern BNK1 can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. According to an embodiment, the first bank pattern BNK1 can include a single layer of an organic insulating layer and / or a single layer of an inorganic insulating layer, but the present disclosure is not limited thereto. According to an embodiment, the first bank pattern BNK1 can be disposed in the form of a plurality of layers in which at least one organic insulating layer and at least one inorganic insulating layer are stacked. However, the material of the first bank pattern BNK1 is not limited to the above-described embodiment, and according to an embodiment, the first bank pattern BNK1 can include a conductive material.

[0210] In an embodiment of the present disclosure, the first bank pattern BNK1 can include at least two sub-bank patterns arranged along the second direction DR2. For example, the first bank pattern BNK1 can include first to third sub-bank patterns SBNK1 to SBNK3 arranged along the second direction DR2. The first to third sub-bank patterns SBNK1 to SBNK3 can be located in the same column. The first to third sub-bank patterns SBNK1 to SBNK3 can have a bar shape extending along the second direction DR2, but the present disclosure is not limited thereto, and the shape of the first to third sub-bank patterns SBNK1 to SBNK3 can be differently changed.

[0211] The first subbank pattern SBNK1, the second subbank pattern SBNK2, and the third subbank pattern SBNK3 can be sequentially arranged along the second direction DR2 when viewed in a plan view. The first subbank pattern SBNK1 and the second subbank pattern SBNK2 can be spaced apart from each other with a constant distance d1 therebetween, and the second subbank pattern SBNK2 and the third subbank pattern SBNK3 can be spaced apart from each other with a constant distance d1 therebetween. In an embodiment of the disclosure, the second subbank pattern SBNK2 and the third subbank pattern SBNK3 adjacent to each other in the second direction DR2 can be spaced apart from each other with a distance d1 equal to or greater than the length L of each light emitting element LD. For example, the second subbank pattern SBNK2 and the third subbank pattern SBNK3 can be spaced apart from each other with a distance d1 of about 5.5 µm to 9 µm, but the disclosure is not limited thereto. The first subbank pattern SBNK1 and the second subbank pattern SBNK2 can also be spaced apart from each other with the distance d1 therebetween.

[0212] The distance d1 between the first subbank pattern SBNK1 and the second subbank pattern SBNK2 and the distance d1 between the second subbank pattern SBNK2 and the third subbank pattern SBNK3 can be the same along the second direction DR2. However, the disclosure is not limited thereto, and according to an embodiment, the distance d1 between the first subbank pattern SBNK1 and the second subbank pattern SBNK2 and the distance d1 between the second subbank pattern SBNK2 and the third subbank pattern SBNK3 can be different from each other.

[0213] The first subbank pattern SBNK1 to the third subbank pattern SBNK3 can be designed to have the same size (or area) as each other to have a uniform light output distribution for each region within the pixel area PXA of each pixel PXL. For example, the first subbank pattern SBNK1 to the third subbank pattern SBNK3 located in the same column in the second direction DR2 can have the same length when viewed in a plan view. However, the disclosure is not limited thereto, and according to an embodiment, the first subbank pattern SBNK1 to the third subbank pattern SBNK3 can be designed to have different sizes (or areas) from each other. For example, when a solution (or a fluid solvent) in which the light emitting element LD is mixed is injected into the pixel area PXA of each pixel PXL by an inkjet printing method, the size (or area) of the subbank pattern located in a specific region can be designed to be smaller than the size (or area) of the subbank pattern located in another region when a relatively large amount of solution drops on the specific region. For example, the size (or area) of the second subbank pattern SBNK2 located at the center in the same column can be smaller than the size (or area) of each of the first subbank pattern SBNK1 and the third subbank pattern SBNK3 located above and below in the same column. Specifically, as described above, the second subbank pattern SBNK2 can be designed to have a size (or area) smaller than the size (or area) of each of the first subbank pattern SBNK1 and the third subbank pattern SBNK3 located above and below in the same column. ​As shown, the length d5 ​​of the second sub-dike pattern SBNK2 in the second direction DR2 can be designed to be shorter than the length d4 of the first sub-dike pattern SBNK1 in the second direction DR2. Furthermore, the length d5 ​​of the second sub-dike pattern SBNK2 in the second direction DR2 can be designed to be shorter than the length d6 of the third sub-dike pattern SBNK3 in the second direction DR2. In this case, the lengths d4 of the first sub-dike pattern SBNK1 and d6 of the third sub-dike pattern SBNK3 in the second direction DR2 can be equal to or different from each other. However, this disclosure is not limited to the above embodiment. According to an embodiment, the length d5 ​​of the second sub-dike pattern SBNK2 in the second direction DR2 can be larger than the length d4 of the first sub-dike pattern SBNK1 in the second direction DR2, and also larger than the length d5 ​​of the third sub-dike pattern SBNK3 in the second direction DR2.

[0214] Each of the first sub-dike patterns SBNK1 to the third sub-dike pattern SBNK3 may have a trapezoidal cross-section that narrows upwards from one surface (or upper surface) of the protective layer PSV along the third direction DR3, but this disclosure is not limited thereto. According to embodiments, such as ​ As shown, the first sub-dam patterns SBNK1 to the third sub-dam patterns SBNK3 may include curved surfaces having a cross-section with a semi-elliptical shape, a semi-circular shape (or a hemispherical shape), etc., in which the width narrows upwards along a third direction DR3 from one surface (or upper surface) of the protective layer PSV. When viewed in cross-section, the shape of each of the first sub-dam patterns SBNK1 to the third sub-dam patterns SBNK3 is not limited to the embodiments described above, and can be varied differently within a range that can improve the efficiency of light emitted from each of the light-emitting elements LD. The first sub-dam patterns SBNK1 to the third sub-dam patterns SBNK3 may be disposed on the same plane on the protective layer PSV and may have the same height (or thickness).

[0215] The second embankment pattern BNK2 may surround at least one side of the peripheral region of the pixel region PXA of each pixel PXL. The peripheral region may include a non-emitting region from which light is not emitted.

[0216] The second bank pattern BNK2 can be a structure that defines (or divides) a pixel area (or emission area) of each pixel PXL and each pixel PXL adjacent thereto, and can be, for example, a pixel defining layer. The second bank pattern BNK2 can be configured to include at least one light blocking material and / or a reflective material to prevent a light leakage defect in which light (or light rays) leaks between each pixel PXL and the pixel PXL adjacent thereto. According to an embodiment, the second bank pattern BNK2 can include a transparent material (or substance). The transparent material can include, for example, a polyamide resin, a polyimide resin, or the like, but the present disclosure is not limited thereto. According to another embodiment, a reflective material layer can be formed on the second bank pattern BNK2 to further improve the efficiency of light emitted from each pixel PXL.

[0217] The second bank pattern BNK2 can be formed and / or disposed on a layer different from those of the first to third sub-bank patterns SBNK1 to SBNK3, but the present disclosure is not limited thereto, and according to an embodiment, the second bank pattern BNK2 can be formed and / or disposed on the same layer as the first to third sub-bank patterns SBNK1 to SBNK3. In an embodiment of the present disclosure, the second bank pattern BNK2 can be formed on a layer different from those of the first to third sub-bank patterns SBNK1 to SBNK3, and can be located on the first insulating layer INS1.

[0218] Each of the first to third electrodes EL1 to EL3 can be disposed in the pixel area PXA of each pixel PXL, and can extend in one direction (for example, the second direction DR2). The first to third electrodes EL1 to EL3 can be disposed on the same surface, and can be disposed to be spaced apart from each other.

[0219] The first to third electrodes EL1 to EL3 can be sequentially arranged along the first direction DR1. The first and second electrodes EL1 and EL2 can be spaced apart from each other along the first direction DR1 and have a constant distance therebetween, and the second and third electrodes EL2 and EL3 can be spaced apart from each other along the first direction DR1 and have a constant distance therebetween. In the pixel area PXA of each pixel PXL, the same distance can be present between the first and second electrodes EL1 and EL2 and between the second and third electrodes EL2 and EL3. However, the present disclosure is not limited thereto, and according to an embodiment, different distances can be present between the first and second electrodes EL1 and EL2 and between the second and third electrodes EL2 and EL3.

[0220] Each of the first to third electrodes EL1 to EL3 can be formed of a material having a constant reflectance. The conductive material can include an opaque metal suitable for reflecting light emitted from the light emitting element LD in an image display direction of the display device. The opaque metal can include, for example, silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and a metal such as an alloy thereof. According to an embodiment, each of the first to third electrodes EL1 to EL3 can include a transparent conductive material (or substance). The transparent conductive material can include a conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), a conductive polymer such as PEDOT, etc. When each of the first to third electrodes EL1 to EL3 includes the transparent conductive material, a separate conductive layer formed of an opaque metal for reflecting light emitted from the light emitting element LD in the image display direction of the display device can be additionally included. However, the material of each of the first to third electrodes EL1 to EL3 is not limited to the above-described materials.

[0221] In addition, each of the first to third electrodes EL1 to EL3 can be disposed and / or formed as a single layer, but the present disclosure is not limited thereto. According to an embodiment, each of the first to third electrodes EL1 to EL3 can be disposed and / or formed as a multi-layer in which at least two materials among a metal, an alloy, a conductive oxide, and a conductive polymer are stacked. Each of the first to third electrodes EL1 to EL3 can be formed of a multi-layer of at least a double layer to minimize distortion due to signal delay when transmitting a signal (or voltage) to both ends of each of the light emitting elements LD. For example, each of the first to third electrodes EL1 to EL3 can be formed of a plurality of layers sequentially stacked in the order of indium tin oxide (ITO) / silver (Ag) / indium tin oxide (ITO).

[0222] In an embodiment of the present disclosure, each of the first to third electrodes EL1 to EL3 can be divided into a first area A and a second area B, the second area B being an area other than the first area A corresponding between the first and second sub bank patterns SBNK1 and SBNK2 and between the second and third sub bank patterns SBNK2 and SBNK3. The first area A of each of the first to third electrodes EL1 to EL3 can be an area not overlapped with the first to third sub bank patterns SBNK1 to SBNK3, and the second area B of each of the first to third electrodes EL1 to EL3 can include an area overlapped with the first to third sub bank patterns SBNK1 to SBNK3.

[0223] The first region A of each of the first to third electrodes EL1 to EL3 can be located on one surface (or upper surface) of the region of the protective layer PSV between the first to third sub-bank patterns SBNK1 to SBNK3, and can not be overlaid with the first to third sub-bank patterns SBNK1 to SBNK3. As shown in FIG. 1A, the first region A of each of the first to third electrodes EL1 to EL3 can have a flat surface profile (or shape) corresponding to one surface (or upper surface) of the protective layer PSV in the third direction DR3. ​

[0224] The first region A of each of the first to third electrodes EL1 to EL3 can have at least two widths W1 in the first direction DR1 along the extension direction of the corresponding electrode. For example, the first region A of the first electrode EL1 can have at least two widths W1 in the first direction DR1 along the extension direction (e.g., the second direction DR2) of the first electrode EL1. The first region A of the second electrode EL2 can have at least two widths W1 in the first direction DR1 along the extension direction of the second electrode EL2. The first region A of the third electrode EL3 can have at least two widths W1 in the first direction DR1 along the extension direction of the third electrode EL3.

[0225] The first region A of the first electrode EL1, the first region A of the second electrode EL2, and the first region A of the third electrode EL3 can have the same size and shape, but the present disclosure is not limited thereto. According to an embodiment, the first region A of the first electrode EL1, the first region A of the second electrode EL2, and the first region A of the third electrode EL3 can have different sizes and shapes.

[0226] When viewed in a plan view, the width of the first region A of each of the first to third electrodes EL1 to EL3 in the first direction DR1 can be narrower than the second region B of the corresponding electrode. For example, the first region A of each of the first to third electrodes EL1 to EL3 can have different widths in the first direction DR1 along the extension direction of the corresponding electrode, or can include concave portions CP1 and CP2 that are recessed (or indented) such that the width is narrowed.

[0227] ​The recessed portions CP1 and CP2, when viewed in a plan view, can include a first recessed portion CP1 recessed from the first virtual line VL1 in the first direction DR1 to be adjacent to the second virtual line VL2, and a second recessed portion CP2 recessed from the second virtual line VL2 in the first direction DR1 to be adjacent to the first virtual line VL1. Here, the first virtual line VL1, when viewed in a plan view, can be a line on which one long side of the second region B of each of the first to third electrodes EL1 to EL3 is located, and the second virtual line VL2 can be a line on which the other long side of the second region B of each of the first to third electrodes EL1 to EL3 is located. The first recessed portion CP1, when viewed in a plan view, can be recessed inward (or toward the other long side of the corresponding electrode) from one long side of the corresponding electrode in the first direction DR1, and the second recessed portion CP2 can be recessed inward (or toward one long side of the corresponding electrode) from the other long side of the corresponding electrode in the first direction DR1.

[0228] The recessed portions CP1 and CP2 of each of the first to third electrodes EL1 to EL3, when viewed in a plan view, can face the recessed portions CP1 and CP2 of the electrodes adjacent in the first direction DR1. For example, the second recessed portion CP2 of the first electrode EL1 can face the first recessed portion CP1 of the second electrode EL2, and the second recessed portion CP2 of the second electrode EL2 can face the first recessed portion CP1 of the third electrode EL3. Although not directly shown in the drawings, the first recessed portion CP1 of the first electrode EL1 can face the second recessed portion CP2 of the third electrode EL3 provided in the pixel PXL adjacent to the corresponding pixel PXL in the first direction DR1.

[0229] The recessed portions CP1 and CP2 can be provided in a standard shape, or can be provided in a shape including a non-square (or irregular) boundary. For example, the first recessed portion CP1, when viewed in a plan view, can have a semi-elliptical shape in which a width in the second direction DR2 narrows toward the other long side of the corresponding electrode (or toward the inner direction) in the first direction DR1. In a plan view, the second recessed portion CP2 can have a semi-elliptical shape in which a width in the second direction DR2 narrows toward one long side of the corresponding electrode (or toward the inner direction) in the first direction DR1.

[0230] The first region A of each of the first to third electrodes EL1 to EL3 including the concave portions CP1 and CP2 can have a non-uniform width W1 along the second direction DR2. Specifically, the first region A of each of the first to third electrodes EL1 to EL3 including the concave portions CP1 and CP2 can have at least two widths W1 in the first direction DR1.

[0231] The second region B of each of the first to third electrodes EL1 to EL3 can be disposed and / or formed on the first to third sub-bank patterns SBNK1 to SBNK3, and can have a surface profile in the third direction DR3 corresponding to the shape of the first to third sub-bank patterns SBNK1 to SBNK3. For example, the second region B of each of the first to third electrodes EL1 to EL3 can include a protruding portion in the third direction DR3 corresponding to the first to third sub-bank patterns SBNK1 to SBNK3 and a flat portion corresponding to the protective layer PSV.

[0232] The second region B of each of the first to third electrodes EL1 to EL3 can have a constant width W2 in the first direction DR1 along the extension direction of the corresponding electrode. For example, the second region B of the first electrode EL1 can have a constant width W2 in the first direction DR1 along the extension direction (or the second direction DR2) of the first electrode EL1. The second region B of the second electrode EL2 can have a constant width W2 in the first direction DR1 along the extension direction (or the second direction DR2) of the second electrode EL2. The second region B of the third electrode EL3 can have a constant width W2 in the first direction DR1 along the extension direction (or the second direction DR2) of the third electrode EL3. The width W1 of the first region A of each of the first to third electrodes EL1 to EL3 in the first direction DR1 can be smaller than the width W2 of the second region B of the corresponding electrode in the first direction DR1. In addition, the first region A of each of the first to third electrodes EL1 to EL3 can have a width W1 in the first direction DR1 equal to the width W2 of the second region B of the corresponding electrode.

[0233] When viewed in a plan view, each of the first to third electrodes EL1 to EL3 including the first region A and the second region B can have a non-uniform width in the first direction DR1 along the extension direction. For example, each of the first to third electrodes EL1 to EL3 can have at least two widths in the first direction DR1 along the extension direction. In this case, the region between two adjacent electrodes from among the first to third electrodes EL1 to EL3 (e.g., a region in which the light emitting elements LD are aligned) can have at least two widths in the first direction DR1 along the extension direction of each of the first to third electrodes EL1 to EL3.

[0234] A distance d3 in the first direction DR1 between the first region A of the first electrode EL1 and the first region A of the second electrode EL2 can be greater than a distance d2 in the first direction DR1 between the second region B of the first electrode EL1 and the second region B of the second electrode EL2. Also, a distance d3 in the first direction DR1 between the first region A of the second electrode EL2 and the first region A of the third electrode EL3 can be greater than a distance d2 in the first direction DR1 between the second region B of the second electrode EL2 and the second region B of the third electrode EL3.

[0235] The first to third subbank patterns SBNK1 to SBNK3 and the first to third electrodes EL1 to EL3 can function as a reflection member that causes light emitted from the light emitting elements LD to travel in an image display direction of the display device to improve light output efficiency of the light emitting elements LD.

[0236] The first electrode EL1 can receive a predetermined alignment signal (or an alignment voltage) from the first power supply line PL1 to function as a first alignment electrode (or a first alignment line) before the light emitting elements LD are aligned in the pixel region PXA of each pixel PXL. The first electrode EL1 can be electrically connected to the driving transistor Tdr through the first contact hole CH1 after the light emitting elements LD are aligned in the pixel region PXA, and can receive a predetermined signal (or a predetermined voltage) from the driving transistor Tdr to function as a driving electrode that drives the light emitting elements LD.

[0237] The second electrode EL2 can receive a predetermined alignment signal (or an alignment voltage) from the first power supply line PL1 or from a power supply line (not shown) different from the first power supply line PL1 and the second power supply line PL2 to function as a second alignment electrode (or a second alignment line) before the light emitting elements LD are aligned in the pixel region PXA of each pixel PXL. The second electrode EL2 can function as a reflection member that reflects light emitted from each of the light emitting elements LD in an image display direction of the display device after the light emitting elements LD are aligned in the pixel region PXA, and can be a path of a driving current input from the light emitting elements LD disposed between the first electrode EL1 and the second electrode EL2.

[0238] The third electrode EL3 can be electrically connected to the second power line PL2 and receive a predetermined alignment signal (or alignment voltage) from the second power line PL2 to function as a third alignment electrode (or third alignment line) through the second contact hole CH2 before the light emitting element LD is aligned in the pixel region PXA of each pixel PXL. The third electrode EL3 can be connected to the second driving power source VSS to function as a driving electrode for driving the light emitting element LD through the second power line PL2 after the light emitting element LD is aligned in the pixel region PXA.

[0239] The alignment signal (or alignment voltage) transmitted to each of the first electrode EL1 to the third electrode EL3 can be an AC signal having a voltage difference and / or a phase difference that can align the light emitting element LD between the first electrode EL1 to the third electrode EL3, but the present disclosure is not limited thereto.

[0240] When the corresponding alignment signal (or alignment voltage) is applied to each of the first electrode EL1 to the third electrode EL3, an electric field can be formed between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3, respectively. The light emitting element LD can be aligned by the electric field formed between the two adjacent electrodes and / or disposed in the pixel region PXA of each pixel PXL.

[0241] In an embodiment of the present disclosure, in the step of aligning the light emitting element LD in the pixel region PXA of each pixel PXL, the light emitting element LD supplied to the pixel region PXA can be controlled to be aligned with a relative bias by controlling the alignment signal (or alignment voltage) applied to each of the first electrode EL1 to the third electrode EL3 or forming a magnetic field.

[0242] In an embodiment of the present disclosure, one of the first electrode EL1 and the third electrode EL3 can be an anode electrode, and the other can be a cathode electrode. For example, the first electrode EL1 can be an anode electrode, and the third electrode EL3 can be a cathode electrode.

[0243] After the light emitting element LD is aligned in the pixel region PXA of each pixel PXL, a portion of the first electrode EL1 and a portion of the second electrode EL2 located between adjacent pixels PXL can be removed to individually (or independently) drive each pixel PXL.

[0244] Each of the light emitting elements LD can be a super small light emitting element (for example, having a size as small as nanometer to micrometer) using an inorganic crystal structure material. For example, each of the light emitting elements LD can be a super small light emitting element manufactured by an etching method or a super small light emitting element manufactured by a growth method.

[0245] At least two to tens of light emitting elements LD can be aligned in and / or disposed in the pixel area PXA of each pixel PXL, but the number of light emitting elements LD is not limited thereto. According to an embodiment, the number of light emitting elements LD aligned in and / or disposed in the pixel area PXA can vary differently.

[0246] Each of the light emitting elements LD can be disposed between two electrodes adjacent to each other in the first direction DR1. The light emitting elements LD can include a first light emitting element LD1 disposed between the first electrode EL1 and the second electrode EL2 and a second light emitting element LD2 disposed between the second electrode EL2 and the third electrode EL3. In the following embodiments, when one of the first light emitting element LD1 and the second light emitting element LD2 is arbitrarily named, or when the first light emitting element LD1 and the second light emitting element LD2 are collectively named, one of the first light emitting element LD1 and the second light emitting element LD2 or both of the first light emitting element LD1 and the second light emitting element LD2 are referred to as the light emitting element LD.

[0247] In an embodiment of the disclosure, each of the light emitting elements LD can emit any one of colored light and / or white light. Each of the light emitting elements LD can be aligned between two adjacent electrodes such that an extension direction (or a length direction of each light emitting element LD) is parallel to the first direction DR1. The light emitting elements LD can be disposed in a form in which the light emitting elements LD are dispersed in a solution, and can be injected into the pixel area PXA of each pixel PXL.

[0248] In an embodiment of the disclosure, the light emitting elements LD can be injected into the pixel area PXA of each pixel PXL by an inkjet printing method, a slot coating method, or other various methods. For example, the light emitting elements LD can be mixed with a volatile solvent, and can be supplied to the pixel area PXA by an inkjet printing method or a slot coating method. At this time, when an alignment signal corresponding to each of the first electrode EL1, the second electrode EL2, and the third electrode EL3 provided to the pixel area PXA is applied, an electric field can be formed between two adjacent electrodes among the first electrode EL1, the second electrode EL2, and the third electrode EL3. Accordingly, the light emitting elements LD can be aligned between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3, respectively.

[0249] After the light emitting elements LD are aligned, the solvent can be evaporated or removed in another method, and thus the light emitting elements LD can finally be aligned in and / or disposed in the pixel area PXA of each pixel PXL.

[0250] The light emitting element LD can be disposed and / or formed on the first insulating layer INS1.

[0251] The first insulating layer INS1 can be formed and / or disposed under each of the light emitting elements LD aligned between the two electrodes in the pixel area PXA of each pixel PXL. The first insulating layer INS1 can fill a space between each of the light emitting elements LD and the protection layer PSV to stably support the light emitting elements LD and prevent the light emitting elements LD from being separated from the protection layer PSV.

[0252] The first insulating layer INS1 can include an inorganic insulating layer formed of an inorganic material or an organic insulating layer formed of an organic material. In an embodiment of the disclosure, the first insulating layer INS1 can be formed of an inorganic insulating layer suitable for protecting the light emitting elements LD from the pixel circuit layer PCL of each pixel PXL, but the disclosure is not limited thereto. According to an embodiment, the first insulating layer INS1 can be formed of an organic insulating layer suitable for planarizing a support surface of the light emitting elements LD.

[0253] In addition, the first insulating layer INS1 can include an opening OPN exposing one region of each of the first to third electrodes EL1 to EL3 and cover a remaining region other than the one region. Here, the contact electrode CNE can be disposed and / or formed on the one region of each of the first to third electrodes EL1 to EL3 exposed by the opening OPN of the first insulating layer INS1.

[0254] The second insulating layer INS2 can be disposed and / or formed on each of the light emitting elements LD. The second insulating layer INS2 can be disposed and / or formed on each of the light emitting elements LD to cover a portion of an upper surface of each of the light emitting elements LD and expose both ends of each of the light emitting elements LD to the outside. The second insulating layer INS2 can be formed as an independent insulating pattern in the pixel area PXA of each pixel PXL, but the disclosure is not limited thereto.

[0255] The second insulating layer INS2 can be configured as a single layer or multiple layers and can include an inorganic insulating layer including at least one inorganic material or an organic insulating layer including at least one organic material. The second insulating layer INS2 can also fix each of the light emitting elements LD aligned in the pixel area PXA. The second insulating layer INS2 can include an inorganic insulating layer suitable for protecting the active layer 12 of each of the light emitting elements LD from external oxygen, moisture, etc. However, the disclosure is not limited thereto. The second insulating layer INS2 can be formed of an organic insulating layer including an organic material according to a design condition, etc. of a display device to which the light emitting elements LD are applied.

[0256] In an embodiment of the disclosure, after the alignment of the light emitting elements LD in the pixel area PXA is completed, by forming the second insulating layer INS2 on the light emitting elements LD, it is possible to prevent the light emitting elements LD from deviating from the alignment position. When there is a gap (or space) between the first insulating layer INS1 and the light emitting elements LD before the second insulating layer INS2 is formed, the gap can be filled with the second insulating layer INS2 during the process of forming the second insulating layer INS2. Accordingly, the second insulating layer INS2 can be formed of an organic insulating layer suitable for filling the gap between the first insulating layer INS1 and the light emitting elements LD.

[0257] In an embodiment of the disclosure, the second insulating layer INS2 can be formed on each of the light emitting elements LD, and thus the active layer 12 of each of the light emitting elements LD can not be in contact with the external conductive material. The second insulating layer INS2 can cover only a portion of the surface of each of the light emitting elements LD, and can expose both ends of each of the light emitting elements LD to the outside.

[0258] The contact electrode CNE can be provided on each of the first electrode EL1 to the third electrode EL3. The contact electrode CNE can be a configuration for further electrically stably connecting the corresponding first electrode EL1 to third electrode EL3 and the light emitting element LD corresponding thereto.

[0259] The contact electrode CNE can include a first contact electrode CNE1 provided on the first electrode EL1, a second contact electrode CNE2 provided on the second electrode EL2, and a third contact electrode CNE3 provided on the third electrode EL3. The first contact electrode CNE1 to the third contact electrode CNE3 can be formed of various transparent conductive materials. For example, the first contact electrode CNE1 to the third contact electrode CNE3 can include at least one of various transparent conductive materials including indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), and indium tin zinc oxide (ITZO), and can be configured to be substantially transparent or translucent to satisfy a predetermined transmittance. However, the material of the first contact electrode CNE1 to the third contact electrode CNE3 is not limited to the above-described embodiment, and according to an embodiment, the first contact electrode CNE1 to the third contact electrode CNE3 can be formed of various opaque conductive materials.

[0260] The first contact electrode CNE1, the second contact electrode CNE2, and the third contact electrode CNE3 can be disposed to be spaced apart from each other in the same plane. The first contact electrode CNE1, the second contact electrode CNE2, and the third contact electrode CNE3 can be disposed on the same layer and can include the same material. However, the disclosure is not limited thereto, and according to an embodiment, the first contact electrode CNE1, the second contact electrode CNE2, and the third contact electrode CNE3 can be disposed on different layers and can include different materials.

[0261] In an embodiment of the disclosure, the first contact electrode CNE1 can be disposed on the first electrode EL1 to be superposed with the first electrode EL1. The first contact electrode CNE1 can be directly disposed on one region of the first electrode EL1 exposed by the opening OPN of the first insulating layer INS1 to be connected to the first electrode EL1. According to an embodiment, when a cap layer (not shown) is disposed on the first electrode EL1 exposed through the opening OPN of the first insulating layer INS1, the first contact electrode CNE1 can be disposed on the cap layer and can be electrically connected to the first electrode EL1 through the cap layer. Here, the cap layer can protect the first electrode EL1 from defects, etc. occurring during a manufacturing process of the display device, and can further enhance the adhesion between the first electrode EL1 and the pixel circuit layer PCL disposed thereunder. The cap layer can be formed of a transparent conductive material such as indium zinc oxide (IZO) to minimize loss of light emitted from each of the light emitting elements LD and reflected in the image display direction of the display device by the first electrode EL1.

[0262] The first contact electrode CNE1 can be directly disposed on one of two ends of each of the first light emitting elements LD1 to be superposed with one end of each of the first light emitting elements LD1. The first contact electrode CNE1 can electrically and stably connect the first electrode EL1 with one of the two ends of each of the first light emitting elements LD1.

[0263] The second contact electrode CNE2 can be disposed on the second electrode EL2 to be superposed with the second electrode EL2. The second contact electrode CNE2 can be directly disposed on one region of the second electrode EL2 exposed by the opening OPN of the first insulating layer INS1 to be electrically and / or physically connected to the second electrode EL2. In addition, the second contact electrode CNE2 can be directly disposed on the other of the two ends of each of the first light emitting elements LD1 to be superposed with the other of the two ends of each of the first light emitting elements LD1. In addition, the second contact electrode CNE2 can be directly disposed on one of the two ends of each of the second light emitting elements LD2 to be superposed with one of the two ends of each of the second light emitting elements LD2. The second contact electrode CNE2 can electrically and stably connect the second electrode EL2, the other of the two ends of each of the first light emitting elements LD1, and one of the two ends of each of the second light emitting elements LD2.

[0264] The first and second contact electrodes CNE1 and CNE2 can be disposed to be spaced apart from each other. For example, the first and second contact electrodes CNE1 and CNE2 can be disposed to be spaced apart from each other with a predetermined distance therebetween on the second insulating layer INS2 of each of the first light emitting elements LD1. The first and second contact electrodes CNE1 and CNE2 can be disposed in the same layer and can be formed through the same process. However, the disclosure is not limited thereto, and according to an embodiment, the first and second contact electrodes CNE1 and CNE2 can be disposed in different layers and can be formed through different processes. When the first and second contact electrodes CNE1 and CNE2 are disposed in different layers and formed through different processes, a separate insulating layer can be disposed between the first and second contact electrodes CNE1 and CNE2.

[0265] The third contact electrode CNE3 can be disposed on the third electrode EL3 to be laminated with the third electrode EL3. The third contact electrode CNE3 can be directly disposed on one region of the third electrode EL3 exposed by the opening OPN of the first insulating layer INS1 to be connected to the third electrode EL3. In addition, the third contact electrode CNE3 can be laminated with the other one of the two ends of each of the second light emitting elements LD2. The third contact electrode CNE3 can electrically and stably connect the third electrode EL3 with the other one of each of the second light emitting elements LD2.

[0266] The second and third contact electrodes CNE2 and CNE3 can be disposed to be spaced apart from each other. For example, the second and third contact electrodes CNE2 and CNE3 can be disposed to be spaced apart from each other with a predetermined distance therebetween on the second insulating layer INS2 of each of the second light emitting elements LD2. The second and third contact electrodes CNE2 and CNE3 can be disposed in the same layer and can be formed through the same process. However, the disclosure is not limited thereto, and according to an embodiment, the second and third contact electrodes CNE2 and CNE3 can be disposed in different layers and can be formed through different processes. When the second and third contact electrodes CNE2 and CNE3 are disposed in different layers and formed through different processes, a separate insulating layer can be disposed between the second and third contact electrodes CNE2 and CNE3.

[0267] The encapsulation layer ENC can be provided and / or formed on the first to third contact electrodes CNE1 to CNE3. The encapsulation layer ENC can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material. For example, the encapsulation layer ENC can have a structure in which at least one inorganic insulating layer or at least one organic insulating layer is alternately stacked. The encapsulation layer ENC can completely cover the display element layer DPL to prevent water, moisture, or the like from penetrating from the outside to the display element layer DPL including the light emitting elements LD.

[0268] When it is assumed that a driving current flows from the first power supply line PL1 to the second power supply line PL2 through the driving transistor Tdr of the pixel circuit layer PCL of each pixel PXL, the driving current can flow into the emission unit EMU of each pixel PXL through the first contact hole CH1. For example, the driving current is supplied to the first electrode EL1 through the first contact hole CH1, and the driving current flows to the second electrode EL2 via the first light emitting element LD1. Accordingly, each of the first light emitting elements LD1 can emit light having a luminance corresponding to a current allocated to each of the first light emitting elements LD1. The driving current flowing through the second electrode EL2 flows to the third electrode EL3 via the second light emitting element LD2. Accordingly, the second light emitting element LD2 can emit light having a luminance corresponding to a current allocated to each of the second light emitting elements LD2. In the above-described method, the driving current of each pixel PXL can flow while sequentially passing through the first light emitting element LD1 and the second light emitting element LD2. Accordingly, each pixel PXL can emit light having a luminance corresponding to a data signal supplied during each frame period.

[0269] According to the above-described embodiment, each of the first to third electrodes EL1 to EL3 can be designed to include a first region A located between the first to third subbank patterns SBNK1 to SBNK3 and not superposed with the first to third subbank patterns SBNK1 to SBNK3, and a second region B other than the first region A, and have at least two widths in the first direction DR1 along the extension direction due to the recessed portions CP1 and CP2 provided in the first region A.

[0270] In this case, a distance d2 in the first direction DR1 between the second regions B of two adjacent electrodes can be narrower than a distance d3 in the first direction DR1 between the first regions A of two adjacent electrodes. For example, the distance d2 in the first direction DR1 between the second region B of the first electrode EL1 and the second region B of the second electrode EL2 can be narrower than the distance d3 in the first direction DR1 between the first region A of the first electrode EL1 and the first region A of the second electrode EL2. Also, the distance d2 in the first direction DR1 between the second region B of the second electrode EL2 and the second region B of the third electrode EL3 can be narrower than the distance d3 in the first direction DR1 between the first region A of the second electrode EL2 and the first region A of the third electrode EL3.

[0271] Also, because the second region B of each of the first electrode EL1 to the third electrode EL3 has the protruding portion corresponding to the first subbank pattern SBNK1 to the third subbank pattern SBNK3 along the third direction DR3, a height of a surface in the third direction DR3 can be higher than a height of the first region A of each of the first electrode EL1 to the third electrode EL3. Accordingly, the second region B of each of the first electrode EL1 to the third electrode EL3 can have a surface profile different from a surface profile of the first region A of each of the first electrode EL1 to the third electrode EL3 in the third direction DR3. That is, a surface profile change of the second region B of each of the first electrode EL1 to the third electrode EL3 in the third direction DR3 can be greater than a surface profile change of the first region A of the corresponding electrode in the third direction DR3.

[0272] At this time, when an alignment signal (or an alignment voltage) corresponding to each of the first electrode EL1 to the third electrode EL3 is applied, an electric field can be concentrated between the second regions B of two adjacent electrodes. As the distance between two adjacent electrodes becomes narrower, the strength of the electric field formed therebetween can become stronger. Also, as the surface profile change of each of the two adjacent electrodes in the third direction DR3 increases (or the surface height of each of the two adjacent electrodes increases), the strength of the electric field formed therebetween can be stronger.

[0273] As the strength of the electric field increases, the magnitude of the dielectrophoretic (DEP) force can increase. DEP can refer to the phenomenon where, when particles are placed in a non-uniform electric field, they are attracted towards either a region with a dense (or strong) gradient of the electric field or a region with a slight (or weak) gradient. The phenomenon of particles being attracted to the region with a dense (or strong) electric field is called positive DEP, while the phenomenon of particles being attracted to the region with a slight (or weak) electric field is called negative DEP. The strength of the DEP force can vary depending on the particle (e.g., the volume of the light-emitting element LD, the dielectric constant of the light-emitting element LD, the dielectric constant of the solvent, the strength of the electric field, etc.). In particular, the strength of the DEP force can be proportional to the strength of the electric field.

[0274] As described above, when a relatively strong electric field is formed between the second regions B of two adjacent electrodes, the intensity of the DEP force increases, allowing the light-emitting element (LD) to move densely between the second regions B of the two adjacent electrodes. In other words, the light-emitting element (LD) can be densely aligned between the second regions B of the two adjacent electrodes. Consequently, the light-emitting element (LD) can be densely aligned only in the desired region (e.g., between the second regions B of the two adjacent electrodes) of the pixel region PXA in each pixel PXL, thus reducing the number of misaligned light-emitting element (LD) components. Therefore, the loss of the light-emitting element (LD) can be minimized, and the number of effective light-emitting element (LD) components per unit area of ​​each pixel PXL can be increased. Furthermore, because the light-emitting element (LD) is densely aligned only in the desired region of the pixel region PXA in each pixel PXL, abnormal alignment defects where the light-emitting element (LD) is aligned in undesired regions can be prevented.

[0275] Therefore, the alignment distribution of the light-emitting elements LD becomes uniform for each pixel PXL, so the intensity (or amount) of light emitted from each pixel PXL can be substantially the same or similar to the intensity (or amount) of light emitted from adjacent pixels PXL. Thus, the display device according to embodiments of this disclosure can have a uniform light output distribution throughout the entire area.

[0276] In addition, by making the light-emitting elements (LDs) densely aligned only in the desired area of ​​the pixel region PXA of each pixel PXL, contact defects between each of the light-emitting elements (LDs) and the electrodes electrically and / or physically connected to the light-emitting elements (LDs) can be minimized.

[0277] ​ The manufacturing process is shown sequentially. ​ A schematic plan view of the pixel method shown. ​ The manufacturing process is shown sequentially. ​ A schematic cross-sectional view of the method of pixelation shown.

[0278] In the following text, based on the combination ​ as well as ​ The manufacturing method is described sequentially. ​ and ​ The pixels shown are those according to an embodiment of this disclosure. ​ as well as ​ In this section, the main differences from the above embodiments are described to avoid overlapping descriptions.

[0279] Reference ​ , ​ as well as ​ A pixel circuit layer PCL is formed on the substrate SUB.

[0280] The pixel circuit layer PCL may include a buffer layer BFL, a transistor T, a first power line PL1 and a second power line PL2, and a protective layer PSV.

[0281] Reference ​ , ​ , ​ , ​ as well as ​ A first dike pattern BNK1 is formed on the protective layer PSV. The first dike pattern BNK1 may include a first sub-dike pattern SBNK1 to a third sub-dike pattern SBNK3 arranged along the second direction DR2.

[0282] The first sub-dike patterns SBNK1 to the third sub-dike patterns SBNK3 can be located in the same column. The first sub-dike patterns SBNK1 to the third sub-dike patterns SBNK3 can be arranged to be spaced apart from each other in the second direction DR2. The distance d1 between each of the first sub-dike patterns SBNK1 to the third sub-dike patterns SBNK3 and its adjacent sub-dike pattern in the second direction DR2 can be determined within a range that minimizes defects (e.g., misalignment defects) in the alignment of the light-emitting elements LD in unintended areas. For example, each of the first sub-dike patterns SBNK1 to the third sub-dike patterns SBNK3 and its adjacent sub-dike pattern in the second direction DR2 can be spaced apart by a distance d1 equal to or greater than the length L of each of the light-emitting elements LD.

[0283] Reference ​ , ​ , ​ as well as ​ A first electrode EL1 to a third electrode EL3, comprising a conductive material (or substance) with high reflectivity, are formed on the first embankment pattern BNK1 and the protective layer PSV.

[0284] The first electrode EL1 can be electrically and / or physically connected to the first power line PL1 and the driving transistor Tdr through the first contact hole CH1. The second electrode EL2 can be electrically and / or physically connected to a third power line not shown. The third electrode EL3 can be electrically and / or physically connected to the second power line PL2 through the second contact hole CH2.

[0285] Each of the first electrode EL1 to the third electrode EL3 can include a first region A positioned between the first sub-bank pattern SBNK1 and the second sub-bank pattern SBNK2 and between the second sub-bank pattern SBNK2 and the third sub-bank pattern SBNK3, respectively, to not be overlapped with the first sub-bank pattern SBNK1 to the third sub-bank pattern SBNK3, and a second region B other than the first region A.

[0286] The first region A of each of the first electrode EL1 to the third electrode EL3 can include the concave portions CP1 and CP2, and can have at least two widths W1 in the first direction DR1 along the extension direction of the corresponding electrode. The second region B of each of the first electrode EL1 to the third electrode EL3 can have a constant width W2 in the first direction DR1. The first region A of each of the first electrode EL1 to the third electrode EL3 can be disposed on one surface (or upper surface) of the passivation layer PSV, and can include a flat portion. The second region B of each of the first electrode EL1 to the third electrode EL3 can include a flat portion disposed on one surface (or upper surface) of the passivation layer PSV and a portion protruding from the flat portion along the third direction DR3 according to the first sub-bank pattern SBNK1 to the third sub-bank pattern SBNK3. Accordingly, the surface profile change of the second region B of each of the first electrode EL1 to the third electrode EL3 in the third direction DR3 can be greater than the surface profile change of the first region A of the corresponding electrode in the third direction DR3.

[0287] Each of the first electrode EL1 to the third electrode EL3 can have a non-uniform width in the first direction DR1 along the extension direction when viewed in a plan view. Accordingly, a region (or gap) between two adjacent electrodes can have a non-uniform width in the first direction DR1 along the extension direction of the first electrode EL1 to the third electrode EL3. For example, the region between two adjacent electrodes can have at least two widths in the first direction DR1. A distance d2 in the first direction DR1 between the second regions B of two adjacent electrodes can be narrower than a distance d3 in the first direction DR1 between the first regions A of two adjacent electrodes.

[0288] Each of the first to third electrodes EL1 to EL3 can be commonly provided for the pixels PXL located in the same pixel column. For example, the first to third electrodes EL1 to EL3 provided for each pixel PXL can be commonly provided for the adjacent pixels PXL provided in the same pixel column as each pixel PXL.

[0289] With reference to ​ , ​ and ​ , an insulating material layer INSM is formed on the first to third electrodes EL1 to EL3 and the protective layer PSV. The insulating material layer INSM can be an inorganic insulating layer including an inorganic material or an organic insulating layer including an organic material.

[0290] Subsequently, a second bank pattern BNK2 is formed in the pixel region PXA of each pixel PXL. The second bank pattern BNK2 can be formed on the insulating material layer INSM. The second bank pattern BNK2 can be a pixel defining layer that defines (or divides) the pixel region (or emission region) of each pixel PXL and the pixel PXL adjacent thereto.

[0291] With reference to ​ , ​ , ​ and ​ , an electric field is formed between two adjacent electrodes by applying an alignment signal (or an alignment voltage) corresponding to each of the first to third electrodes EL1 to EL3.

[0292] Subsequently, in a state in which an electric field is formed between two adjacent electrodes, a mixed solution including a light emitting element LD is injected into the pixel region PXA of each of the pixels PXL using an inkjet printing method or the like. For example, an inkjet nozzle can be provided on the protective layer PSV, and a solvent mixed with a plurality of light emitting elements LD can be injected into the pixel region PXA of each of the pixels PXL through the inkjet nozzle. The method of injecting the light emitting element LD into the pixel region PXA of each of the pixels PXL is not limited to the above-described embodiment, and the method of injecting the light emitting element LD can be changed differently.

[0293] After the light emitting element LD is injected into the pixel region PXA of each of the pixels PXL, the solvent can be removed.

[0294] When the light emitting elements LD are injected into the pixel region PXA of each of the pixels PXL, self-alignment of the light emitting elements LD can be guided by the electric fields respectively formed between the first electrode EL1 and the second electrode EL2 and between the second electrode EL2 and the third electrode EL3. Accordingly, the first light emitting element LD1 can be aligned between the first electrode EL1 and the second electrode EL2, and the second light emitting element LD2 can be aligned between the second electrode EL2 and the third electrode EL3. In an embodiment of the present disclosure, the first light emitting element LD1 can be densely aligned between the second region B of the first electrode EL1 and the second region B of the second electrode EL2, and the second light emitting element LD2 can be densely aligned between the second region B of the second electrode EL2 and the second region B of the third electrode EL3.

[0295] The first light emitting element LD1 and the second light emitting element LD2 can be aligned between two adjacent electrodes on the insulating material layer INSM in the pixel region PXA of each of the pixels PXL. For example, the first light emitting element LD1 can be aligned on the insulating material layer INSM between the second region B of the first electrode EL1 and the second region B of the second electrode EL2, and the second light emitting element LD2 can be aligned on the insulating material layer INSM between the second region B of the second electrode EL2 and the second region B of the third electrode EL3.

[0296] Referring to ​ , ​ , ​ and ​ , after the light emitting elements LD are aligned in the pixel region PXA of each of the pixels PXL, a second insulating layer INS2 is formed on each of the light emitting elements LD. The second insulating layer INS2 can cover at least a portion of the upper surface of each of the light emitting elements LD to expose both ends of each of the light emitting elements LD other than the active layer 12 to the outside.

[0297] The first insulating layer INS1 including at least one opening OPN exposing one region of each of the first electrode EL1 to the third electrode EL3 is formed by etching the insulating material layer INSM through a process of forming the second insulating layer INS2 or an etching process performed before and after the process of forming the second insulating layer INS2.

[0298] When performing the process of forming the first insulating layer INS1 and the second insulating layer INS2, a portion of each of the first electrode EL1 and the second electrode EL2 can be removed, allowing each pixel PXL to be driven independently (or separately) from its adjacent pixels PXL. Therefore, each of the first electrode EL1 and the second electrode EL2 provided for each pixel PXL can be electrically and / or physically separated from the first electrode EL1 and the second electrode EL2 provided for adjacent pixels PXL located in the same pixel column.

[0299] Reference ​ , ​ , ​ as well as ​ First contact electrode CNE1 to third contact electrode CNE3 are formed on the second insulating layer INS2.

[0300] A first contact electrode CNE1 may be formed on the first electrode EL1 and may be stacked on one end of each of the first electrode EL1 and the first light-emitting element LD1. A second contact electrode CNE2 may be formed on the second electrode EL2 and may be stacked on the other end of the second electrode EL2, the first light-emitting element LD1, and the second light-emitting element LD2. A third contact electrode CNE3 may be formed on the third electrode EL3 and may be stacked on the other end of the third electrode EL3 and the second light-emitting element LD2.

[0301] Reference ​ , ​ as well as ​ An encapsulation layer ENC is formed covering the first contact electrode CNE1 to the third contact electrode CNE3. The encapsulation layer ENC may have a structure in which at least one inorganic layer and at least one organic layer are alternately stacked, but this disclosure is not limited thereto.

[0302] ​ An illustration is shown according to another embodiment. ​ The pixels are a schematic plan view that only includes a portion of the display element layer.

[0303] about ​ The pixels described herein primarily represent points that differ from those in the above embodiments, in order to avoid overlapping descriptions. Parts not specifically described in this disclosure are consistent with the above embodiments, and the same reference numerals indicate the same components, and similar reference numerals indicate similar components.

[0304] Reference ​ , ​ as well as ​The first bank pattern BNK1 and the first to third electrodes EL1 to EL3 can be disposed in the pixel area PXA of each of the pixels PXL. In an embodiment of the disclosure, the first bank pattern BNK1 can include a first to third sub-bank patterns SBNK1 to SBNK3.

[0305] Each of the first to third electrodes EL1 to EL3 can include a first area A1 located in an area between the sub-bank patterns so as not to be overlapped with the sub-bank patterns, and a second area B other than the first area A.

[0306] The first area A of each of the first to third electrodes EL1 to EL3 can be located between the first and second sub-bank patterns SBNK1 and SBNK2 and between the second and third sub-bank patterns SBNK2 and SBNK3, respectively, and can not be overlapped with the first to third sub-bank patterns SBNK1 to SBNK3. The second area B of each of the first to third electrodes EL1 to EL3 can be an area other than the first area A, and can include an area overlapped with the first to third sub-bank patterns SBNK1 to SBNK3.

[0307] The first area A of each of the first to third electrodes EL1 to EL3 can have at least two widths W1 in the first direction DR1 along an extension direction of the corresponding electrode. The second area B of each of the first to third electrodes EL1 to EL3 can have a constant width W2 in the first direction DR1 along the extension direction of the corresponding electrode.

[0308] The first area A of each of the first to third electrodes EL1 to EL3 can include a first and second concave portions CP1 and CP2 concaved toward an inner direction of the corresponding electrode. The first and second concave portions CP1 and CP2 can be disposed in a standardized shape (e.g., a polygonal shape). The first and second concave portions CP1 and CP2 may, for example, have a triangular shape as shown in FIG. 11A, can have a trapezoidal shape as shown in FIG. 11B, or can have a rectangular shape as shown in FIG. 11C. However, the shape of the first and second concave portions CP1 and CP2 is not limited to the above-described shapes, and can be modified differently according to design conditions of the display device or the like. ​ Figure 17b Figure 17c

[0309] ​​​The distance between the first area A of the first electrode EL1 including the first concave portion CP1 and the second concave portion CP2 and the first area A of the second electrode EL2 adjacent in the first direction DR1 can be wider than the distance d2 between the second area B of the first electrode EL1 and the second area B of the second electrode EL2. Also, the distance d3 between the first area A of the second electrode EL2 and the first area A of the third electrode EL3 adjacent in the first direction DR1 can be wider than the distance d2 between the second area B of the second electrode EL2 and the second area B of the third electrode EL3. That is, the distance d2 in the first direction DR1 between the second areas B of two adjacent electrodes can be narrower than the distance d3 in the first direction DR1 between the first areas A of two adjacent electrodes.

[0310] When the corresponding alignment signal (or alignment voltage) is applied to each of the first electrode EL1 to the third electrode EL3, a strong intensity electric field can be formed between the second areas B of two adjacent electrodes from among the first electrode EL1 to the third electrode EL3, and thus the light emitting element LD can be densely aligned between the second areas B of two adjacent electrodes. Finally, the light emitting element LD can be selectively aligned only in a desired area in the pixel area PXA of each of the pixels PXL.

[0311] Although the above has been described with reference to the preferred embodiments of the present disclosure, it will be understood by those skilled in the art or those with ordinary knowledge in the corresponding field that the present disclosure can be variously changed and modified without departing from the spirit and technical scope of the present disclosure described in the claims.

[0312] Therefore, the technical scope of the present disclosure should not be limited to what has been described in the above detailed description of the specific embodiments, but should be defined by the claims.

Claims

1. A display device, the display device comprising: The substrate comprises multiple pixel regions; as well as A pixel, set in each of the plurality of pixel regions. The pixel includes: a first electrode and a second electrode extending on the substrate in a first direction and spaced apart from each other in a second direction different from the first direction; a dam pattern disposed between the substrate and the first electrode and between the substrate and the second electrode, and including at least two sub-dam patterns located in the same column and spaced apart from each other; and a plurality of light-emitting elements disposed between the first electrode and the second electrode. Each of the first electrode and the second electrode has at least two widths along the extending direction in the second direction. Each of the first electrode and the second electrode includes a first region corresponding to the region between the at least two sub-dike patterns and a second region other than the first region. Wherein, the first region of each of the first electrode and the second electrode has at least two widths in the second direction along the extension direction of the first electrode and the second electrode, and the second region of each of the first electrode and the second electrode has a constant width in the second direction along the extension direction of the first electrode and the second electrode.

2. The display device according to claim 1, wherein, The first region of each of the first electrode and the second electrode has a width in the second direction that is less than or equal to the width of the second region of the corresponding electrode.

3. The display device according to claim 2, wherein, The width of the first region of the first electrode in the second direction and the width of the first region of the second electrode in the second direction are equal to each other, and The width of the second region of the first electrode in the second direction and the width of the second region of the second electrode in the second direction are equal to each other.

4. The display device according to claim 1, wherein, The first region of each of the first electrode and the second electrode includes a recessed portion that is recessed in the second direction, such that the width of the first region in the second direction decreases along the extension direction of the corresponding electrode.

5. The display device according to claim 4, wherein, The recessed portion includes a non-square boundary.

6. The display device according to claim 4, wherein, The recessed portion has a polygonal shape or a circular curved surface shape.

7. The display device according to claim 6, wherein, When viewed in a plan view, the distance between the first electrode and the second electrode in the second direction has at least two widths along the extending directions of the first electrode and the second electrode.

8. The display device according to claim 7, wherein, The recessed portion of the first electrode and the recessed portion of the second electrode face each other.

9. The display device according to claim 8, wherein, The distance between the first region of the first electrode and the first region of the second electrode in the second direction is greater than the distance between the second region of the first electrode and the second region of the second electrode in the second direction.

10. The display device according to claim 1, wherein, Two adjacent sub-dike patterns in the first direction are spaced apart from each other by a distance equal to or greater than the length of each of the plurality of light-emitting elements in the extension direction of each of the plurality of light-emitting elements disposed between the first electrode and the second electrode.

11. The display device according to claim 10, wherein, The sub-dike patterns are identical to each other.

12. The display device according to claim 1, wherein, When viewed in cross-section, the first region and the second region of each of the first electrode and the second electrode have different surface profiles.

13. The display device according to claim 1, wherein, The pixels also include: A first contact electrode is provided to electrically connect the first electrode to one end of each of the plurality of light-emitting elements; and The second contact electrode electrically connects the second electrode to the other end of each of the plurality of light-emitting elements.

14. A display device, the display device comprising: A substrate includes a display area and a non-display area, the display area including a plurality of pixel areas, and the non-display area surrounding at least one side of the display area; as well as A pixel, set in each of the plurality of pixel regions. The pixel includes a pixel circuit layer disposed on the substrate and a display element layer disposed on the pixel circuit layer. The pixel circuit layer includes at least one transistor disposed on the substrate, a power line electrically connected to the transistor, and a protective layer disposed on the power line. The display element layer includes: a first electrode and a second electrode, the first electrode and the second electrode extending in a first direction and spaced apart from each other in a second direction different from the first direction; a dam pattern disposed between the protective layer and the first electrode and between the protective layer and the second electrode, and including a first sub-dam pattern to a third sub-dam pattern arranged along the first direction and located in the same column; a plurality of light-emitting elements disposed between the first electrode and the second electrode; a first contact electrode electrically connecting one end of the first electrode and each of the plurality of light-emitting elements; and a second contact electrode electrically connecting the second electrode to the other end of each of the plurality of light-emitting elements. Wherein, the first sub-dike pattern to the third sub-dike pattern are spaced apart from each other, and Each of the first electrode and the second electrode has at least two widths along the extending direction in the second direction. Each of the first electrode and the second electrode includes a first region corresponding to the region between the first sub-dike pattern and the third sub-dike pattern, and a second region other than the first region. The first region of each of the first electrode and the second electrode has at least two widths along the extending direction of the first electrode and the second electrode, and the second region of each of the first electrode and the second electrode has a constant width along the extending direction of the first electrode and the second electrode.

15. The display device according to claim 14, wherein, The first region of each of the first electrode and the second electrode includes a recessed portion that is recessed in the second direction, such that the width of the first region in the second direction decreases along the extension direction of the corresponding electrode.

16. The display device according to claim 15, wherein, The recessed portion has a polygonal shape or a circular curved surface shape.

17. The display device according to claim 14, wherein, The distance between the first electrode and the second electrode in the second direction has at least two widths along the extending directions of the first electrode and the second electrode.

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