Display substrate, preparation method thereof and display device

Abstract

The present disclosure provides a display substrate, a manufacturing method thereof, and a display device. The display substrate includes a display area and an edge area located at a periphery of the display area; the edge area includes a composite insulating layer disposed on a base, a power line disposed on the composite insulating layer, and an isolation dam disposed on the power line, the isolation dam is provided with an auxiliary power line, and the auxiliary power line located at a side of the isolation dam adjacent to the display area and the auxiliary power line located at a side of the isolation dam away from the display area are both overlapped on the power line.

Description

Technical Field

[0001] This disclosure relates to, but is not limited to, the field of display technology, and particularly to a display substrate, a method for preparing the same, and a display device. Background Technology

[0002] Organic light-emitting diodes (OLEDs) are active-matrix display devices with advantages such as self-illumination, wide viewing angle, high contrast, low power consumption, extremely fast response speed, thinness, flexibility, and low cost. With the continuous development of display technology, flexible displays using OLEDs as the light-emitting device and thin-film transistors (TFTs) for signal control have become the mainstream products in the display field. Summary of the Invention

[0003] The following is an overview of the subject matter described in detail herein. This overview is not intended to limit the scope of the claims.

[0004] This disclosure provides a display substrate, including a display area and an edge area surrounding the display area; the edge area includes a composite insulating layer disposed on a substrate, a power line disposed on the composite insulating layer, and an isolation dam disposed on the power line, wherein an auxiliary power line is disposed in the isolation dam, and the auxiliary power line located on the side of the isolation dam adjacent to the display area and the auxiliary power line located on the side of the isolation dam away from the display area are both connected to the power line.

[0005] In an exemplary embodiment, the isolation dam includes a first isolation dam and a second isolation dam. The second isolation dam is disposed on the power line, and the first isolation dam is disposed on an auxiliary power line on the side of the second isolation dam adjacent to the display area. The auxiliary power line is disposed in the second isolation dam, and the auxiliary power line on the side of the second isolation dam adjacent to the display area and the auxiliary power line on the side of the second isolation dam away from the display area are both connected to the power line.

[0006] In an exemplary embodiment, the edge region further includes a second connection electrode, which is disposed in the first isolation dam. The second connection electrode located on the side of the first isolation dam adjacent to the display area and the second connection electrode located on the side of the first isolation dam away from the display area are both connected to the auxiliary power line.

[0007] In an exemplary embodiment, the second isolation dam further includes a first dam base, a third dam base, and a fifth dam base; the first dam base is disposed on the power line, and the first dam base includes a first surface away from the power line, a first proximal side adjacent to the display area, and a first distal side away from the display area; the auxiliary power line covers the first surface, the first proximal side, and the first distal side of the first dam base; the third dam base is disposed on the auxiliary power line covering the first surface, and the fifth dam base is disposed on the third dam base.

[0008] In an exemplary embodiment, the second isolation dam further includes a first dam base, a third dam base, and a fifth dam base; the first dam base is disposed on the power line, and the first dam base includes a first surface away from the power line, a first proximal surface adjacent to the display area, and a first distal surface away from the display area; the auxiliary power line covers the first proximal surface and the first distal surface of the first dam base, and partially covers the first surface of the first dam base; the third dam base is disposed on the auxiliary power line that partially covers the first surface, and the fifth dam base is disposed on the third dam base; or, the auxiliary power line covers the first proximal surface and the first distal surface of the first dam base, the third dam base is disposed on the first surface of the first dam base, and the fifth dam base is disposed on the third dam base.

[0009] In an exemplary embodiment, a first venting structure is provided on the auxiliary power line in the second isolation dam.

[0010] In an exemplary embodiment, the first venting structure includes at least one first through hole, the first length of the first through hole being 80% to 100% of the first length of the first surface, the second length of the first through hole being 20% ​​to 60% of the first length of the first through hole, and the spacing between adjacent first through holes being 20% ​​to 60% of the first length of the first through hole; the first length is a characteristic dimension of the second isolation dam along the direction away from the display area, and the second length is a characteristic dimension along the extension direction of the second isolation dam.

[0011] In an exemplary embodiment, the first isolation dam further includes a second dam base and a fourth dam base; the second dam base is disposed on the auxiliary power line, and the second dam base includes a second surface away from the power line, a second proximal side adjacent to the display area, and a second distal side away from the display area; the second connecting electrode covers the second surface, the second proximal side, and the second distal side of the second dam base; the fourth dam base is disposed on the second connecting electrode covering the second surface.

[0012] In an exemplary embodiment, the first isolation dam further includes a second dam base and a fourth dam base; the second dam base is disposed on the auxiliary power line, and the second dam base includes a second surface away from the power line, a second proximal surface adjacent to the display area, and a second distal surface away from the display area; the second connecting electrode covers the second proximal surface and the second distal surface of the second dam base, and partially covers the second surface of the second dam base, and the fourth dam base is disposed on the second connecting electrode that partially covers the second surface; or, the second connecting electrode covers the second proximal surface and the second distal surface of the second dam base, and the fourth dam base is disposed on the second surface of the second dam base.

[0013] In an exemplary embodiment, a second venting structure is provided on the second connecting electrode in the first isolation dam.

[0014] In an exemplary embodiment, the second venting structure includes at least one second through hole, the first length of the second through hole being 80% to 100% of the first length of the second surface, the second length of the second through hole being 20% ​​to 60% of the first length of the second through hole, and the spacing between adjacent second through holes being 20% ​​to 60% of the first length of the second through hole; the first length is a characteristic dimension along the direction away from the display area of ​​the first isolation dam, and the second length is a characteristic dimension along the extension direction of the first isolation dam.

[0015] In an exemplary embodiment, the second isolation dam further includes a first passivated dam base; the first passivated dam base is disposed on the power line, and the first dam base is disposed on the first passivated dam base.

[0016] In an exemplary embodiment, the first isolation dam further includes a second passivated dam base; the second passivated dam base is disposed on the power line, and the auxiliary power line covers the second passivated dam base; the second dam base is disposed on the auxiliary power line covering the second passivated dam base.

[0017] In an exemplary embodiment, the first isolation dam further includes a second passivated dam base, and the second isolation dam further includes a first passivated dam base; the second passivated dam base is disposed on the power line, the auxiliary power line covers the second passivated dam base, and the second dam base is disposed on the auxiliary power line covering the second passivated dam base; the first passivated dam base is disposed on the power line, and the first dam base is disposed on the first passivated dam base.

[0018] In an exemplary embodiment, the first isolation dam further includes a flat dam foundation; the flat dam foundation is disposed on the power line, and the auxiliary power line covers the flat dam foundation; the second dam foundation is disposed on the auxiliary power line covering the flat dam foundation.

[0019] In an exemplary embodiment, the flat dam foundation is disposed in the same layer as the first dam foundation, and the thickness of the flat dam foundation is 30% to 70% of the thickness of the first dam foundation.

[0020] In an exemplary embodiment, the display area includes a driving structure layer disposed on a substrate and a light-emitting element disposed on the driving structure layer; the power line is disposed in the same layer as the first source / drain metal layer of the driving structure layer, the auxiliary power line is disposed in the same layer as the second source / drain metal layer of the driving structure layer, and the second connecting electrode is disposed in the same layer as the anode of the light-emitting element.

[0021] This disclosure also provides a display device, including the aforementioned display substrate.

[0022] This disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and an edge area located around the display area; the fabrication method includes:

[0023] A composite insulation layer and power lines disposed on the composite insulation layer are formed in the edge region of the substrate;

[0024] An isolation dam is formed on the side of the power line away from the substrate. An auxiliary power line is provided in the isolation dam. The auxiliary power line located on the side of the isolation dam adjacent to the display area and the auxiliary power line located on the side of the isolation dam away from the display area are both connected to the power line.

[0025] In an exemplary embodiment, an isolation dam is formed on the power line, and an auxiliary power line is provided in the isolation dam, including:

[0026] A first dam foundation is formed on the power line;

[0027] An auxiliary power line is formed on the power line and the first dam foundation. The auxiliary power line is connected to the power line on a first side adjacent to the display area and a second side away from the display area. The auxiliary power line between the first side and the second side covers the first dam foundation.

[0028] A second dam base and a third dam base are formed. The third dam base is set on the auxiliary power line covering the first dam base, and the second dam base is set on the auxiliary power line between the first dam base and the display area.

[0029] A second connection electrode is formed to connect with the auxiliary power line, and the second connection electrode covers the second dam foundation;

[0030] A fourth dam foundation and a fifth dam foundation are formed. The fourth dam foundation is disposed on the second connecting electrode covering the second dam foundation, and the fifth dam foundation is disposed on the third dam foundation. The second dam foundation, the second connecting electrode and the fourth dam foundation form a first isolation dam, and the first dam foundation, the auxiliary power line, the third dam foundation and the fifth dam foundation form a second isolation dam.

[0031] After reading and understanding the accompanying diagrams and detailed descriptions, the other aspects can be understood. Attached Figure Description

[0032] The accompanying drawings are provided to further illustrate the technical solutions of this disclosure and form part of the specification. They are used together with the embodiments of this disclosure to explain the technical solutions of this disclosure and do not constitute a limitation on the technical solutions of this disclosure. The shapes and sizes of the components in the drawings do not reflect actual proportions and are only intended to illustrate the content of this disclosure.

[0033] Figure 1 This is a schematic diagram of the structure of a display substrate;

[0034] Figure 2 This is a schematic diagram of an equivalent circuit for an OLED pixel driving circuit.

[0035] Figure 3 This is a schematic diagram of the structure of the edge region of a display substrate;

[0036] Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0037] Figure 5 for Figure 4 Sectional view along the middle AA direction;

[0038] Figure 6 This is a schematic diagram showing the pattern of the driving structure layer and the circuit structure layer after the present disclosure is formed;

[0039] Figure 7 for Figure 6 Sectional view along the middle AA direction;

[0040] Figure 8 This is a schematic diagram showing the pattern of the fifth insulating layer after it has been formed according to this disclosure;

[0041] Figure 9 for Figure 8 Sectional view along the middle AA direction;

[0042] Figure 10 This is a schematic diagram showing the formation of the first planarization layer pattern according to this disclosure;

[0043] Figure 11 for Figure 10 Sectional view along the middle AA direction;

[0044] Figure 12 This is a schematic diagram showing the formation of the second source / drain metal layer pattern according to this disclosure;

[0045] Figure 13 for Figure 12 Sectional view along the middle AA direction;

[0046] Figure 14 for Figure 12 Sectional view along the BB direction;

[0047] Figure 15 This is a schematic diagram showing the second planarization layer pattern formed according to the present disclosure;

[0048] Figure 16 for Figure 15 Sectional view along the middle AA direction;

[0049] Figure 17 This is a schematic diagram showing the anode and second connecting electrode patterns formed according to this disclosure;

[0050] Figure 18 for Figure 17 Sectional view along the middle AA direction;

[0051] Figure 19 for Figure 17 Sectional view along the BB direction;

[0052] Figure 20 This is a schematic diagram showing the pixel definition layer and isolation pillar pattern formed according to this disclosure;

[0053] Figure 21 for Figure 20 Sectional view along the middle AA direction;

[0054] Figure 22 This is a schematic diagram showing the organic light-emitting layer and cathode pattern formed according to the present disclosure;

[0055] Figure 23 for Figure 22 Sectional view along the middle AA direction;

[0056] Figure 24 This is an enlarged view of the second isolation dam disclosed in this publication;

[0057] Figure 25 This is a schematic diagram of the structure of another display substrate as an exemplary embodiment of the present disclosure;

[0058] Figure 26 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0059] Figure 27 This is a schematic diagram of the structure of another display substrate as an exemplary embodiment of the present disclosure.

[0060] Explanation of reference numerals in the attached figures:

[0061] 1—Glass carrier plate; 10—Substrate; 11—First insulating layer;

[0062] 12—Second insulating layer; 13—Third insulating layer; 14—Fourth insulating layer;

[0063] 15—Fifth insulating layer; 16—First planarization layer; 17—Second planarization layer;

[0064] 21—Anode; 22—Pixel definition layer; 23—Isolation pillar;

[0065] 24—Organic light-emitting layer; 25—Cathode; 26—Encapsulation layer;

[0066] 100—Display area; 101—First transistor; 102—Second transistor;

[0067] 103—Third transistor; 104—First storage capacitor; 105—Second storage capacitor;

[0068] 106—First connecting electrode; 107—Second connecting electrode; 200—Binding area;

[0069] 300—Edge area; 301—Circuit area; 302—Isolation dam area;

[0070] 303—Cracked dam area; 304—Cut zone; 310—Power line;

[0071] 320—Auxiliary power supply line; 401—First dam foundation; 402—Second dam foundation;

[0072] 403—Third dam foundation; 404—Fourth dam foundation; 405—Fifth dam foundation;

[0073] 410—First isolation dam; 411—First passivated dam foundation; 420—Second isolation dam;

[0074] 421—Second passivated dam foundation; 431—Plain dam foundation. Detailed Implementation

[0075] To make the objectives, technical solutions, and advantages of this disclosure clearer, embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. Note that the implementation methods can be carried out in many different forms. Those skilled in the art will readily understand that the methods and content can be varied in various forms without departing from the spirit and scope of this disclosure. Therefore, this disclosure should not be construed as limited to the content described in the following embodiments. Without conflict, the embodiments and features in the embodiments of this disclosure can be arbitrarily combined with each other.

[0076] In the accompanying drawings, the size of the constituent elements, the thickness of the layers, or the area are sometimes exaggerated for clarity. Therefore, one aspect of this disclosure is not necessarily limited to these dimensions, and the shapes and sizes of the components in the drawings do not reflect true proportions. Furthermore, the drawings schematically illustrate ideal examples, and one aspect of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0077] The ordinal numbers “first,” “second,” and “third” used in this specification are used to avoid confusion among the constituent elements, not to limit their quantity.

[0078] In this specification, for convenience, terms such as "middle," "upper," "lower," "front," "rear," "vertical," "horizontal," "top," "bottom," "inner," and "outer" are used to indicate orientation or positional relationships in conjunction with the accompanying drawings. This is solely for the purpose of facilitating the description and simplification, and does not imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, it should not be construed as a limitation of this disclosure. The positional relationships of the constituent elements may be appropriately varied depending on the orientation of each constituent element being described. Therefore, the use of terms not limited to those described in the specification may be appropriately replaced as needed.

[0079] In this specification, unless otherwise expressly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they may refer to a fixed connection, a detachable connection, or an integral connection; a mechanical connection or an electrical connection; a direct connection, an indirect connection via an intermediate component, or a connection within two components. Those skilled in the art will understand the specific meaning of these terms in this disclosure based on the specific circumstances.

[0080] In this specification, a transistor is a device that includes at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region through which current primarily flows.

[0081] In this specification, the first electrode can be the drain electrode and the second electrode can be the source electrode, or vice versa. In cases where transistors with opposite polarities are used or the current direction changes during circuit operation, the functions of the "source electrode" and "drain electrode" may sometimes be interchanged. Therefore, in this specification, the "source electrode" and "drain electrode" can be interchanged.

[0082] In this specification, "electrical connection" includes the situation where components are connected together by elements that have a certain electrical function. There are no particular limitations on what constitutes an "electrical function," as long as it allows for the transmission and reception of electrical signals between the connected components. Examples of "electrical functions" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements with various functions.

[0083] In this specification, "parallel" refers to the state where the angle formed by two straight lines is greater than or equal to -10° and less than 10°, and therefore also includes the state where the angle is greater than or equal to -5° and less than 5°. Similarly, "perpendicular" refers to the state where the angle formed by two straight lines is greater than or equal to 80° and less than 100°, and therefore also includes the state where the angle is greater than or equal to 85° and less than 95°.

[0084] In this specification, the terms "film" and "layer" may be interchanged. For example, "conductive layer" may sometimes be replaced with "conductive film." Similarly, "insulating film" may sometimes be replaced with "insulating layer."

[0085] In this disclosure, “about” means a value that is not strictly limited and allows for process and measurement errors.

[0086] Figure 1 This is a schematic diagram of the structure of a display substrate. (Example) Figure 1 As shown, in an exemplary embodiment, the display substrate includes a display area 100, a bonding area 200 located on one side of the display area 100, and an edge area 300 located on the other sides of the display area 100. The display area 100 includes at least a plurality of regularly arranged display units (sub-pixels), the bonding area 200 includes at least an isolation dam and a bonding circuit that connects the signal lines of the plurality of display units to an external driving device, and the edge area 300 includes at least an isolation dam, a gate driving circuit, and a second power line VSS that transmits voltage signals to the plurality of display units. The isolation dam of the bonding area 200 and the edge area 300 forms a ring structure surrounding the display area 100.

[0087] In an exemplary embodiment, within a plane perpendicular to the display substrate, the display unit includes a driving structure layer disposed on the substrate, a light-emitting element disposed on the driving structure layer, and an encapsulation layer disposed on the light-emitting element. The driving structure layer includes a pixel driving circuit, the light-emitting element is connected to the pixel driving circuit, the light-emitting element is configured to emit light, and the pixel driving circuit is configured to drive the light-emitting element. In an exemplary embodiment, the pixel driving circuit may include multiple thin-film transistors (TFTs) and storage capacitors, such as 3T1C, 4T1C, 5T1C, 6T1C, or 7T1C, etc., which are not limited in this disclosure.

[0088] Figure 2 This is a schematic diagram of an equivalent circuit for an OLED pixel driving circuit, illustrating a 3T1C driving structure. For example... Figure 2 As shown, the pixel driving circuit is electrically connected to the first scan line GN, the second scan line SN, the data line DN, the first power supply line VDD, and the compensation line SE. The pixel driving circuit includes a first transistor T1, a second transistor T2, a third transistor T3, and a storage capacitor C. ST In an exemplary embodiment, the first transistor T1 is a driving transistor, the second transistor T2 is a switching transistor, and the third transistor T3 is a compensation transistor. In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second electrode of the second transistor T2 and the storage capacitor C. ST The first terminal of the first transistor T1 is connected to the first power supply line VDD, and the second terminal of the first transistor T1 is connected to the storage capacitor C. ST The second electrode of the first transistor T1 and the second electrode of the third transistor T3 are connected. The gate electrode of the second transistor T2 is connected to the scan line GN, and the first electrode of the second transistor T2 is connected to the data line DN. The gate electrode of the third transistor T3 is connected to the second scan line SN, and the first electrode of the third transistor T3 is connected to the compensation line SE. The anode of the OLED is connected to the second electrode of the first transistor T1, and the cathode of the OLED is connected to the second power line VSS. The OLED is configured to emit light of corresponding brightness in response to the current at the second electrode of the first transistor T1. In an exemplary embodiment, the third transistor T3 can extract the threshold voltage Vth and mobility of the first transistor T1 in response to the compensation timing to compensate for the threshold voltage Vth, and the storage capacitor C ST Configured to maintain the voltage of nodes N1 and N2 within one frame of emission cycle.

[0089] Figure 3 This is a schematic diagram of the structure of the edge region of a display substrate. Figure 1 A magnified view of region C. (See image below.) Figure 3As shown, in a plane parallel to the display substrate, the edge region 300 includes a circuit region 301, an isolation dam region 302, a crack dam region 303, and a cutting region 304 sequentially arranged along a direction away from the display region 100. In an exemplary embodiment, the circuit region 301 includes at least a gate driving circuit, which is connected to a first scan line and a second scan line of the pixel driving circuit in the display region 100. The isolation dam region 302 includes at least a power line 310, a first isolation dam 410, and a second isolation dam 420. The power line 310 extends along a direction parallel to the edge 110 of the display region and is connected to a second power line VSS of the pixel driving circuit in the display region 100. The first isolation dam 410 and the second isolation dam 420 extend along a direction parallel to the edge 110 of the display region and are configured to block moisture from entering the display region 100 from the edge region 300. The distance between the first isolation dam 410 and the edge 110 of the display area is less than the distance between the second isolation dam 420 and the edge 110 of the display area; that is, the second isolation dam 420 is located on the side of the first isolation dam 410 away from the display area 100. In an exemplary embodiment, the crack dam area 303 includes a plurality of cracks disposed on the composite insulating layer. The plurality of cracks are configured to reduce the stress on the display area 100 and the circuit area 301 during the cutting process, avoid affecting the film structure of the display area 100 and the circuit area 301, and prevent the cracks from propagating in the direction of the display area 100 and the circuit area 301. In an exemplary embodiment, the cutting area 304 includes a cutting groove disposed on the composite insulating layer. The cutting groove is configured such that after all the film layers of the display substrate are prepared, the cutting equipment cuts along the cutting groove respectively. In an exemplary embodiment, the edge 110 of the display area is the edge of the display area 100 adjacent to the edge area 300.

[0090] In an exemplary embodiment, the low voltage (VSS) required by the pixel driving circuit in the display area 100 is introduced from the bonding pads of the bonding area 200, passes through the bonding area 200, enters the edge area 300, and is delivered to the second power line VSS of each pixel driving circuit through the ring-shaped power line 310 in the edge area 300. Because the power line has a certain impedance, there is a voltage drop during voltage signal transmission. Therefore, the voltage of the power line 310 farther from the bonding area 200 is lower than the voltage of the power line 310 closer to the bonding area 200. This voltage loss in the power line 310 reduces the uniformity of display brightness in the display area, which has become a significant factor affecting high-quality display.

[0091] To improve the uniformity of display brightness, this disclosure provides a display substrate. On a plane parallel to the display substrate, the display substrate includes a display area and an edge area located around the display area. The edge area includes a composite insulating layer disposed on a substrate, power lines disposed on the composite insulating layer, and an isolation dam disposed on the power lines. An auxiliary power line is disposed in the isolation dam, and the auxiliary power line located on the side of the isolation dam adjacent to the display area and the auxiliary power line located on the side of the isolation dam away from the display area are both connected to the power lines.

[0092] In an exemplary embodiment, the isolation dam includes a first isolation dam and a second isolation dam. The second isolation dam is disposed on the power line, and the first isolation dam is disposed on an auxiliary power line on the side of the second isolation dam adjacent to the display area. The auxiliary power line is disposed in the second isolation dam, and the auxiliary power line on the side of the second isolation dam adjacent to the display area and the auxiliary power line on the side of the second isolation dam away from the display area are both connected to the power line.

[0093] In an exemplary embodiment, the edge region further includes a second connection electrode, which is disposed in the first isolation dam. The second connection electrode located on the side of the first isolation dam adjacent to the display area and the second connection electrode located on the side of the first isolation dam away from the display area are both connected to the auxiliary power line.

[0094] In an exemplary embodiment, the second isolation dam may include a first dam foundation, an auxiliary power line, a third dam foundation, and a fifth dam foundation, or may include a first passivated dam foundation, a first dam foundation, an auxiliary power line, a third dam foundation, and a fifth dam foundation.

[0095] In an exemplary embodiment, the auxiliary power line in the second isolation dam is provided with a first venting structure.

[0096] In an exemplary embodiment, the first isolation dam may include a second dam base, a second connecting electrode, and a fourth dam base, or may include a second passivated dam base, an auxiliary power line, a second dam base, a second connecting electrode, and a fourth dam base, or may include a flat dam base, an auxiliary power line, a second dam base, a second connecting electrode, and a fourth dam base.

[0097] In an exemplary embodiment, the second connecting electrode in the first isolation dam is provided with a second venting structure.

[0098] The display area includes a driving structure layer disposed on a substrate and a light-emitting element disposed on the driving structure layer; the power line is disposed in the same layer as the first source / drain metal layer of the driving structure layer, the auxiliary power line is disposed in the same layer as the second source / drain metal layer of the driving structure layer, and the second connecting electrode is disposed in the same layer as the anode of the light-emitting element.

[0099] In an exemplary embodiment, the first dam base is disposed on the same layer as the first flat layer of the driving structure layer, the second and third dam bases are disposed on the same layer as the second flat layer of the driving structure layer, the fourth and fifth dam bases are disposed on the same layer as the pixel definition layer of the light-emitting element, and the composite insulating layer includes a first insulating layer, a second insulating layer, a third insulating layer and a fourth insulating layer stacked together.

[0100] In an exemplary embodiment, the first passivated dam base and the second passivated dam base are disposed in the same layer as the fifth insulating layer, and the flat dam base is disposed in the same layer as the first dam base, wherein the thickness of the flat dam base is 30% to 70% of the thickness of the first dam base.

[0101] In an exemplary embodiment, the edge region includes a circuit area, an isolation dam area, a crack dam area, and a cutting area arranged sequentially along a direction away from the display area. The power line, auxiliary power line, and isolation dam are disposed in the isolation dam area, the crack dam area is provided with a crack dam, and the cutting area is provided with a cutting groove.

[0102] This disclosure provides a display substrate that achieves a parallel double-layer power trace structure by forming power lines and auxiliary power lines in the edge region. This reduces the resistance of the power trace in the edge region, minimizes the voltage drop of the voltage signal, improves the uniformity of display brightness in the display area, and enhances the display quality.

[0103] Figure 4 This is a schematic diagram of the structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 5 for Figure 4 The cross-sectional view along line AA illustrates the cross-sectional structure of the display area and peripheral area of ​​a top-emitting OLED. According to the light emission direction, OLEDs can be divided into bottom-emitting, top-emitting, and bifacial-emitting types. Compared with bottom-emitting OLEDs, top-emitting OLEDs have advantages such as high aperture ratio, high color purity, and ease of achieving high resolution (Pixels Per Inch, PPI), and are gradually becoming the mainstream structure. For top-emitting OLEDs, since the light emission direction is on the cathode side, the cathode needs to be very thin to ensure good light transmittance. Therefore, the voltage drop of the low-voltage power supply line 310 providing the cathode has a significant impact on improving the uniformity of display brightness.

[0104] like Figure 4 and Figure 5As shown, and in combination Figures 6 to 24 The exemplary embodiment of this disclosure shows that the display substrate includes a display area 100 and an edge area 300. The edge area 300 includes a circuit area 301, an isolation dam area 302, a crack dam area 303 and a cutting area 304 arranged sequentially along a direction away from the display area 100.

[0105] In an exemplary embodiment, the display area 100 of the display substrate includes:

[0106] Base 10;

[0107] A first insulating layer 11 disposed on the substrate 10;

[0108] A semiconductor layer disposed on the first insulating layer 11, the semiconductor layer including at least a first active layer;

[0109] Second insulating layer 12 covering the semiconductor layer;

[0110] A first gate metal layer is disposed on the second insulating layer 12, the first gate metal layer including at least a first gate electrode;

[0111] A third insulating layer 13 and a fourth insulating layer 14 covering the first gate metal layer are provided thereon, and two first vias are provided thereon to expose the first active layer.

[0112] A first source / drain metal layer is disposed on the fourth insulating layer 14. The first source / drain metal layer includes at least a first source electrode and a first drain electrode. The first source electrode and the first drain electrode are respectively connected to the first active layer through a first via.

[0113] A fifth insulating layer 15 and a first planarization layer 16 covering the first source and drain metal layers are provided thereon, and a second via is provided thereon to expose the first drain electrode.

[0114] A first connection electrode 106 is disposed on the first planarization layer 16, and the first connection electrode 106 is connected to the first drain electrode through a second via.

[0115] A second planarization layer 17 covers the first connecting electrode 106, and a third via is provided thereon to expose the first connecting electrode 106;

[0116] An anode 21 is disposed on the second planarization layer 17, and the anode 21 is connected to the first connecting electrode 106 through a third via.

[0117] A pixel definition layer 22 is provided on the anode 21, and the pixel definition layer 22 is provided with pixel openings that expose the anode 21;

[0118] An organic light-emitting layer 24 is disposed within the pixel opening, and the organic light-emitting layer 24 is connected to the anode 22;

[0119] A cathode 25 is provided on the organic light-emitting layer 24 and the pixel definition layer 22, and the cathode 25 is connected to the organic light-emitting layer 24.

[0120] The encapsulation layer 26 covering the above structure is a stacked structure of inorganic material / organic material / inorganic material.

[0121] In an exemplary embodiment, the edge region 300 of the display substrate includes:

[0122] Base 10;

[0123] A first insulating layer 11 disposed on the substrate 10;

[0124] A semiconductor layer disposed on the first insulating layer 11, the semiconductor layer including at least a second active layer and a third active layer located in the circuit region 301;

[0125] Second insulating layer 12 covering the semiconductor layer;

[0126] A first gate metal layer is disposed on the second insulating layer 12, the first gate metal layer including at least a second gate electrode, a third gate electrode, a first capacitor electrode and a second capacitor electrode located in the circuit region 301;

[0127] A third insulating layer 13 covering the first gate metal layer;

[0128] A second gate metal layer is disposed in the third insulating layer 13, the second gate metal layer including at least a third capacitor electrode and a fourth capacitor electrode located in the circuit region 301;

[0129] The fourth insulating layer 14 covering the second gate metal layer is provided with a plurality of first vias exposing the second active layer and the third active layer on the fourth insulating layer 14 of the circuit region 301. The fourth insulating layer 14 of the crack dam region 303 forms a crack dam 31 including a plurality of cracks. The fourth insulating layer 14 of the cutting region 304 forms a cutting groove 32 including a first groove and a second groove.

[0130] A first source / drain metal layer is disposed on the fourth insulating layer 14. The first source / drain metal layer includes at least a second source electrode, a second drain electrode, a third source electrode, and a third drain electrode located in the circuit region 301, and a power line 310 located in the isolation dam region 302. The second source electrode and the second drain electrode are respectively connected to the second active layer through a first via, and the third source electrode and the third drain electrode are respectively connected to the third active layer through a first via.

[0131] The fifth insulating layer 15 covering the first source / drain metal layer, the fifth insulating film of the crack dam area 303 and the cutting area 304 are removed, and the fifth insulating layer 15 of the isolation dam area 302 covers the edge of the power line 310.

[0132] A first flat layer 16 is disposed in the circuit area 301, the crack dam area 303 and the cutting area 304, and a first dam foundation 401 is formed in the isolation dam area 302; the first flat layer 16 in the circuit area 301 is disposed on the fifth insulating layer 15, the first flat layer 16 in the crack dam area 303 completely fills the crack dam 31, the first flat layer 16 in the cutting area 304 completely fills the groove 32, and the first dam foundation 401 in the isolation dam area 302 is disposed on the power line 310;

[0133] An auxiliary power line 320 is installed in the isolation dam area 302. The auxiliary power line 320 covers the first surface of the first dam foundation 401 away from the power line 310, the first near side of the first dam foundation 401 adjacent to the display area 100, and the first far side of the first dam foundation 401 away from the display area 100. The auxiliary power line 320 on the side of the first dam foundation 401 adjacent to the display area 100 and the auxiliary power line 320 on the side of the first dam foundation 401 away from the display area 100 are both connected to the power line 310. A first venting structure is provided on the auxiliary power line 320 covering the first surface of the first dam foundation 401.

[0134] A second flat layer 17 is provided in the circuit area 301, and a second dam base 402 and a third dam base 403 are provided in the isolation dam area 302. The third dam base 403 is provided on the auxiliary power line 320 covering the first surface, and the second dam base 402 is provided on the auxiliary power line 320 on the side of the first dam base 401 adjacent to the display area 100.

[0135] The second connecting electrode 107 is disposed in the circuit area 301 and the isolation dam area 302. The second connecting electrode 107 in the circuit area 301 is disposed on the second planarization layer 17, and a plurality of fourth vias are disposed thereon. The second connecting electrode 107 in the isolation dam area 302 covers the second surface of the second dam base 402 away from the power line 310, the second near side of the second dam base 402 adjacent to the display area 100, and the second far side of the second dam base 402 away from the display area 100, and also covers part of the surface of the third dam base 403. The second connecting electrode 107 located on the side of the second dam base 402 adjacent to the display area 100 and the second connecting electrode 107 located on the side of the second dam base 402 away from the display area 100 are both connected to the auxiliary power line 320. The second connecting electrode 107 covering the second surface of the second dam base 402 is provided with a second venting structure.

[0136] Multiple isolation pillars 23 are provided in the circuit area 301, and a fourth dam base 404 and a fifth dam base 405 are provided in the isolation dam area 302; the positions of the multiple isolation pillars 23 correspond to the positions of the multiple fourth vias provided on the second connecting electrode 107, and the second connecting electrode 107 is exposed between adjacent isolation pillars 23; the fourth dam base 404 is provided on the second connecting electrode 107 covering the second surface, and the fifth dam base 405 is provided on the third dam base 403; the second dam base 402, the second connecting electrode 107 covering the second surface and the fourth dam base 404 form a first isolation dam 410; the first dam base 401, the auxiliary power line 320 covering the first surface, the third dam base 403 and the fifth dam base 405 form a second isolation dam 420;

[0137] A cathode 25 is disposed in the circuit area 301, and the cathode 25 encloses a plurality of spacer pillars 23. A second connecting electrode 107 is exposed between the cathode 25 and the plurality of spacer pillars 23.

[0138] The encapsulation layer 26 covering the above structure, the encapsulation layer 26 of the circuit region 301 is a stacked structure of inorganic material / organic material / inorganic material, and the encapsulation layer 26 of the isolation dam region 302 is a stacked structure of inorganic material / inorganic material.

[0139] The following description uses the fabrication process of a display substrate as an example. The "patterning process" described in this disclosure includes, for metallic, inorganic, or transparent conductive materials, processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping; for organic materials, it includes processes such as organic material coating, mask exposure, and development. Deposition can be performed using any one or more of sputtering, evaporation, and chemical vapor deposition; coating can be performed using any one or more of spraying, spin coating, and inkjet printing; etching can be performed using any one or more of dry etching and wet etching. This disclosure does not limit the methods used. A "thin film" refers to a thin film made of a certain material on a substrate using deposition, coating, or other processes. If the "thin film" does not require a patterning process during the entire fabrication process, it can also be called a "layer." If the "thin film" requires a patterning process during the entire fabrication process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern." The phrase "A and B are arranged in the same layer" in this disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the dimension of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of this disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" means that the boundary of the orthographic projection of B falls within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0140] In an exemplary embodiment, the display substrate includes a display area 100 and an edge area 300. The edge area 300 includes a circuit area 301, an isolation dam area 302, a crack dam area 303, and a cutting area 304 sequentially disposed along a direction away from the display area 100. The fabrication process of the display substrate may include the following operations.

[0141] (1) A substrate 10 is prepared on a glass carrier plate 1. In an exemplary embodiment, the substrate 10 may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked on the glass carrier plate 1. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or surface-treated polymer soft film, etc. The materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., to improve the substrate's resistance to water and oxygen. The first and second inorganic material layers are also called barrier layers. The material of the semiconductor layer may be amorphous silicon (a-Si). In an exemplary embodiment, taking the stacked structure PI1 / Barrier1 / a-si / PI2 / Barrier2 as an example, its fabrication process may include: firstly, coating a layer of polyimide on a glass substrate 1, curing it to form a first flexible (PI1) layer; then depositing a barrier film on the first flexible layer to form a first barrier (Barrier1) layer covering the first flexible layer; then depositing an amorphous silicon film on the first barrier layer to form an amorphous silicon (a-si) layer covering the first barrier layer; then coating another layer of polyimide on the amorphous silicon layer, curing it to form a second flexible (PI2) layer; and finally depositing a barrier film on the second flexible layer to form a second barrier (Barrier2) layer covering the second flexible layer, thus completing the fabrication of the substrate 10. After this process, both the display area 100 and the peripheral area 300 include the substrate 10.

[0142] (2) Patterns for a driving structure layer and a circuit structure layer are fabricated on the substrate 10. The driving structure layer of the display area 100 includes a first transistor 101 constituting a pixel driving circuit, and the circuit structure layer of the peripheral area 300 includes a second transistor 102, a third transistor 103, a first storage capacitor 104, and a second storage capacitor 105 constituting an array substrate gate driver on array (GOA) circuit, and also includes a power line 310. In an exemplary embodiment, the fabrication process of the driving structure layer and the circuit structure layer may include:

[0143] A first insulating film and a semiconductor film are sequentially deposited on a substrate 10. The semiconductor film is patterned by a patterning process to form a first insulating layer 11 covering the entire substrate 10, and a semiconductor layer pattern disposed on the first insulating layer 11. The semiconductor layer pattern includes at least a first active layer located in the display area 100, and a second active layer and a third active layer located in the circuit area 301.

[0144] Subsequently, a second insulating film and a first metal film are deposited sequentially. The first metal film is patterned by a patterning process to form a second insulating layer 12 covering the semiconductor layer pattern, and a first gate metal layer pattern disposed on the second insulating layer 12. The first gate metal layer pattern includes at least a first gate electrode located in the display area 100, and a second gate electrode, a third gate electrode, a first capacitor electrode, and a second capacitor electrode located in the circuit area 301.

[0145] Subsequently, a third insulating film and a second metal film are deposited sequentially. The second metal film is patterned using a patterning process to form a third insulating layer 13 covering the first gate metal layer, and a second gate metal layer pattern disposed on the third insulating layer 13. The second gate metal layer pattern includes at least a third capacitor electrode and a fourth capacitor electrode located in the circuit region 301. The position of the third capacitor electrode corresponds to the position of the first capacitor electrode, and the position of the fourth capacitor electrode corresponds to the position of the second capacitor electrode.

[0146] Subsequently, a fourth insulating film is deposited, and a patterning process is used to form multiple first vias, crack dams 31, and dicing grooves 32. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the two first vias in the display area 100 are etched away, exposing the two ends of the first active layer. The four first vias in the circuit area 301 respectively expose the two ends of the second and third active layers. Crack dams 31 are formed in the crack dam area 303, and each crack dam 31 includes multiple spaced cracks, each exposing the surface of the first insulating layer 11. Dicing grooves 32 are formed in the dicing area 304, and each dicing groove includes a first groove and a second groove. The first groove exposes the substrate 10, and the second groove exposes the first groove; that is, the orthographic projection of the first groove onto the substrate 10 includes the orthographic projection of the second groove onto the substrate 10. After this patterning process, the isolation dam area 302 includes a composite insulating layer disposed on the substrate 10, the crack dam area 303 includes a composite insulating layer with multiple cracks disposed on the substrate 10, and the cutting area 304 includes a composite insulating layer with grooves disposed on the substrate 10. In an exemplary embodiment, the composite insulating layer includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the substrate 10.

[0147] In an exemplary embodiment, the cracks, the first groove, and the second groove can be formed using a two-step patterning process. For example, firstly, the fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 are etched using a first mask (Etch Bending A Mask, abbreviated as EBA Mask) to form the second groove in the cutting area 304, multiple cracks are formed in the crack dam area 303, and multiple first vias are formed in the circuit area 301 and the display area 100. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the second groove and the multiple cracks are etched away, exposing the surface of the first insulating layer 11. The fourth insulating layer 14, the third insulating layer 13, and the second insulating layer 12 within the multiple first vias are also etched away, exposing the two ends of the first active layer, the second active layer, and the third active layer, respectively. Then, the first insulating layer 11 within the second groove in the cutting area 304 is etched using a second mask (Etch Bending B Mask, abbreviated as EBB Mask) to form the first groove on the first insulating layer 11. The first insulating layer within the first groove is etched away, exposing the surface of the substrate 10. Thus, in the cutting area 304, the second groove exposes the first groove, and the first groove exposes the substrate 10, forming a stepped groove structure. In the crack dam area 303, multiple spaced cracks expose the surface of the first insulating layer 11, forming an uneven crack dam structure. EBA MASK and EBB MASK processes are patterning processes that groove the bending area of ​​the bonding region to reduce the thickness of the bending area. In the exemplary embodiment, the uneven crack dam structure formed in the crack dam area 303 is to avoid affecting the film structure of the display area 100 and the circuit area 301 during the cutting process. The multiple spaced cracks can not only reduce the stress on the display area 100 and the circuit area 301, but also prevent the fracture from propagating in the direction of the display area 100 and the circuit area 301. In the exemplary embodiment, a portion of the thickness of the second barrier layer in the substrate 10 can be etched away in the first groove.

[0148] Subsequently, a third metal thin film is deposited and patterned using a patterning process to form a first source / drain metal layer pattern on the fourth insulating layer 14. The first source / drain metal layer pattern includes at least: a first source electrode and a first drain electrode formed in the display area 100; a second source electrode, a second drain electrode, a third source electrode, and a third drain electrode formed in the circuit area 301; and a power line 310 formed in the isolation dam area 302. The first source electrode and the first drain electrode are respectively connected to the first active layer through first vias; the second source electrode and the second drain electrode are respectively connected to the second active layer through first vias; and the third source electrode and the third drain electrode are respectively connected to the third active layer through first vias. The power line 310 formed in the isolation dam area 302 is disposed on the fourth insulating layer 14, with a gap between the end of the power line 310 away from the display area 100 and the crack dam 31. In an exemplary embodiment, the thickness of the first source / drain metal layer can be approximately 700 nm to 1000 nm. In some possible implementations, the thickness of the first source / drain metal layer can be approximately 860 nm.

[0149] At this point, the driving structure layer and circuit structure layer patterns have been fabricated on the substrate 10, as follows: Figure 6 and Figure 7 As shown, Figure 7 for Figure 6 A cross-sectional view along the AA direction. In an exemplary embodiment, the first active layer, the first gate electrode, the first source electrode, and the first drain electrode constitute the first transistor 101; the second active layer, the second gate electrode, the second source electrode, and the second drain electrode constitute the second transistor 102; the third active layer, the third gate electrode, the third source electrode, and the third drain electrode constitute the third transistor 103; the first capacitor electrode and the third capacitor electrode constitute the first storage capacitor 104; and the second capacitor electrode and the fourth capacitor electrode constitute the second storage capacitor 105. In an exemplary embodiment, the first transistor 101 may be a driving transistor in a pixel driving circuit; the second transistor 102 may be a scanning transistor in a GOA circuit that outputs a scan (SCAN) signal; and the third transistor 103 may be an enabling transistor in a GOA circuit that outputs an enable (EM) signal. The driving transistor, the scan transistor, and the enabling transistor may all be thin-film transistors (TFTs).

[0150] (3) A fifth insulating film is deposited on the substrate on which the aforementioned pattern is formed. The fifth insulating film is patterned using a patterning process to form a fifth insulating layer 15 pattern in the display area 100, the circuit area 301, and the isolation dam area 302. The fifth insulating film in the crack dam area 303 and the cutting area 304 is removed. The fifth insulating layer 15 in the display area 100 and the circuit area 301 covers the source and drain electrodes of the first transistor 101, the second transistor 102, and the third transistor 103. The fifth insulating layer 15 in the isolation dam area 302 only covers the edge of the power line 310. That is, the first edge of the power line 310 adjacent to the display area 100 and the second edge away from the display area 100 are covered by the fifth insulating layer 15. The fifth insulating layer 15 between the first edge and the second edge is removed, exposing the surface of the power line 310. Figure 8 and Figure 9 As shown, Figure 9 for Figure 8 Sectional view along the AA direction.

[0151] (4) A first planar thin film is coated on the substrate on which the aforementioned pattern is formed. The first planar thin film is patterned by a patterning process to form a first planar (PLN) layer 16 in the display area 100, circuit area 301, crack dam area 303, and cutting area 304. A second via, a partition, and a planar dam base pattern are formed on the first planar layer 16. The second via is formed in the display area 100. The first planar layer 16 and the fifth insulating layer 15 within the second via are removed, exposing the surface of the first drain electrode of the first transistor 101. A partition is formed in the isolation dam area 302. The first planar layer 16 within the partition is removed, exposing the surface of the power line 310. A first dam base 401 is formed on the power line 310 within the partition. The first planar layer 16 formed in the crack dam area 303 completely fills the crack in the crack dam 31. The first planar layer 16 formed in the cutting area 304 completely fills the groove 32, such as Figure 10 and Figure 11 As shown, Figure 11 for Figure 10 A cross-sectional view along the AA direction. In an exemplary embodiment, the first length of the first dam base 401 may be approximately 20 μm to 60 μm, and the first dam base 401 is configured to form a second isolation dam. In this disclosure, "first length" refers to a feature dimension along the direction away from the display area of ​​the first or second isolation dam, i.e., a feature dimension perpendicular to the extension direction of the first or second isolation dam.

[0152] (5) A fourth metal thin film is deposited on the substrate on which the aforementioned pattern is formed. The fourth metal thin film is patterned using a patterning process to form a second source / drain metal layer pattern. The second source / drain metal layer pattern includes at least a connecting electrode 106 and an auxiliary power line 320. The first connecting electrode 106 is formed in the display area 100 and is connected to the first drain electrode of the first transistor 101 through a second via. The auxiliary power line 320 is formed in the isolation dam area 302. The auxiliary power line 320 covers the surface of the first dam base 401. The first side of the auxiliary power line 320 adjacent to the display area 100 and the second side away from the display area 100 are both connected to the power line 310. That is, the auxiliary power line 320 is disposed on the power line 310 exposed on both sides of the first dam base 401 to realize the connection between the power line 310 and the auxiliary power line 320. A first venting structure K1 is provided on the auxiliary power line 320, such as... Figure 12 , Figure 13 and Figure 14 As shown, Figure 13 for Figure 12 Sectional view along the AA direction. Figure 14 for Figure 12 A cross-sectional view along the BB direction. In an exemplary embodiment, the first dam base 401 includes a first surface (upper surface) away from the power line 310, a first near side (right side surface) adjacent to the display area 100, and a first far side (left side surface) away from the display area 100. A first venting structure K1 is disposed on the auxiliary power line 320 covering the first surface of the first dam base 401, and the orthographic projection of the first venting structure K1 on the substrate is within the orthographic projection range of the first surface on the substrate. In an exemplary embodiment, the first venting structure K1 may be at least one first through hole, and the auxiliary power line 320 within at least one first through hole is removed, exposing the first surface of the first dam base 401. In this way, the power line 310 of the first source / drain metal layer and the auxiliary power line 320 of the second source / drain metal layer form a double-layer power line in the edge region 300. By overlapping in the isolation dam area 302, a parallel structure of double-layer power lines is achieved, reducing the resistance of the power lines in the edge region, minimizing the voltage drop of the voltage signal, improving the uniformity of display brightness in the display area, and improving display quality. In an exemplary embodiment, a plurality of first through holes may be spaced apart along the edge direction of the display area. In a plane parallel to the display substrate, the shape of the first through holes may be triangular, rectangular, polygonal, circular, or elliptical, etc. In an exemplary embodiment, the shape of the first through hole may be rectangular, with a first length of approximately 10 μm to 40 μm, a second length of approximately 10 μm to 40 μm, and a spacing between adjacent first through holes of approximately 10 μm to 40 μm. In this disclosure, "second length" refers to a feature dimension along the extension direction of the first or second isolation dam, i.e., a feature dimension along the edge direction of the display area.

[0153] In an exemplary embodiment, the cross-sectional shape of the first dam base 401 in a plane perpendicular to the display substrate can be trapezoidal. The first length of the upper base (first surface) on the side away from the substrate is less than the first length of the lower base on the side adjacent to the substrate. The first length of the upper base (first surface) can be approximately 20 μm to 40 μm. In an exemplary embodiment, the shape of the first through hole can be a first strip extending along a direction away from the display area. The first length of the first strip can be approximately 80% to 100% of the first length of the upper base (first surface) in the first dam base. The second length of the first strip can be approximately 20% to 60% of the first length of the first strip. The spacing between adjacent first strips can be approximately 20% to 60% of the first length of the first strip. In an exemplary embodiment, the first length of the first strip can be approximately 20 μm to 40 μm, the second length of the first strip can be approximately 10 μm to 20 μm, and the spacing between adjacent first strips can be approximately 10 μm to 20 μm.

[0154] In an exemplary embodiment, the first dam foundation 401 includes a first surface, a first proximal side, and a first distal side. The auxiliary power line 320 covering the surface of the first dam foundation 401 can mean that the auxiliary power line 320 completely covers the first proximal side and the first distal side of the first dam foundation 401, and partially covers the first surface of the first dam foundation 401, such as... Figure 13 As shown. Partially covering the first surface of the first dam base 401 means that the auxiliary power line 320 covers a portion of the first surface (first near area) adjacent to the display area 100 and a portion of the first surface (first far area) away from the display area 100. The area between the first near area and the first far area is the location of the first through hole, exposing the first surface of the first dam base 401. In an exemplary embodiment, the auxiliary power line 320 covering the surface of the first dam base 401 may mean that the auxiliary power line 320 only completely covers the first near side and the first far side of the first dam base 401, that is, the first surface of the first dam base 401 is entirely the location of the first through hole.

[0155] In an exemplary embodiment, the first dam foundation 401 includes a first surface, a first proximal side, and a first distal side. The auxiliary power line 320 covering the surface of the first dam foundation 401 can mean that the auxiliary power line 320 completely covers the first surface, the first proximal side, and the first distal side of the first dam foundation 401; that is, the auxiliary power line 320 wraps around the first surface, the first proximal side, and the first distal side of the first dam foundation 401, such as... Figure 14 As shown.

[0156] In an exemplary embodiment, the first venting structure K1 provided on the auxiliary power line 320 is configured to form a venting channel to discharge gases generated during the planarization of the film layer during the process, thereby preventing film peeling and improving process quality. In an exemplary embodiment, the thickness of the second source / drain metal layer can be approximately 700 nm to 1000 nm. In some possible implementations, the thickness of the second source / drain metal layer can be approximately 860 nm.

[0157] (6) A second planarization film is coated on the substrate on which the aforementioned pattern is formed, and the second planarization film is patterned by a patterning process to form a pattern of a second planarization layer 17, a second dam base 402, and a third dam base 403. The second planarization layer 17 is formed in the display area 100 and the circuit area 301, and a third via is provided thereon. The second planarization layer 17 inside the third via is developed away, exposing the surface of the first connecting electrode 106. The second dam foundation 402 and the third dam foundation 403 are formed in the isolation dam area 302. The third dam foundation 403 is disposed on the auxiliary power line 320 covering the first surface of the first dam foundation 401. The second dam foundation 402 is disposed on the auxiliary power line 320 on the side of the first dam foundation 401 adjacent to the display area 100. The distance between the second dam foundation 402 and the display area 100 is less than the distance between the first dam foundation 401 and the display area 100. The auxiliary power line 320 is exposed on both the side of the second dam foundation 402 adjacent to the third dam foundation 403 and the side of the second dam foundation 402 away from the third dam foundation 403. Figure 15 and Figure 16 As shown, Figure 16 for Figure 15 A cross-sectional view along the AA direction. In an exemplary embodiment, the first length of the second dam foundation 402 may be approximately 20 μm to 60 μm, the first length of the third dam foundation 403 may be approximately 20 μm to 60 μm, the orthographic projection of the first dam foundation 401 on the base includes the orthographic projection of the third dam foundation 403 on the base, and the second dam foundation 402 and the third dam foundation 403 are configured to form two isolation dams.

[0158] (7) A transparent conductive film is deposited on the substrate on which the aforementioned pattern is formed. The transparent conductive film is patterned by a patterning process to form the anode 21 and the second connecting electrode 107 pattern. The anode 21 is formed on the second planarization layer 17 of the display area 100 and is connected to the first connecting electrode 106 through a third via. The second connecting electrode 107 is formed in the circuit area 301 and the isolation dam area 302. A portion of the second connecting electrode 107 is disposed on the second planarization layer 17 of the circuit area 301, on which a plurality of fourth vias are disposed. Another portion of the second connecting electrode 107 is disposed in the isolation dam area 302. The second connecting electrode 107 covers the second dam base 402, partially covers the third dam base 403, and covers the surface of the auxiliary power lines 320 exposed on both sides of the second dam base 402. The second connecting electrode 107 is provided with a second venting structure K2, such as... Figure 17 , Figure 18 and Figure 19 As shown, Figure 18 for Figure 17 Sectional view along the AA direction. Figure 19 for Figure 17 A cross-sectional view along the BB direction. In an exemplary embodiment, the second dam base 402 includes a second surface (upper surface) on the side away from the power line 310, a second near side (right side surface) on the side adjacent to the display area 100, and a second far side (left side surface) on the side away from the display area 100. The second venting structure K2 is disposed on the second connecting electrode 107 covering the second surface of the second dam base 402, and the orthographic projection of the second venting structure K2 on the substrate is located within the orthographic projection range of the second surface on the substrate. In an exemplary embodiment, the second venting structure K2 may be at least one second through hole, in which the second connecting electrode 107 is removed, exposing the second surface of the second dam base 402. Since the second connecting electrode 107 is connected to the auxiliary power line 320, and the auxiliary power line 320 is connected to the power line 310, the connection between the second connecting electrode 107 and the power line 310 is realized. In an exemplary embodiment, a plurality of second through holes may be spaced apart along the edge direction of the display area, and in a plane parallel to the display substrate, the shape of the second through holes may be triangular, rectangular, polygonal, circular, or elliptical, etc. In an exemplary embodiment, the shape of the second through hole can be rectangular, the first length of the rectangle can be about 10 μm to 40 μm, the second length of the rectangle can be about 10 μm to 40 μm, and the spacing between adjacent second through holes can be about 10 μm to 40 μm.

[0159] In an exemplary embodiment, the cross-sectional shape of the second dam base 402 in a plane perpendicular to the display substrate can be trapezoidal. The first length of the upper base (second surface) on the side away from the substrate is less than the first length of the lower base on the side adjacent to the substrate. The first length of the upper base (second surface) can be approximately 20 μm to 40 μm. In an exemplary embodiment, the shape of the second through hole can be a second strip extending along a direction away from the display area. The first length of the second strip can be approximately 80% to 100% of the first length of the upper base (second surface) in the second dam base. The second length of the second strip can be approximately 20% to 60% of the first length of the second strip. The spacing between adjacent second strips can be approximately 20% to 60% of the first length of the second strip. In an exemplary embodiment, the first length of the second strip can be approximately 20 μm to 40 μm. The second length of the second strip can be approximately 10 μm to 20 μm. The spacing between adjacent second through holes can be approximately 10 μm to 20 μm.

[0160] In an exemplary embodiment, the second dam foundation 402 includes a second surface, a second proximal side, and a second distal side. The second connecting electrode 107 covering the surface of the second dam foundation 402 can mean that the second connecting electrode 107 completely covers the second proximal side and the second distal side of the second dam foundation 402, and partially covers the second surface of the second dam foundation 402, such as... Figure 18 As shown. Partially covering the second surface of the second dam base 402 means that the second connecting electrode 107 covers a portion of the second surface adjacent to the display area 100 (second near region) and a portion of the second surface away from the display area 100 (second far region). The area between the second near region and the second far region is the location of the second through hole, exposing the second surface of the second dam base 402. In an exemplary embodiment, the second connecting electrode 107 covering the surface of the second dam base 402 may mean that the second connecting electrode 107 only completely covers the second near side and the second far side of the second dam base 402, that is, the second surface of the second dam base 402 is entirely the location of the second through hole.

[0161] In an exemplary embodiment, the second dam foundation 402 includes a second surface, a second proximal side, and a second distal side. The second connecting electrode 107 covering the surface of the second dam foundation 402 can mean that the second connecting electrode 107 completely covers the second surface, the second proximal side, and the second distal side of the second dam foundation 402; that is, the second connecting electrode 107 wraps around the second surface, the second proximal side, and the second distal side of the second dam foundation 402. Figure 19 As shown.

[0162] In an exemplary embodiment, the second venting structure K2 provided on the second connecting electrode 107 is configured to form a venting channel to release the gas generated during the planarization of the film layer during the process, thereby avoiding film layer peeling and improving process quality.

[0163] (8) A pixel definition film is coated on the substrate on which the aforementioned pattern is formed. The pixel definition film is patterned by a patterning process to form a pixel definition (PDL) layer 22, isolation pillars (PS) 23, a fourth dam base 404, and a fifth dam base 405 pattern. The pixel definition layer 22 is formed in the display area 100 and has pixel openings. The pixel definition film inside the pixel openings is developed away, exposing the surface of the anode 21. A plurality of isolation pillars (PS) 23 are formed in the circuit area 301. The positions of the plurality of isolation pillars 23 correspond to the positions of the plurality of fourth vias provided on the second connection electrode 107. The second connection electrode 107 is exposed between adjacent isolation pillars 23. The fourth dam foundation 404 and the fifth dam foundation 405 are formed in the isolation dam area 302. The fourth dam foundation 404 is disposed on the second connecting electrode 107 covering the second surface of the second dam foundation 402, and the fifth dam foundation 405 is disposed on the third dam foundation 403. The second dam foundation 402, the second connecting electrode 107 covering the second surface, and the fourth dam foundation 404 form the first isolation dam 410. The first dam foundation 401, the auxiliary power line 320 covering the first surface, the third dam foundation 403, and the fifth dam foundation 405 form the second isolation dam 420. Figure 20 and Figure 21 As shown, Figure 21 for Figure 20 Sectional view along the AA direction.

[0164] In an exemplary embodiment, the distance between the first isolation dam 410 and the display area 100 is less than the distance between the second isolation dam 420 and the display area 100. The first length of the fourth dam base 404 can be approximately 20 μm to 60 μm, the first length of the fifth dam base 405 can be approximately 20 μm to 60 μm, the orthographic projection of the second dam base 402 on the substrate includes the orthographic projection of the fourth dam base 404 on the substrate, the orthographic projection of the third dam base 403 on the substrate includes the orthographic projection of the fifth dam base 405 on the substrate, the first length of the orthographic projection of the first isolation dam 410 and the second isolation dam 420 on the substrate 10 can be approximately 20 μm to 60 μm, and the spacing between the first isolation dam 410 and the second isolation dam 420 can be approximately 20 μm to 60 μm. In an exemplary embodiment, the cross-sectional shape of the first isolation dam 410 and the second isolation dam 420 can be trapezoidal in a plane perpendicular to the display substrate.

[0165] (9) An organic light-emitting layer 24 and a cathode 25 are sequentially formed on the substrate on which the aforementioned pattern is formed. The organic light-emitting layer 24 is formed within the pixel opening of the display area 100, thereby connecting the organic light-emitting layer 24 to the anode 21. Since the anode 21 is connected to the first connecting electrode 106, and the first connecting electrode 106 is connected to the drain electrode of the first transistor 101, the connection between the organic light-emitting layer 24 and the drain electrode of the first transistor 101 is achieved. A portion of the cathode 25 is formed on the organic light-emitting layer 24 in the display area 100, and the cathode 25 is connected to the organic light-emitting layer 24. Another portion of the cathode 25 is formed in the circuit area 301. The cathode 25 encloses multiple spacer pillars 23, and the second connecting electrode 107 exposed between the cathode 25 and the multiple spacer pillars 23 is connected, such as... Figure 22 and Figure 23 As shown, Figure 23 for Figure 22 A cross-sectional view along the AA direction. Since the cathode 25 is connected to the second connecting electrode 107, the second connecting electrode 107 is connected to the auxiliary power line 320, and the auxiliary power line 320 is connected to the power line 310, the connection between the cathode 25 and the power line 310 is achieved. In an exemplary embodiment, the organic light-emitting layer 24 may include a stacked hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron injection layer. The cathode may be any one or more of magnesium (Mg), silver (Ag), aluminum (Al), copper (Cu), and lithium (Li), or an alloy made of any one or more of the aforementioned metals.

[0166] (10) An encapsulation layer 26 is formed based on the aforementioned pattern. The encapsulation layer 26 is formed in the display area 100, the circuit area 301, and the isolation dam area 302. The encapsulation layer 26 in the display area 100 and the circuit area 301 adopts a stacked structure of a first encapsulation layer, a second encapsulation layer, and a third encapsulation layer. The first encapsulation layer is made of inorganic material, covering the cathode 24 in the display area 100, wrapping multiple spacer pillars 23 in the circuit area 301, and wrapping the first isolation dam 410 and the second isolation dam 420 in the isolation dam area 302. The second encapsulation layer is made of organic material and is disposed in the display area 100 and the circuit area 301. The third encapsulation layer is made of inorganic material, covering the second encapsulation layer in the display area 100 and the circuit area 301, and covering the first encapsulation layer in the isolation dam area 302. The encapsulation layer 26 of the display area 100 and the circuit area 301 adopts a stacked structure of inorganic material / organic material / inorganic material, with the organic material layer disposed between the two inorganic material layers. The encapsulation layer 26 of the isolation dam area 302 adopts a stacked structure of inorganic material / inorganic material. In an exemplary embodiment, since the area of ​​the isolation dam area 302 adjacent to the crack dam area 303 exposes the surface of the fifth insulating layer 15, the two inorganic material layers of the isolation dam area 302 are directly formed on the fifth insulating layer 15, ensuring the encapsulation effect and process quality. In an exemplary embodiment, the preparation process of the display substrate may further include: peeling the display substrate from the glass carrier plate 1 by a peeling process, attaching a back film to the back side of the display substrate (the side of the substrate 10 away from the film layer) by a roller bonding method, cutting along the cutting groove using a cutting device, etc., to form a display substrate as shown in the figure. Figure 4 and Figure 5 As shown.

[0167] In an exemplary embodiment, the first, second, third, fourth, and fifth insulating layers can be any one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and can be single-layer, multi-layer, or composite layers. The first insulating layer is called a buffer layer, used to improve the substrate's resistance to water and oxygen. The second and third insulating layers are called gate insulating (GI) layers, the fourth insulating layer is called an interlayer insulating (ILD) layer, and the fifth insulating layer is called a passivation (PVX) layer. The first, second, third, and fourth metal thin films can be made of metallic materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al), titanium (Ti), and molybdenum (Mo), or alloys of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and can be single-layer structures or multi-layer composite structures, such as Ti / Al / Ti. The transparent conductive film can include indium tin oxide (ITO) or indium zinc oxide (IZO). The pixel definition layer can be made of polyimide, acrylic, or polyethylene terephthalate, etc. The active layer thin film can be made of various materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene, and polythiophene. That is, this disclosure applies to transistors manufactured based on oxide technology, silicon technology, and organic technology.

[0168] An exemplary embodiment of this disclosure forms a power line 310 through a first source / drain metal layer and an auxiliary power line 320 through a second source / drain metal layer, forming a double-layer power line in the edge region 300. The auxiliary power line 320 crosses the second isolation dam and connects to the power line 310, achieving a parallel double-layer power trace structure. This reduces the resistance of the power trace in the edge region 300, minimizes voltage signal drop, improves the uniformity of display brightness in the display area, and enhances display quality. An exemplary embodiment of this disclosure also provides a first venting structure and a second venting structure on the auxiliary power line 320 and the second connecting electrode 107, forming a venting channel. This effectively releases gas generated during the planarization process, preventing film peeling and improving process quality. The display substrate fabrication process of this exemplary embodiment of this disclosure has good process compatibility, is simple to implement, easy to execute, has high production efficiency, low production cost, and high yield.

[0169] Combination Figures 4 to 23The exemplary embodiment of this disclosure shows that the display substrate includes a display area 100 and an edge area 300. In an exemplary embodiment, the display area 100 includes a driving structure layer disposed on the substrate 10, a light-emitting structure layer disposed on the driving structure layer, and an encapsulation layer disposed on the light-emitting structure layer. The driving structure layer includes at least a first transistor 101 forming a pixel driving circuit, and the light-emitting structure layer includes at least an anode 21, an organic light-emitting layer 24, and a cathode 25.

[0170] In an exemplary embodiment, the edge region 300 includes a circuit region 301, an isolation dam region 302, a crack dam region 303, and a cutting region 304. In an exemplary embodiment, the circuit region 301 includes a circuit structure layer disposed on the substrate 10, a circuit connection layer disposed on the circuit structure layer, and an encapsulation layer disposed on the circuit connection layer. The circuit structure layer includes at least a second transistor 102, a third transistor 103, a first storage capacitor 104, and a second storage capacitor 105 forming a GOA circuit. The circuit connection layer includes at least a second connection electrode 107 that connects the power line 310 to the cathode 25.

[0171] In an exemplary embodiment, the isolation dam region 302 includes a composite insulating layer disposed on the substrate 10, a power line 310 disposed on the composite insulating layer, an auxiliary power line 320 disposed on the composite insulating layer, a second connecting electrode 107, a first isolation dam 410, a second isolation dam 420, and an encapsulation layer encapsulating the first isolation dam 410 and the second isolation dam 420. The first side of the auxiliary power line 320 adjacent to the display area 100 and the second side away from the display area 100 overlap with the power line 310. The auxiliary power line 320 between the first side and the second side is disposed in the second isolation dam 420. The second connecting electrode 107 is disposed in the first isolation dam 410 and overlaps with the auxiliary power lines 320 exposed on both sides of the first isolation dam 410.

[0172] In an exemplary embodiment, the crack dam region 303 includes a composite insulating layer disposed on the substrate 10, the composite insulating layer having a crack dam 31, and a first planarization layer 16 covering and filling the crack dam 31.

[0173] In an exemplary embodiment, the cutting area 304 includes a composite insulating layer disposed on the substrate 10, the composite insulating layer having a cutting groove 32, and a first planarization layer 16 covering and filling the cutting groove 32.

[0174] In an exemplary embodiment, the composite insulating layer includes a first insulating layer 11, a second insulating layer 12, a third insulating layer 13, and a fourth insulating layer 14 stacked on the substrate 10.

[0175] Figure 24 This is an enlarged view of the second isolation dam disclosed in this publication. Figure 24As shown, power line 310 is disposed on the fourth insulating layer 14, first dam base 401 is disposed on power line 310, auxiliary power line 320 completely covers the left and right surfaces of first dam base 401, and partially covers the upper surface of first dam base 401. The auxiliary power line 320 partially covering the upper surface of first dam base 401 means that the auxiliary power line 320 covers a portion of the first surface (first near area) adjacent to the display area and a portion of the first surface (first far area) away from the display area. The area between the first near area and the first far area is the area where the first venting structure (first through hole) is disposed, and the area where the first venting structure is located exposes the upper surface of first dam base 401. Third dam base 403 is disposed on auxiliary power line 320 located on first dam base 401, second connecting electrode 107 is disposed on auxiliary power line 320 and covers a portion of the surface of third dam base 403, and fifth dam base 405 is disposed on third dam base 403. In an exemplary embodiment, the angle β between the left (right) surface and the lower surface of the first dam foundation 401 can be approximately 30° to 60°, and the thickness of the power line 310 and the auxiliary power line 320 can be approximately 700 nm to 1000 nm. In some possible implementations, the angle β between the left (right) surface and the lower surface of the first dam foundation 401 can be approximately 45°, and the thickness of the power line 310 and the auxiliary power line 320 can be approximately 860 nm.

[0176] The structure of the display substrate and its fabrication process disclosed herein are merely illustrative. In the exemplary embodiments, the corresponding structure and patterning processes may be modified and added or reduced as needed, and this disclosure does not limit the scope of the invention.

[0177] Figure 25 This is a schematic diagram of another display substrate structure as an exemplary embodiment of the present disclosure, illustrating a cross-sectional structure of a top-emitting OLED display area and a peripheral area. In an exemplary embodiment, the structure of the display area 100 can be substantially the same as in the aforementioned embodiments, and the structures of the circuit area 301, the crack dam area 303, and the cutting area 304 in the edge area 300 can be substantially the same as in the aforementioned embodiments, except for the structure of the isolation dam area 302. In an exemplary embodiment, the first isolation dam 410 of the isolation dam area 302 includes a second dam base 402, a second connecting electrode 107, and a fourth dam base 404 stacked sequentially, and the second isolation dam 420 of the isolation dam area 302 includes a first passivation dam base 411, a first dam base 401, an auxiliary power line 320, a third dam base 403, and a fifth dam base 405 stacked sequentially.

[0178] In an exemplary embodiment, the isolation dam area 302 of the edge region 300 includes:

[0179] Base 10;

[0180] A composite insulating layer disposed on the substrate 10;

[0181] Power line 310 disposed on composite insulation layer;

[0182] A fifth insulating layer 15 covering the edge of the power line 310, and a first passivation dam base 411 disposed on the power line 310;

[0183] The first dam foundation 401 is set on the first passivated dam foundation 411, and the first passivated dam foundation 411 and the first dam foundation 401 form the first composite dam foundation;

[0184] An auxiliary power line 320 is provided on the power line 310 and the first composite dam foundation. The auxiliary power line 320 covers the first surface of the first composite dam foundation away from the power line 310, the first near side of the first composite dam foundation adjacent to the display area 100, and the first far side of the first composite dam foundation away from the display area 100. The auxiliary power line 320 on the side of the first composite dam foundation adjacent to the display area 100 and the auxiliary power line 320 on the side of the first composite dam foundation away from the display area 100 are both connected to the power line 310. A first venting structure is provided on the auxiliary power line 320 covering the first surface of the first composite dam foundation.

[0185] A third dam base 403 is disposed on the auxiliary power line 320 covering the first surface, and a second dam base 402 is disposed on the auxiliary power line 320 on the side of the first composite dam base adjacent to the display area 100.

[0186] The second connecting electrode 107 covers the second surface of the second dam base 402 away from the power line 310, the second near side of the second dam base 402 adjacent to the display area 100, and the second far side of the second dam base 402 away from the display area 100. The second connecting electrode 107 located on the side of the second dam base 402 adjacent to the display area 100 and the second connecting electrode 107 located on the side of the second dam base 402 away from the display area 100 are both connected to the auxiliary power line 320. The second connecting electrode 107 covering the second surface of the second dam base 402 is provided with a second venting structure.

[0187] A fourth dam base 404 is disposed on the second connecting electrode 107 covering the second surface, and a fifth dam base 405 is disposed on the third dam base 403; the second dam base 402, the second connecting electrode 107 covering the second surface and the fourth dam base 404 form a first isolation dam 410, and the first passivation dam base 411, the first dam base 401, the auxiliary power line 320 covering the first surface, the third dam base 403 and the fifth dam base 405 form a second isolation dam 420;

[0188] The encapsulation layer 26 encapsulates the first isolation dam 410 and the second isolation dam 420. The encapsulation layer 26 is an inorganic material / inorganic material stack structure.

[0189] In an exemplary embodiment Figure 25 The fabrication process of the display substrate shown can be basically the same as that of the aforementioned embodiment. The difference is that, during the process of forming the pattern of the fifth insulating layer 15 through the patterning process, a first passivation dam base 411 is simultaneously formed on the power line 310 of the isolation dam area 302. The first passivation dam base 411 is disposed in the same layer as the fifth insulating layer 15 and is formed by the same patterning process.

[0190] In an exemplary embodiment, by forming a first passivated dam foundation, the height of the second isolation dam can be increased, thereby improving the isolation effect of the second isolation dam on water vapor and improving product quality and service life.

[0191] Figure 26 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating a cross-sectional structure of a top-emitting OLED display area and a peripheral area. In an exemplary embodiment, the structure of the display area 100 can be substantially the same as in the previous embodiment, and the structures of the circuit area 301, the crack dam area 303, and the cutting area 304 in the edge area 300 can be substantially the same as in the previous embodiment, except for the structure of the isolation dam area 302. In an exemplary embodiment, the first isolation dam 410 of the isolation dam area 302 includes a second passivation dam base 421, an auxiliary power line 320, a second dam base 402, a second connecting electrode 107, and a fourth dam base 404 stacked sequentially, and the second isolation dam 420 of the isolation dam area 302 includes a first dam base 401, an auxiliary power line 320, a third dam base 403, and a fifth dam base 405 arranged sequentially.

[0192] In an exemplary embodiment, the isolation dam area 302 of the edge region 300 includes:

[0193] Base 10;

[0194] A composite insulating layer disposed on the substrate 10;

[0195] Power line 310 disposed on composite insulation layer;

[0196] A fifth insulating layer 15 covering the edge of the power line 310, and a second passivation dam base 421 disposed on the power line 310;

[0197] The first dam base 401 is set on the power line 310, and the distance between the first dam base 401 and the display area 100 is greater than the distance between the second passivation dam base 421 and the display area 100;

[0198] An auxiliary power line 320 is provided on the power line 310, the second passivation dam base 421, and the first dam base 401. The auxiliary power line 320 covers the second passivation dam base 421 and the first dam base 401 respectively. The auxiliary power line 320 located on the side of the second passivation dam base 421 adjacent to the display area 100, the auxiliary power line 320 located on the side of the first dam base 401 away from the display area 100, and the auxiliary power line 320 located between the second passivation dam base 421 and the first dam base 401 are all connected to the power line 310. A first venting structure is provided on the auxiliary power line 320 covering the first surface of the first dam base 401.

[0199] A third dam base 403 is disposed on the auxiliary power line 320 covering the first surface, and a second dam base 402 is disposed on the auxiliary power line 320 covering the upper surface of the second passivated dam base 421. The second passivated dam base 421, the auxiliary power line 320 covering the upper surface of the second passivated dam base 421, and the second dam base 402 form a second composite dam base.

[0200] The second connecting electrode 107 covers the second surface of the second composite dam base away from the power line 310, the second near side of the second composite dam base adjacent to the display area 100, and the second far side of the second composite dam base away from the display area 100. The second connecting electrode 107 located on the side of the second composite dam base adjacent to the display area 100 and the second connecting electrode 107 located on the side of the second composite dam base away from the display area 100 are both connected to the auxiliary power line 320. The second connecting electrode 107 covering the second surface of the second composite dam base is provided with a second venting structure.

[0201] A fourth dam base 404 is disposed on the second connecting electrode 107 covering the second surface, and a fifth dam base 405 is disposed on the third dam base 403; the second passivation dam base 421, the auxiliary power line 320 covering the upper surface of the second passivation dam base 421, the second dam base 402, the second connecting electrode 107 covering the second surface and the fourth dam base 404 form a first isolation dam 410, and the first dam base 401, the auxiliary power line 320 covering the first surface, the third dam base 403 and the fifth dam base 405 form a second isolation dam 420;

[0202] The encapsulation layer 26 encapsulates the first isolation dam 410 and the second isolation dam 420. The encapsulation layer 26 is an inorganic material / inorganic material stack structure.

[0203] In an exemplary embodiment Figure 26The fabrication process of the display substrate shown can be basically the same as that of the aforementioned embodiment. The difference is that, during the patterning process of forming the fifth insulating layer 15, a second passivation dam base 421 is simultaneously formed on the power line 310 of the isolation dam area 302. The second passivation dam base 421 is disposed in the same layer as the fifth insulating layer 15 and is formed by the same patterning process.

[0204] In an exemplary embodiment, by forming a second passivated dam base, the height of the first isolation dam can be increased, thereby improving the isolation effect of the first isolation dam on water vapor and improving product quality and service life.

[0205] In an exemplary embodiment, it can be Figure 25 and Figure 26 The structures are combined such that, during the patterning process of forming the fifth insulating layer 15, a first passivation dam base 411 and a second passivation dam base 421 are simultaneously formed on the power line 310 of the isolation dam area 302. Thus, the first isolation dam 410 of the formed isolation dam area 302 includes a second passivation dam base 421, an auxiliary power line 320, a second dam base 402, a second connecting electrode 107, and a fourth dam base 404 arranged in sequence, and the second isolation dam 420 of the isolation dam area 302 includes a first passivation dam base 411, a first dam base 401, an auxiliary power line 320, a third dam base 403, and a fifth dam base 405 arranged in sequence.

[0206] Figure 27 This is a schematic diagram of the structure of another display substrate according to an exemplary embodiment of the present disclosure, illustrating a cross-sectional structure of a top-emitting OLED display area and a peripheral area. In an exemplary embodiment, the structure of the display area 100 can be substantially the same as in the previous embodiment, and the structures of the circuit area 301, the crack dam area 303, and the cutting area 304 in the edge area 300 can be substantially the same as in the previous embodiment, except for the structure of the isolation dam area 302. In an exemplary embodiment, the first isolation dam 410 of the isolation dam area 302 includes a flat dam base 431, an auxiliary power line 320, a second dam base 402, a second connecting electrode 107, and a fourth dam base 404 stacked sequentially, and the second isolation dam 420 of the isolation dam area 302 includes a first dam base 401, an auxiliary power line 320, a third dam base 403, and a fifth dam base 405 arranged sequentially.

[0207] In an exemplary embodiment, the isolation dam area 302 of the edge region 300 includes:

[0208] Base 10;

[0209] A composite insulating layer disposed on the substrate 10;

[0210] Power line 310 disposed on composite insulation layer;

[0211] The fifth insulation layer 15 covers the edge of the power cord 310;

[0212] The first dam base 401 and the flat dam base 431 are set on the power line 310. The distance between the flat dam base 431 and the display area 100 is smaller than the distance between the first dam base 401 and the display area 100. The thickness of the flat dam base 431 is smaller than the thickness of the first dam base 401.

[0213] An auxiliary power line 320 is provided on the power line 310, the flat dam foundation 431, and the first dam foundation 401. The auxiliary power line 320 covers the flat dam foundation 431 and the first dam foundation 401 respectively. The auxiliary power line 320 located on the side of the flat dam foundation 431 adjacent to the display area 100, the auxiliary power line 320 located on the side of the first dam foundation 401 away from the display area 100, and the auxiliary power line 320 located between the flat dam foundation 431 and the first dam foundation 401 are all connected to the power line 310. A first venting structure is provided on the auxiliary power line 320 covering the first surface of the first dam foundation 401.

[0214] A third dam foundation 403 is provided on the auxiliary power line 320 covering the first surface, and a second dam foundation 402 is provided on the upper surface of the flat dam foundation 431. The flat dam foundation 431, the auxiliary power line 320 covering the flat dam foundation 431, and the second dam foundation 402 form a third composite dam foundation.

[0215] The second connecting electrode 107 covers the second surface of the third composite dam base away from the power line 310, the second near side of the third composite dam base adjacent to the display area 100, and the second far side of the third composite dam base away from the display area 100. The second connecting electrode 107 located on the side of the third composite dam base adjacent to the display area 100 and the second connecting electrode 107 located on the side of the third composite dam base away from the display area 100 are both connected to the auxiliary power line 320. The second connecting electrode 107 covering the second surface of the third composite dam base is provided with a second venting structure.

[0216] A fourth dam base 404 is disposed on the second connecting electrode 107 covering the second surface, and a fifth dam base 405 is disposed on the third dam base 403; a flat dam base 431, an auxiliary power line 320 covering the upper surface of the flat dam base 431, a second dam base 402, a second connecting electrode 107 covering the second surface, and a fourth dam base 404 form a first isolation dam 410; a first dam base 401, an auxiliary power line 320 covering the first surface, a third dam base 403, and a fifth dam base 405 form a second isolation dam 420;

[0217] The encapsulation layer 26 encapsulates the first isolation dam 410 and the second isolation dam 420. The encapsulation layer 26 is an inorganic material / inorganic material stack structure.

[0218] In an exemplary embodiment Figure 27 The fabrication process of the display substrate shown is substantially the same as that of the aforementioned embodiments. The difference lies in that, during the patterning process of the first planarization layer 16, a first dam base 401 and a flat dam base 431 are simultaneously formed on the power lines 310 of the isolation dam area 302. The first dam base 401 and the flat dam base 431 are disposed in the same layer and formed by the same patterning process. In an exemplary embodiment, a halftone or grayscale mask patterning process can be used to make the thickness of the flat dam base 431 less than the thickness of the first dam base 401. In an exemplary embodiment, the thickness of the flat dam base 431 can be approximately 30% to 70% of the thickness of the first dam base 401.

[0219] In an exemplary embodiment, by forming a flat dam foundation, the height of the first isolation dam can be increased, thereby improving the isolation effect of the first isolation dam on water vapor and improving product quality and service life.

[0220] This disclosure also provides a method for fabricating a display substrate, the display substrate including a display area and an edge area located around the display area; in an exemplary embodiment, the fabrication method includes:

[0221] S1. A composite insulating layer and a power line disposed on the composite insulating layer are formed in the edge region of the substrate;

[0222] S2. An isolation dam is formed on the side of the power line away from the substrate. An auxiliary power line is provided in the isolation dam. The auxiliary power line located on the side of the isolation dam adjacent to the display area and the auxiliary power line located on the side of the isolation dam away from the display area are both connected to the power line.

[0223] In an exemplary embodiment, the composite insulating layer may include a first insulating layer, a second insulating layer, a third insulating layer, and a fourth insulating layer stacked together.

[0224] In an exemplary embodiment, step S2 may include:

[0225] A first dam foundation is formed on the power line;

[0226] An auxiliary power line is formed on the power line and the first dam foundation. The auxiliary power line is connected to the power line on a first side adjacent to the display area and a second side away from the display area. The auxiliary power line between the first side and the second side covers the first dam foundation.

[0227] A second dam base and a third dam base are formed. The third dam base is set on the auxiliary power line covering the first dam base, and the second dam base is set on the auxiliary power line between the first dam base and the display area.

[0228] A second connection electrode is formed to connect with the auxiliary power line, and the second connection electrode covers the second dam foundation;

[0229] A fourth dam foundation and a fifth dam foundation are formed. The fourth dam foundation is disposed on the second connecting electrode covering the second dam foundation, and the fifth dam foundation is disposed on the third dam foundation. The second dam foundation, the second connecting electrode and the fourth dam foundation form a first isolation dam, and the first dam foundation, the auxiliary power line, the third dam foundation and the fifth dam foundation form a second isolation dam.

[0230] This disclosure provides a method for fabricating a display substrate. By forming power lines and auxiliary power lines in the edge region, and connecting the auxiliary power lines across a second isolation dam to the power lines via a connection structure, a parallel double-layer power trace structure is achieved. This reduces the resistance of the power traces in the edge region, minimizes the voltage drop of the voltage signal, improves the uniformity of display brightness in the display area, and enhances display quality. An exemplary embodiment of this disclosure further enhances the display quality by providing a first venting structure and a second venting structure on the auxiliary power line and the second connecting electrode, respectively. The first and second venting structures form a venting channel, which can effectively release the gas generated by the planarization layer during the process, preventing film peeling and improving process quality. The method for fabricating the display substrate according to the exemplary embodiment of this disclosure has good process compatibility, is simple to implement, easy to carry out, has high production efficiency, low production cost, and high yield.

[0231] This disclosure also provides a display device, including the display substrate of the foregoing embodiments. The display device can be any product or component with display function, such as a mobile phone, tablet computer, television, monitor, laptop computer, digital photo frame, or navigator.

[0232] While the embodiments disclosed herein are as described above, the content is merely for the purpose of facilitating understanding of this disclosure and is not intended to limit this disclosure. Any person skilled in the art to which this disclosure pertains may make any modifications and changes in the form and details of the implementation without departing from the spirit and scope disclosed herein; however, the scope of patent protection of this application shall still be determined by the scope defined in the appended claims.

Claims

1. A display substrate, the display substrate comprising a display area and an edge area surrounding the display area; the edge area comprising a composite insulating layer disposed on a substrate, power lines disposed on the composite insulating layer, and an isolation dam disposed on the power lines, wherein an auxiliary power line is disposed in the isolation dam, and an auxiliary power line located on the side of the isolation dam adjacent to the display area and an auxiliary power line located on the side of the isolation dam away from the display area are both connected to the power lines; wherein, The display area includes a driving structure layer disposed on a substrate and a light-emitting element disposed on the driving structure layer; the power line is disposed on the same layer as the first source-drain metal layer of the driving structure layer, and the auxiliary power line is disposed on the same layer as the second source-drain metal layer of the driving structure layer. as well as The power line and the auxiliary power line form a parallel double-layer power line in the edge region.

2. The display substrate according to claim 1, wherein, The isolation dam includes a first isolation dam and a second isolation dam. The second isolation dam is disposed on the power line. The first isolation dam is disposed on the auxiliary power line on the side of the second isolation dam adjacent to the display area. The auxiliary power line is disposed in the second isolation dam. The auxiliary power line on the side of the second isolation dam adjacent to the display area and the auxiliary power line on the side of the second isolation dam away from the display area are both connected to the power line.

3. The display substrate according to claim 2, wherein, The edge region also includes a second connection electrode, which is disposed in the first isolation dam. The second connection electrode located on the side of the first isolation dam adjacent to the display area and the second connection electrode located on the side of the first isolation dam away from the display area are both connected to the auxiliary power line.

4. The display substrate according to claim 2, wherein, The second isolation dam further includes a first dam base, a third dam base, and a fifth dam base; the first dam base is disposed on the power line, and the first dam base includes a first surface away from the power line, a first proximal side adjacent to the display area, and a first distal side away from the display area; the auxiliary power line covers the first surface, the first proximal side, and the first distal side of the first dam base; the third dam base is disposed on the auxiliary power line covering the first surface, and the fifth dam base is disposed on the third dam base.

5. The display substrate according to claim 2, wherein, The second isolation dam further includes a first dam base, a third dam base, and a fifth dam base; the first dam base is disposed on the power line, and the first dam base includes a first surface away from the power line, a first proximal surface adjacent to the display area, and a first distal surface away from the display area; the auxiliary power line covers the first proximal surface and the first distal surface of the first dam base, and partially covers the first surface of the first dam base; the third dam base is disposed on the auxiliary power line that partially covers the first surface, and the fifth dam base is disposed on the third dam base; or, the auxiliary power line covers the first proximal surface and the first distal surface of the first dam base, the third dam base is disposed on the first surface of the first dam base, and the fifth dam base is disposed on the third dam base.

6. The display substrate according to claim 5, wherein, The auxiliary power line in the second isolation dam is equipped with a first venting structure.

7. The display substrate according to claim 6, wherein, The first venting structure includes at least one first through hole, the first length of the first through hole being 80% to 100% of the first length of the first surface, the second length of the first through hole being 20% ​​to 60% of the first length of the first through hole, and the spacing between adjacent first through holes being 20% ​​to 60% of the first length of the first through hole; the first length is a characteristic dimension along the direction away from the display area of ​​the second isolation dam, and the second length is a characteristic dimension along the extension direction of the second isolation dam.

8. The display substrate according to claim 3, wherein, The first isolation dam further includes a second dam base and a fourth dam base; the second dam base is disposed on the auxiliary power line, and the second dam base includes a second surface away from the power line, a second proximal side adjacent to the display area, and a second distal side away from the display area; the second connecting electrode covers the second surface, the second proximal side, and the second distal side of the second dam base; the fourth dam base is disposed on the second connecting electrode covering the second surface.

9. The display substrate according to claim 3, wherein, The first isolation dam further includes a second dam base and a fourth dam base; the second dam base is disposed on the auxiliary power line, and the second dam base includes a second surface away from the power line, a second proximal surface adjacent to the display area, and a second distal surface away from the display area; the second connecting electrode covers the second proximal surface and the second distal surface of the second dam base, and partially covers the second surface of the second dam base, and the fourth dam base is disposed on the second connecting electrode that partially covers the second surface; or, the second connecting electrode covers the second proximal surface and the second distal surface of the second dam base, and the fourth dam base is disposed on the second surface of the second dam base.

10. The display substrate according to claim 9, wherein, A second venting structure is provided on the second connecting electrode in the first isolation dam.

11. The display substrate according to claim 10, wherein, The second venting structure includes at least one second through hole, the first length of the second through hole being 80% to 100% of the first length of the second surface, the second length of the second through hole being 20% ​​to 60% of the first length of the second through hole, and the spacing between adjacent second through holes being 20% ​​to 60% of the first length of the second through hole; the first length is a characteristic dimension along the direction away from the display area of ​​the first isolation dam, and the second length is a characteristic dimension along the extension direction of the first isolation dam.

12. The display substrate according to any one of claims 4 to 11, wherein, The second isolation dam also includes a first dam foundation and a first passivated dam foundation; the first passivated dam foundation is disposed on the power line, and the first dam foundation is disposed on the first passivated dam foundation.

13. The display substrate according to any one of claims 4 to 11, wherein, The first isolation dam further includes a second dam foundation and a second passivated dam foundation; the second passivated dam foundation is disposed on the power line, and the auxiliary power line covers the second passivated dam foundation; the second dam foundation is disposed on the auxiliary power line covering the second passivated dam foundation.

14. The display substrate according to any one of claims 4 to 11, wherein, The first isolation dam further includes a second dam foundation and a second passivated dam foundation, the second isolation dam further includes a first dam foundation and a first passivated dam foundation; the second passivated dam foundation is disposed on the power line, the auxiliary power line covers the second passivated dam foundation, the second dam foundation is disposed on the auxiliary power line covering the second passivated dam foundation; the first passivated dam foundation is disposed on the power line, the first dam foundation is disposed on the first passivated dam foundation.

15. The display substrate according to any one of claims 4 to 11, wherein, The first isolation dam also includes a second dam foundation and a flat dam foundation; the flat dam foundation is disposed on the power line, and the auxiliary power line covers the flat dam foundation; the second dam foundation is disposed on the auxiliary power line covering the flat dam foundation.

16. The display substrate according to claim 15, wherein, The second isolation dam also includes a first dam foundation, wherein the flat dam foundation is disposed in the same layer as the first dam foundation, and the thickness of the flat dam foundation is 30% to 70% of the thickness of the first dam foundation.

17. The display substrate according to claim 3, wherein, The second connecting electrode is disposed in the same layer as the anode of the light-emitting element.

18. A display device comprising a display substrate as described in any one of claims 1 to 17.

19. A method for fabricating a display substrate, the display substrate comprising a display area and an edge area located around the display area; the fabrication method comprising: A composite insulation layer and power lines disposed on the composite insulation layer are formed in the edge region of the substrate; An isolation dam is formed on the side of the power line away from the substrate. An auxiliary power line is disposed within the isolation dam. Both the auxiliary power line located on the side of the isolation dam adjacent to the display area and the auxiliary power line located on the side of the isolation dam away from the display area are connected to the power line. The display area includes a driving structure layer disposed on a substrate and a light-emitting element disposed on the driving structure layer; the power line is disposed on the same layer as the first source-drain metal layer of the driving structure layer, and the auxiliary power line is disposed on the same layer as the second source-drain metal layer of the driving structure layer. as well as The power line and the auxiliary power line form a parallel double-layer power line in the edge region.

20. The preparation method according to claim 19, wherein, An isolation dam is formed on the power line, and an auxiliary power line is provided in the isolation dam, including: A first dam foundation is formed on the power line; An auxiliary power line is formed on the power line and the first dam foundation. The auxiliary power line is connected to the power line on a first side adjacent to the display area and a second side away from the display area. The auxiliary power line between the first side and the second side covers the first dam foundation. A second dam base and a third dam base are formed. The third dam base is set on the auxiliary power line covering the first dam base, and the second dam base is set on the auxiliary power line between the first dam base and the display area. A second connection electrode is formed to connect with the auxiliary power line, and the second connection electrode covers the second dam foundation; A fourth dam foundation and a fifth dam foundation are formed. The fourth dam foundation is disposed on the second connecting electrode covering the second dam foundation, and the fifth dam foundation is disposed on the third dam foundation. The second dam foundation, the second connecting electrode and the fourth dam foundation form a first isolation dam, and the first dam foundation, the auxiliary power line, the third dam foundation and the fifth dam foundation form a second isolation dam.

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