A bypass scheduling method for a posit instruction and a processor

Abstract

This invention discloses a bypass scheduling method and processor for POSIT instructions. The bypass scheduling method for POSIT instructions includes: S1, comparing the tags of the destination registers and source registers of different POSIT instructions in the emitter pipeline to determine the producer and consumer of the POSIT instruction; S2, during the execution of the POSIT instruction acting as a producer, the calculation results generated in the producer's calculation phase or write-back phase are directly bypassed to the consumer via the bypass data path as the consumer's source operand without being packaged. This invention, through the bypass mechanism, can avoid the data extraction and reassembly operations between POSIT instructions with dependencies, effectively improving the execution efficiency of POSIT instructions and reducing the power consumption of POSIT instruction execution.

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