Chip and electronic device

By designing the connection between logic circuits and metal layers in the chip to switch and update the version number, the problem of additional modifications to the metal layer during chip redesign is solved, thereby reducing redesign costs and improving the flexibility and accuracy of version number recording.

CN122287487APending Publication Date: 2026-06-26XINXIN HANGTU (SUZHOU) TECHNOLOGY CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
XINXIN HANGTU (SUZHOU) TECHNOLOGY CO LTD
Filing Date
2024-12-17
Publication Date
2026-06-26

AI Technical Summary

Technical Problem

During chip redesign, when modifying the chip version number, existing technologies require additional modifications to one or more metal layers, leading to increased redesign costs.

Method used

Design a chip version number recording circuit that updates the version number by switching the connection relationship between the logic circuit and the metal layer without requiring additional modification to the metal layer. CMOS logic circuits and TIE-L/TIE-H cells are used to ensure signal stability and reliability. The logic circuits are integrated within the device layer to reduce dependence on external metal layers.

Benefits of technology

It reduced the cost of chip redesign, improved the flexibility and accuracy of version number recording, simplified circuit layout, reduced manufacturing costs, and improved the reliability of signal transmission.

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Abstract

This application relates to the field of integrated circuit technology, and particularly to a chip and electronic device. The chip includes: N metal layers, each metal layer including a low-level signal output section and a high-level signal output section; a chip version number recording circuit, including M logic circuits, where M is the number of binary bits of the chip version number, and M output signals corresponding one-to-one with the M logic circuits for recording the chip version number; wherein, the logic circuits include N signal input terminals, each of which corresponds one-to-one with the N metal layers, and the signal input terminals are electrically connected to the low-level signal output section or high-level signal output section of the corresponding metal layer. When the connection relationship between one of the signal input terminals and the corresponding metal layer is switched, the output signal of the logic circuit is also switched. The chip provided by this application does not require modification of one or more additional metal layers due to changes in the chip version number, thereby reducing the chip redesign cost.
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