Memory device and operating method thereof, memory system

Abstract

This disclosure provides a memory device and its operation method, and a memory system. The memory device includes: a memory cell array including multiple pages, each page including multiple memory cells; and peripheral circuitry coupled to the memory cell array. The peripheral circuitry is configured to: perform a programming operation on the memory cells of a selected page from the multiple pages; during the programming operation, apply a first programming pulse and a first verification pulse to a word line coupled to the selected page; at a first moment when the first verification pulse is applied, detect a first failure bit count of the selected page; and, based on a comparison between the first failure bit count and a first preset value, determine whether to apply a second programming pulse to the word line, wherein the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse; the first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and in particular to a memory device and its operation method, and a memory system. Background Technology

[0002] Memory devices are storage devices used to store information in modern information technology. As a typical non-volatile semiconductor memory, NAND flash memory has become a mainstream product in the memory market due to its high storage density, controllable production costs, suitable erasure speed, and retention characteristics.

[0003] However, as the requirements for memory devices continue to increase, there are still many problems with memory devices when performing programming operations. Summary of the Invention

[0004] This disclosure provides a memory device, its operation method, and a memory system.

[0005] In one aspect, embodiments of this disclosure provide a memory device, the memory device comprising:

[0006] A memory cell array comprising multiple pages, each page comprising multiple memory cells;

[0007] Peripheral circuitry, coupled to the memory cell array; the peripheral circuitry is configured as follows:

[0008] A programming operation is performed on the memory cells of a selected page from the plurality of pages; during the programming operation, a first programming pulse and a first verification pulse are applied to the word line coupled to the selected page; at the first moment of the application of the first verification pulse, a first failure bit count of the selected page is detected; and,

[0009] Based on the comparison result between the first failure bit count and the first preset value, it is determined whether to apply a second programming pulse to the word line, wherein the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse; the first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse.

[0010] In the above scheme, the peripheral circuit is further configured as follows:

[0011] When the first failure bit count is less than or equal to the first preset value, no second programming pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0012] In the above scheme, the peripheral circuit is further configured as follows:

[0013] When the first failure bit count is greater than the first preset value, a second programming pulse is applied to the word line.

[0014] In the above scheme, the peripheral circuit is further configured as follows:

[0015] At a second moment after the first verification pulse is applied, the second failure bit count of the selected page is detected; the second moment is earlier than the first moment; and...

[0016] During the application of the second programming pulse, a second verification pulse is applied to the word line based on the comparison result between the second failure bit count and the second preset value. The second preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state when the second failure bit count is detected.

[0017] In the above scheme, the peripheral circuit is further configured as follows:

[0018] When the second failure bit count is less than or equal to the second preset value, no second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0019] When the second failure bit count is greater than the second preset value, a second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0020] In the above scheme, the peripheral circuit includes a first latch and a second latch; wherein, the first latch is used at least to store the detected second failure bit count, and the second latch is used at least to store the detected first failure bit count.

[0021] In the above scheme, the peripheral circuit is further configured as follows:

[0022] After the programming and verification phases of the programming operation are completed, a recovery pulse is applied to the word line coupled to the selected page.

[0023] In the above scheme, the number of bits stored in the memory unit includes one bit.

[0024] On one hand, embodiments of this disclosure provide a memory system, including: a memory device as described in the above embodiments of this disclosure; and

[0025] A memory controller; the memory controller is coupled to the memory device and is used to control the memory device.

[0026] On one hand, embodiments of this disclosure provide an operation method for a memory device, the memory device comprising: a plurality of pages, each page comprising a plurality of memory cells; the operation method comprising:

[0027] A programming operation is performed on the memory cells of a selected page from the plurality of pages; during the programming operation, a first programming pulse and a first verification pulse are applied to the word line coupled to the selected page; at the first moment of the application of the first verification pulse, a first failure bit count of the selected page is detected; and,

[0028] Based on the comparison result between the first failure bit count and the first preset value, it is determined whether to apply a second programming pulse to the word line, wherein the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse; the first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse.

[0029] In the above scheme, determining whether to apply a second programming pulse to the word line based on the comparison result of the first failure bit count and the first preset value includes: when the first failure bit count is less than or equal to the first preset value, not applying a second programming pulse to the word line, and the programming phase and verification phase of the programming operation end.

[0030] In the above scheme, determining whether to apply a second programming pulse to the word line based on the comparison result of the first failure bit count and the first preset value includes:

[0031] When the first failure bit count is greater than the first preset value, a second programming pulse is applied to the word line.

[0032] The method in the above scheme further includes:

[0033] At a second moment after the first verification pulse is applied, the second failure bit count of the selected page is detected; the second moment is earlier than the first moment; and...

[0034] During the application of the second programming pulse, a second verification pulse is applied to the word line based on the comparison result between the second failure bit count and the second preset value. The second preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state when the second failure bit count is detected.

[0035] In the above scheme, determining whether to apply a second verification pulse to the word line based on the comparison result between the second failure bit count and the second preset value includes:

[0036] When the second failure bit count is less than or equal to the second preset value, no second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0037] When the second failure bit count is greater than the second preset value, a second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0038] The method in the above scheme further includes:

[0039] After detecting the second failure bit count of the selected page, the first failure bit count is stored in the second latch; after detecting the first failure bit count of the selected page, the first failure bit count is stored in the first latch.

[0040] The method in the above scheme further includes:

[0041] After the programming and verification phases of the programming operation are completed, a recovery pulse is applied to the word line coupled to the selected page.

[0042] This disclosure provides a memory device and its operation method, a memory system, the memory device comprising: a memory cell array including a plurality of pages, each page including a plurality of memory cells; peripheral circuitry coupled to the memory cell array; the peripheral circuitry being configured to: perform a programming operation on the memory cells of a selected page from the plurality of pages; during the programming operation, apply a first programming pulse and a first verification pulse to a word line coupled to the selected page; at a first moment when the first verification pulse is applied, detect a first failure bit count of the selected page; and, based on a comparison result between the first failure bit count and a first preset value, determine whether to apply a second programming pulse to the word line, the level corresponding to the second programming pulse being higher than the level corresponding to the first programming pulse; the first preset value being used to characterize the number of boundaries of the memory cells in the selected page that have not reached the target programming state after the first programming pulse. In this embodiment of the disclosure, during the programming operation, a first failure bit count and a first preset value are acquired. The first failure bit count represents the actual number of memory cells in the selected page that have not reached the programming state after the first programming pulse. The first preset value represents the maximum number of memory cells in the selected page that have not reached the target programming state after the first programming pulse. By comparing the first failure bit count with the first preset value, it is determined whether a second programming pulse with a higher level needs to be applied to the word line coupled to the selected page. Thus, in this embodiment of the disclosure, it is possible to determine whether a second programming pulse needs to be applied based on the actual programming state of the memory cell, thereby reducing the application of unnecessary programming pulses, which can improve programming efficiency. At the same time, it can reduce the damage to the memory cell caused by excess programming pulses, thereby improving the reliability of the memory. Attached Figure Description

[0043] Figure 1 This is a schematic diagram of an exemplary system having a memory system according to an embodiment of the present disclosure;

[0044] Figure 2a This is a schematic diagram of an exemplary memory card having a memory system according to an embodiment of the present disclosure;

[0045] Figure 2b This is a schematic diagram of an exemplary solid-state drive with a memory system according to an embodiment of the present disclosure;

[0046] Figure 3a This is a schematic diagram showing the distribution of memory cells in a three-dimensional NAND flash memory according to an embodiment of the present disclosure;

[0047] Figure 3b This is a schematic diagram of an exemplary memory device including peripheral circuitry according to an embodiment of the present disclosure;

[0048] Figure 4This is a schematic cross-sectional view of a memory cell array including NAND flash memory strings according to an embodiment of the present disclosure;

[0049] Figure 5 This is a schematic diagram of an exemplary memory device including a memory cell array and peripheral circuitry according to an embodiment of the present disclosure;

[0050] Figure 6 This is a timing diagram illustrating the application of different programming pulses during the execution of a programming operation in one embodiment of the present disclosure;

[0051] Figure 7 This is a schematic diagram illustrating the threshold voltage change of a memory cell during repeated programming or overprogramming in one embodiment of this disclosure;

[0052] Figure 8a This is a timing diagram illustrating the application of different programming pulses during the execution of a programming operation in another embodiment of this disclosure;

[0053] Figure 8b This is a schematic diagram of the programming timing in one embodiment of the present disclosure without the application of a second programming pulse and a second verification pulse;

[0054] Figure 8c This is a schematic diagram of the programming timing for applying the second programming pulse and the second verification pulse in one embodiment of the present disclosure;

[0055] Figure 9 This is a schematic diagram illustrating the implementation flow of an operation method for a memory device according to an embodiment of the present disclosure. Detailed Implementation

[0056] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the specific embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0057] In the following description, numerous specific details are set forth in order to provide a more thorough understanding of this disclosure. However, it will be apparent to those skilled in the art that this disclosure may be practiced without one or more of these details. In other instances, to avoid confusion with this disclosure, certain technical features well-known in the art have not been described; that is, not all features of actual embodiments are described herein, nor are well-known functions and structures described in detail.

[0058] In the accompanying drawings, for clarity, the dimensions of layers, areas, and elements, as well as their relative dimensions, may be exaggerated. The same reference numerals denote the same elements throughout.

[0059] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this disclosure, the first element, component, area, layer, or portion discussed below may be referred to as a second element, component, area, layer, or portion. And the discussion of a second element, component, area, layer, or portion does not imply that the first element, component, area, layer, or portion necessarily exists in this disclosure.

[0060] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below,” “under,” or “below” other elements or features will be oriented “above” other elements or features. Therefore, the exemplary terms “below” and “under” can include both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0061] To gain a more detailed understanding of the features and technical content of the embodiments of this disclosure, the implementation of the embodiments of this disclosure will be described in detail below with reference to the accompanying drawings. The accompanying drawings are for reference and illustration only and are not intended to limit the embodiments of this disclosure.

[0062] The memory devices in the embodiments of this disclosure include, but are not limited to, three-dimensional NAND type memory. For ease of understanding, three-dimensional NAND type memory will be used as an example for explanation.

[0063] Figure 1A block diagram of an exemplary system 100 having a memory device according to some aspects of this disclosure is shown. System 100 may be a mobile phone, desktop computer, laptop computer, tablet computer, vehicle computer, game console, printer, positioning device, wearable electronic device, smart sensor, virtual reality (VR) device, augmented reality (AR) device, or any other suitable electronic device having storage therein. Figure 1 As shown, system 100 may include a host 108 and a memory system 102, the memory system 102 having one or more memory devices 104 and a memory controller 106. The host 108 may be a processor of an electronic device (e.g., a central processing unit (CPU)) or a system-on-a-chip (SoC) (e.g., an application processor (AP)). The host 108 may be configured to send data to or receive data from the memory device 104.

[0064] According to some embodiments, memory controller 106 is coupled to memory device 104 and host 108 and is configured to control memory device 104. Memory controller 106 can manage data stored in memory device 104 and communicate with host 108. In some embodiments, memory controller 106 is designed to operate in low duty cycle environments, such as Secure Digital (SD) cards, Compact Flash (CF) cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc. In some embodiments, memory controller 106 is designed to operate in high duty cycle environments in solid state drives (SSDs) or embedded multimedia cards (eMMCs), which serve as data storage for mobile devices such as smartphones, tablets, laptops, etc., and for enterprise storage arrays.

[0065] The memory controller 106 can be configured to control the operation of the memory device 104, such as read, erase, and program operations. The memory controller 106 can also be configured to manage various functions relating to data stored or to be stored in the memory device 104, including but not limited to bad block management, garbage collection, logical-to-physical address translation, wear leveling, etc. In some embodiments, the memory controller 106 is also configured to process error-correcting codes (ECC) relating to data read from or written to the memory device 104. The memory controller 106 can also perform any other suitable functions, such as formatting the memory device 104. The memory controller 106 can communicate with external devices (e.g., host 108) according to specific communication protocols. For example, the memory controller 106 can communicate with external devices through at least one of various interface protocols, such as USB, MMC, Peripheral Component Interconnect (PCI), PCI-E, Advanced Technology Attachment (ATA), Serial ATA, Parallel ATA, Small Computer System Interface (SCSI), Enhanced Small Drive Interface (ESDI), Integrated Drive Electronics (IDE), and FireWire.

[0066] The memory controller 106 and one or more memory devices 104 can be integrated into various types of storage devices, for example, included in the same package (e.g., a Universal Flash Storage (UFS) package or an eMMC package). That is, the memory system 102 can be implemented and packaged into different types of end electronic products. Figure 2aIn one example shown, the memory controller 106 and a single memory device 104 can be integrated into the memory card 202. The memory card 202 may include a PC card (PCMCIA, Personal Computer Memory Card International Association), a CF card (Compact Flash), a Smart Media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (Secure Digital Card) (SD, miniSD, microSD, SDHC), UFS, etc. The memory card 202 may also include a connection between the memory card 202 and a host computer (e.g., Figure 1 The host 108) is coupled to the memory card connector 204. In such a... Figure 2b In another example shown, the memory controller 106 and multiple memory devices 104 may be integrated into the SSD 206. The SSD 206 may also include a connection between the SSD 206 and a host (e.g., Figure 1 The SSD connector 208 is coupled to the host 108. In some embodiments, the storage capacity and / or operating speed of the SSD 206 is greater than the storage capacity and / or operating speed of the memory card 202.

[0067] Figure 3a An exemplary schematic diagram of a memory cell array for a three-dimensional NAND flash memory is provided, such as... Figure 3a As shown, the memory cell array of a three-dimensional NAND flash memory consists of several rows of parallel, staggered memory cell rows parallel to the gate isolation structure. Each pair of memory cell rows is separated by a gate isolation structure and an up-select gate isolation structure. Each memory cell row includes multiple memory cells. The gate isolation structure may include a first gate isolation structure and a second gate isolation structure. The first gate isolation structure divides the memory cell array into multiple memory blocks. Multiple second gate isolation structures can divide the memory blocks into multiple finger memory regions. An up-select gate isolation structure located in the middle of each finger memory region can divide the finger memory region into two parts, thereby dividing the finger memory region into two memory chips. Figure 3a The memory block shown contains 6 memory chips; however, in practical applications, the number of memory chips in a memory block is not limited to this. A memory cell in a memory block coupled to a word line can be called a memory page.

[0068] It should be noted that, Figure 3aThe number of memory cell rows between the gate isolation structure and the top-select gate isolation structure given is merely an exemplary example and is not intended to limit the number of memory cell rows contained in a single memory region of the three-dimensional NAND memory in this disclosure. In practical applications, the number of memory cell rows contained in a single memory region can be adjusted according to actual conditions, such as 2, 4, 8, 16, etc.

[0069] Figure 3b A schematic circuit diagram of an exemplary memory device 300, including peripheral circuitry, is shown according to some aspects of this disclosure. The memory device 300 may be... Figure 1 An example of memory device 104 is provided. Memory device 300 may include a memory cell array 301 and peripheral circuitry 302 coupled to the memory cell array 301. The memory cell array 301 is illustrated as a three-dimensional NAND-type memory cell array, wherein the memory cells 306 are provided in the form of an array of NAND memory strings 308, each NAND memory string 308 extending vertically above a substrate (not shown). In some embodiments, each NAND memory string 308 includes a plurality of memory cells 306 coupled in series and stacked vertically. Each memory cell 306 may hold a continuous analog value, such as voltage or charge, depending on the number of electrons trapped in the region of the memory cell 306. Each memory cell 306 may be a floating-gate type memory cell including a floating-gate transistor, or a charge-trapping type memory cell including a charge-trapping transistor.

[0070] In some implementations, each memory cell 306 is a single-level cell (SLC) having two possible memory states and thus capable of storing one bit of data. For example, a first memory state "0" may correspond to a first voltage range, and a second memory state "1" may correspond to a second voltage range. In some implementations, each memory cell 306 is a multi-level cell (MLC) capable of storing more than a single bit of data in more than four memory states. For example, an MLC may store two bits per cell, three bits per cell (also known as a trinary-level cell (TLC)), or four bits per cell (also known as a quad-level cell (QLC)). Each MLC can be programmed to take a range of possible nominal storage values. In one example, if each MLC stores two bits of data, the MLC can be programmed to take one of three possible programming levels from the erase state by writing one of the three possible nominal storage values ​​to the cell. A fourth nominal storage value can be used for the erase state.

[0071] like Figure 3b As shown, each NAND memory string 308 may include a bottom select gate (BSG) 310 at its source end and a top select gate (TSG) 312 at its drain end. BSG 310 and TSG 312 may be configured to activate the selected NAND memory string 308 during read and program operations. In some embodiments, the sources of the NAND memory strings 308 in the same memory block 304 are coupled via a common source line (SL) 314 (e.g., a common SL). In other words, according to some embodiments, all NAND memory strings 308 in the same memory block 304 have an array common source (ACS). According to some embodiments, the TSG 312 of each NAND memory string 308 is coupled to a corresponding bit line (BL) 316, from which data can be read or written via an output bus (not shown). In some implementations, each NAND memory string 308 is configured to be selected or deselected by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having TSG 312) or a deselection voltage (e.g., 0V) to the corresponding TSG 312 via one or more TSG lines 313 and / or by applying a selection voltage (e.g., higher than the threshold voltage of the transistor having BSG 310) or a deselection voltage (e.g., 0V) to the corresponding BSG 310 via one or more BSG lines 315.

[0072] like Figure 3bAs shown, NAND memory strings 308 can be organized into multiple memory blocks 304, each of which may have a common source line 314 (e.g., coupled to ground). In some embodiments, each memory block 304 is the basic data unit for an erase operation, i.e., all memory cells 306 on the same memory block 304 are erased simultaneously. To erase memory cells 306 in a selected memory block, an erase voltage (Vers) (e.g., a high positive voltage (e.g., 20V or higher)) can be used to bias and couple the source line 314 of the selected memory block and the unselected memory blocks on the same plane as the selected memory block. It should be understood that in some examples, erase operations can be performed at the half-block level, at the quarter-block level, or at a level with any suitable number of memory blocks or any suitable fraction of memory blocks. Memory cells 306 of adjacent NAND memory strings 308 can be coupled via word lines 318, which select which row of memory cells 306 is affected by read and program operations. In some implementations, each word line 318 is coupled to a page 320 of a memory cell 306, where the page 320 is the basic data unit used for programming operations. The size of a page 320, in bits, can be related to the number of NAND memory strings 308 coupled by word lines 318 in a memory block 304. Each word line 318 may include multiple control gates (gate electrodes) at each memory cell 306 in the corresponding page 320, as well as gate lines coupling the control gates. (This is in conjunction with the preceding...) Figure 3a A page 320 contains multiple memory cells 306, which are separated by an up-select gate isolation structure and a gate isolation structure. The multiple memory cells between the up-select gate isolation structure and the gate isolation structure are arranged into multiple memory cell rows, each of which is parallel to the gate isolation structure and the up-select gate isolation structure. The memory cells in the memory chip that share the same word line form a programmable (read / write) page.

[0073] Figure 4 A schematic cross-sectional view of an exemplary memory cell array 301 including NAND memory strings 308 is shown, according to some aspects of this disclosure. Figure 4 As shown, the NAND memory string 308 may include a stacked structure 410, which includes multiple gate layers 411 and multiple insulating layers 412 stacked alternately in sequence, and a memory string 308 perpendicularly penetrating the gate layers 411 and insulating layers 412. The gate layers 411 and insulating layers 412 may be stacked alternately, with adjacent gate layers 411 separated by an insulating layer 412. The number of pairs of gate layers 411 and insulating layers 412 in the stacked structure 410 determines the number of memory cells included in the memory cell array 401.

[0074] The constituent materials of the gate layer 411 may include conductive materials. Conductive materials include, but are not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicides, or any combination thereof. In some embodiments, each gate layer 411 includes a metal layer, such as a tungsten layer. In some embodiments, each gate layer 411 includes a doped polysilicon layer. Each gate layer 411 may include a control gate surrounding a memory cell. The gate layer 411 at the top of the stack 410 may extend laterally as an upper select gate line, the gate layer 411 at the bottom of the stack 410 may extend laterally as a lower select gate line, and the gate layer 411 extending laterally between the upper and lower select gate lines may serve as a word line layer.

[0075] In some embodiments, the stacked structure 410 may be disposed on the substrate 401. The substrate 401 may include silicon (e.g., single-crystal silicon), silicon-germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon-on-insulator (SOI), germanium-on-insulator (GOI), or any other suitable material.

[0076] In some embodiments, the NAND memory string 308 includes a channel structure extending vertically through the stacked structure 410. In some embodiments, the channel structure includes channel vias filled with one or more semiconductor materials (e.g., as a semiconductor channel) and one or more dielectric materials (e.g., as a memory film). In some embodiments, the semiconductor channel includes silicon, for example, polysilicon. In some embodiments, the memory film is a composite dielectric layer including a tunneling layer, a storage layer (also referred to as a "charge trap / storage layer"), and a barrier layer. The channel structure may have a cylindrical shape (e.g., a pillar shape). According to some embodiments, the semiconductor channel, tunneling layer, storage layer, and barrier layer are arranged radially from the center of the pillar toward the outer surface of the pillar in this order. The tunneling layer may include silicon oxide, silicon oxynitride, or any combination thereof. The storage layer may include silicon nitride, silicon oxynitride, or any combination thereof. The barrier layer may include silicon oxide, silicon oxynitride, a high dielectric constant (high k) dielectric, or any combination thereof. In one example, the memory film may include a composite layer of silicon oxide / silicon oxynitride / silicon oxide (ONO).

[0077] Return to reference Figure 3bPeripheral circuitry 302 can be coupled to memory cell array 301 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313. Peripheral circuitry 302 can include any suitable analog, digital, and mixed-signal circuitry to facilitate operation of memory cell array 301 by applying voltage and / or current signals to each target memory cell 306 via bit line 316, word line 318, source line 314, BSG line 315, and TSG line 313, and by sensing voltage and / or current signals from each target memory cell 306. Peripheral circuitry 302 can include various types of peripheral circuitry formed using metal-oxide-semiconductor (MOS) technology. For example, Figure 5 Some exemplary peripheral circuitry is shown. Peripheral circuitry 302 includes a page buffer / sensor amplifier 504, a column decoder / bit line driver 506, a row decoder / word line driver 508, a voltage generator 510, control logic 512, a register 514, an interface 516, and a data bus 518. It should be understood that in some examples, additional peripheral circuitry may be included. Figure 5 Additional peripheral circuitry not shown.

[0078] Page buffer / sensor amplifier 504 can be configured to read data from memory cell array 301 and program (write) data to memory cell array 301 according to control signals from control logic 512. In one example, page buffer / sensor amplifier 504 can store a page of programming data (write data) to be programmed into a page 320 of memory cell array 301. In another example, page buffer / sensor amplifier 504 can perform a programming verification operation to ensure that data has been correctly programmed into memory cell 306 coupled to selected word line 318. In yet another example, page buffer / sensor amplifier 504 can also sense a low-power signal from bit line 316 representing a data bit stored in memory cell 306 and amplify a small voltage swing to a recognizable logic level during read operations. Column decoder / bit line driver 506 can be configured to be controlled by control logic 512 and select one or more NAND memory strings 308 by applying a bit line voltage generated from voltage generator 510.

[0079] The row decoder / word line driver 508 can be configured to be controlled by control logic 512 and to select / deselect memory blocks 304 of the memory cell array 301 and to select / deselect word lines 318 of the memory blocks 304. The row decoder / word line driver 508 can also be configured to drive word lines 318 using word line voltages generated from voltage generator 510. In some embodiments, the row decoder / word line driver 508 can also select / deselect and drive BSG lines 315 and TSG lines 313. As described in detail below, the row decoder / word line driver 508 is configured to perform programming operations on memory cells 306 coupled to one or more selected word lines 318. The voltage generator 510 can be configured to be controlled by control logic 512 and to generate word line voltages (e.g., read voltage, programming voltage, pass voltage, channel boost voltage, verification voltage, etc.), bit line voltages, and source line voltages to be supplied to the memory cell array 301.

[0080] In some specific embodiments, the programming operation may include multiple stages. For example, the programming operation may include a channel pre-charge stage, a channel boost stage, a programming pulse stage, and a recovery stage. In the channel pre-charge stage, a voltage generator can generate the voltage required for the next stage, such as the voltage applied to each gate, the channel boost voltage, etc.; in the channel boost stage, a channel boost voltage can be applied to the selected word line; in the programming pulse stage, the target voltage for each programming operation can be applied to the selected word line. In the recovery stage, the voltage can be reduced to the corresponding voltage for both unselected and selected word lines. The recovery stage can achieve the purpose of step-down to the corresponding voltage once or multiple times, such as first reducing the voltage to an intermediate voltage, maintaining it at that intermediate voltage for a period of time, and then reducing it to the corresponding voltage.

[0081] Control logic 512 can be coupled to each of the peripheral circuits described above and is configured to control the operation of each peripheral circuit. Register 514 can be coupled to control logic 512 and includes a status register, a command register, and an address register for storing status information, command opcodes (OP codes), and command addresses for controlling the operation of each peripheral circuit. Interface 516 can be coupled to control logic 512 and acts as a control buffer to buffer control commands received from the host (not shown) and relay them to control logic 512, as well as to buffer status information received from control logic 512 and relay it to the host. Interface 516 can also be coupled to column decoder / bitline driver 506 via data bus 518 and acts as a data I / O interface and data buffer to buffer data and relay it to or from memory cell array 301.

[0082] In NAND flash memory, Single-Level Cell (SLC) memory holds a certain market share due to its advantages such as fast read / write speeds, high reliability, and long lifespan. It should be noted that the number of bits stored in a memory cell in SLC mode includes one bit.

[0083] Typically, Incremental Step-Pulse Programming (ISPP) is used to write to NAND flash memory. For NAND flash memory, write operations are performed on a page-by-page basis, with each page containing multiple memory cells. Specifically, in SLC mode, at the start of programming, a first programming pulse is applied to the selected page in the memory. Then, programming verification is performed on that page to check if the threshold voltage of each memory cell in the page reaches the target threshold voltage. If the number of memory cells not written to the target threshold voltage exceeds the allowable range, a second programming pulse with a higher voltage is applied, and programming verification is performed again after the second programming pulse. This process of applying programming pulses and performing programming verification is repeated until the number of memory cells not written to the target threshold voltage is within the allowable range, at which point the programming of the entire page is complete.

[0084] To facilitate the evaluation of the number of memory cells in a page that have not been written to the target threshold voltage after a programming pulse is applied, the Failed Bit Count (FBC) is introduced. The Failed Bit Count refers to the number of bits in the page that have not been written to the target threshold voltage. In practical applications, during programming verification, the relationship between the Failed Bit Count and the target Failed Bit Count can be used to determine whether programming has succeeded.

[0085] For example, if the number of failed bits on the page is greater than the target number of failed bits (i.e., the number of failed bits on the page is not within the allowable range of the target number of failed bits), a new programming pulse with a higher voltage is applied, and programming verification is performed again after applying this new programming pulse. This process of applying programming pulses and performing verification is repeated until the number of failed bits on the page is less than or equal to the target number of failed bits (i.e., the number of failed bits on the page is within the allowable range of the target number of failed bits), at which point the programming of the entire page is complete.

[0086] In some embodiments, a maximum number of programming pulses can be set. When the number of programming pulses applied is less than this maximum number, the process of applying programming pulses and performing verification can be repeated until the number of failed bits is less than or equal to the target number of failed bits. When the number of programming pulses applied is equal to the maximum number, and the number of failed bits is still greater than the target number of failed bits, programming of the page can be stopped, and the programming of the page is considered to have failed.

[0087] It should be noted that the target threshold voltage is used to determine whether a memory cell has reached the target programming state. Specifically, when the threshold voltage of a memory cell is greater than the target threshold voltage, the memory cell has reached the programming state. When the threshold voltage of a memory cell is less than or equal to the target threshold voltage, the memory cell has not reached the target programming state.

[0088] As mentioned above, the programming method requires multiple programming pulses, and after each programming pulse, a verification voltage needs to be applied to check the programming result of the page. Therefore, the programming time (Tprog) is relatively long.

[0089] In some specific embodiments, a Dynamic Single Level Cell (DSLC) mode has evolved to shorten programming time. In DSLC mode, a large programming pulse is applied to a page, causing the page to be written to the target programming state in one go. Here, writing a page to the target programming state means making the number of failed bits of the page less than or equal to the target number of failed bits. This DSLC programming mode can shorten programming time. However, DSLC mode may cause the threshold voltage of the memory cell in the page to be much higher than the target threshold voltage (also known as overprogramming). As the number of erase and write cycles increases, overprogramming causes the threshold voltage of the programmed state of the memory cell to shift, and the erase state to degrade, reducing the reliability of the NAND flash memory.

[0090] Based on this, in order to overcome the shortcomings of SLC mode or DSLC mode, such as slow programming speed and reduced reliability, this disclosure proposes a new programming mode, referring to... Figure 6 When programming using this new mode, a first programming pulse, a first verification pulse, a second programming pulse, and a second verification pulse are sequentially applied to the word lines coupled to the selected page to write the page to the target programming state. During the application of the second programming pulse, a comparison and judgment are made regarding whether a second verification pulse is needed. For example, if the failure bit count (the aforementioned number of failure bits) is less than the maximum number of memory cells in the selected page that have not reached the target programming state (the target number of failure bits), then a second verification pulse is not needed for the selected page; if the failure bit count (the aforementioned number of failure bits) is greater than the maximum number of memory cells in the selected page that have not reached the target programming state (the target number of failure bits), then a second verification pulse is needed for the selected page. Here, the second verification pulse and the recovery pulse can be applied using the same pulse.

[0091] However, in this programming operation, it's possible that after applying the first programming pulse to the word line coupled to the selected page, the selected page has already been written to the target programming state; in this case, there's no need to apply a second programming pulse to the selected page. However, since the determination of whether a second programming pulse needs to be applied (also known as the verification count (Vfc, VerifyCount)) is always performed simultaneously with the second programming pulse, in some specific embodiments, regardless of whether the selected page has reached the target programming state after the first programming pulse is applied, this programming mode will continue to apply a second programming pulse to the selected page. In this case, the programming time is not shortened, and some memory cells may suffer from repeated programming (or over-programming), which may cause more serious damage to some memory cells, thereby reducing the reliability of the memory device.

[0092] For example, the memory device may include multiple test blocks, each with a different number of erase / write cycles. Here, block 87 (Block = 87) is used as an example for illustration. (Refer to...) Figure 7 , Figure 7 The image shows the comparison results of two threshold voltage distribution curves for memory cells corresponding to the same selected page; where, Figure 7 The horizontal axis represents the threshold voltage, and the vertical axis represents the number of memory cells. The two dashed lines represent the threshold voltage distribution curves of the memory cells in the selected page after applying the first programming pulse, and the two solid lines represent the threshold voltage distribution curves of the memory cells in the selected page after applying the first and second programming pulses, respectively. Here, the two dashed lines correspond one-to-one with the two solid lines; that is, one dashed line and its corresponding solid line are used to illustrate the threshold voltage distribution curves when one programming pulse and two programming pulses are applied to the memory cells, respectively. Figure 7 As can be seen, after applying a second programming pulse to a memory cell that does not require a second programming pulse, the shift of the threshold voltage corresponding to the memory cell, whether in the erase state or the programming state, is more severe.

[0093] Based on this, the present disclosure provides another memory device and a corresponding programming operation method, wherein the memory device includes: a memory cell array including multiple pages, each page including multiple memory cells;

[0094] Peripheral circuitry, coupled to the memory cell array; the peripheral circuitry is configured as follows:

[0095] The memory cells of the selected page from the plurality of pages are programmed; during the programming operation, a first programming pulse and a first verification pulse are applied to the word line coupled to the selected page; at the first moment of the application of the first verification pulse, the first failure bit count (i.e., the number of failure bits at the first moment) of the selected page is detected; and,

[0096] Based on the comparison result between the first failure bit count and the first preset value (i.e., the target failure bit count at the first moment), it is determined whether to apply a second programming pulse to the word line. The level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse. The first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse.

[0097] Here, the selected page can be any one of multiple pages in the memory cell array; the memory cell is used to store data. The peripheral circuitry includes: a voltage generator, a row driver, control logic, etc.

[0098] Here, the voltage generator can be understood with reference to the aforementioned voltage generator 510. This voltage generator is used to generate a series of voltages required for programming operations, such as programming pulses and verification pulses, which are applied to the word lines coupled to the selected page. The row driver can specifically be the aforementioned... Figure 5 The WL driver 508 is used; the voltage generator is coupled to the word line of the selected page via a row driver. The control logic can be referred to above. Figure 5 We will understand the control logic 512 in it.

[0099] In some specific embodiments, the control logic may, upon receiving a programming operation (write) instruction, respond to the programming operation instruction by controlling the voltage generator to generate a first programming pulse and a first verification pulse, and controlling the row driver to apply the first programming pulse and the first verification pulse to the word line coupled to the selected page.

[0100] It should be noted that the programming operation described here includes at least a programming phase, a verification phase, and a recovery phase. The programming phase can be understood as applying a programming pulse to the word line coupled to the selected page to program (write) the selected page; the verification phase can be understood as applying a verification pulse to the word line coupled to the selected page after applying the programming pulse to verify whether the selected page has reached the target programming state; the recovery phase can be understood as applying a recovery pulse to the word line coupled to the selected page after the selected page has reached the programming state to reduce the voltage of the selected page to the target voltage.

[0101] After applying a first programming pulse and a first verification pulse to the word line coupled to the selected page, the control logic is configured to detect a first failure bit count of the selected page at a first moment when the first verification pulse is applied. Figure 8a , Figure 8b , Figure 8c The fine detection shown in the diagram, and the detection of the second failure bit count of the selected page at the second moment when the first verification pulse is applied. Figure 8a , Figure 8b , Figure 8c The diagram shows a coarse detection; here, the second time step is earlier than the first time step, i.e., the second failure bit count (i.e., the number of failure bits at the second time step) is detected first, followed by the first failure bit count. The voltages corresponding to the first and second time steps are different. The voltages corresponding to the first and second time steps can be adjusted according to the actual situation. The voltage corresponding to the first time step can be near the minimum value of the threshold voltage corresponding to the target programming state, and the voltage corresponding to the second time step can be less than the minimum value of the threshold voltage corresponding to the target programming state. Specifically, the voltage corresponding to the first time step can be the voltage during the stable period of the verification pulse, and the voltage corresponding to the second time step can be a certain voltage during the ramp-up period of the verification pulse. For example, the voltage corresponding to the first time step is 1.2V, and the voltage corresponding to the second time step is 0.8V.

[0102] In some embodiments, the peripheral circuitry further includes: a first latch and a second latch; wherein the first latch is used at least to store a second failure bit count detected; and the second latch is used at least to store a first failure bit count detected.

[0103] Here, after detecting the second failure bit count of the selected page, the second failure bit count is stored in the first latch; after detecting the first failure bit count of the selected page, the first failure bit count is stored in the second latch. For example, the first latch is an L latch, and the second latch is an S latch.

[0104] Here, the first programming pulse is the initial programming pulse. For example, the initial programming pulse could be the first programming pulse applied to the selected page after the memory cell array has been erased. The signal value of the first verification pulse could be equal to the target threshold voltage of a single-level memory cell, to verify whether each memory cell in the selected page has been written to the target threshold voltage.

[0105] In some specific embodiments, it can be determined, based on the verification result of the first verification pulse, whether a second programming pulse needs to be applied to the word line coupled to the selected page after applying the first programming pulse and the first verification pulse.

[0106] In other specific embodiments, it can also be determined whether a second verification pulse needs to be applied to the word line coupled to the selected page after the second programming pulse is applied, based on the comparison result of the second failure bit count and the second preset value.

[0107] Based on this, in some embodiments, the programming logic is further configured as follows:

[0108] After the first programming pulse (or at or after the first moment), a first preset value is obtained; the first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse.

[0109] In addition, when detecting the second failure bit count (at the second moment), a second preset value (i.e., the target failure bit count at the second moment) is obtained. The second preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state when detecting the second failure bit count.

[0110] Here, the first preset value and the second preset value can be understood as the target number of failed bits at different times. Both are measured and stored based on actual experience before leaving the factory. Both the first and second preset values ​​can be stored in the registers or latches of the memory device. When it is necessary to use the first and / or second preset values ​​for calculation, judgment, or comparison, they can be directly obtained from the registers or latches according to actual needs. In some specific embodiments, the first preset value is less than the second preset value; for example, the first preset value is 200 and the second preset value is 3000. Furthermore, it should be noted that the number of boundary values ​​can be understood as the maximum number of memory cells that the memory can allow to not reach the target programming state at a given time.

[0111] To better understand the criteria for determining whether to apply a second programming pulse to the word line coupled to the selected page, a detailed explanation with examples is provided below.

[0112] In some specific embodiments, it can be determined whether to apply a second programming pulse to the word line coupled to the selected page based on the comparison result of the first failure bit count and the first preset value. Figure 8a , Figure 8b , Figure 8c (The detailed verification judgment shown in the figure).

[0113] For example, at the first moment, the first preset value is 200, meaning that after the first programming pulse, the maximum number of memory cells in the selected page that have not reached the target programming state is 200. If the detected first failure bit count is 150, meaning the first failure bit count is less than the first preset value, it can be determined that after the first programming pulse is applied, all memory cells in the selected page can reach the target programming state. Therefore, it is not necessary to apply a second programming pulse to the word line coupled to the selected page. (Refer to...) Figure 8a At this point, the programming and verification phases of the programming operation end. If the first fault bit count is 300, meaning the first fault bit count is greater than the first preset value, then after applying the first programming pulse and the first verification pulse, a second programming pulse needs to be applied to the word line coupled to the selected page, as per the reference. Figure 8b , Figure 8c If the first fault bit count is 200, meaning the first fault bit count equals the first preset value, there is no need to apply a second programming pulse to the word line coupled to the selected page. (Refer to...) Figure 8a .

[0114] In other words, when the first failure bit count is less than or equal to the first preset value, there is no need to apply a second programming pulse to the word line, and the programming and verification phases of the programming operation end. When the first failure bit count is greater than the first preset value, a second programming pulse needs to be applied to the word line.

[0115] Here, the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse.

[0116] It should be noted that regardless of whether a second programming pulse is applied to the word line coupled to the selected page, the verification count of the selected page is completed after the first verification pulse is applied (or before the second programming pulse is applied).

[0117] Additionally, it should be noted that during the application of the first verification pulse, if there is sufficient time, it is also possible to determine whether the selected page needs to be subjected to the second verification pulse after the application of the second programming pulse by comparing the result of the second failure bit count with the second preset value. The specific judgment situation is described later and will not be repeated here.

[0118] In some embodiments, the comparison result between the first failure bit count and the first preset value can be understood as a fine verification result, and the comparison result between the second preset value and the second failure bit count can be understood as a coarse verification result. Here, the criterion for determining whether to apply a second programming pulse to the word line coupled to the selected page is still based on the fine verification result.

[0119] It should be noted that, Figure 8aThe timing diagram shows the application of the first programming pulse, the first verification pulse, and the recovery pulse during the programming operation; Figure 8b The diagram shows the timing of the application of the first programming pulse, the first verification pulse, the second programming pulse, and the recovery pulse during the programming operation. Figure 8c The diagram shows the timing of the application of the first programming pulse, the first verification pulse, the second programming pulse, the second verification pulse, and the recovery pulse during the programming operation. Figure 8c The second verification pulse and the recovery pulse are not applied by the same pulse.

[0120] Based on this, in this embodiment of the disclosure, it can be determined whether a second programming pulse needs to be applied according to the actual programming state of the memory cell, thereby reducing the number of unnecessary programming pulses and thus improving programming efficiency. At the same time, it can reduce the damage of unnecessary programming pulses to the memory cell and improve reliability.

[0121] The following section provides a detailed explanation of the criteria for determining whether a second verification pulse is applied to the word lines coupled to the selected page, using examples.

[0122] In some specific embodiments, during the application of the second programming pulse, a determination is made as to whether to apply a second verification pulse to the word line based on the comparison result between the second failure bit count and the second preset value. Figure 8b , Figure 8c (The rough verification judgment shown in the figure).

[0123] Here, during the application of the second programming pulse, a second preset value is compared with a second failure bit count. Specifically, if the second failure bit count is less than or equal to the second preset value, a second verification pulse is not applied to the word line. Figure 8b The programming and verification phases of the programming operation are completed; when the second failure bit count is greater than the second preset value, a second verification pulse is applied to the word line, referring to... Figure 8c The programming and verification phases of the programming operation are now complete.

[0124] For example, at the second time point, the obtained second preset value is 3000, meaning the maximum number of memory cells in the selected page that have not reached the target programming state at that time is 3000. If the detected second failure bit count is 2000, meaning the second failure bit count is less than the second preset value, it indicates that a second verification pulse does not need to be applied to the selected page after applying the second programming pulse. At this time, the programming and verification phases of the programming operation end. If the detected second failure bit count is 4000, meaning the second failure bit count is greater than the second preset value, it indicates that a second verification pulse needs to be applied to the selected page after applying the second programming pulse. If the obtained second failure bit count is 3000, meaning the second failure bit count is equal to the second preset value, it is no longer necessary to apply a second verification pulse to the word line coupled to the selected page.

[0125] Based on this, refer to Figure 8a , Figure 8b , Figure 8c In some embodiments, the peripheral circuitry is further configured as follows:

[0126] After the programming and verification phases of the programming operation are completed, a recovery pulse is applied to the word line coupled to the selected page to restore the word line coupled to the target voltage.

[0127] In some embodiments, the memory device includes, but is not limited to, a three-dimensional NAND flash memory.

[0128] This disclosure also provides a memory system, the memory system comprising:

[0129] One or more memory devices as described in any of the above embodiments; and

[0130] A memory controller, which is coupled to and controls the memory device.

[0131] Here, the specific structure and composition of the memory system can be referred to the foregoing. Figure 1 , Figure 2a , Figure 2b The relevant structure and composition of the memory system 102 are described below. For the sake of brevity, they will not be elaborated here.

[0132] In some embodiments, the memory system includes a memory card or a solid-state drive.

[0133] Based on the above-described memory device, this disclosure also provides a method for operating the memory device, such as... Figure 9 As shown, the memory device includes: a plurality of pages, each page including a plurality of memory cells; the operation method includes:

[0134] Step S901: Program the memory cell of the selected page from the plurality of pages; during the programming operation, apply a first programming pulse and a first verification pulse to the word line coupled to the selected page; at the first moment of the application of the first verification pulse, detect the first failure bit count of the selected page; and,

[0135] Step S902: Based on the comparison result between the first failure bit count and the first preset value, determine whether to apply a second programming pulse to the word line, wherein the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse; the first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse.

[0136] In some embodiments, determining whether to apply a second programming pulse to the word line based on the comparison result of the first failed bit count and a first preset value includes:

[0137] When the first failure bit count is less than or equal to the first preset value, no second programming pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0138] In some embodiments, determining whether to apply a second programming pulse to the word line based on the comparison result of the first failed bit count and a first preset value includes:

[0139] When the first failure bit count is greater than the first preset value, a second programming pulse is applied to the word line.

[0140] In some embodiments, the method further includes: detecting a second failure bit count of the selected page at a second moment when the first verification pulse is applied; the second moment being earlier than the first moment; and,

[0141] During the application of the second programming pulse, a second verification pulse is applied to the word line based on the comparison result between the second failure bit count and the second preset value. The second preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state when the second failure bit count is detected.

[0142] In some embodiments, determining whether to apply a second verification pulse to the word line based on the comparison result between the second failure bit count and the second preset value includes:

[0143] When the second failure bit count is less than or equal to the second preset value, no second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0144] When the second failure bit count is greater than the second preset value, a second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

[0145] In some embodiments, the method further includes: storing the second failure bit count in a first latch after detecting a second failure bit count of the selected page; and storing the first failure bit count in a second latch after detecting a first failure bit count of the selected page.

[0146] In some embodiments, the method further includes applying a recovery pulse to the word line coupled to the selected page after the programming and verification phases of the programming operation have ended.

[0147] In this embodiment of the disclosure, during the programming operation, a first failure bit count and a first preset value are acquired. The first failure bit count represents the actual number of memory cells in the selected page that have not reached the target programming state after the first programming pulse. The first preset value represents the maximum number of memory cells in the selected page that have not reached the target programming state after the first programming pulse. By comparing the first failure bit count with the first preset value, it is determined whether a second programming pulse with a higher level needs to be applied to the word line coupled to the selected page. In this way, it is possible to determine whether a second programming pulse needs to be applied based on the actual programming state of the memory cell, reducing the number of unnecessary programming pulses and thus improving programming efficiency. At the same time, it is possible to reduce the damage to the memory cell caused by excess programming pulses and improve reliability.

[0148] It should be understood that the phrase "an embodiment" or "one embodiment" throughout the specification means that a specific feature, structure, or characteristic related to the embodiment is included in at least one embodiment of this disclosure. Therefore, "in one embodiment" or "one embodiment" appearing throughout the specification does not necessarily refer to the same embodiment. Furthermore, these specific features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that in the various embodiments of this disclosure, the sequence numbers of the above-described processes do not imply a sequential order of execution; the execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this disclosure. The sequence numbers of the above-described embodiments are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0149] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0150] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A memory device, characterized in that, include: A memory cell array comprising multiple pages, each page comprising multiple memory cells; Peripheral circuitry is coupled to the memory cell array; The peripheral circuit is configured as follows: A programming operation is performed on the memory cell of a selected page from the plurality of pages; during the execution of the programming operation, a first programming pulse and a first verification pulse are applied to the word line coupled to the selected page; at the first moment when the first verification pulse is applied, the first failure bit count of the selected page is detected; At a second moment when the first verification pulse is applied, the second failure bit count of the selected page is detected; the second moment is earlier than the first moment; the voltage of the first verification pulse corresponding to the first moment is greater than the voltage of the first verification pulse corresponding to the second moment; as well as, Based on the comparison result between the first failure bit count and the first preset value, it is determined whether to apply a second programming pulse to the word line, wherein the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse; The first preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state after the first programming pulse; During the application of the second programming pulse, a second verification pulse is applied to the word line based on the comparison result between the second failure bit count and the second preset value. The second preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state when the second failure bit count is detected.

2. The memory device according to claim 1, characterized in that, The peripheral circuit is also configured to: When the first failure bit count is less than or equal to the first preset value, no second programming pulse is applied to the word line, and the programming and verification phases of the programming operation end.

3. The memory device according to claim 1, characterized in that, The peripheral circuit is also configured to: When the first failure bit count is greater than the first preset value, a second programming pulse is applied to the word line.

4. The memory device according to claim 3, characterized in that, The peripheral circuit is also configured to: When the second failure bit count is less than or equal to the second preset value, no second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end. When the second failure bit count is greater than the second preset value, a second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

5. The memory device according to claim 3, characterized in that, The peripheral circuit includes a first latch and a second latch; wherein the first latch is used to store at least the detected second failure bit count, and the second latch is used to store at least the detected first failure bit count.

6. The memory device according to claim 2 or 4, characterized in that, The peripheral circuit is also configured to: After the programming and verification phases of the programming operation are completed, a recovery pulse is applied to the word line coupled to the selected page.

7. The memory device according to any one of claims 1 to 6, characterized in that, The memory cell stores one bit of data.

8. A memory system, characterized in that, include: The memory device as described in any one of claims 1 to 7; as well as Memory controller; The memory controller is coupled to the memory device and is used to control the memory device.

9. A method of operating a memory device, characterized in that, The memory device includes: a plurality of pages, each page including a plurality of memory cells; the operation method includes: The memory cells of a selected page from the plurality of pages are programmed; during the programming operation, a first programming pulse and a first verification pulse are applied to the word lines coupled to the selected page; at a first moment when the first verification pulse is applied, a first fault bit count of the selected page is detected; at a second moment when the first verification pulse is applied, a second fault bit count of the selected page is detected; the second moment is earlier than the first moment; the voltage of the first verification pulse corresponding to the first moment is greater than the voltage of the first verification pulse corresponding to the second moment; and, Based on the comparison result between the first failure bit count and the first preset value, it is determined whether to apply a second programming pulse to the word line, wherein the level corresponding to the second programming pulse is higher than the level corresponding to the first programming pulse; the first preset value is used to characterize the number of memory cell boundaries in the selected page that have not reached the target programming state after the first programming pulse; During the application of the second programming pulse, a second verification pulse is applied to the word line based on the comparison result between the second failure bit count and the second preset value. The second preset value is used to characterize the number of memory cells in the selected page that have not reached the target programming state when the second failure bit count is detected.

10. The method of operating the memory device according to claim 9, characterized in that, The step of determining whether to apply a second programming pulse to the word line based on the comparison result between the first failed bit count and the first preset value includes: When the first failure bit count is less than or equal to the first preset value, no second programming pulse is applied to the word line, and the programming and verification phases of the programming operation end.

11. The method of operating the memory device according to claim 9, characterized in that, The step of determining whether to apply a second programming pulse to the word line based on the comparison result between the first failed bit count and the first preset value includes: When the first failure bit count is greater than the first preset value, a second programming pulse is applied to the word line.

12. The method of operating the memory device according to claim 11, characterized in that, The step of determining whether to apply a second verification pulse to the word line based on the comparison result between the second failure bit count and the second preset value includes: When the second failure bit count is less than or equal to the second preset value, no second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end. When the second failure bit count is greater than the second preset value, a second verification pulse is applied to the word line, and the programming and verification phases of the programming operation end.

13. The method of operating the memory device according to claim 11, characterized in that, The method further includes: After detecting the second failure bit count of the selected page, the second failure bit count is stored in the first latch; After detecting the first failure bit count of the selected page, the first failure bit count is stored in the second latch.

14. The method of operating the memory device according to claim 10 or 12, characterized in that, The method further includes: After the programming and verification phases of the programming operation are completed, a recovery pulse is applied to the word line coupled to the selected page.

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