Shift register, gate drive circuit and display device

Abstract

The present invention discloses a shift register, a gate drive circuit, and a display device. The shift register includes an output subcircuit, a first reset subcircuit, and an absorption subcircuit. The input of the first reset subcircuit, the output of the output subcircuit, and the input of the absorption subcircuit are all connected to an output node. The control terminal of the first reset subcircuit is configured to be connected to a low level when the output subcircuit writes a high level to the output node, thereby causing the output node to output a gate drive signal. The absorption subcircuit is configured to absorb leakage current generated between the output node and the output of the first reset subcircuit when a high level is written to the output node. This invention solves the problem of the tail row in the display panel being unable to be driven, thereby improving the output stability of the display panel.

Description

Technical Field

[0001] The present invention relates to the field of display drive technology, and in particular to a shift register, a gate drive circuit and a display device. Background Art

[0002] A GOA (Gate Driven on Array) driver circuit integrates a shift register on the display panel's array substrate to form a gate drive circuit, enabling progressive scanning. This eliminates the need for a separate gate drive circuit, reducing production costs and enabling narrow-bezel panel designs. It is used by a wide variety of displays. Currently, GOA driver circuits used in VR (Virtual Reality) display products suffer from a problem where the last row cannot be driven during the drive process, resulting in abnormal output. Summary of the Invention

[0003] In view of the above problems, the present invention proposes a shift register, a gate drive circuit and a display device, which can be more stable when the output node is converted from a low level to a written high level, thereby improving the stability of the output gate drive signal, solving the problem that the last row in the current display panel cannot be driven, and improving the output stability of the display panel.

[0004] In the first aspect, the present application provides the following technical solutions through an embodiment:

[0005] A shift register comprises: an output subcircuit, a first reset subcircuit, and an absorption subcircuit; the input end of the first reset subcircuit, the output end of the output subcircuit, and the input end of the absorption subcircuit are all connected to an output node; the control end of the first reset subcircuit is configured to be connected to a low level when the output subcircuit writes a high level to the output node, so that the output node outputs a gate drive signal; the absorption subcircuit is configured to absorb leakage current generated between the output node and the output end of the first reset subcircuit when a high level is written to the output node.

[0006] Optionally, the absorption subcircuit includes a first absorption capacitor;

[0007] A first end of the first absorption capacitor is connected to the output node, and a second end of the first absorption capacitor is configured to be connected to a low level.

[0008] Optionally, the absorption sub-circuit includes a P-type transistor;

[0009] The first terminal of the P-type transistor is connected to the output node, and the second terminal and the control terminal of the P-type transistor are both configured to be connected to a low level.

[0010] Optionally, the first reset sub-circuit includes a first transistor and a second transistor, the first end of the first transistor and the control end of the second transistor are both connected to the output node, and the control end of the first transistor is connected to the first end of the second transistor; the first end of the first transistor is the input end of the first reset sub-circuit, and the control end of the first transistor is the control end of the first reset sub-circuit; the second end of the first transistor and the second end of the second transistor are both configured to be connected to a low level.

[0011] Optionally, the first reset sub-circuit further includes a second absorption capacitor;

[0012] A first end of the second absorption capacitor is connected to the control end of the first transistor; and a second end of the second absorption capacitor is configured to be connected to a low level.

[0013] Optionally, the shift register further includes: an input subcircuit; an output terminal of the input subcircuit and a control terminal of the output subcircuit are both connected to a pull-up node;

[0014] The input sub-circuit is configured to write a high level to the pull-up node under the control of a drive trigger signal to charge the output sub-circuit; the output sub-circuit is configured to write a high level to the output node after charging is completed to enable the output node to output a gate drive signal.

[0015] Optionally, the output sub-circuit includes: a storage capacitor and a third transistor; the first end of the storage capacitor and the control end of the third transistor are both connected to the pull-up node; the second end of the storage capacitor and the second end of the third transistor are both connected to the output node; the first end of the storage capacitor is the control end of the output sub-circuit, the first end of the third transistor is the input end of the output sub-circuit, and the second end of the third transistor is the output end of the output sub-circuit;

[0016] The first end of the storage capacitor is configured to be charged when a high level is written to the pull-up node; the first end of the third transistor is configured to receive a high-level clock signal after charging is completed to write a high level to the output node.

[0017] Optionally, the shift register further includes: a second reset sub-circuit, wherein an input terminal of the second reset sub-circuit is connected to the pull-up node, an output terminal of the second reset sub-circuit is configured to be connected to a low level, and a control terminal of the second reset sub-circuit is configured to be connected to a reset signal;

[0018] The second reset sub-circuit is configured to write a low level to the pull-up node under the control of a reset signal.

[0019] In the second aspect, based on the same inventive concept, this application provides the following technical solution through an embodiment:

[0020] A gate drive circuit for driving a display panel, the gate drive circuit comprising a plurality of shift registers as described in any one of the first aspects above, wherein the plurality of shift registers are cascaded in sequence; each shift register is configured to drive a row of sub-pixels in the display panel.

[0021] In the third aspect, based on the same inventive concept, this application provides the following technical solution through an embodiment:

[0022] A display device comprises sub-pixels arranged in an array and a shift register as described in any one of the first aspects above, wherein each row of the sub-pixels corresponds to one shift register; and the shift register is configured to drive the sub-pixels corresponding to a row.

[0023] A shift register, a gate drive circuit, and a display device provided in an embodiment of the present invention absorb leakage current generated between an output node and an output end of a first reset subcircuit by an absorption subcircuit when an output subcircuit writes a high level to the output node, thereby ensuring stability when the output node is converted from a low level to a written high level, ensuring that the output subcircuit can output a gate drive signal normally and stably, solving the problem of the tail row in the current display panel being unable to be driven, and improving the output stability of the display panel.

[0024] The above description is only an overview of the technical solution of the present invention. In order to more clearly understand the technical means of the present invention, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present invention more obvious and easy to understand, the specific implementation methods of the present invention are specifically listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Various other advantages and benefits will become apparent to those skilled in the art upon reading the detailed description of the preferred embodiment below. The accompanying drawings are for illustration purposes only and are not to be considered as limiting the present invention. The same reference symbols are used throughout the drawings to represent the same components. In the drawings:

[0026] Figure 1 Schematic diagram of the driving circuit structure of the double-sided driving product in an embodiment of the present invention;

[0027] Figure 2 for Figure 1 The driving timing diagram corresponding to the double-sided drive product;

[0028] Figure 3 for Figure 1 Schematic diagram of the structure of the double-sided drive product when the drive circuit is not improved;

[0029] Figure 4 1 is a schematic diagram of a first implementation structure of a shift register in an embodiment of the present invention;

[0030] Figure 5 2 is a schematic diagram of a second implementation structure of a shift register in an embodiment of the present invention;

[0031] Figure 6 FIG3 is a schematic diagram of a third implementation structure of a shift register in an embodiment of the present invention;

[0032] Figure 7 2 is a schematic diagram of a fourth implementation structure of a shift register in an embodiment of the present invention;

[0033] Figure 8 FIG5 is a schematic diagram of a fifth implementation structure of a shift register in an embodiment of the present invention;

[0034] Figure 9 FIG. 6 is a schematic diagram of a sixth implementation structure of a shift register in an embodiment of the present invention. DETAILED DESCRIPTION

[0035] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0036] Currently, the GOA drive circuits used in VR display products have a problem where the last row cannot be driven during the driving process, resulting in abnormal output. Analysis has found that compared to the input signal CLK corresponding to the GOA circuit, the gate drive signal output by the GOA circuit rises more slowly and has a longer power-up time. This results in a shorter charging time for the sub-pixel gate of the panel, or even an inability to charge to a high level. When the GOA circuits are cascaded, the sub-pixel gate voltage decreases step by step based on the charging sequence from first to last. When a certain row is reached, the GOA circuit at the next level may fail to drive, ultimately leading to display abnormalities.

[0037] For example, in a dual-side 4CLK driven product, the clock signal on each side of the display panel is 4CLK, and the CLK signals corresponding to the two sides differ by 1 / 8 cycle, forming an 8CLK structure. Figure 1 The control sequence corresponding to the nth row is as follows Figure 2 As shown, the corresponding group of sub-pixel gate voltages (Gate1 to Gate4 are the first side of the double-sided drive, and Gate5 to Gate8 are the second side of the double-sided drive) are as shown in FIG. Figure 3 As shown. Figure 3It can be seen that the gate voltage amplitudes of Gate1 to Gate4 decrease step by step, and the gate voltage amplitudes of Gate5 to Gate8 also decrease step by step; for example, the amplitude a1 is greater than the amplitude a2.

[0038] To address this issue, one embodiment of the present invention increases the gate charge rate of the sub-pixel by increasing the voltage difference between the gate-on voltage (VGH) and the gate-off voltage (VGL). However, during application, it was found that while this solution can improve the display problems caused by the inability to drive to a certain extent, it will lead to increased product power consumption and increased switching losses, which in turn leads to excessive power consumption and shortens the product lifespan.

[0039] Therefore, see Figure 4 In another embodiment of the present invention, a shift register 100 is provided. In the shift register 100, an absorption sub-circuit 130 is added to prevent leakage at the output node N of the shift register 100, which causes the sub-pixel gate to be unable to be quickly charged to a high level.

[0040] The shift register 100 includes an output sub-circuit 110, a first reset sub-circuit 120, and an absorption sub-circuit 130. The input of the first reset sub-circuit 120, the output of the output sub-circuit 110, and the input of the absorption sub-circuit 130 are all connected to an output node N. The control terminal of the first reset sub-circuit 120 is configured to be connected to a low level when the output sub-circuit 110 writes a high level to the output node N, so that the output node N outputs a gate drive signal. The output node N may be the output terminal of the shift register 100. The gate drive signal is a high-level signal. The absorption sub-circuit 130 is configured to absorb leakage current generated between the output node N and the output terminal of the first reset sub-circuit 120 when the output node N is written to a high level.

[0041] It is understandable that when the output sub-circuit 110 is connected to the charging signal, a Miller platform will be generated. When the output sub-circuit 110 switches from the charging state to outputting a high-level gate drive signal, the first reset sub-circuit 120 needs to remain in the off state. However, at this time, when the output sub-circuit 110 is charged, a first parasitic capacitance is generated in the first reset sub-circuit 120. When the output sub-circuit 110 is charged and writes a high level to the output node N, the Miller platform ends. At this time, a very high instantaneous voltage change (dV / dt) is generated between the first reset sub-circuit 120 and the output node N, thereby discharging the first parasitic capacitance and generating a current at the control terminal of the first reset sub-circuit 120 to form a voltage drop. The control terminal of the first reset sub-circuit 120 generates a spike voltage, reaches the turn-on voltage, and instantly turns on the first reset sub-circuit 120, causing leakage. Leakage current is generated in the first reset sub-circuit 120, and the output terminal of the first reset sub-circuit 120 is connected to a low level, thereby lowering the voltage of the output node N, resulting in a prolonged charging time of the sub-pixel gate, and even difficulty in completing charging. In other words, the thin-film transistors of the sub-pixels in the driven sub-pixel row are difficult to effectively turn on, making it difficult to drive the sub-pixels in that row. The data signal transmission time is insufficient, and the liquid crystal is not effectively flipped, resulting in poor display.

[0042] In the present application, an absorption sub-circuit 130 is added. When the output sub-circuit 110 writes a high level to the output node N, the absorption sub-circuit 130 can absorb the current generated between the output node N and the output terminal of the first reset sub-circuit 120, thereby preventing leakage current from occurring in the first reset sub-circuit 120. This allows the output node N to remain stable when transitioning from a low level to a high level, thereby ensuring that the output sub-circuit 110 can normally output the gate drive signal.

[0043] See also Figure 5 In some implementations, the absorption sub-circuit 130 may include a first absorption capacitor C1; the first end of the first absorption capacitor C1 is connected to the output node N, and the second end of the first absorption capacitor C1 is configured to be connected to a low level. In other words, the first end of the first absorption capacitor C1 is the input end, and the second end of the first absorption capacitor C1 is the output end. The low level may be the gate-off voltage (VGL). The current drained by the first absorption capacitor C1 can prevent leakage current between the output node N and the output end of the first reset sub-circuit 120, thereby ensuring a stable high level at the output node N.

[0044] See also Figure 6In some implementations, the absorption sub-circuit 130 includes a P-type transistor P1; the first end of the P-type transistor P1 is connected to the output node N, and the second end of the P-type transistor P1 is configured to be connected to a low level. That is, the first end of the P-type transistor P1 is an input end, and the second end of the P-type transistor P1 is an output end. The low level can be a gate-off voltage (VGL), so the control end of the P-type transistor P1 can also be connected to a low level (VGL), at which time the P-type transistor P1 remains in an off state. When a very high instantaneous voltage change occurs at the output node N, the P-type transistor P1 can divert the generated instantaneous voltage due to the parasitic diode formed inside, effectively avoiding leakage current between the input end and the output end of the first reset sub-circuit 120, ensuring that the voltage of the output node N will not be pulled down, the gate drive signal can be output normally, and the gate charging time of the sub-pixel is shortened.

[0045] See also Figure 7 In some implementations, the first reset sub-circuit 120 includes a first transistor T1 and a second transistor T2. The first terminal of the first transistor T1 and the control terminal of the second transistor T2 are both connected to the output node N. The control terminal of the first transistor T1 is connected to the first terminal of the second transistor T2 and is also connected to the pull-down node QB. The first terminal of the first transistor T1 is the input terminal of the first reset sub-circuit 120, and the control terminal of the first transistor T1 is the control terminal of the first reset sub-circuit 120. The second terminal of the first transistor T1 and the second terminal of the second transistor T2 are both configured to be connected to a low level. It is understandable that when a high level is written to the output node N, the control terminal of the second transistor T2 also maintains a high level, the second transistor T2 is turned on, and a low level is written to the pull-down node QB, causing the first transistor T1 to remain off.

[0046] It should be noted that in Figure 7 Also shown are a first parasitic capacitor Cgd4 and a second parasitic capacitor Cgd3.

[0047] Without the absorption sub-circuit 130, when a very high instantaneous voltage change occurs at the output node N, the control terminal of the second transistor T2 turns on and, with the presence of resistance, generates a transient current flowing through the second transistor T2 at the control terminal of the first transistor T1. This generates a voltage drop across the second transistor T2, which in turn generates a spike voltage at the control terminal of the first transistor T1, i.e., at the pull-down node QB. This turns on the second transistor T2, lowering the voltage at the output node N and increasing the sub-pixel gate charging time. However, with the addition of the absorption sub-circuit 130, the current can be diverted through the absorption sub-circuit 130, preventing leakage current from the first transistor T1 and effectively preventing the aforementioned leakage.

[0048] Furthermore, the first reset sub-circuit 120 also includes a second absorption capacitor C2, the first end of which is connected to the control end of the first transistor T1, that is, connected to the pull-down node QB. The second end of the second absorption capacitor C2 is configured to be connected to a low level and can be configured to be connected to the gate-off voltage (VGL). The second absorption capacitor C2 can absorb the current flowing through the second transistor T2 generated by the peak voltage of the control end of the first transistor T1. Combined with the absorption sub-circuit 130, it can further ensure that the second transistor T2 will not be abnormally turned on when the output sub-circuit 110 outputs the gate drive signal. In addition, since the setting position of the second absorption capacitor C2 is connected to the control end of the second transistor T2, its capacitance will have a certain impact on the response speed of the second transistor T2. In some implementations, the capacitance of the second absorption capacitor C2 can be set to 5nF to 15nF, for example, 7nF, 9nF, 10nF, 13nF, and so on. If the capacitance of the second absorption capacitor C2 is too small, it can hardly absorb current. If the capacitance is too large, although the current absorption effect can be improved, it will seriously affect the switching speed of the second transistor T2, increase the power consumption of the second transistor T2, cause heat, increase switching losses, and easily cause the second transistor T2 to burn out.

[0049] See also Figure 8 and Figure 9 In some implementations, the shift register 100 further includes an input subcircuit 140. The output terminal of the input subcircuit 140 and the control terminal of the output subcircuit 110 are both connected to the pull-up node Q. The control terminal of the input subcircuit 140 is configured to receive a drive trigger signal, and the control terminal of the input subcircuit 140 can be the trigger terminal of the shift register 100. The input subcircuit 140 is configured to write a high level to the pull-up node Q under the control of the drive trigger signal to charge the output subcircuit 110. If the shift register 100 is cascaded to form a gate drive circuit, the drive trigger signal can be the gate drive signal of the previous stage. The previous stage here refers to the previous stage shift register 100 cascaded with the current stage shift register 100; the next stage refers to the next stage shift register 100 cascaded with the current stage shift register 100. The gate drive signal output by the output subcircuit 110 can drive the gate of the sub-pixels corresponding to the row to turn on, or it can trigger the start of the next stage shift register 100. Furthermore, the output sub-circuit 110 is configured to write a high level to the output node N after charging is completed, so that the output node N outputs a gate drive signal. It is understandable that when charging is completed, the clock signal connected to the input end of the output sub-circuit 110 becomes a high level, and a high level can be written to the output node N, so that the output node N can output a high-level gate drive signal.

[0050] Specifically, the output sub-circuit 110 may include a storage capacitor C3 and a third transistor T3; the first end of the storage capacitor C3 and the control end of the third transistor T3 are both connected to the pull-up node Q; and the second end of the storage capacitor C3 and the second end of the third transistor T3 are both connected to the output node N. The first end of the storage capacitor C3 serves as the control end of the output sub-circuit 110, the first end of the third transistor T3 serves as the input end of the output sub-circuit 110, and the second end of the third transistor T3 serves as the output end of the output sub-circuit 110. The first end of the storage capacitor C3 is configured to charge when a high level is written to the pull-up node Q. The first end of the third transistor T3 is configured to receive a high-level clock signal after charging is complete, so as to write a high level to the output node N. Specifically, while the storage capacitor C3 is being charged, the first end of the third transistor T3 is configured to receive a low-level clock signal. At this time, a second parasitic capacitor Cgd3 formed between the third transistor T3 and the pull-up node Q is also charged. When the low-level clock signal turns to a high level after the charging signal ends, the storage capacitor C3 and the second parasitic capacitor Cgd3 begin to discharge so that the third transistor T3 remains turned on, so that the entire output sub-circuit 110 can write a high level to the output node N, and then output a high-level gate drive signal through the output node N.

[0051] In some implementations, the input subcircuit 140 may include a fourth transistor T4, wherein the first terminal of the fourth transistor T4 is configured to receive a high voltage level, the second terminal of the fourth transistor T4 is connected to the pull-up node Q, and the control terminal of the fourth transistor T4 is configured to receive a drive trigger signal. The first terminal of the fourth transistor T4 serves as the input terminal of the input subcircuit 140, and the second terminal of the fourth transistor T4 serves as the output terminal of the input subcircuit 140. When the input subcircuit 140 is in operation, under the control of the drive trigger signal, the fourth transistor T4 writes the input high voltage level to the pull-up node Q through the fourth transistor T4 to charge the storage capacitor C3. This ensures that the storage capacitor C3 can be effectively charged, allowing the output node N to provide a gate drive signal. When the shift register 100 is cascaded to form a gate drive circuit, if the first reset subcircuit 120 of the previous stage leaks, the level of the drive trigger signal may not be able to fully turn on the fourth transistor T4, resulting in insufficient charging of the storage capacitor C3 of the current stage and a gradual decrease in the high voltage level written to the output node N.

[0052] In some implementations, the shift register 100 further includes a second reset subcircuit 150, wherein the input of the second reset subcircuit 150 is connected to the pull-up node Q, the output of the second reset subcircuit 150 is configured to receive a low level, and the control terminal of the second reset subcircuit 150 is configured to receive a reset signal. The control terminal of the second reset subcircuit 150 may serve as the reset terminal of the shift register 100. The second reset subcircuit 150 is configured to write a low level to the pull-up node Q under the control of the reset signal. If the shift register 100 is cascaded to form a gate drive circuit, the reset signal may be the gate drive signal output by the next stage. Specifically, the second reset subcircuit 150 may include a fifth transistor T5, wherein the first terminal of the fifth transistor T5 serves as the output terminal of the second reset subcircuit 150, the second terminal of the fifth transistor T5 serves as the input terminal of the second reset subcircuit 150, and the control terminal of the fifth transistor T5 serves as the control terminal of the second reset subcircuit 150.

[0053] In some implementations, a switch sub-circuit 200 may be further provided between the pull-up node Q and the input sub-circuit 140. This switch sub-circuit is also located between the second reset sub-circuit 150 and the pull-up node Q. The switch sub-circuit 200 may include a sixth transistor T6, a first terminal of which is connected to the output terminal of the input sub-circuit 140, a second terminal of which is connected to the pull-up node Q, and a control terminal of the sixth transistor T6 is configured to be connected to a high level, which may be a gate-throw voltage (VGH).

[0054] In some implementations, the shift register 100 further includes a third reset sub-circuit 160, wherein a control terminal of the third reset sub-circuit 160 may be connected to the pull-down node QB, an input terminal of the third reset sub-circuit 160 may be connected to the pull-up node Q, and an output terminal of the third reset sub-circuit 160 may be connected to the pull-down node QB. The third reset sub-circuit 160 may be configured to write a high level to the pull-down node QB after a high level is written to the output node N, thereby writing a low level to the pull-up node Q, thereby resetting the pull-up node Q. The third reset sub-circuit 160 may include a seventh transistor T7, wherein a control terminal of the seventh transistor T7 is connected to the pull-down node QB, a first terminal of the seventh transistor T7 is connected to the pull-up node Q, and a second terminal of the seventh transistor T7 is configured to be connected to a low level.

[0055] As will be appreciated, the shift register 100 may further include a control sub-circuit 170, wherein the input and control terminals of the control sub-circuit 170 are configured to receive a control signal, which may be provided by a clock signal. The output terminal of the control sub-circuit 170 is connected to the pull-down node QB. Under the control of the control signal, a high level may be written to the pull-down node QB via the control sub-circuit 170, thereby controlling the third reset sub-circuit 160 to reset the pull-up node Q. The control sub-circuit 170 may include an eighth transistor T8, wherein the first terminal and the control terminal of the eighth transistor T8 are configured to receive the control signal, and the second terminal of the eighth transistor T8 is connected to the pull-down node QB.

[0056] In some implementations, the shift register 100 may further include a fourth reset subcircuit 180, wherein the control terminal of the fourth reset subcircuit 180 is connected to the pull-up node Q, the input terminal of the fourth reset subcircuit 180 is connected to the pull-down node QB, and the output terminal of the fourth reset subcircuit 180 is configured to be connected to a low level. The fourth reset subcircuit 180 may be configured to write a low level to the pull-down node QB when a high level is written to the pull-up node Q, thereby resetting the pull-down node QB. It will be appreciated that the fourth reset subcircuit 180 may include a ninth transistor T9, wherein the control terminal of the ninth transistor T9 is connected to the pull-up node Q, the first terminal of the ninth transistor T9 is connected to the pull-down node QB, and the second terminal of the ninth transistor T9 is configured to be connected to a low level. When a high level is written to the pull-up node Q, the ninth transistor T9 may be turned on, thereby writing a low level to the pull-down node QB.

[0057] In some implementations, the shift register 100 further includes a fifth reset subcircuit 190, wherein the input of the fifth reset subcircuit 190 is connected to the pull-up node Q, the output of the fifth reset subcircuit 190 is configured to be connected to a low level, and the control terminal of the fifth reset subcircuit 190 is configured to be connected to a global reset signal. The fifth reset subcircuit 190 is configured to reset the upper and lower nodes under the control of the global reset signal. For example, when the shift register 100 is started, the fifth reset subcircuit 190 may receive a high-level global reset signal, thereby resetting the pull-up node Q. Furthermore, the fifth reset subcircuit 190 may include a tenth transistor T10, wherein the first terminal of the tenth transistor T10 may be connected to the pull-up node Q, the second terminal of the tenth transistor T10 may be configured to be connected to a low level, and the control terminal of the tenth transistor T10 may be configured to be connected to the global reset signal.

[0058] In summary, the shift register 100 provided in this embodiment absorbs the current generated between the output node N and the output terminal of the first reset subcircuit 120 when the output subcircuit 110 writes a high level to the output node N. This prevents leakage current from occurring in the first reset subcircuit 120, thereby ensuring that the output node N remains stable when transitioning from a low level to a high level. This ensures that the output subcircuit 110 can properly output gate drive signals, resolves the problem of the last row in the display panel being unable to be driven, and improves the output stability of the display panel.

[0059] Based on the same inventive concept, in another embodiment of the present invention, a gate driving circuit is provided for driving a display panel. The gate driving circuit includes the multiple shift registers described in the aforementioned embodiments, and the multiple shift registers are cascaded in sequence; each shift register is used to drive a row of sub-pixels in the display panel, that is, each row of sub-pixels corresponds to a shift register.

[0060] Specifically, the output end of the shift register in the nth row can be connected to the drive trigger end of the shift register in the n+4th row. At the same time, the output end of the shift register in the nth row can be configured to output a high-level gate drive signal to drive the sub-pixels in the nth row. At the same time, the gate drive signal in the nth row triggers the start of the shift register in the n+4th row. When n is greater than or equal to 5, the trigger end of the shift register in the nth row is connected to the output end of the shift register in the n-4th row. When the shift register in the n-4th row outputs a high-level gate drive signal, the shift register in the nth row can be started. The reset end of the shift register in the nth row is connected to the output end of the shift register in the n+4th row. When the shift register in the n+4th row outputs a high-level gate drive signal, the shift register in the nth row is reset. Wherein, n is a positive integer.

[0061] It should be noted that the main structure of the gate drive circuit provided in this embodiment has been described in the aforementioned shift register embodiment. The specific implementation details and beneficial effects of the gate drive circuit of this embodiment can be found in the relevant description of the aforementioned shift register embodiment, and will not be repeated here.

[0062] Based on the same inventive concept, this embodiment further provides a display device, which may include arrayed subpixels and the shift register described in the aforementioned embodiment, with each row of subpixels corresponding to one shift register; the shift register is configured to drive the subpixels corresponding to a row. The display device in this embodiment may be any product or component with a display function, such as a VR device, a mobile phone, an LCD panel, an OLED panel, an electronic paper, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, or a navigation system.

[0063] Since the shift register included in the display device according to the embodiment of the present invention has been described in the previous embodiment, those skilled in the art will be able to understand the specific structure and effect principle of the display device based on the display device described in the embodiment of the present invention, and therefore will not be described in detail here. Any display device including the shift register according to the embodiment of the present invention falls within the scope of protection of the present invention.

[0064] In the description provided herein, numerous specific details are described. However, it is understood that embodiments of the present invention may be practiced without these specific details. In some instances, well-known methods, structures, and techniques are not shown in detail so as not to obscure the understanding of this description.

[0065] Similarly, it should be understood that in order to streamline the present disclosure and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the invention, various features of the invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting an intention that the claimed invention requires more features than are expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all the features of the individual embodiments disclosed above. Accordingly, the claims following the detailed description are hereby expressly incorporated into this detailed description, with each claim standing on its own as a separate embodiment of the invention.

[0066] Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and further may be divided into a plurality of submodules or subunits or subcomponents. All features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed herein may be combined in any combination, except that at least some of such features and / or processes or units are mutually exclusive. Unless expressly stated otherwise, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

[0067] Furthermore, those skilled in the art will appreciate that although some embodiments herein include certain features included in other embodiments but not other features, combinations of features from different embodiments are intended to be within the scope of the present invention and to form different embodiments. For example, in the claims below, any of the claimed embodiments may be used in any combination.

[0068] It should be noted that the above embodiments illustrate rather than limit the invention, and that a person skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference signs placed between brackets should not be construed as limiting the claims. The word "comprising" does not exclude the presence of components or steps not listed in the claims. The word "a" or "an" preceding a component does not exclude the presence of a plurality of such components. The present invention may be implemented by means of hardware comprising several different components and by means of a suitably programmed computer. In a unit claim enumerating several means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third etc. does not indicate any order. These words may be interpreted as names.

Claims

1. A shift register, characterized in that: include: an output sub-circuit, a first reset sub-circuit, and an absorption sub-circuit; an input end of the first reset sub-circuit, an output end of the output sub-circuit, and an input end of the absorption sub-circuit are all connected to an output node; The control terminal of the first reset sub-circuit is configured to be connected to a low level when the output sub-circuit writes a high level to the output node, so that the output node outputs a gate drive signal; The absorption sub-circuit is configured to absorb leakage current generated between the output node and the output terminal of the first reset sub-circuit when a high level is written to the output node; The first reset sub-circuit includes a first transistor and a second transistor, wherein a first terminal of the first transistor and a control terminal of the second transistor are both connected to the output node, and the control terminal of the first transistor is connected to the first terminal of the second transistor; the first terminal of the first transistor is an input terminal of the first reset sub-circuit, and the control terminal of the first transistor is a control terminal of the first reset sub-circuit; The second end of the first transistor and the second end of the second transistor are both configured to be connected to a low level.

2. The shift register according to claim 1, wherein: The absorption subcircuit includes a first absorption capacitor; A first end of the first absorption capacitor is connected to the output node, and a second end of the first absorption capacitor is configured to be connected to a low level.

3. The shift register according to claim 1, wherein: The absorption sub-circuit includes a P-type transistor; The first terminal of the P-type transistor is connected to the output node, and the second terminal and the control terminal of the P-type transistor are both configured to be connected to a low level.

4. The shift register according to claim 1, wherein: The first reset subcircuit further includes a second absorption capacitor; A first end of the second absorption capacitor is connected to the control end of the first transistor; and a second end of the second absorption capacitor is configured to be connected to a low level.

5. The shift register according to claim 1, wherein: Also includes: an input subcircuit; an output terminal of the input subcircuit and a control terminal of the output subcircuit are both connected to a pull-up node; The input sub-circuit is configured to write a high level to the pull-up node under the control of a driving trigger signal to charge the output sub-circuit; The output sub-circuit is configured to write a high level to the output node after charging is completed, so that the output node outputs a gate driving signal.

6. The shift register according to claim 5, wherein: The output sub-circuit comprises: a storage capacitor and a third transistor; a first end of the storage capacitor and a control end of the third transistor are both connected to a pull-up node; a second end of the storage capacitor and a second end of the third transistor are both connected to the output node; the first end of the storage capacitor is the control end of the output sub-circuit, the first end of the third transistor is the input end of the output sub-circuit, and the second end of the third transistor is the output end of the output sub-circuit; The first end of the storage capacitor is configured to be charged when a high level is written to the pull-up node; The first terminal of the third transistor is configured to receive a high-level clock signal after charging is completed, so as to write a high level to the output node.

7. The shift register according to claim 1, wherein: Also includes: a second reset sub-circuit, wherein an input terminal of the second reset sub-circuit is connected to a pull-up node, an output terminal of the second reset sub-circuit is configured to be connected to a low level, and a control terminal of the second reset sub-circuit is configured to be connected to a reset signal; The second reset sub-circuit is configured to write a low level to the pull-up node under the control of a reset signal.

8. A gate drive circuit, characterized in that: Used to drive a display panel, the gate driving circuit includes a plurality of shift registers according to any one of claims 1 to 7, and the plurality of shift registers are cascaded in sequence; each shift register is configured to drive a row of sub-pixels in the display panel.

9. A display device, characterized in that: The invention comprises sub-pixels arranged in an array and the shift register according to any one of claims 1 to 7, wherein each row of the sub-pixels corresponds to one shift register; and the shift register is configured to drive the sub-pixels corresponding to a row.

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