A multi-phase high-precision current-sharing control method applied to constant on-time control

Abstract

The application is a kind of multi-phase high-precision current-sharing control method applied to constant on-time control, which obtains the on-time adjustment quantity by PI compensation module and low-pass filter module from the current difference quantity of continuous sampling of each phase current and average current, the high bit of the adjustment quantity controls the value of the reference value V of the counter in the on-time control module, and the low bit controls the length of the enabled delay line in the delay line module, the counter timing control of the on-time control module is combined with the delay line timing control of the delay line module to improve the control precision of the digital pulse width modulator. ref Compared with the multi-phase COT controller without current-sharing mechanism, the application can ensure the direct current quantity of each phase inductor current consistent and improve the stability and reliability of the system under the steady-state operation condition.

Description

Technical Field

[0001] This invention relates to switching power supplies, and more particularly to a high-precision digital current sharing control method for multiphase constant on-time (COT) controllers. Background technology:

[0002] Currently, voltage regulation modules are increasingly trending towards higher current and higher power consumption. This trend has led to a growing number of applications for multiphase high-current circuits. Multiphase constant on-time (COT) is a mainstream control method, characterized by high efficiency under light loads, large system bandwidth, and simple compensation networks. However, during the operation of a multiphase COT circuit, each phase may operate in slightly different states, resulting in differences in current and power consumption. These differences can affect the reliability and stability of the power supply system. The main reasons for this inconsistency are: firstly, during startup, phase interleaving causes inconsistent on-times for the multiphase currents, resulting in an initial current difference; secondly, deviations in the parameters of each phase power module, such as subtle differences in the RC parameters inside the gate and the drain-source resistance Rds, lead to inductor current deviations during operation. To ensure that each phase circuit operates in an ideal state, it is necessary to maintain a balance in the inductor current across all phases.

[0003] Most current current sharing methods are designed for analog control, such as output impedance methods and master-slave configuration methods. However, these methods are not suitable for digital COT control circuits. This is because, unlike analog circuits where a sawtooth wave generator is used to compare a compensated voltage signal with the signal to generate the drive signal for the MOS pin, in digital control systems, the digital PWM waveform generator module converts the duty cycle signal into the corresponding switching control signal. Its basic principle is that a counter counts according to a clock signal, generating a sawtooth-like output. This count value is then compared with a given reference value V. ref Comparison, i.e. Figure 8 The linear position in the diagram. Initially, the counter is reset to 0, and the reference value is greater than the counter value. At this time, the drive signal output is high. When the count value exceeds the reference value, the drive signal output is low, that is, it becomes low at point b, thus outputting as shown. Figure 8 The PWM waveform shown.

[0004] Traditional digital current sharing modules use a reference value V ref Adjustments can be made by increasing V. ref The value of V increases the conduction time of the circuit, thereby increasing the inductor current of that phase; decreasing V refThe value of the duty cycle is adjusted to reduce the conduction time of the circuit, thereby reducing the inductor current of that phase. However, under this digital current sharing control method, the minimum change in the duty cycle is one clock cycle, which makes the adjustment granularity coarse and prone to overshoot. In order to obtain a better current sharing effect, a high-precision current sharing method is required to precisely adjust the conduction time. Summary of the Invention

[0005] Technical problem: In order to improve the operation of multiphase COT circuits and enhance the reliability of the circuits, this invention proposes a multiphase high-precision current sharing control method for constant on-time control.

[0006] Technical Solution: To achieve the above objectives, this invention employs a multiphase high-precision current sharing control method for constant on-time control, specifically applied in a BUCK converter. Its basic idea is to pass the current difference between continuously sampled phase currents and the average current through a PI compensation module and a low-pass filter module to obtain the on-time adjustment amount. The high-order control reference value V of this adjustment amount is... ref The lower digit controls the length selection of the delay line, combining the counter with the delay line to improve the control accuracy of DPWM.

[0007] Digital COT control can be regarded as a fixed-frequency control system because the load is in a stable state and the cycle remains basically unchanged in steady state.

[0008] This control method is based on the following modules: a current sampling module, a low-pass filter module, a PI compensation module, a state transition module, a delay line module, and a turn-on time control module. The current sampling module, low-pass filter module, and PI compensation module are connected in sequence. The current sampling module receives the phase current value and the average current value, and transmits the processed result to the low-pass filter module and the PI compensation module in sequence to obtain the turn-on time adjustment signal. The state transition module provides an enable signal to control the working sequence of the three modules. The delay line module and the turn-on time control module jointly implement the function of a digital pulse width modulator. When the PWM is pulled high, the adjustment signal given by the first three modules is read. Based on the signal, the turn-on time control module controls the turn-on time of the delay line module. Finally, the delay line module outputs the PWM pull-low signal.

[0009] The current difference between continuously sampled phase currents and the average current is processed by a PI compensation module and a low-pass filter module to obtain the conduction time adjustment. The high-order value of this adjustment controls the counter reference value V in the conduction time control module. ref The lower bit controls the length of the enabled delay line in the delay line module, combining the counter timing control of the conduction time control module with the delay line timing control of the delay line module to improve the control accuracy of the digital pulse width modulator.

[0010] Current sampling module: Samples the difference between the average current and the current in each phase to obtain the input value for subsequent filters;

[0011] Low-pass filter module: This module is used to perform low-pass filtering on the input signal to filter out high-frequency ripple interference;

[0012] PI Compensation Module: This module accepts the input from the current sampling module and performs PI filtering on it. By using the poles of the PI network, it eliminates the steady-state error of the system and outputs a conduction time adjustment signal.

[0013] Delay line module: When enabled by the conduction time control module, the control signal is delayed by different times according to the low bit value of the conduction time adjustment, and then output as the turn-off signal of the MOS switch signal to turn off the upper MOSFET drive of the power stage.

[0014] State transition module: This module controls the state of the system and enables each module. This module is implemented using a finite state machine.

[0015] On-time control module: Adjusts the reference value of the DPWM counter according to the high bit and sign bit output by the filter module, and enables the delay line module when the counter counts to the reference value.

[0016] The aforementioned flow sharing control method is specifically as follows:

[0017] Step 1: The current sampling module samples the current difference signal between the average current and the current of each phase;

[0018] The ADC module samples the current values ​​of each phase and calculates the average current value by adding and shifting these currents. However, the frequency of these values ​​is the sampling frequency of the ADC module. Directly using them may lead to metastability due to insufficient setup time in digital circuits, affecting the operation of subsequent modules. Therefore, a lower frequency clock control register is used to store the average current signal i on the rising edge of the clock. Lave and the phase current signal i Li And by subtraction, we get i Lave -i Li That is, the signal that needs to be further processed;

[0019] Step 2: The current difference signal passes through a low-pass filter module to remove ripple interference;

[0020] Since the switching power supply operates by performing high-frequency switching conversion on the input DC voltage and then rectifying and filtering it before outputting, there is an inherent high-frequency current ripple in the current. This ripple will interfere with the output, so a low-pass filter module is needed to filter out the high-frequency signal. In this method, a digital filtering method is used. The s-domain parameters of the designed low-pass filter are transformed by bilinear transformation to obtain the z-domain parameters. The expression equation can be obtained by expansion. The current output is calculated based on the input sampled last time, the input sampled now, and the output sampled last time.

[0021] Step 3: After being processed by the low-pass filter module, the signal is then passed through the PI compensation module to eliminate the steady-state error of the system and obtain the conduction time adjustment amount;

[0022] Since the DC gain of the power stage system is not very large, it will cause an error in the steady-state output, and the output value will deviate from the expected value. To eliminate this deviation, a zero-pole is added to the system, which can increase the steady-state gain. This pole is provided by the PI compensation module, and the implementation process is similar to that of the low-pass filter module mentioned above.

[0023] Step 4: The conduction time control module adjusts the corresponding time of the quantity counter according to the conduction time.

[0024] In steady state, the system has a default number of on-clock cycles V. ref Adjustments need to be made based on this; when the adjustment amount is positive, V is directly adjusted. ref Adding the high-order data of the adjustment, a new on-time count reference value is obtained, and the low-order data of the adjustment is directly passed to the delay line module; when the adjustment is negative, V... ref Subtracting the high-order part of the adjustment value yields a new on-time count reference value. Subtracting the low-order part of the adjustment value from the maximum adjustable input value of the delay line yields new data that is passed to the delay line module. When the PWM is pulled high, the counter of the on-time control module starts working. When the counter reaches the count reference value, it stops counting and enables the connected delay line module.

[0025] Step 5: After the delay line module is enabled, the module performs a specific delay based on the low-order value of the conduction time adjustment, and outputs the MOS turn-off signal to complete the current sharing adjustment.

[0026] After the delay module is enabled, the corresponding number of delay units are enabled according to the adjustment amount given by the conduction time adjustment module. The delay time of each delay unit is fixed. When the delay time of the delay unit is reached, the delay line module outputs a MOS turn-off signal.

[0027] Beneficial effects: Compared with the prior art, the present invention has the following advantages:

[0028] The high-precision digital current sharing control algorithm based on COT circuits used in this invention takes the COT control of Buck converter as a typical application. Compared with multi-phase COT controllers without current sharing mechanism, it can ensure that the DC current of each phase inductor is consistent under steady-state operation conditions, thereby improving the stability and reliability of the system.

[0029] The digital high-precision current sharing control algorithm used in this invention has a zero and a pole in the transfer function of the current sharing module, which reduces the steady-state error of the current sharing module.

[0030] The digital high-precision current sharing control algorithm used in this invention includes a low-pass filter module to avoid the influence of current ripple on the sampled values.

[0031] The digital high-precision current sharing control algorithm used in this invention employs a delay line for delay, so that the control accuracy is no longer limited by the system clock, and higher control accuracy can be obtained.

[0032] The high-precision digital current sharing control algorithm used in this invention is implemented entirely digitally, requiring no additional analog circuitry. Attached Figure Description

[0033] Figure 1 This is a block diagram of a two-phase COT control system using the current sharing module of this invention, where H(s) is the designed current sharing module.

[0034] Figure 2 This is a block diagram of the internal structure of the current sharing module H(S).

[0035] Figure 3 This is a PWM control timing diagram.

[0036] Figure 4 This is a schematic diagram of the delay line module.

[0037] Figure 5 This is a schematic diagram of a delay unit.

[0038] Figure 6 This is a layout diagram of the delay line module.

[0039] Figure 7 These are Simplis simulation waveforms used in a 2-phase BUCK converter. (a) shows the two-phase current without current sharing, (b) shows the two-phase current with non-high-precision current sharing, and (c) shows the two-phase current with high-precision current sharing.

[0040] Figure 8 This explains the working principle of the DPWM module. Detailed Implementation

[0041] To illustrate the present invention more clearly, the technical solution of the present invention will be further explained below with reference to the accompanying drawings.

[0042] Figure 1 The system block diagram for applying the digital current sharing algorithm of this invention in a Buck converter with two-phase current COT control is shown below. The following assumptions are made: In steady state, the system's operating period is T, and the system clock period is T. clk The MOSFET is turned on by default during one switching cycle. ref One system clock cycle. The inductor current of each phase is sampled to obtain the digital quantity i of the two-phase current. L1 i L2 After summing the two-phase circuit and applying a gain of 1 / 2, the average two-phase current i is obtained. Lave The difference between the mean and the current of each phase can be used to obtain the current difference signal i. Lave -i L1 and i Lave -i L2 The current difference signal of each phase passes through the current sharing module to obtain the conduction time adjustment amount. Based on this conduction time adjustment amount, combined with the PWM conduction signal, a reset signal for the SR flip-flop is given to adjust the conduction of the MOS and the inductor current, thereby completing the current sharing regulation.

[0043] Figure 2 This is a schematic diagram of the internal structure of the current sharing module. Taking the first phase circuit as an example, the current difference signal i Lave -i L1 The input current sampling module samples the data based on the rising edge of the system clock. Due to ripple in the two-phase current, the sampled value needs to be processed by a low-pass filter module and a PI compensation module. After processing, the on-time adjustment amount data[n-1:0] is obtained. This adjustment amount is divided into two parts: coarse adjustment amount data[n-1:m] and fine adjustment amount data[m-1:0]. The coarse adjustment part is adjusted by the on-time control module to adjust the number of conduction cycles. Based on the coarse adjustment signal data[n-1:m], the enable signal for the delay line is given, and the fine adjustment data is sent to the delay line module. The fine adjustment part is controlled by the delay line module, thereby completing the high-precision adjustment of the on-time and finally giving the MOS turn-off signal.

[0044] This embodiment performs low-pass filtering and PI filtering on the sampled signal. The low-pass filter module is needed because the two-phase current has ripple, which adds a ripple variation to the sampled current difference signal. Filtering is required to remove high-frequency signals, resulting in the DC component shown in the figure as the input signal. The low-pass filter module used in this scheme is expressed as follows:

[0045]

[0046] Meanwhile, since there is an inherent steady-state error in the two-phase current, a zero and a pole are introduced in the frequency domain to increase the DC gain and reduce the steady-state error. Therefore, a PI filter of the following form is designed, and its expression is:

[0047]

[0048] The s-domain expressions of the low-pass filter module and the PI compensation module are converted into z-domain functions using the bilinear method, enabling the processing of discrete digital quantities. After filtering, the data adjustment amount can be obtained as data[n-1:0]. The above is the filtering part of the sampled data.

[0049] This embodiment uses a combination of DPWM and a delay line to control the PWM conduction, which improves control accuracy and avoids excessive resource consumption. The specific control timing is as follows: Figure 3 As shown. The PWM conduction time consists of two parts. One part uses the traditional DPWM control method with an adjustment accuracy equal to the system clock accuracy. The other part uses a delay line for fine control. The specific control timing is as follows: First, the compensation module provides the time adjustment amount data[n-1:0]. When the PWM wave is high, a counter controlled by the system clock is started, and the counter value is the default number of conduction clock cycles V. ref Adding the high-order bits of the previously calculated adjustment amount, data[n-1:m], when the counter reaches the predetermined counter value, the delay line module is enabled, and the low-order bits of the adjustment amount, data[m-1:0], are also passed to the delay module. The delay line module contains 2... m Each delay line unit enables the corresponding number of delay line units based on the value of data[m-1:0], thereby controlling the delay time.

[0050] The delay line in this example is composed of a multiplexer (MUX), enabling high-precision delays down to the picosecond range. The specific delay time needs to be determined based on the layout and routing. The main body of the delay line module consists of several delay line units arranged side by side, such as... Figure 4As shown, the delay time is controlled by controlling each delay line unit. First, the adjustment value needs to be converted. Based on the adjustment value, the control signal of the data[m-1:0]th delay module is set to high level, while the rest are low level, i.e., One-Hot encoding is performed. Next, this control signal is input to the corresponding delay unit. The high-level control signal generates a pulse signal at the input of the corresponding controlled delay module, and a fixed delay is achieved through an internally connected MUX selector chain. Delay units controlled by the low level only experience a fixed delay on their input signals. Finally, after signal transmission, a PWM shutdown signal is output after the data[m-1:0]th delay unit time after the delay line module is enabled, completing the PWM control and awaiting the next switching cycle.

[0051] Figure 5 This section details the delay unit. The main body of this unit consists of four MUX selectors connected in series. The selection port inputs of the last three are always 1, meaning the output of the previous MUX can be output to the next stage through the current MUX. The gating signal of the first MUX is controlled by `mux_en`, which is obtained by performing a NAND operation on the control signal `ctrl` and the signal `trig`. `trig` is a pulse signal generated when the delay line module is enabled by the on-time adjustment module. When `ctrl` is low, the `mux_en` signal is always high, meaning the MUX does not perform any additional processing on the input signal of the delay unit; it simply delays the signal through the MUX's inherent circuitry before sending it to the next MUX selector. When `ctrl` is high, the `mux_en` signal is low, allowing signals connected to high-level input ports to pass through the MUX, thus generating a pulse signal. The signal length is controlled by the length of `trig`. This pulse signal is passed through subsequent delay modules, ultimately controlling the shutdown of the MOS transistor. Figure 5 The right half of the diagram shows the waveforms when the control signal ctrl is high. Since placement and routing also affect the delay line performance, manual placement and routing of the delay units is necessary to ensure consistent line delays across all units. This embodiment uses an FPGA for implementation. Figure 6 This is the layout and routing diagram of the delay line module on the PFGA.

[0052] Figure 7 These are Simplis simulation waveforms for a 2-phase COT control system, showing waveforms without current sharing, without high-precision current sharing (i.e., without sampling delay lines), and with high-precision current sharing. The comparison shows that this current sharing method can maintain consistent DC components in the steady-state inductance of each phase, and the use of delay blocks can reduce output voltage fluctuations. Furthermore, this method is applicable to circuits with any number of phases.

[0053] The above description, in conjunction with the accompanying drawings, provides a further detailed explanation of the present invention. It should not be construed that the specific implementation of the present invention is limited to these descriptions; the above descriptions are merely preferred embodiments of the present invention. For those skilled in the art, any modifications, equivalent substitutions, or improvements made without departing from the principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A multiphase high-precision current sharing control method applied to constant on-time control, characterized in that, The control method is based on the following modules: current sampling module, low-pass filter module, PI compensation module, state transition module, delay line module, and conduction time control module. The current sampling module, low-pass filter module, and PI compensation module are connected in sequence. The current sampling module receives the phase current value and the average current value, and transmits the processed result to the low-pass filter module and the PI compensation module in sequence to obtain the conduction time adjustment signal. The state transition module provides an enable signal to control the working sequence of the three modules. The delay line module and the conduction time control module jointly implement the function of the digital pulse width modulator. When the PWM is pulled high, the adjustment signal given by the first three modules is read. According to the signal, the conduction time control module controls the turn-on time of the delay line module. Finally, the delay line module outputs the PWM pull-down signal. The current difference between continuously sampled phase currents and the average current is processed by a PI compensation module and a low-pass filter module to obtain the conduction time adjustment. The high-order value of this adjustment controls the counter reference value V in the conduction time control module. ref The lower bit controls the length of the enabled delay line in the delay line module, combining the counter timing control of the conduction time control module with the delay line timing control of the delay line module to improve the control accuracy of the digital pulse width modulator.

2. The multiphase high-precision current sharing control method for constant on-time control according to claim 1, characterized in that, Current sampling module: Samples the difference between the average current and the current in each phase to obtain the input value for subsequent filters; Low-pass filter module: This module is used to perform low-pass filtering on the input signal to filter out high-frequency ripple interference; PI Compensation Module: This module accepts the input from the current sampling module and performs PI filtering on it. By using the poles of the PI network, it eliminates the steady-state error of the system and outputs a conduction time adjustment signal. Delay line module: When enabled by the conduction time control module, the control signal is delayed by different times according to the low bit value of the conduction time adjustment, and then output as the turn-off signal of the MOS switch signal to turn off the upper MOSFET drive of the power stage. State transition module: This module controls the state of the system and enables each module. This module is implemented using a finite state machine. On-time control module: Adjusts the reference value of the DPWM counter according to the high bit and sign bit output by the filter module, and enables the delay line module when the counter counts to the reference value.

3. The multiphase high-precision current sharing control method for constant on-time control according to claim 1, characterized in that, The aforementioned flow sharing control method is specifically as follows: Step 1: The current sampling module samples the current difference signal between the average current and the current of each phase; The ADC module samples the current values ​​of each phase and calculates the average current value by adding and shifting these current values. However, the frequency of these values ​​is the sampling frequency of the ADC module. Directly using this may lead to metastability due to insufficient setup time in digital circuits, affecting the operation of subsequent modules. Therefore, a lower frequency clock control register is used to store the average current signal i on the rising edge of the clock. Lave and the phase current signal i Li And by subtraction, we get i Lave -i Li That is, the signal that needs to be further processed; Step 2: The current difference signal passes through a low-pass filter module to remove ripple interference; Since the switching power supply operates by performing high-frequency switching conversion on the input DC voltage and then rectifying and filtering it before outputting, there is an inherent high-frequency current ripple in the current. This ripple will interfere with the output, so a low-pass filter module is needed to filter out the high-frequency signal. In this method, a digital filtering method is used. The s-domain parameters of the designed low-pass filter are transformed by bilinear transformation to obtain the z-domain parameters. The expression equation can be obtained by expansion. The current output is calculated based on the input sampled last time, the input sampled now, and the output sampled last time. Step 3: After being processed by the low-pass filter module, the signal is then passed through the PI compensation module to eliminate the steady-state error of the system and obtain the conduction time adjustment amount; Since the DC gain of the power stage system is not very large, it will cause an error in the steady-state output, and the output value will deviate from the expected value. To eliminate this deviation, a zero-pole is added to the system, which can increase the steady-state gain. This pole is provided by the PI compensation module, and the implementation process is similar to that of the low-pass filter module mentioned above. Step 4: The conduction time control module adjusts the corresponding time of the quantity counter according to the conduction time. In steady state, the system has a default number of on-clock cycles V. ref Adjustments need to be made based on this; when the adjustment amount is positive, V is directly adjusted. ref Adding the high-order data of the adjustment, a new on-time count reference value is obtained, and the low-order data of the adjustment is directly passed to the delay line module; when the adjustment is negative, V... ref Subtracting the high-order part of the adjustment value yields a new on-time count reference value. Subtracting the low-order part of the adjustment value from the maximum adjustable input value of the delay line yields new data that is passed to the delay line module. When the PWM is pulled high, the counter of the on-time control module starts working. When the counter reaches the count reference value, it stops counting and enables the connected delay line module. Step 5: After the delay line module is enabled, the module performs a specific delay based on the low-order value of the conduction time adjustment, and outputs the MOS turn-off signal to complete the current sharing adjustment. After the delay module is enabled, the corresponding number of delay units are enabled according to the adjustment amount given by the conduction time adjustment module. The delay time of each delay unit is fixed. When the delay time of the delay unit is reached, the delay line module outputs a MOS turn-off signal.

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