Measuring system and method for periodic signals

Abstract

The application provides a kind of periodic signal measurement method and system, comprising: step S1: the measured signal with period T1 is transmitted to PAM4 chip, and the synchronous clock is input to PLL1, and the period of synchronous clock is nT1;Step S2: based on the synchronous clock, PLL1 and PLL2 are set, so that PLL2 outputs high-precision sampling trigger clock;Step S3: the analog unit in PAM4 chip is preprocessed to the measured signal, then is transmitted to ADC, and ADC converts the preprocessed measured signal into digital signal according to sampling trigger clock and stores in FIFO memory space;Step S4: MCU transmits the sampling data in FIFO memory space to PC, and PC calculates the test index of the signal to be measured after digital processing;Step S5: PC reconstructs the sampling data to recover the signal to be measured;Step S6: the recovered signal to be measured and the calculated test index of the signal to be measured are displayed through display screen.

Description

Technical Field

[0001] This invention relates to the field of optical network communication technology, specifically to a system and method for measuring periodic signals, and more specifically to a system and method for measuring periodic signals based on a PAM4 network chip. Background Technology

[0002] In the research and development and production of optical modules, eye diagram analysis and eye diagram template testing are required. Sampling oscilloscopes are widely used due to their high bandwidth, high resolution, and low noise. Sampling oscilloscopes are primarily designed for measuring periodic signals. Unlike real-time oscilloscopes, sampling oscilloscopes sample the data only once with each trigger signal. Upon the next trigger, a small delay is added after the trigger signal before sampling again, until a complete periodic waveform is sampled. Because sampling oscilloscopes reconstruct the signal through multiple repeated samplings, even if the frequency of the measured signal is very high, the signal can be reconstructed point by point using a very low sampling rate.

[0003] Sampling oscilloscope structure as follows Figure 1 As shown, it consists of two parts: the main unit and the plug-in module. The main unit includes an ADC converter, FIFO memory, synchronization generator, sequential delay generator, and microprocessor system. The plug-in module includes a sampling head and an amplifier. The sampling head converts the high-speed signal into a short-duration DC signal, which is then amplified and digitized by the main unit's ADC. The data from each short-duration DC signal is combined to form a waveform that can be displayed on the screen. The waveform information (time, amplitude, etc.) is then mathematically processed to represent the actual signal information.

[0004] The principles and methods of traditional testing systems are:

[0005] 1. Connect the signal under test and the synchronization clock to the oscilloscope respectively, where the period of the signal under test is T1 and the period of the synchronization clock is nT1.

[0006] 2. The sequential delay generator delays the synchronization clock by ΔT and uses it as the sampling trigger clock for the ADC.

[0007] 3. The ADC converts the measured signal into a digital signal based on the delayed sampling pulse and stores it in the FIFO memory space. Its sampling process is as follows: Figure 2 As shown.

[0008] 4. The microprocessor system digitally processes the sampled data in the FIFO memory to calculate various indicators of the measured signal, such as eye height, eye width, eye diagram template tolerance, SNR, etc. At the same time, it reconstructs the sampled data, recovers the measured signal, and displays it on the screen.

[0009] Traditional testing methods have at least the following drawbacks: 1. They are large and heavy, making them difficult to carry and move; 2. The systems are complex, with long design, development, and production cycles; 3. They are costly, with a single sampling oscilloscope for measuring 28Gbps signals costing over 300,000 RMB. Therefore, a new testing system and method are needed to solve these problems.

[0010] Patent document CN112462121B (application number: 202011092482.X) discloses an eye diagram waveform analyzer system and an eye diagram testing method. The system includes: an equalizer, a clock data recovery circuit, and an eye diagram waveform analyzer. After the input signal is adjusted by the equalizer, the clock data recovery circuit recovers the clock information of the input signal and inputs the clock information and the input signal into the eye diagram waveform analyzer. The eye diagram waveform analyzer includes an algorithm logic module, a first phase interpolator, and a first sampler. The algorithm logic module controls the first phase interpolator to output a clock that traverses N phases and controls the threshold voltage of the first sampler to traverse M voltage values, thereby testing the bit error rate at each phase and each voltage value to obtain an eye diagram with M*N test points. Summary of the Invention

[0011] In view of the deficiencies in the prior art, the purpose of this invention is to provide a method and system for measuring periodic signals.

[0012] A method for measuring a periodic signal according to the present invention includes:

[0013] Step S1: Transmit the measured signal with a period of T1 to the PAM4 chip, and input the synchronization clock to PLL1. The period of the synchronization clock is nT1.

[0014] Step S2: Based on the synchronous clock settings, PLL1 and PLL2 are configured so that PLL2 outputs a high-precision sampling trigger clock;

[0015] Step S3: The analog unit built into the PAM4 chip preprocesses the measured signal and then transmits it to the ADC. The ADC converts the preprocessed measured signal into a digital signal according to the sampling trigger clock and stores it in the FIFO memory space.

[0016] Step S4: The MCU transmits the sampled data from the FIFO memory space to the PC. The PC then performs digital processing to calculate the test parameters of the signal under test.

[0017] Step S5: The PC reconstructs the sampled data to recover the signal to be measured;

[0018] Step S6: Display the recovered test signal and the calculated test parameters of the test signal on the display screen.

[0019] Preferably, the PLL1 uses either a synchronization signal or a crystal oscillator as the reference clock.

[0020] Preferably, the high-precision sampling trigger clock output by the PLL2 adopts:

[0021] T2=nT1+ΔT

[0022] Among them, ΔT and the highest frequency f of the measured signal should satisfy the Nyquist sampling theorem: ΔT≤1 / 2f.

[0023] Preferably, the sampling period is T2. After m samplings, one sampling cycle of the periodic signal is completed. The relationship between the sampling cycle period t and the period T1 of the measured signal is t = m(nT1 + ΔT) = (mn + 1)T1.

[0024] Preferably, the test indicators of the signal under test include: eye height, eye width, eye diagram template tolerance, and SNR.

[0025] Preferably, step S5 employs the following method: according to the Nyquist theorem, when the sampling frequency is greater than twice the maximum frequency in the signal, the original signal is recovered.

[0026] A measurement system for a periodic signal according to the present invention includes:

[0027] Module M1: Transmits the measured signal with a period of T1 to the PAM4 chip and inputs the synchronization clock to PLL1. The period of the synchronization clock is nT1.

[0028] Module M2: Based on the synchronous clock settings of PLL1 and PLL2, PLL2 outputs a high-precision sampling trigger clock;

[0029] Module M3: The analog unit built into the PAM4 chip preprocesses the measured signal and then transmits it to the ADC. The ADC converts the preprocessed measured signal into a digital signal according to the sampling trigger clock and stores it in the FIFO memory space.

[0030] Module M4: The MCU transmits the sampled data from the FIFO memory space to the PC, and the PC performs digital processing to calculate the test parameters of the signal under test;

[0031] Module M5: The PC reconstructs the sampled data to recover the signal to be measured;

[0032] Module M6: Displays the recovered test signal and the calculated test parameters of the test signal on the display screen.

[0033] Preferably, the PLL1 uses either a synchronization signal or a crystal oscillator as the reference clock.

[0034] Preferably, the high-precision sampling trigger clock output by the PLL2 adopts:

[0035] T2=nT1+ΔT

[0036] Among them, ΔT and the highest frequency f of the measured signal should satisfy the Nyquist sampling theorem: ΔT≤1 / 2f;

[0037] The sampling period is T2. After m samplings, one sampling cycle of the periodic signal is completed. The relationship between the sampling cycle period t and the period T1 of the measured signal is t = m(nT1 + ΔT) = (mn + 1)T1.

[0038] Preferably, the test indicators of the signal under test include: eye height, eye width, eye diagram template tolerance, and SNR.

[0039] Compared with the prior art, the present invention has the following beneficial effects:

[0040] 1. Small size and light weight, easy to carry and move;

[0041] 2. This invention utilizes a widely used PLL to control the sampling trigger clock, eliminating the need for a dedicated delay generator and simplifying the design.

[0042] 3. This invention uses the functions integrated in the PAM4 network chip to replace the complex and expensive components in the sampling oscilloscope, thereby improving integration and reducing production cycle and production cost;

[0043] 4. This invention can avoid the use of expensive testing equipment in certain specific fields, thus reducing testing costs; Attached Figure Description

[0044] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0045] Figure 1 This is a schematic diagram of a sampling oscilloscope.

[0046] Figure 2 This is a schematic diagram of the sampling process of a sampling oscilloscope.

[0047] Figure 3 This is a schematic diagram of a measurement system for periodic signals.

[0048] Figure 4 This is a schematic diagram of the measurement and sampling process for a periodic signal. Detailed Implementation

[0049] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0050] Example 1

[0051] The purpose of this invention is to address the shortcomings of existing technologies by providing a periodic signal measurement system and method based on the PAM4 network chip. The PAM4 network chip is widely used in optical network communication and is a key component of optical modules. Internally, it integrates analog signal processing units (including AGC (Automatic Gain Control), VGA (Variable Gain Amplifier), emphasis, equalization, etc.), ADC (Analog-to-Digital Converter), PLL (Phase-Locked Loop), FIFO memory, and CDR (Clock Data Recovery). The signal under test undergoes analog signal processing, including filtering, amplification, and emphasis. The ADC samples the signal under test, and mathematical operations are performed on the sampled data to reconstruct the waveform. The CDR primarily tracks the signal under test. This invention, based on the PAM4 network chip, fully utilizes its integrated analog and digital units, and integrates it with a PLL, MCU, PC, etc., to form a periodic signal testing system. Figure 3 As shown.

[0052] A method for measuring a periodic signal according to the present invention includes:

[0053] Step S1: Transmit the measured signal with a period of T1 to the PAM4 chip, and input the synchronization clock to PLL1. The period of the synchronization clock is nT1.

[0054] Step S2: Based on the synchronous clock settings, PLL1 and PLL2 are configured so that PLL2 outputs a high-precision sampling trigger clock;

[0055] Step S3: The analog unit built into the PAM4 chip preprocesses the measured signal and then transmits it to the ADC. The ADC converts the preprocessed measured signal into a digital signal according to the sampling trigger clock and stores it in the FIFO memory space.

[0056] Step S4: The MCU transmits the sampled data in the FIFO memory space to the PC. The PC performs digital processing and calculates the preset parameters of the signal under test.

[0057] Step S5: The PC reconstructs the sampled data to recover the signal to be measured;

[0058] Step S6: Display the recovered test signal and the calculated test parameters of the test signal on the display screen.

[0059] Specifically, PLL1 uses either a synchronization signal or a crystal oscillator as its reference clock. PLL1 outputs its clock to PLL2 as a reference, and PLL2 outputs its clock to the ADC for sampling triggering.

[0060] Specifically, the high-precision sampling trigger clock output by the PLL2 adopts:

[0061] T2=nT1+ΔT

[0062] Among them, ΔT and the highest frequency f of the measured signal should satisfy the Nyquist sampling theorem: ΔT≤1 / 2f.

[0063] Specifically, the sampling period is T2. After m samplings, one sampling cycle of the periodic signal is completed. The relationship between the sampling cycle period t and the period T1 of the measured signal is t = m(nT1 + ΔT) = (mn + 1)T1. The sampling process is as follows: Figure 4 As shown.

[0064] Specifically, the test indicators of the signal under test include: eye height, eye width, eye diagram template tolerance, and SNR.

[0065] Specifically, step S5 employs the following principle: According to the Nyquist theorem, when the sampling frequency is greater than twice the maximum frequency in the signal, the original signal can be recovered.

[0066] A measurement system for a periodic signal according to the present invention includes:

[0067] Module M1: Transmits the measured signal with a period of T1 to the PAM4 chip and inputs the synchronization clock to PLL1. The period of the synchronization clock is nT1.

[0068] Module M2: Based on the synchronous clock settings of PLL1 and PLL2, PLL2 outputs a high-precision sampling trigger clock;

[0069] Module M3: The analog unit built into the PAM4 chip preprocesses the measured signal and then transmits it to the ADC. The ADC converts the preprocessed measured signal into a digital signal according to the sampling trigger clock and stores it in the FIFO memory space.

[0070] Module M4: The MCU transmits the sampled data from the FIFO memory space to the PC, and the PC performs digital processing to calculate the test parameters of the signal under test;

[0071] Module M5: The PC reconstructs the sampled data to recover the signal to be measured;

[0072] Module M6: Displays the recovered test signal and the calculated test parameters of the test signal on the display screen.

[0073] Specifically, PLL1 uses either a synchronization signal or a crystal oscillator as its reference clock. PLL1 outputs its clock to PLL2 as a reference, and PLL2 outputs its clock to the ADC for sampling triggering.

[0074] Specifically, the high-precision sampling trigger clock output by the PLL2 adopts:

[0075] T2=nT1+ΔT

[0076] Among them, ΔT and the highest frequency f of the measured signal should satisfy the Nyquist sampling theorem: ΔT≤1 / 2f.

[0077] Specifically, the sampling period is T2. After m samplings, one sampling cycle of the periodic signal is completed. The relationship between the sampling cycle period t and the period T1 of the measured signal is t = m(nT1 + ΔT) = (mn + 1)T1. The sampling process is as follows: Figure 4 As shown.

[0078] Specifically, the test indicators of the signal under test include: eye height, eye width, eye diagram template tolerance, and SNR.

[0079] Specifically, module M5 adopts the following approach: According to the Nyquist theorem, when the sampling frequency is greater than twice the maximum frequency in the signal, the original signal can be recovered.

[0080] Those skilled in the art will understand that, in addition to implementing the system, apparatus, and their modules provided by this invention in purely computer-readable program code, the same program can be implemented in the form of logic gates, switches, application-specific integrated circuits, programmable logic controllers, and embedded microcontrollers by logically programming the method steps. Therefore, the system, apparatus, and their modules provided by this invention can be considered a hardware component, and the modules included therein for implementing various programs can also be considered structures within the hardware component; alternatively, modules for implementing various functions can be considered both software programs implementing the method and structures within the hardware component.

[0081] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in this application can be arbitrarily combined with each other.

Claims

1. A method of measuring a periodic signal, characterized by, The method comprises the following steps: Step S1: transmitting a measured signal with a period of T1 to a PAM4 chip and inputting a synchronous clock with a period of nT1 to PLL1; Step S2: setting PLL1 and PLL2 based on the synchronous clock, so that PLL2 outputs a high-precision sampling trigger clock; Step S3: an analog unit built in the PAM4 chip pre-processes the measured signal, and then transmits the pre-processed signal to an ADC, which converts the pre-processed signal into a digital signal according to the sampling trigger clock and stores the digital signal in a FIFO memory space; Step S4: an MCU transmits the sampling data in the FIFO memory space to a PC, and the PC calculates a test index of the measured signal through digital processing; Step S5: the PC reconstructs and recovers the measured signal from the sampling data; Step S6: displaying the recovered measured signal and the calculated test index of the measured signal on a display screen.

2. The method of measuring a periodic signal according to claim 1, wherein, The PLL1 adopts: the PLL1 selects a synchronous signal or a crystal oscillator as a reference clock.

3. The method of measuring a periodic signal according to claim 1, wherein, The high-precision sampling trigger clock output by the PLL2 adopts: T2 = nT1 + ΔT Wherein, ΔT and the highest frequency f of the measured signal should satisfy the Nyquist sampling theorem: ΔT ≤ 1 / 2f.

4. The method of measuring a periodic signal according to claim 1, wherein, The sampling period is T2, and one sampling cycle of the period signal is completed after m times of sampling. The relationship between a sampling cycle period t and the period T1 of the measured signal is t = m(nT1 + ΔT) = (mn + 1)T1.

5. The method of measuring a periodic signal according to claim 1, wherein, The test index of the measured signal comprises: eye height, eye width, eye pattern template tolerance and SNR.

6. The method of measuring a periodic signal according to claim 1, wherein, The step S5 adopts: according to the Nyquist theorem, when the sampling frequency is greater than 2 times the maximum frequency in the signal, the original signal can be recovered.

7. A measuring system of a periodic signal, characterized by The method comprises the following steps: Module M1: transmitting a measured signal with a period of T1 to a PAM4 chip and inputting a synchronous clock with a period of nT1 to PLL1; Module M2: setting PLL1 and PLL2 based on the synchronous clock, so that PLL2 outputs a high-precision sampling trigger clock; Module M3: an analog unit built in the PAM4 chip pre-processes the measured signal, and then transmits the pre-processed signal to an ADC, which converts the pre-processed signal into a digital signal according to the sampling trigger clock and stores the digital signal in a FIFO memory space; Module M4: an MCU transmits the sampling data in the FIFO memory space to a PC, and the PC calculates a test index of the measured signal through digital processing; Module M5: the PC reconstructs and recovers the measured signal from the sampling data; Module M6: displaying the recovered measured signal and the calculated test index of the measured signal on a display screen.

8. The measurement system of a periodic signal according to claim 7, characterized in that, The PLL1 adopts: the PLL1 selects a synchronous signal or a crystal oscillator as a reference clock.

9. The system for measuring a periodic signal according to claim 7, wherein, The high-precision sampling trigger clock output by the PLL2 adopts: T2 = nT1 + ΔT Wherein, ΔT and the highest frequency f of the measured signal should satisfy the Nyquist sampling theorem: ΔT ≤ 1 / 2f; The sampling period is T2, and one sampling cycle of the period signal is completed after m times of sampling. The relationship between a sampling cycle period t and the period T1 of the measured signal is t = m(nT1 + ΔT) = (mn + 1)T1.

10. The system for measuring a periodic signal according to claim 7, wherein, The test index of the to-be-tested signal includes eye height, eye width, eye pattern template tolerance, and SNR.

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