Method for manufacturing inner spacer of ring gate transistor
By using SiN and SiO2 to form the inner sidewall of SiON in the gate-around transistor, the problems of high dielectric constant of SiN and incompatibility of SiO2 etching are solved, parasitic capacitance is reduced and process compatibility is improved, thus enhancing the electrical performance of the device.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- FUDAN UNIVERSITY
- Filing Date
- 2022-11-15
- Publication Date
- 2026-06-26
AI Technical Summary
In the prior art, the high dielectric constant of SiN is not conducive to reducing the parasitic capacitance of gate-around transistors, while the low dielectric constant of SiO2 is incompatible with the etching process, leading to damage to other structures of the device.
SiON, formed from SiN and SiO2, is used as the inner wall material. Silicon oxide and silicon nitride are cyclically deposited through atomic layer deposition technology, and their ratio and thickness are adjusted to form a low dielectric constant dielectric material, which is compatible with other processes in terms of etching properties.
This reduces parasitic capacitance, improves process compatibility, avoids damage to other structural layers during etching, and enhances the electrical performance of the device.
Smart Images
Figure CN115579292B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of semiconductors, and more particularly to a method for fabricating the inner wall of a gate-ring transistor. Background Technology
[0002] GAAFETs require an inner wall structure to isolate the metal gate and source / drain to reduce parasitic capacitance. The smaller the dielectric constant of the dielectric material forming the inner wall, the better it is for reducing parasitic capacitance. However, in published literature, SiN is usually deposited as the dielectric material for the inner wall. Since SiN has a relatively large dielectric constant, using SiN as the dielectric material for the inner wall is not conducive to reducing parasitic capacitance.
[0003] Because SiO2 has a relatively small dielectric constant, using SiO2 as an inner wall material requires etching to remove excess deposited dielectric material. Etching SiO2 can damage other structures in the device. Therefore, depositing SiO2 as an inner wall material is not compatible with other processes. Thus, developing a method for fabricating inner walls that is compatible with other processes in device fabrication and also helps reduce parasitic capacitance has become a key technical issue that needs to be addressed by those skilled in the art. Summary of the Invention
[0004] This invention provides a method for fabricating the inner wall of a gate-around transistor to solve the problems of the large dielectric constant of the inner wall material, which is not conducive to reducing parasitic capacitance, and the poor compatibility of the etching process of the inner wall with other processes.
[0005] According to a first aspect of the present invention, a method for fabricating the inner wall of a gate-ring transistor is provided, comprising:
[0006] A gate-around transistor structure is formed, the gate-around transistor structure including a substrate and a plurality of fin structures and a plurality of dummy gate stacks arranged along a first direction formed on the substrate; the plurality of dummy gate stacks span each fin structure and are arranged along a second direction; the second direction is perpendicular to the first direction; the fin structure includes: a sacrificial layer and a channel layer stacked at intervals;
[0007] The fin structure between the dummy gate stacks is etched to form source / drain cavities;
[0008] Etch the two ends of the sacrificial layer along the first direction to form an inner sidewall cavity;
[0009] Silicon oxide and silicon nitride are deposited in the cavity of the inner sidewall;
[0010] The silicon oxide and silicon nitride outside the inner sidewall cavity are etched away to form an inner sidewall in the inner sidewall cavity, wherein the inner sidewall is composed of silicon oxynitride.
[0011] Optionally, after depositing silicon oxide and silicon nitride in the inner wall cavity, the method further includes:
[0012] The silicon oxide and the silicon nitride are annealed so that the cavity in the inner sidewall is filled with silicon oxynitride.
[0013] Optionally, the ratio of nitrogen to oxygen in the silicon oxynitride is adjustable.
[0014] Optionally, the ratio of nitrogen to oxygen in the silicon oxynitride is achieved by adjusting the thickness ratio between the deposited silicon nitride and silicon oxide.
[0015] Optionally, the thickness of the silicon oxide is 1:1, 2:1, 3:1, 1:2, or 1:3.
[0016] Optionally, the ratio of oxygen content to nitrogen content in the silicon oxynitride decreases sequentially along the direction away from the sacrificial layer. Optionally, the deposition of silicon oxide and silicon nitride in the inner wall cavity is performed using a cyclic precipitation method.
[0017] Optionally, the cyclic precipitation method is atomic layer deposition.
[0018] Optionally, silicon oxide and silicon nitride are deposited in the inner wall cavity, specifically including:
[0019] A layer of silicon oxide and a layer of silicon nitride are deposited sequentially;
[0020] Repeat the above steps to fill the cavity in the inner sidewall with the spaced-apart stacked silicon oxide and silicon nitride layers.
[0021] Optionally, after each deposition of one layer of the silicon oxide and one layer of the silicon nitride, the process further includes:
[0022] The silicon oxide and the silicon nitride are annealed to form the silicon oxynitride.
[0023] Optionally, the thickness of each deposited silicon oxide and / or silicon nitride layer is between 0.01 nm and 3 nm.
[0024] Optionally, when depositing silicon oxide and silicon nitride in the inner wall cavity, the precursors selected are: dichlorosilane, bis(tert-butylamino)silane, tris(dimethylamino)silane, bis(diethylamino)silane, or bis(isopropylamino)silane.
[0025] According to a second aspect of the present invention, a method for fabricating a gate-around transistor is provided, comprising the method for fabricating the inner wall of the gate-around transistor as described in any of the first aspects of the present invention.
[0026] According to a third aspect of the present invention, a method for manufacturing an electronic device is provided, including the method for manufacturing the inner wall of the ring gate transistor described in the second aspect of the present invention.
[0027] According to a fourth aspect of the present invention, an inner wall of a gate ring transistor is provided, which is fabricated using the method for fabricating the inner wall of a gate ring transistor according to any one of the second aspects of the present invention.
[0028] According to a fifth aspect of the present invention, a gate-around transistor is provided, including the inner sidewall of the gate-around transistor described in the fourth aspect of the present invention.
[0029] According to a sixth aspect of the present invention, an electronic device is provided, comprising the gate-ring transistor described in the fifth aspect of the present invention.
[0030] This invention provides a method for fabricating the inner sidewall of a gate-around transistor. The method involves depositing silicon oxide and silicon nitride in the inner sidewall cavity, and then etching away the silicon oxide and silicon nitride outside the cavity to form the inner sidewall. The inner sidewall is composed of silicon oxynitride. Since silicon oxynitride (SiO2) formed from silicon oxide and silicon nitride is a low-dielectric-constant dielectric material and differs from silicon oxide in its etching properties, it is compatible with other processes. Therefore, the technical solution provided by this invention solves the problems of the high dielectric constant of the inner sidewall material in gate-around transistors, which is detrimental to reducing parasitic capacitance, and the poor compatibility of the inner sidewall etching process with other processes. This achieves the technical effect of reducing the parasitic capacitance of the device while improving process compatibility, avoiding damage to other structural layers during etching, and thus improving the electrical performance of the device. Attached Figure Description
[0031] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0032] Figure 1 This is a schematic flowchart of a method for fabricating the inner sidewall of a ring gate transistor according to an embodiment of the present invention;
[0033] Figure 2This is a schematic diagram of the device structure at different process stages fabricated using the method for fabricating the inner sidewall of a gate-ring transistor according to an embodiment of the present invention. Figure 1 ;
[0034] Figure 3 This is a schematic diagram of the device structure at different process stages fabricated using the method for fabricating the inner sidewall of a gate-ring transistor according to an embodiment of the present invention. Figure 2 ;
[0035] Figure 4 This is a schematic diagram of the device structure at different process stages fabricated using the method for fabricating the inner sidewall of a gate-ring transistor according to an embodiment of the present invention. Figure 3 ;
[0036] Explanation of reference numerals in the attached figures:
[0037] 101-Substrate;
[0038] 102-channel layer;
[0039] 103 - Sacrificial Layer;
[0040] 104-spacer layer
[0041] 105-Dummy gate;
[0042] 106 - Inner wall;
[0043] 107-Source epitaxial layer;
[0044] 108-Drain epitaxial layer. Detailed Implementation
[0045] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0046] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification, claims, and accompanying drawings of this invention are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that embodiments of the invention described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover a non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.
[0047] GAAFETs require an inner wall structure to isolate the metal gate and source / drain to reduce parasitic capacitance. A lower dielectric constant for the dielectric material forming the inner wall is more beneficial for reducing parasitic capacitance. However, published literature typically uses SiN as the inner wall dielectric material. Since SiN has a relatively high dielectric constant, using SiN as the inner wall dielectric material is not conducive to reducing parasitic capacitance. Although SiO2 has a relatively low dielectric constant, using SiO2 as the inner wall material requires subsequent etching to remove excess deposited dielectric material (SiO2). Etching SiO2 can damage other structures in the device. In other words, the process of using SiO2 as the inner wall material is incompatible with subsequent processes.
[0048] Therefore, the technical problems existing in traditional techniques are: the large dielectric constant of SiN makes it difficult to reduce parasitic capacitance; and the small dielectric constant of silicon dioxide makes it incompatible with the etching steps of the inner wall and other processes.
[0049] Since silicon oxynitride (SiON) formed by SiN and SiO2 is a low dielectric constant dielectric material, its etching properties differ from those of SiO2, and it is compatible with other processes.
[0050] In view of this, the inventors of this application have used SiN and SiO2 to fabricate the inner sidewalls, which can solve the above problems and achieve the technical effect of reducing the parasitic capacitance of the device while avoiding damage to other structural layers during the etching process, thereby improving the electrical performance of the device.
[0051] Specifically, the inventors of this application have chosen atomic layer deposition (ALD) to construct the inner sidewalls with a low dielectric constant (low k). Furthermore, compared to methods that directly deposit SiON dielectric material using a specific precursor to form the inner sidewalls, this application also provides a preferred method: cyclic deposition of SiN and SiO2. Since there are more types of precursors available for depositing SiN and SiO2, relatively inexpensive precursors can be used, thereby reducing costs. Moreover, by adjusting the thickness of the deposited SiO2 and SiN, the O and N content in the final SiON dielectric material can be adjusted, thereby regulating the dielectric constant and process compatibility characteristics of the inner sidewalls.
[0052] The technical solution of the present invention will be described in detail below with reference to specific embodiments. These specific embodiments can be combined with each other, and the same or similar concepts or processes may not be described again in some embodiments.
[0053] According to an embodiment of the present invention, a method for fabricating the inner wall 106 of a gate-ring transistor is provided, comprising:
[0054] S11: Forming a gate-ring transistor structure, the gate-ring transistor structure including a substrate 101 and a plurality of fin structures and a plurality of dummy gate 105 stacks formed on the substrate 101 along a first direction; the plurality of dummy gate 105 stacks span each fin structure and are arranged along a second direction; the second direction is perpendicular to the first direction; the fin structure includes: a sacrificial layer 103 and a channel layer 102 stacked at intervals;
[0055] S12: Etch the fin structure between the stacked dummy gates 105 to form source-drain cavities;
[0056] S13: Etch both ends of the sacrificial layer 103 along the first direction to form an inner sidewall 106 cavity;
[0057] S14: Deposit silicon oxide and silicon nitride in the cavity of the inner sidewall 106;
[0058] S15: Etch away the silicon oxide and silicon nitride outside the cavity of the inner sidewall 106 to form an inner sidewall 106 in the cavity of the inner sidewall 106, wherein the inner sidewall 106 is composed of silicon oxynitride.
[0059] The dummy gate 105 stack includes a dummy gate 105 spanning the fin structure and spacer layers 104 arranged along the second direction; the spacer layers 104 are in close contact with the two side walls of the dummy gate 105 along the second direction.
[0060] The present invention provides a method for fabricating the inner sidewall 106 of a gate-ring transistor. The method involves depositing silicon oxide and silicon nitride in the cavity of the inner sidewall 106, and then etching away the silicon oxide and silicon nitride outside the cavity of the inner sidewall 106 to form the inner sidewall 106 within the cavity. The inner sidewall 106 is composed of silicon oxynitride. Since silicon oxynitride (SiON) formed from SiN and SiO2 is a low dielectric constant dielectric material, its etching properties differ from those of SiO2, making it compatible with other processes.
[0061] Therefore, the technical solution provided by the present invention solves the problems of the large dielectric constant of the inner wall 106 of the gate ring transistor, which is not conducive to reducing parasitic capacitance, and the poor compatibility of the etching process of the inner wall 106 with other processes; it achieves the technical effect of improving process compatibility while reducing the parasitic capacitance of the device, avoiding damage to other structural layers during the etching process, and thus improving the electrical performance of the device.
[0062] In one specific embodiment, when depositing silicon oxide and silicon nitride in the cavity of the inner sidewall 106, the precursors selected are:
[0063] DCS: Dichlorosilane; BTBAS: Bis(t-butylamino)silane; 3DMAS: Tris(dimethylamino)silane; BDEAS(SAM24)Bis(diethylamino)silane; or DIPAS: Diisopropylaminosilane. In one embodiment, the deposition of silicon oxide and silicon nitride in the cavity of the inner sidewall 106 is performed by a cyclic deposition method. In a specific embodiment, the cyclic deposition method is atomic layer deposition.
[0064] Compared to the technical solution of directly depositing SiON dielectric material using a specific precursor to form the inner sidewall 106, a preferred technical solution provided in this application is that since there are more types of precursors available for depositing SiN and SiO2, the technical solution of cyclic precipitation of SiN and SiO2 can use relatively inexpensive precursors, thereby reducing costs.
[0065] In one embodiment, step S14, depositing silicon oxide and silicon nitride in the cavity of the inner sidewall 106, specifically includes:
[0066] A layer of silicon oxide and a layer of silicon nitride are deposited sequentially;
[0067] Repeat the above steps to fill the cavity of the inner sidewall 106 with the spaced-apart stacked silicon oxide layer and silicon nitride layer.
[0068] In one embodiment, the thickness of each deposited silicon oxide and / or silicon nitride layer is between 0.01 nm and 2 nm.
[0069] In a preferred embodiment, to promote the formation of silicon oxynitride from silicon oxide and silicon nitride, after depositing silicon oxide and silicon nitride in the cavity of the inner sidewall 106, the method further includes annealing the silicon oxide and silicon nitride so that the cavity of the inner sidewall 106 is filled with silicon oxynitride.
[0070] In one embodiment, to promote the formation of silicon oxynitride from silicon oxide and silicon nitride, after all silicon oxide and silicon nitride have been deposited in the cavity of the inner sidewall 106, the method further includes:
[0071] The silicon oxide and the silicon nitride are annealed to form the silicon oxynitride in the cavity of the inner sidewall 106.
[0072] In another embodiment, to further promote the formation of silicon oxynitride from silicon oxide and silicon nitride, several layers of silicon oxide and several layers of silicon nitride may be deposited in the cavity of the inner sidewall 106, and then the several layers of silicon oxide and several layers of silicon nitride may be annealed to form the silicon oxynitride in the cavity of the inner sidewall 106.
[0073] In other embodiments, the silicon oxide and silicon nitride may be annealed after each deposition of one layer of the silicon oxide and one layer of the silicon nitride to form the silicon oxynitride.
[0074] In one embodiment, the ratio of nitrogen to oxygen in the silicon oxynitride structure of the inner wall 106 is adjustable.
[0075] In one embodiment, the ratio of nitrogen to oxygen in the formed silicon oxynitride is achieved by adjusting the thickness ratio between the deposited silicon nitride and silicon oxide.
[0076] When a layer of silicon oxide and a layer of silicon nitride are deposited sequentially to fill the cavity of the inner sidewall 106 with the spaced-stacked silicon oxide and silicon nitride layers, the ratio of nitrogen to oxygen in the silicon oxynitride can be adjusted in real time.
[0077] In one embodiment, after step S15, the thickness of the silicon oxide is 1:1, 2:1, 3:1, 1:2, or 1:3.
[0078] The greater the thickness ratio of silicon dioxide to silicon nitride (the greater the thickness of silicon dioxide), the smaller the dielectric constant of the material and the worse the process compatibility.
[0079] In one embodiment, the ratio of the oxygen content to the nitrogen content in the silicon oxynitride increases sequentially along the direction away from the sacrificial layer.
[0080] In another embodiment, the ratio of oxygen content to nitrogen content in the silicon oxynitride may exhibit other changing trends along the direction away from the sacrificial layer;
[0081] In order to better protect the source epitaxial layer and / or drain epitaxial layer during subsequent release of the channel layer, in a preferred embodiment, the ratio of the oxygen content to the nitrogen content in the silicon oxynitride decreases sequentially in the direction away from the sacrificial layer.
[0082] Of course, in other embodiments, the thickness ratio of silicon oxide to silicon nitride can be other ratios, and this application is not limited thereto.
[0083] Secondly, according to an embodiment of the present invention, a method for fabricating a gate-around transistor is also provided, including the method for fabricating the inner sidewall 106 of the gate-around transistor as described in any of the foregoing embodiments of the present invention. Specifically, it includes:
[0084] After performing step S16: etching away the silicon oxide and silicon nitride outside the cavity of the inner sidewall 106 to form the inner sidewall 106 in the cavity of the inner sidewall 106, the method further includes:
[0085] S16: Form source epitaxial layer 107 and / or drain epitaxial layer 108 in the source-drain cavity;
[0086] S17: Sequentially forming other structures of the ring gate transistor; this step is prior art and will not be described in detail here.
[0087] Furthermore, according to an embodiment of the present invention, a method for manufacturing an electronic device is also provided, including the method for manufacturing the inner wall 106 of the ring gate transistor described in the foregoing embodiments of the present invention.
[0088] In addition, according to an embodiment of the present invention, an inner wall 106 of a gate ring transistor is also provided, which is fabricated using the fabrication method of the inner wall 106 of the gate ring transistor described in any of the foregoing embodiments of the present invention.
[0089] According to other embodiments of the present invention, a gate ring transistor is provided, including the inner sidewall 106 of the gate ring transistor described in the foregoing embodiments of the present invention.
[0090] The technical solution provided by this invention utilizes the inner sidewall 106 made of SiN and SiO2. Since SiN and SiO2 form silicon oxynitride (SiON), a low dielectric constant dielectric material, and its etching properties differ from those of SiO2, it is compatible with other processes. Therefore, the gate ring transistor fabricated using the technical solution provided by this invention reduces the parasitic capacitance of the device while avoiding damage to other structural layers during the etching process, thus improving the electrical performance of the device.
[0091] As can be seen, the technical solution provided by the present invention solves the problem that the parasitic capacitance of the ring gate transistor is large due to the large dielectric constant of the inner wall 106 of the ring gate transistor, as well as the problem that other structural layers of the ring gate transistor are damaged during the etching process of the inner wall 106; it achieves the technical effect of reducing the parasitic capacitance of the device while avoiding damage to other structural layers during the etching process, thereby improving the electrical performance of the device.
[0092] Finally, according to one embodiment of the present invention, an electronic device is also provided, including the gate ring transistor described in the foregoing embodiments of the present invention.
[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A method for fabricating the inner wall of a gate-ring transistor, characterized in that, include: A ring gate transistor structure is formed, the ring gate transistor structure including a substrate and a plurality of fin structures and a plurality of dummy gate stacks formed on the substrate and arranged along a first direction; The plurality of dummy gate stacks span each fin structure and are arranged along the second direction; The second direction is perpendicular to the first direction; The fin structure includes: spaced-apart sacrificial layers and channel layers; The fin structure between the dummy gate stacks is etched to form source / drain cavities; Etch the two ends of the sacrificial layer along the first direction to form an inner sidewall cavity; Silicon oxide and silicon nitride are deposited in the cavity of the inner sidewall; The silicon oxide and silicon nitride outside the inner sidewall cavity are etched away to form an inner sidewall in the inner sidewall cavity, wherein the inner sidewall is composed of silicon oxynitride.
2. The method for fabricating the inner wall of the ring-gate transistor according to claim 1, characterized in that, After depositing silicon oxide and silicon nitride in the inner wall cavity, the process further includes: The silicon oxide and the silicon nitride are annealed so that the cavity in the inner sidewall is filled with silicon oxynitride.
3. The method for fabricating the inner wall of the ring-gate transistor according to claim 2, characterized in that, The ratio of nitrogen to oxygen in the silicon oxynitride is adjustable.
4. The method for fabricating the inner wall of the ring-gate transistor according to claim 3, characterized in that, The ratio of nitrogen to oxygen in the silicon oxynitride is achieved by adjusting the thickness ratio between the deposited silicon nitride and silicon oxide.
5. The method for fabricating the inner wall of the ring-gate transistor according to claim 4, characterized in that, The thickness of the silicon oxide is 1:1, 2:1, 3:1, 1:2 or 1:
3.
6. The method for fabricating the inner wall of the ring-gate transistor according to claim 5, characterized in that, The ratio of oxygen content to nitrogen content in the silicon oxynitride decreases sequentially along the direction away from the sacrificial layer.
7. The method for fabricating the inner wall of the ring-gate transistor according to claim 6, characterized in that, The method used to deposit silicon oxide and silicon nitride in the inner wall cavity is a cyclic precipitation method.
8. The method for fabricating the inner wall of the ring-gate transistor according to claim 7, characterized in that, The cyclic precipitation method is atomic layer deposition.
9. The method for fabricating the inner wall of the ring-gate transistor according to claim 8, characterized in that, Depositing silicon oxide and silicon nitride in the inner wall cavity specifically includes: Perform the step of sequentially depositing one layer of silicon oxide and one layer of silicon nitride; Repeat the above steps to fill the cavity in the inner wall with the spaced-apart stacked silicon oxide and silicon nitride.
10. The method for fabricating the inner wall of the ring-gate transistor according to claim 9, characterized in that, After each deposition of one layer of the silicon oxide and one layer of the silicon nitride, the process further includes: The silicon oxide and the silicon nitride are annealed to form the silicon oxynitride.
11. The method for fabricating the inner wall of a gate-ring transistor according to any one of claims 9 or 10, characterized in that, The thickness of each deposited silicon oxide and / or silicon nitride layer is between 0.01 nm and 2 nm.
12. The method for fabricating the inner wall of the ring-gate transistor according to claim 11, characterized in that, When depositing silicon oxide and silicon nitride in the inner wall cavity, the precursors selected are: dichlorosilane, bis(tert-butylamino)silane, tris(dimethylamino)silane, bis(diethylamino)silane, or bis(isopropylamino)silane.
13. A method for fabricating a gate-ring transistor, characterized in that, The method of fabricating the inner wall of the ring gate transistor according to any one of claims 1-12.
14. A method for manufacturing an electronic device, characterized in that, The method for fabricating the inner wall of the gate ring transistor as described in claim 13.