Display panel and driving method thereof

Abstract

The present invention discloses a display panel and a driving method thereof, wherein a display area of ​​the display panel is provided with a plurality of sub-pixels and a plurality of data lines; a non-display area is provided with a multiplexer and a plurality of shift registers; a plurality of sub-pixels are divided into a plurality of groups, each group of sub-pixels includes n rows of sub-pixels, each shift register is connected to a group of sub-pixels; each column of sub-pixels is connected to n data lines; in a group of sub-pixels, sub-pixels in different rows of the same column are connected to different data lines; the multiplexer includes a plurality of selection circuits, the input end of the selection circuit is electrically connected to the data signal output end of the driving chip, the selection circuit includes n*n selection units, the selection unit is connected between the input end of the selection circuit and the corresponding data line, the control end of the selection unit is used to access a gating signal, and the gating signals accessed by the control ends of different selection units in the same selection circuit are not completely the same. The display panel is conducive to reducing the number of ports for outputting data signals and reducing costs.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a driving method thereof. Background Art

[0002] Active-matrix organic light-emitting diode (AMOLED) is widely used in the display field due to its fast response speed, high contrast and wide viewing angle.

[0003] The display panel includes multiple data lines to write data signals into the corresponding sub-pixels of the display panel. The existing AMOLED MUX driving scheme requires a large number of ports for outputting data signals, resulting in a large number of data signal output ports of the driver chip during product design, which easily causes the problem of increased cost of the driver chip. Summary of the invention

[0004] The present invention provides a display panel and a driving method thereof, so as to reduce the number of ports for outputting data signals and reduce the cost of driving chips.

[0005] According to one aspect of the present invention, a display panel is provided, the display panel comprising: a display area and a non-display area adjacent to the display area, the display area being provided with a plurality of sub-pixels and a plurality of data lines; the non-display area being provided with a multiplexer and a plurality of shift registers;

[0006] The plurality of sub-pixels are divided into a plurality of groups, each group of sub-pixels includes n rows of sub-pixels, each shift register is connected to a group of sub-pixels; each column of sub-pixels is connected to n data lines, n≥2; wherein, in a group of sub-pixels, sub-pixels in the same column but different rows are connected to different data lines;

[0007] The multiplexer includes a plurality of selection circuits, the input end of the selection circuit is electrically connected to the data signal output end of the driving chip, the selection circuit includes n*n selection units, in which the first end of the selection unit is electrically connected to the input end of the selection circuit, and the second end of each selection unit is electrically connected to the data line connected to the n columns of sub-pixels in a one-to-one correspondence; the control end of the selection unit is used to access the selection signal, and the control end of different selection units in the same selection circuit accesses the selection signal that is not completely the same, so that each selection unit is turned on in time.

[0008] Optionally, the n*n selection units included in different selection circuits are arranged in the same manner;

[0009] Optionally, in different selection circuits, the selection units connected to sub-pixels at the same relative position are located in the same row.

[0010] Optionally, the display panel further includes n*n selection control lines, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, the n*n selection control lines are electrically connected to control ends of n*n selection units in each selection circuit in a one-to-one correspondence, and the selection units at the same relative position in different selection circuits are connected to the same selection control lines;

[0011] Optionally, the selection unit includes a transistor, a first electrode of the transistor serves as a first end of the selection unit, a second electrode of the transistor serves as a second end of the selection unit, and a gate of the transistor serves as a control end of the selection unit.

[0012] Optionally, the display panel further includes n*n-1 selection control lines, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, and among the n*n selection units included in the selection circuit, control ends of n*n-1 of the selection units are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the control end of the remaining selection unit is connected to the n*n-1 selection control lines;

[0013] Optionally, the selection unit connected to one of the selection control lines includes a first control transistor, and the selection unit connected to n*n-1 selection control lines includes n*n-1 second control transistors, the control ends of the n*n-1 second control transistors are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the channel types of the first control transistor and the second control transistor are opposite.

[0014] Optionally, in the data lines connected to a column of sub-pixels, the sub-pixels connected to each data line have the same color.

[0015] Optionally, the colors of the sub-pixels in different groups are arranged in the same manner.

[0016] Optionally, the display panel further comprises a plurality of gate lines, each of the shift registers is connected to one of the gate lines, and n rows of sub-pixels in a group of sub-pixels are connected to the same gate line;

[0017] Alternatively, each of the shift registers is connected to n gate lines, each row of the sub-pixels is connected to one gate line, and the n gate lines corresponding to a same group of sub-pixels are connected to the same shift register.

[0018] According to another aspect of the present invention, a method for driving a display panel is provided, for driving any one of the above-mentioned display panels, the method for driving a display panel comprising:

[0019] Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels;

[0020] When the shift register outputs a valid scanning signal, the selection signals connected to each selection unit in the selection circuit are controlled to be valid in turn, so as to turn on each selection unit in turn and transmit the data signal input from the input end of the selection circuit to the corresponding sub-pixel in a time-sharing manner, wherein, at one moment, only one selection unit in a selection circuit is turned on.

[0021] Optionally, the n*n selection units included in different selection circuits are arranged in the same manner; in different selection circuits, the selection units connected to sub-pixels at the same relative position are located in the same row; the display panel includes n*n selection control lines, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, the n*n selection control lines are electrically connected to control ends of the n*n selection units in each selection circuit in a one-to-one correspondence, and the selection units at the same relative position in different selection circuits are connected to the same selection control lines;

[0022] When the shift register outputs a valid scanning signal, the selection signals connected to the selection units in the selection circuit are sequentially controlled to be valid, so as to sequentially turn on the selection units and transmit the data signals inputted from the input end of the selection circuit to the corresponding sub-pixels in a time-sharing manner, including:

[0023] When the shift register outputs a valid scan signal, providing a valid selection signal to the n*n selection control lines connected to the selection circuit in sequence;

[0024] Optionally, at the moment when any selection unit of the selection circuit is turned on, among the n*n selection control lines connected to the selection circuit, only the selection control line connected to the turned-on selection unit transmits a first level signal, and the selection signals transmitted on the remaining n*n-1 selection control lines are all second level signals.

[0025] Optionally, the n*n selection units included in different selection circuits are arranged in the same manner; in different selection circuits, the selection units connected to sub-pixels at the same relative position are located in the same row; and n*n-1 selection control lines are further included, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, and among the n*n selection units included in the selection circuit, control ends of n*n-1 selection units are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the control end of the remaining selection unit is connected to the n*n-1 selection control lines;

[0026] When the shift register outputs a valid scanning signal, the selection signals connected to the selection units in the selection circuit are sequentially controlled to be valid, so as to sequentially turn on the selection units and transmit the data signals inputted from the input end of the selection circuit to the corresponding sub-pixels in a time-sharing manner, including:

[0027] When the shift register outputs a valid scan signal, a valid selection signal is sequentially provided to the n*n-1 selection control lines connected to the selection circuit, so that the selection units connected to one of the selection control lines are sequentially turned on; and an invalid selection signal is provided to the n*n-1 selection control lines, so that the selection units connected to the n*n-1 selection control lines are turned on;

[0028] Optionally, at the moment when any selection unit connected to only one selection control line included in the selection circuit is turned on, only the selection signal transmitted on the selection control line connected to the turned-on selection unit is a first level signal, and the selection signals transmitted on the remaining n*n-2 selection control lines are all second level signals;

[0029] When the selection units simultaneously connected to n*n-1 selection control lines included in the selection circuit are turned on, the selection signals transmitted on the selection control lines are all second level signals.

[0030] The display panel provided by the embodiment of the present invention comprises: a display area and a non-display area adjacent to the display area, wherein the display area is provided with a plurality of sub-pixels and a plurality of data lines; the non-display area is provided with a multiplexer and a plurality of shift registers; wherein the plurality of sub-pixels are divided into a plurality of groups, each group of sub-pixels comprises n rows of sub-pixels, and each shift register is connected to a group of sub-pixels; each column of sub-pixels is connected to n data lines, where n≥2; wherein, in a group of sub-pixels, sub-pixels in the same column but different rows are connected to different data lines; the multiplexer comprises a plurality of selection circuits, the input end of the selection circuit is electrically connected to the data signal output end of the driving chip, the selection circuit comprises n*n selection units, in the n*n selection units, the first end of the selection unit is electrically connected to the input end of the selection circuit, and the second end of the selection unit is electrically connected to the data lines connected to the n columns of sub-pixels in a one-to-one correspondence; the control end of the selection unit is used to access a selection signal, and the selection signals accessed to the control ends of different selection units in the same selection circuit are not completely the same, so that each selection unit is turned on in time sharing. By setting a multiplexer, and setting the multiplexer to include multiple selection circuits, the selection circuit includes multiple selection units, and the multiple selection units included in the same selection circuit are connected to different data lines, and the control terminals of different selection units in the same selection circuit are connected to different selection signals, so as to control each selection unit to be turned on in time-sharing manner, so as to realize the time-sharing transmission of data signals to different sub-pixels. Since all the selection units in the same selection circuit are connected to the data signal output terminal of the same driver chip, the n*n data lines only need to be connected to the data signal output terminal of one driver chip to realize the time-sharing writing of the data signal, which saves the number of driver chip output ports and is conducive to reducing the production cost of the driver chip. At the same time, one shift register can control n rows of sub-pixels in a group, which is conducive to saving the number of shift registers and simplifying the display panel structure.

[0031] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0033] Figure 1 is a schematic diagram of the structure of a display panel;

[0034] Figure 2 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0035] Figure 3 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0036] Figure 4 is a driving timing diagram of a display panel provided by an embodiment of the present invention;

[0037] Figure 5 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0038] Figure 6 is a schematic structural diagram of another display panel provided by an embodiment of the present invention;

[0039] Figure 7 is another driving timing sequence of a display panel provided by an embodiment of the present invention;

[0040] Figure 8 A flow chart of a method for driving a display panel provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0042] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0043] As described in the background technology, in the prior art AMOLED MUX driving solution, the number of ports for the driver chip to output data signals is relatively large. Figure 1 , Figure 1The present invention is a structural schematic diagram of a display panel, which includes a plurality of sub-pixels 10, a plurality of data lines 11 and a plurality of gate lines 12. The sub-pixels 10 are arranged in an array, each row of sub-pixels 10 is connected to a gate line 12, each column of sub-pixels is connected to a data line 11, and a data line 11 is correspondingly connected to a port of a driving chip, so that the driving chip transmits a data signal to the corresponding sub-pixel 10 through the data line 11. Figure 1 The display panel exemplarily shows that it includes four rows and four columns of sub-pixels 10, and the four gate lines 12 connecting the sub-pixels 10 in the first row to the sub-pixels 10 in the fourth row are respectively used to transmit the first control signal Gate1, the second control signal Gate2, the third control signal Gate3 and the fourth control signal Gate4, and the four data lines 11 connecting the sub-pixels 10 in the first column to the sub-pixels 10 in the fourth column are respectively used to transmit the first data signal Source1, the second data signal Source2, the third data signal Source3 and the fourth data signal Source4. When the display panel is working, the first control signal Gate1 first controls the sub-pixels 10 of the first row to turn on, and the first data signal Source1 to the fourth data signal Source4 respectively write data signals to the sub-pixels of the first row, and then the second control signal Gate2, the third control signal Gate3 and the fourth control signal Gate4 control the sub-pixels 10 of the second row, the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row to turn on in sequence, and the first data signal Source1 to the fourth data signal Source4 respectively write data signals to the sub-pixels 10 of the second row, the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row. In this scheme, each row of sub-pixels 10 uses a control signal, and each column of sub-pixels 10 uses a data signal, that is, each column of sub-pixels 10 corresponds to a port of a driver chip, and the ports of the driver chip corresponding to sub-pixels 10 in different columns are different, resulting in a large number of ports required for the driver chip, which increases the cost of the driver chip.

[0044] In view of the above technical problems, the present invention provides a new display panel. Figure 2 A schematic diagram of a display panel according to an embodiment of the present invention is provided. Figure 2 The display panel includes: a display area AA and a non-display area NAA adjacent to the display area AA, the display area AA is provided with a plurality of sub-pixels 10 and a plurality of data lines 11; the non-display area is provided with a multiplexer 13 and a plurality of shift registers 14;

[0045] The plurality of sub-pixels 10 are divided into a plurality of groups, each group of sub-pixels includes n rows of sub-pixels 10, each shift register 14 is connected to a group of sub-pixels 10; each column of sub-pixels 10 is connected to n data lines 11, n≥2; wherein in a group of sub-pixels 10, sub-pixels in the same column but different rows are connected to different data lines 11;

[0046] The multiplexer 13 includes a plurality of selection circuits 131, and the input end of the selection circuit 131 is electrically connected to the data signal output end of the driver chip. As an example, the input end of the selection circuit 131 can be electrically connected to the data signal output end of the driver chip in a one-to-one correspondence. The selection circuit 131 includes n*n selection units 1311, and the first ends of the n*n selection units 1311 in the selection circuit 131 are all electrically connected to the input end of the selection circuit 131, and the second ends of the n*n selection units 1311 are electrically connected to the data lines 11 connected to the n columns of sub-pixels 10 in a one-to-one correspondence; the control end of the selection unit 1311 is used to access the selection signal, and the selection signals accessed to the control ends of different selection units 1311 in the same selection circuit 131 are not completely the same, so that each selection unit 1311 is turned on in time-sharing manner.

[0047] The display area AA is an area in the display panel where the picture is displayed. The display area AA is provided with a plurality of sub-pixels 10. For example, the sub-pixels include red sub-pixels R, green sub-pixels G and blue sub-pixels B. Sub-pixels 10 of different colors are written with different data signals via correspondingly connected data lines 11 to cooperate in the picture display. The non-display area NAA may be a frame area of ​​the display panel. A multiplexer 13 and a shift register 14 are provided in the non-display area NAA to avoid the influence on the light emitted in the display area AA. When n is 2, each group of sub-pixels includes 2 rows of sub-pixels 10, and each column of sub-pixels is connected to 2 data lines. For example, when the display panel includes four rows and four columns of sub-pixels, the first and second rows of sub-pixels 10 are a group, and the third and fourth rows of sub-pixels 10 are a group. The sub-pixels 10 of the first row and the sub-pixels 10 of the third row of each column of sub-pixels 10 can be connected to the same data line 11, and the sub-pixels of the second row and the sub-pixels 10 of the fourth row of each column of sub-pixels can be connected to the same data line 11. Alternatively, the first and third rows of sub-pixels 10 are a group, the second and fourth rows of sub-pixels 10 are a group, the sub-pixels 10 in the first row and the sub-pixels in the second row of each column of sub-pixels 10 can be connected to the same data line 11, and the sub-pixels in the third row and the sub-pixels in the fourth row of each column of sub-pixels can be connected to the same data line 11. When n is 3 or more, the above rules are followed and so on, and this embodiment is not repeated here. The shift register 14 is used to transmit a control signal to each corresponding group of sub-pixels to control the corresponding group of sub-pixels 10 to turn on, so as to facilitate the writing of subsequent data signals.

[0048] In this embodiment, the display panel includes four rows and four columns of sub-pixels 10 as an example. The first and second rows of sub-pixels 10 are a group of sub-pixels, and the third and fourth rows of sub-pixels 10 are a group of sub-pixels. The sub-pixels 10 in the first row and the sub-pixels 10 in the third row of each column of sub-pixels 10 can be connected to the same data line 11, and the sub-pixels 10 in the second row and the sub-pixels 10 in the fourth row of each column of sub-pixels 10 can be connected to the same data line 11. In this embodiment, two selection circuits 131 are included, and each selection circuit 131 corresponds to an output end of the driver chip. In this embodiment, the two output ends of the driver chip are used to transmit the first data line signal Source1 and the second data signal Source2 respectively. As an optional method, the selection signal connected to each selection unit 1311 can be different. When the display panel is working, the shift register 14 corresponding to the first and second rows of sub-pixels 10 controls the first and second rows of sub-pixels to be turned on, and the shift register 14 corresponding to the third and fourth rows of sub-pixels 10 controls the third and fourth rows of sub-pixels to be turned off. During the period when the sub-pixels 10 in the first and second rows are turned on, the selection units 1311 corresponding to the sub-pixels 10 in the first row and the first column and the selection units 1311 corresponding to the sub-pixels 10 in the first row and the third column can be turned on by the selection signal, so as to transmit the first data signal Source1 outputted from the data signal output terminal of the driving chip to the sub-pixels 10 in the first row and the first column, and transmit the second data signal Source2 to the sub-pixels 10 in the first row and the third column. Then, the selection units 1311 corresponding to the sub-pixels 10 in the first row and the second column and the selection units 1311 corresponding to the sub-pixels 10 in the first row and the fourth column can be turned on by the selection signal, so as to transmit the first data signal Source1 to the sub-pixels 10 in the first row and the second column, and transmit the second data signal Source2 to the sub-pixels 10 in the first row and the fourth column. Then, the selection unit 1311 corresponding to the sub-pixel 10 in the second row and the first column and the selection unit 1311 corresponding to the sub-pixel 10 in the second row and the third column are controlled to be turned on by the selection signal, so as to transmit the first data signal Source1 to the sub-pixel 10 in the second row and the first column, and the second data signal Source2 to the sub-pixel 10 in the second row and the third column. Finally, the selection unit 1311 corresponding to the sub-pixel 10 in the second row and the second column and the selection unit 1311 corresponding to the sub-pixel 10 in the second row and the fourth column are controlled to be turned on by the selection signal, so as to transmit the first data signal Source1 to the sub-pixel 10 in the second row and the second column, and the second data signal Source2 to the sub-pixel 10 in the second row and the fourth column. After the data signal is written into the sub-pixels 10 in the first row and the second row, the sub-pixels 10 in the first row and the second row are controlled to be turned off, and the sub-pixels 10 in the third row and the fourth row are controlled to be turned on, so as to write the data signal to the sub-pixels 10 in the third row and the fourth row in time division. The specific process is the same as the writing process of the first row and the second row, and will not be repeated here.Finally, the data signal is written into the sub-pixel 10 in a time-division manner by time-division conduction of the selection unit 1311. In this embodiment, the sub-pixels of four rows and four columns only need the data signal output terminals of two driving chips to realize the time-division writing of the data signal, compared with the prior art, such as. Figure 1 The number of data signal output terminals of the driver chip of the display panel is 4, which greatly saves the number of output ports of the driver chip.

[0049] By setting a multiplexer, and setting the multiplexer to include multiple selection circuits, the selection circuit includes multiple selection units, and the multiple selection units included in the same selection circuit are connected to different data lines, and the control terminals of different selection units in the same selection circuit are connected to different selection signals, so as to control each selection unit to be turned on in time-sharing manner, so as to realize the time-sharing transmission of data signals to different sub-pixels. Since all the selection units in the same selection circuit are connected to the data signal output terminal of the same driver chip, n*n data lines only need to be connected to the data signal output terminal of one driver chip to realize the time-sharing writing of data signals, which saves the number of output ports of the driver chip and is conducive to reducing the production cost of the driver chip.

[0050] Continue to refer Figure 2 Optionally, the n*n selection units 1311 included in different selection circuits 131 are arranged in the same manner.

[0051] by Figure 2 Taking the display panel including four rows and four columns of sub-pixels 10 as an example, the display panel includes two selection circuits 131, each selection circuit 131 includes four selection units 1311, and the four selection units 1311 are arranged in staggered rows. Specifically, taking the selection circuits 131 corresponding to the sub-pixels 10 in the first column and the second column as an example, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the first column, the first row and the first column and the third row are located in the first row of the setting area of ​​the selection circuit 131, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the second column, the first row and the second column and the third row are located in the second row of the setting area of ​​the selection circuit 131, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the first column, the second row and the first column and the fourth row are located in the third row of the setting area of ​​the selection circuit 131, and the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the second column, the second row and the second column and the fourth row are located in the fourth row of the setting area of ​​the selection circuit 131. The arrangement of the four selection units 1311 included in another selection circuit 131 is the same. The arrangement of the n*n selection units 1311 included in different selection circuits 131 is the same, which can make the layout devices and signal lines of the display panel distributed regularly, which is conducive to simplifying the manufacturing process of the display panel. Figure 2, Optionally, in different selection circuits 131, the selection units 1311 connected to the sub-pixels 10 at the same relative position are located in the same row. The sub-pixels 10 at the same relative position can be understood as that the number of rows and columns of the sub-pixels 10 at a certain position in the first group of sub-pixels relative to the first group of sub-pixels are the same as the number of rows and columns of the sub-pixels at the corresponding position in the second group of sub-pixels relative to the second group of sub-pixels. For example, the sub-pixels 10 in the first and second rows are divided into one group, and the sub-pixels 10 in the third and fourth rows are divided into another group. The number of rows and columns of the sub-pixels 10 in the first row and the first column relative to the sub-pixels 10 in this group is 1, and the number of rows and columns of the sub-pixels 10 in the first row and the first column relative to the sub-pixels 10 in this group is 1, and the number of rows and columns of the sub-pixels 10 in the first row and the first column relative to the sub-pixels 10 in this group is 1. Therefore, the sub-pixels 10 in the first row and the first column and the sub-pixels in the first row and the first column belong to the sub-pixels 10 at the same relative position in the sub-pixels 10 of different groups.

[0052] by Figure 2 For example, the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 of the first column, the first row, and the first column and the third row and the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 of the third column, the first row, the third column, and the third row are located in the same row. The selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 of the first column, the second row, the first column, and the fourth row and the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 of the third column, the second row, the third column, and the fourth row are located in the same row. The selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 of the second column, the first row, the second column, and the third row and the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 of the fourth column, the first row, the fourth column, and the third row are located in the same row. The selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the second column, the second row, and the second column, the fourth row and the selection units 1311 connected to the data lines 11 corresponding to the sub-pixels 10 in the fourth column, the second row, and the fourth column, the fourth row are located in the same row. In different selection circuits 131, the selection units 1311 connected to the sub-pixels 10 in the same relative position are located in the same row, that is, n selection units 1311 can be arranged in one row, which can save the setting area of ​​the multiplexer 13, reduce the area of ​​the display panel, and facilitate miniaturization of the display panel.

[0053] Continue to refer Figure 2Optionally, in the data lines 11 corresponding to the sub-pixels 10 in a column, the sub-pixels 10 connected to each data line 11 have the same color. Since the relationship between the grayscale and the data voltage corresponding to the sub-pixels of different colors is different, it is necessary to output data voltages to different colors based on different references. In the display panel of this embodiment, in a column, the sub-pixels 10 connected to each data line 11 have the same color, and the output data voltage output by the driver chip to one data line can be based on the same reference, which is conducive to simplifying the internal program of the driver chip.

[0054] Continue to refer Figure 2 Optionally, the colors of the sub-pixels 10 in different groups are arranged in the same manner.

[0055] In this embodiment, Figure 2 Taking the structure of the display panel shown as an example, it is exemplarily shown that the sub-pixels 10 in the first row and the first column and the sub-pixels 10 in the first row and the third column are all red sub-pixels R, the sub-pixels 10 in the first column and the second row and the sub-pixels 10 in the first column and the fourth row are blue sub-pixels B, the four sub-pixels in the second column are all green sub-pixels G, the sub-pixels 10 in the third column and the first row and the sub-pixels in the third column and the third row are all blue sub-pixels B, the sub-pixels 120 in the third column and the second row and the sub-pixels 10 in the third column and the fourth row are all red sub-pixels R, and the sub-pixels 10 in the fourth column are all green sub-pixels G. Since the relationship between the grayscale and the data voltage corresponding to the sub-pixels 10 of different colors is different, it is necessary to output the data voltage to the sub-pixels 10 of different colors based on different references. In the display panel of this embodiment, the color arrangement of the sub-pixels 10 of different groups connected to each selection circuit 131 is the same. When the driver chip outputs the data voltage to the selection circuit connected to each output terminal, the change rule of the relationship between the grayscale and the data voltage is the same, which is also conducive to the simplification of the internal program of the driver chip.

[0056] Figure 3 A schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 3 Optionally, the display panel further includes n*n selection control lines 15, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, the n*n selection control lines 15 are electrically connected to the control ends of the n*n selection units 1311 in each selection circuit 131 in a one-to-one correspondence, and the selection units 1311 at the same relative position in different selection circuits 131 are connected to the same selection control lines 15.

[0057] by Figure 3Taking the example that the display panel shown includes four rows and four columns of sub-pixels 10, and each group of sub-pixels 10 includes two rows of sub-pixels 10, the display panel includes four selection control lines 15, which are respectively used to transmit the first selection control signal MUX1, the second selection control signal MUX2, the third selection control signal MUX3 and the fourth selection control signal MUX4. In different selection circuits 131, the selection units 1311 connected to the sub-pixels 10 at the same relative position are located in the same row, the selection control line 15 corresponding to the first selection control signal MUX1 is connected to the selection unit 1311 of the first row, the selection control line 15 corresponding to the second selection control signal MUX2 is connected to the selection unit 1311 of the second row, the selection control line 15 corresponding to the third selection control signal MUX3 is connected to the selection unit 1311 of the third row, and the selection control line 15 corresponding to the fourth selection control signal MUX4 is connected to the selection unit 1311 of the fourth row. The selection signal is transmitted in time-sharing through the four selection control lines to realize the time-sharing conduction of the four rows of selection units 1311. The selection signal is a signal for controlling the selection unit 1311 to be turned on, and the selection control signal also includes a non-selection signal, which is a signal for controlling the selection unit 1311 to be turned off.

[0058] Continue to refer Figure 3 Optionally, the selection unit 1311 includes a transistor, a first electrode of the transistor serves as a first end of the selection unit 1311 , a second electrode of the transistor serves as a second end of the selection unit 1311 , and a gate of the transistor serves as a control end of the selection unit 1311 .

[0059] The transistor can be an n-type transistor or a p-type transistor. When the transistor is a p-type transistor, the gating signal is a low level and the non-gating signal is a high level. When the transistor is an n-type transistor, the gating signal is a high level and the non-gating signal is a low level. The selection unit 1311 includes a transistor to realize the time-sharing writing of the data signal, which has a simple structure and is easy to implement.

[0060] Continue to refer Figure 3 Optionally, the display panel further includes a plurality of gate lines 12 , each shift register is connected to a gate line 12 , and n rows of sub-pixels 10 in a group of sub-pixels 10 are connected to the same gate line 12 .

[0061] by Figure 3 For example, the display panel includes two gate lines 12, one gate line 12 connects the sub-pixels 10 in the first row and the second row, and is used to transmit the first control signal Gate1. The other gate line 12 connects the sub-pixels 10 in the third row and the fourth row, and is used to transmit the second control signal Gate2. The shift register transmits a signal to the sub-pixels 10 in the corresponding row through the corresponding gate line 12 to control the sub-pixels 10 in the corresponding row to turn on or off.

[0062] Figure 4A driving timing diagram of a display panel provided by an embodiment of the present invention, Figure 4 The timing shown is applicable to Figure 3 In the display panel shown, for example, the data line 11 corresponding to the first row and the third row of the sub-pixel 10 in the first column is connected to the first transistor T1, the data line 11 corresponding to the second row and the fourth row of the sub-pixel 10 in the first column is connected to the second transistor T2, the data line 11 corresponding to the first row and the third row of the sub-pixel 10 in the second column is connected to the third transistor T3, the data line 11 corresponding to the second row and the fourth row of the sub-pixel 10 in the second column is connected to the fourth transistor T4, the data line 11 corresponding to the first row and the third row of the sub-pixel 10 in the third column is connected to the fifth transistor T5, and the data line 11 corresponding to the second row and the fourth row of the sub-pixel 10 in the third column is connected to the fifth transistor T6. The corresponding data line 11 is connected to the sixth transistor T6, the data line 11 corresponding to the first row and the third row of the fourth column of the sub-pixel 10 is connected to the seventh transistor T7, the data line 11 corresponding to the second row and the fourth row of the sub-pixel 10 of the fourth column is connected to the eighth transistor T8, the selection circuit 131 to which the first transistor T1 to the fourth transistor T4 belong is connected to one output end of the driving chip to transmit the first data signal Source1 in time-sharing, the selection circuit 131 to which the fifth transistor T1 to the eighth transistor T8 belong is connected to the other output end of the driving chip to transmit the second data signal Source2 in time-sharing, and Figure 3 The transistors included in the display panel shown in FIG. 1 are all P-type transistors.

[0063] refer to Figure 3 and Figure 4Taking the first writing stage t1 of the display panel as an example, in the first writing stage t1, the first control signal Gate1 is at a low level, and the second control signal Gate2 is at a high level. In the first writing stage t1, the first control signal Gate1 controls the sub-pixels 10 of the first row and the sub-pixels 10 of the second row to be turned on, and the second control signal Gate2 controls the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row to be turned off. The first writing stage t1 includes a first sub-stage t11, a second sub-stage t12, a third sub-stage t13, and a fourth sub-stage t14. In the first sub-stage t11, the first selection control signal MUX1 is at a low level, the second selection control signal MUX2, the third selection control signal MUX3 and the fourth selection control signal MUX4 are all at high levels, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned on, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned off, the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned off, and the fourth selection control signal MUX4 controls the fourth transistor T4 and the eighth transistor T8 to be turned off, the first data signal Source1 is written into the sub-pixel 10 of the first row and the first column through the turned-on first transistor T1, and the second data signal Source2 is written into the sub-pixel 10 of the first row and the third column through the turned-on fifth transistor T5. In the second sub-stage t12, the second selection control signal MUX2 is at a low level, the first selection control signal MUX1, the third selection control signal MUX3 and the fourth selection control signal MUX4 are all at high levels, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned on, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned off, the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned off, and the fourth selection control signal MUX4 controls the fourth transistor T4 and the eighth transistor T8 to be turned off, the first data signal Source1 is written into the sub-pixel 10 of the first row and the second column through the turned-on third transistor T3, and the second data signal Source2 is written into the sub-pixel 10 of the first row and the fourth column through the turned-on seventh transistor T7.In the third sub-stage t13, the third selection control signal MUX3 is at a low level, the first selection control signal MUX1, the second selection control signal MUX2 and the fourth selection control signal MUX4 are at a high level, the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned on, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned off, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned off, and the fourth selection control signal MUX4 controls the fourth transistor T4 and the eighth transistor T8 to be turned off, the first data signal Source1 is written into the sub-pixel 10 of the second row and the first column through the turned-on second transistor T2, and the second data signal Source2 is written into the sub-pixel 10 of the second row and the third column through the turned-on sixth transistor T6. In the fourth sub-phase t14, the fourth selection control signal MUX4 is at a low level, the first selection control signal MUX1, the second selection control signal MUX2 and the third selection control signal MUX3 are all at high levels, the fourth selection control signal MUX4 controls the fourth transistor T4 and the eighth transistor T8 to be turned on, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned off, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned off, and the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned off, the first data signal Source1 is written into the sub-pixel 10 of the second row and the second column through the turned-on fourth transistor T4, and the second data signal Source2 is written into the sub-pixel 10 of the second row and the fourth column through the eighth transistor T7. In this embodiment, the sub-pixels 10 of the first row and the second row are written with data signals in a time-sharing manner through the above-mentioned 8 transistors. The working process of the display panel also includes a second writing stage. The difference between the second writing stage and the first writing stage t1 is that the first control signal Gate1 is at a high level and the second control signal Gate2 is at a low level. In the second writing stage, the first control signal Gate1 controls the sub-pixels 10 of the first row and the sub-pixels 10 of the second row to be turned off, and the second control signal Gate2 controls the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row to be turned on. The other processes are the same as the first writing stage and will not be repeated here, so as to realize the time-sharing writing of data signals to the sub-pixels 10 of the third row and the sub-pixels 10 of the fourth row.

[0064] Figure 5 A schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 5 Optionally, each shift register is connected to n gate lines 12, each row of sub-pixels 10 is connected to a gate line 12, and the n gate lines 12 corresponding to the same group of sub-pixels 10 are connected to the same shift register.

[0065] Figure 5 The display panel shown is Figure 3The difference is that each row of sub-pixels 10 is connected to a corresponding gate line 12, and the n gate lines 12 connected to the sub-pixels 10 in the same group are connected to the same shift register, that is, the signals on the n gate lines connected to the sub-pixels 10 in the same group are the same. Figure 5 The gate line 12 connected to the sub-pixels in the first row and the gate line connected to the sub-pixels 10 in the second row are both used to transmit the first control signal Gate1, the gate line 12 connected to the sub-pixels in the third row and the gate line connected to the sub-pixels 10 in the fourth row are both used to transmit the second control signal Gate2, Figure 4 The drive timing shown also applies to Figure 5 The display panel shown, and Figure 5 The working process of the display panel shown is similar to Figure 3 The working process of the display surface shown is the same and will not be repeated here.

[0066] In this embodiment, for the sub-pixels of four rows and four columns, the display panel can be driven through two control signals (the first control signal Gate1 and the second control signal Gate2), two output terminals of the driving chip and four selection control lines, which saves the number of signals and the number of data signal output terminals of the driving chip, and is conducive to reducing the cost of the driving chip.

[0067] Figure 6 A schematic diagram of another display panel provided by an embodiment of the present invention, referring to Figure 6 Optionally, the display panel also includes n*n-1 selection control lines 15, the selection control lines 15 are used to transmit selection control signals, the selection control signals include selection signals, among the n*n selection units 1311 included in the selection circuit 131, the control ends of n*n-1 selection units 1311 are electrically connected to the n*n-1 selection control lines 15 in a one-to-one correspondence, and the control end of the remaining selection unit 1311 is connected to the n*n-1 selection control lines 15.

[0068] by Figure 6 Taking the display panel shown as an example, Figure 6 The display panel includes four rows and four columns of sub-pixels 10, each group of sub-pixels 10 includes two rows of sub-pixels 10, the display panel includes three selection control lines 15, each selection circuit 131 includes four selection units 1311, three of the four selection units 1311 are respectively connected to one selection control line 15, and the remaining one selection unit 1311 is connected to three selection control lines 15 at the same time.

[0069] Continue to refer Figure 6Optionally, the selection unit 1311 connected to one selection control line 15 includes a first control transistor, and the selection unit 1311 connected to n*n-1 selection control lines 15 includes n*n-1 second control transistors, and the control ends of the n*n-1 second control transistors are electrically connected to the n*n-1 selection control lines 15 in a one-to-one correspondence, and the channel types of the first control transistor and the second control transistor are opposite. The first electrode of the first control transistor serves as the first end of the selection unit 131, the second electrode of the first control transistor serves as the second end of the selection unit 131, the gate of the first control transistor serves as the control end of the selection unit 131, the first electrode of the second control transistor serves as the first end of the selection unit 131, the second electrode of the second control transistor serves as the second end of the selection unit 131, and the gate of the second control transistor serves as the control end of the selection unit 131. If the first control transistor is a P-type transistor, the second control transistor is an N-type transistor. Alternatively, if the first control transistor is an N-type transistor, the second control transistor is a P-type transistor.

[0070] Figure 6 The structure shown is Figure 5 The difference is that Figure 6 It includes three selection control lines 15, which are respectively used to output the first selection control signal MUX1, the second selection control signal MUX2 and the third selection control signal MUX3, and the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and the fourth row of the second column is a structure in which the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are connected in series. The selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and the fourth row of the fourth column is a structure in which the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are connected in series. The other structures are the same as Figure 5The display panel shown is the same and will not be described again. Among them, the first transistor T1, the second transistor T2, the third transistor T3, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7 are all first control transistors, and the eighth transistor T8, the ninth transistor T9, the tenth transistor T10, the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are all second control transistors. After the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 are connected in series in sequence, the second electrode of the eighth transistor T8 serves as the second end of the corresponding selection unit 1311, the first electrode of the tenth transistor T10 serves as the first end of the corresponding selection unit 1311, and the gates of the eighth transistor T8, the ninth transistor T9 and the tenth transistor T10 serve as the control ends of the corresponding selection unit 1311. After the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 are connected in series in sequence, the second electrode of the eleventh transistor T11 serves as the second end of the corresponding selection unit 1311, the first electrode of the thirteenth transistor T13 serves as the first end of the corresponding selection unit 1311, and the gates of the eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13 all serve as control ends of the corresponding selection unit 1311.

[0071] Figure 7 Another driving timing diagram of a display panel provided by an embodiment of the present invention, Figure 7 The timing diagram shown applies to Figure 6 In the display panel shown, Figure 6 The first control transistors are all P-type transistors, and the second control transistors are all N-type transistors. Figure 7The working process of the display panel shown includes a first writing stage t1. In the first writing stage, the first control signal Gate1 is at a low level, the second control signal Gate2 is at a high level, the first control signal Gate1 controls the sub-pixels 10 of the first and second rows to turn on, and the second control signal Gate2 controls the sub-pixels 10 of the third and fourth rows to turn off. The first writing stage t1 includes a first sub-stage t11, a second sub-stage t12, a third sub-stage t13, and a fourth sub-stage t14. In the first sub-stage t11, the first selection control signal MUX1 is at a low level, the second selection control signal MUX2 and the third selection control signal MUX3 are both at high levels, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned on, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned off, the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned off, the first selection control signal MUX1 controls the tenth transistor T10 and the thirteenth transistor T13 to be turned off, the second selection control signal MUX2 controls the ninth transistor T9 and the twelfth transistor T12 to be turned on, the third selection control signal MUX3 controls the eighth transistor T8 and the eleventh transistor T11 to be turned on, the first data signal Source1 is written into the sub-pixel 10 of the first row and the first column through the turned-on first transistor T1, and the second data signal Source2 is written into the sub-pixel 10 of the first row and the third column through the turned-on fifth transistor T5. In the second sub-stage t12, the second selection control signal MUX2 is at a low level, the first selection control signal MUX1 and the third selection control signal MUX3 are both at high levels, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned on, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned off, the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned off, the first selection control signal MUX1 controls the tenth transistor T10 and the thirteenth transistor T13 to be turned on, the second selection control signal MUX2 controls the ninth transistor T9 and the twelfth transistor T12 to be turned off, the third selection control signal MUX3 controls the eighth transistor T8 and the eleventh transistor T11 to be turned on, the first data signal Source1 is written into the sub-pixel 10 of the first row and the second column through the turned-on third transistor T3, and the second data signal Source2 is written into the sub-pixel 10 of the first row and the fourth column through the turned-on seventh transistor T7.In the third sub-phase t13, the third selection control signal MUX3 is at a low level, the first selection control signal MUX1 and the second selection control signal MUX2 are both at a high level, the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned on, the first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned off, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned off, the first selection control signal MUX1 controls the tenth transistor T10 and the thirteenth transistor T13 to be turned on, the second selection control signal MUX2 controls the ninth transistor T9 and the twelfth transistor T12 to be turned on, and the third selection control signal MUX3 controls the eighth transistor T8 and the eleventh transistor T11 to be turned off. The first data signal Source1 is written into the sub-pixel 10 of the second row and the first column through the turned-on second transistor T2, and the second data signal Source2 is written into the sub-pixel 10 of the second row and the third column through the turned-on sixth transistor T6. In the fourth sub-phase t14, the first selection control signal MUX1, the second selection control signal MUX2 and the third selection control signal MUX3 are all high level, the first selection control signal MUX1 controls the tenth transistor T10 and the thirteenth transistor T13 to be turned on, the second selection control signal MUX2 controls the ninth transistor T9 and the twelfth transistor T12 to be turned on, and the third selection control signal MUX3 controls the eighth transistor T8 and the eleventh transistor T11 to be turned on. The first selection control signal MUX1 controls the first transistor T1 and the fifth transistor T5 to be turned off, the second selection control signal MUX2 controls the third transistor T3 and the seventh transistor T7 to be turned off, and the third selection control signal MUX3 controls the second transistor T2 and the sixth transistor T6 to be turned off. The first data signal Source1 is written into the sub-pixel 10 of the second row and the second column through the turned-on eighth transistor T8, the ninth transistor T9 and the tenth transistor T10, and the second data signal Source2 is written into the sub-pixel 10 of the second row and the fourth column through the turned-on eleventh transistor T11, the twelfth transistor T12 and the thirteenth transistor T13. In this embodiment, the 12 transistors are used to write data signals to the sub-pixels 10 in the first row and the second row in a time-sharing manner. The operation process of the display panel also includes a second writing stage. The difference between the second writing stage and the first writing stage t1 is that the first control signal Gate1 is at a high level and the second control signal Gate2 is at a low level. In the second writing stage, the first control signal Gate1 controls the sub-pixels 10 in the first row and the sub-pixels 10 in the second row to be turned off, and the second control signal Gate2 controls the sub-pixels 10 in the third row and the sub-pixels 10 in the fourth row to be turned on. The other processes are the same as those in the first writing stage and will not be repeated here, so as to realize the time-sharing writing of data signals to the sub-pixels 10 in the third row and the sub-pixels 10 in the fourth row.

[0072] An embodiment of the present invention further provides a method for driving a display panel, which is used to drive any of the above-mentioned display panels. Figure 8 A schematic diagram of a display panel driving method according to an embodiment of the present invention is provided. Figure 2 and Figure 8 , the driving method of the display panel includes:

[0073] S10: Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels.

[0074] The effective scanning signal is a signal that turns on a sub-pixel. Figure 2 In the display panel shown, the shift registers 14 corresponding to the sub-pixels 10 in the first and second rows first output valid scan signals to control the sub-pixels 10 in the first and second rows to turn on. After the sub-pixels in the first and second rows complete writing of data signals, the shift registers 14 corresponding to the sub-pixels 10 in the third and fourth rows then output valid scan signals to control the sub-pixels 10 in the third and fourth rows to turn on, thereby completing writing of data signals to the sub-pixels 10 in the third and fourth rows.

[0075] S20: When the shift register outputs a valid scan signal, the selection signals connected to the selection units in the selection circuit are controlled to be valid in turn, so as to turn on the selection units in turn and transmit the data signals input from the input end of the selection circuit to the corresponding sub-pixels in a time-sharing manner, wherein, at one moment, only one selection unit in a selection circuit is turned on.

[0076] When the shift register outputs a valid scanning signal, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 of the first row and the third row of the first column, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 of the first row and the third row of the second column, the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 of the second row and the fourth row of the first column, and the selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 of the second row and the fourth row of the second column can be controlled to be turned on in sequence, so as to write data signals to the sub-pixels 10 of the first row and the second row in time division. Among them, the selection unit 1311 corresponding to the sub-pixel 10 of the first row and the third row of the first column and the selection unit 1311 corresponding to the sub-pixel 10 of the first row and the third row of the third column can be turned on at the same time. The selection unit 1311 corresponding to the sub-pixel 10 of the first row and the third row of the second column can be turned on at the same time as the selection unit 1311 corresponding to the sub-pixel 10 of the first row and the third row of the fourth column. The selection unit 1311 connected to the data line 11 corresponding to the sub-pixel 10 in the second row and fourth row of the first column can be turned on simultaneously with the selection unit 1311 corresponding to the sub-pixel 10 in the second row and fourth row of the third column, and the selection unit 1311 corresponding to the sub-pixel 10 in the second row and fourth row of the second column can be turned on simultaneously with the selection unit 1311 corresponding to the sub-pixel 10 in the second row and fourth row of the fourth column. Through the above control, data signals can be written to two sub-pixels in four rows and four columns of sub-pixels 10 at the same time.

[0077] The beneficial effects of this embodiment are the same as those of the display panel, and will not be described in detail here.

[0078] Optionally, the n*n selection units included in different selection circuits are arranged in the same manner; in different selection circuits, the selection units connected to sub-pixels in the same relative position are located in the same row; the display panel includes n*n selection control lines, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, the n*n selection control lines are electrically connected to the control ends of the n*n selection units in each selection circuit in a one-to-one correspondence, and the selection units in the same relative position in different selection circuits are connected to the same selection control lines.

[0079] In view of the structure of the above display panel, this embodiment provides another method for driving the display panel, including:

[0080] Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels.

[0081] When the shift register outputs a valid scan signal, a valid selection signal is sequentially provided to the n*n selection control lines connected to the selection circuit.

[0082] The driving method in this embodiment can drive Figure 3The display panel shown. Figure 3 , when the shift register outputs a valid scanning signal, a valid selection signal is sequentially provided to the n*n selection control lines 15 connected to the selection circuit 131, so as to sequentially control the selection units 1311 in the selection circuit 131 to be turned on in sequence, thereby time-sharingly controlling the sub-pixel 10 to complete the writing of the data signal. Optionally, at the moment when any selection unit 1311 of the selection circuit 131 is turned on, among the n*n selection control lines 15 connected to the selection circuit 131, only the selection signal transmitted on the selection control line 15 connected to the turned-on selection unit 1311 is a first level signal, and the selection signals transmitted on the remaining n*n-1 selection control lines 15 are all second level signals. The first level signal is a valid selection signal to control the corresponding selection unit 1311 to be turned on. The second level signal is an invalid selection signal to control the corresponding selection unit 1311 to be turned off.

[0083] Optionally, the n*n selection units included in different selection circuits are arranged in the same manner; in different selection circuits, the selection units connected to sub-pixels in the same relative position are located in the same row; and n*n-1 selection control lines are also included, which are used to transmit selection control signals, and the selection control signals include selection signals. Among the n*n selection units included in the selection circuit, the control ends of n*n-1 selection units are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the control end of the remaining one selection unit is connected to the n*n-1 selection control lines.

[0084] With respect to the above display panel, this embodiment provides another method for driving the display panel, and the driving method includes:

[0085] Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels.

[0086] When the shift register outputs a valid scanning signal, a valid selection signal is sequentially provided to the n*n-1 selection control lines connected to the selection circuit, so that the selection units connected to one selection control line are sequentially turned on; and an invalid selection signal is provided to the n*n-1 selection control lines, so that the selection units connected to the n*n-1 selection control lines are turned on. The driving method in this embodiment can drive Figure 6 The display panel shown. Figure 6, the selection unit 1311 connected to n*n-1 selection control lines 15 is turned on only when all the connected selection control lines 15 are non-valid selection signals. In other cases, this selection unit 1311 is not turned on. Therefore, valid selection signals are sequentially provided to the n*n-1 selection control lines 15 connected to the selection circuit 131 to control the selection unit 1311 connected to one selection control line 15 to be turned on in sequence. Then, invalid selection signals are provided to the n*n-1 selection control lines 15 to turn on the selection unit 1311 connected to the n*n-1 selection control lines 15, thereby realizing the time-sharing conduction of the selection unit 1311. Optionally, when any selection unit 1311 included in the selection circuit 131 and connected to only one selection control line 15 is turned on, the selection signal transmitted on the selection control line 15 connected to only the turned-on selection unit 1311 is a first level signal, and the selection signals transmitted on the remaining n*n-2 selection control lines 15 are all second level signals; when the selection unit 1311 included in the selection circuit 131 and connected to n*n-1 selection control lines 15 is turned on, the selection signals transmitted on the selection control lines 15 are all second level signals. Figure 6 For the display panel shown, the first level signal is a low level, and the second level signal is a high level. The first level signal is an effective selection signal for the selection unit 1311 connected to only one selection control line 15, and when the signals on n*n-1 selection control lines 15 are all at the second level, it is an effective selection signal for the selection unit 1311 connected to n*n-1 selection control lines 15 at the same time.

[0087] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0088] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A display panel, characterized in that: include: A display area and a non-display area adjacent to the display area, wherein the display area is provided with a plurality of sub-pixels and a plurality of data lines; and the non-display area is provided with a multiplexer and a plurality of shift registers; The plurality of sub-pixels are divided into a plurality of groups, each group of sub-pixels includes n rows of sub-pixels, each shift register is connected to a group of sub-pixels; each column of sub-pixels is connected to n data lines, n≥2; wherein, in a group of sub-pixels, sub-pixels in the same column but different rows are connected to different data lines; The multiplexer comprises a plurality of selection circuits, the input end of the selection circuit is electrically connected to the data signal output end of the driving chip, the selection circuit comprises n*n selection units, in which the first end of the selection unit is electrically connected to the input end of the selection circuit, and the second end of each selection unit is electrically connected to the data line connected to the n columns of sub-pixels in a one-to-one correspondence; the control end of the selection unit is used to access the selection signal, and the control end of different selection units in the same selection circuit accesses different selection signals, so that each selection unit is turned on in time-sharing manner; The display panel also includes n*n-1 selection control lines, which are used to transmit selection control signals, and the selection control signals include selection signals. Among the n*n selection units included in the selection circuit, the control ends of n*n-1 of the selection units are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the control end of the remaining one selection unit is connected to the n*n-1 selection control lines.

2. The display panel according to claim 1, characterized in that: The n*n selection units included in different selection circuits are arranged in the same manner.

3. The display panel according to claim 2, characterized in that: In different selection circuits, the selection units connected to sub-pixels at the same relative position are located in the same row.

4. The display panel according to claim 1, characterized in that: The selection unit connected to one of the selection control lines includes a first control transistor, and the selection unit connected to n*n-1 selection control lines includes n*n-1 second control transistors, the control ends of the n*n-1 second control transistors are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the channel types of the first control transistor and the second control transistor are opposite.

5. The display panel according to claim 1, characterized in that: In the data lines corresponding to the connection of the sub-pixels in a column, the sub-pixels connected to each data line have the same color.

6. The display panel according to claim 1, characterized in that: The colors of the sub-pixels in different groups are arranged in the same manner.

7. The display panel according to any one of claims 1 to 6, characterized in that: It also includes a plurality of gate lines, each of the shift registers is connected to one of the gate lines, and n rows of sub-pixels in a group of sub-pixels are connected to the same gate line; Alternatively, each of the shift registers is connected to n gate lines, each row of the sub-pixels is connected to one gate line, and the n gate lines corresponding to a same group of sub-pixels are connected to the same shift register.

8. A method for driving a display panel, characterized in that: Used to drive the display panel according to any one of claims 1 to 7, the driving method of the display panel comprising: Each shift register sequentially inputs a valid scanning signal to a corresponding group of sub-pixels; When the shift register outputs a valid scanning signal, the selection signals connected to each selection unit in the selection circuit are controlled to be valid in turn, so as to turn on each selection unit in turn and transmit the data signal input from the input end of the selection circuit to the corresponding sub-pixel in a time-sharing manner, wherein, at one moment, only one selection unit in a selection circuit is turned on.

9. The method for driving a display panel according to claim 8, wherein: The n*n selection units included in different selection circuits are arranged in the same manner; in different selection circuits, the selection units connected to sub-pixels at the same relative position are located in the same row; and n*n-1 selection control lines are further included, the selection control lines are used to transmit selection control signals, the selection control signals include selection signals, among the n*n selection units included in the selection circuit, the control ends of n*n-1 selection units are electrically connected to the n*n-1 selection control lines in a one-to-one correspondence, and the control end of the remaining selection unit is connected to the n*n-1 selection control lines; When the shift register outputs a valid scanning signal, the selection signals connected to the selection units in the selection circuit are sequentially controlled to be valid, so as to sequentially turn on the selection units and transmit the data signals inputted from the input end of the selection circuit to the corresponding sub-pixels in a time-sharing manner, including: When the shift register outputs a valid scan signal, a valid selection signal is provided to the n*n-1 selection control lines connected to the selection circuit in sequence, so that the selection units connected to one of the selection control lines are turned on in sequence; and an invalid selection signal is provided to the n*n-1 selection control lines, so that the selection units connected to the n*n-1 selection control lines are turned on.

10. The method for driving a display panel according to claim 9, wherein: When any selection unit connected to only one selection control line included in the selection circuit is turned on, the selection signal transmitted on the selection control line connected to the turned-on selection unit is a first level signal, and the selection signals transmitted on the remaining n*n-2 selection control lines are all second level signals; When the selection units simultaneously connected to n*n-1 selection control lines included in the selection circuit are turned on, the selection signals transmitted on the selection control lines are all second level signals.

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