Driving circuit, driving method and array substrate

Abstract

The invention provides a driving circuit, a driving method and an array substrate. Relates to the technical field of display, and is characterized in that a trigger signal generation sub-circuit is electrically connected with a first frame start signal input line, a second frame start signal input line and a shift register, and is configured to generate an initial light-emitting control signal according to a first frame start signal and a second frame start signal, and transmit the initial light-emitting control signal to the shift register; at least part of the shift registers are configured to generate a target light-emitting control signal according to the trigger signal and transmit the target light-emitting control signal to the pixel circuit; the initial light emission control signal is configured to be used as a trigger signal of the partial shift register; the initial light-emitting control signals are pulse signals with unequal pulse widths. The driving circuit is simple in design, and the requirement of the pixel circuit for pulse signals with unequal pulse widths is met.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a driving circuit and a driving method, and an array substrate. Background Art

[0002] With the development of display technology, the types of display products have gradually increased, and the performance requirements have gradually increased. PWM (Pulse Width Modulation) dimming technology can accurately adjust the brightness of the display panel by adjusting the pulse width, that is, the duty cycle, and has attracted widespread attention in the industry. In related technologies, the equal pulse width PWM model has a simple control logic and is easy to implement and integrate into DIC (display driver chip, Display IC), reducing the complexity and cost of chip design.

[0003] However, mainstream DIC cannot output VGL pulse signals of unequal widths, which limits its flexibility in achieving some special display effects or complex brightness control. Summary of the invention

[0004] This application adopts the following technical solutions:

[0005] An embodiment of the present application provides a driving circuit, the driving circuit comprising a trigger signal generating subcircuit and a plurality of shift registers arranged in cascade;

[0006] The trigger signal generating subcircuit is electrically connected to the first frame start signal input line, the second frame start signal input line and the shift register respectively, and is configured to generate an initial light emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light emitting control signal to the shift register;

[0007] At least part of the shift register is electrically connected to the pixel circuit, and at least part of the shift register is configured to generate a target light emitting control signal according to a trigger signal, and transmit the target light emitting control signal to the pixel circuit;

[0008] Wherein, the initial light-emitting control signal is configured to be used as a trigger signal for part of the shift register; the initial light-emitting control signal is a pulse signal with different pulse widths.

[0009] In the driving circuit provided in some embodiments of the present application, the pulse width of the first frame start signal is fixed, and the second frame start signal is a frame start signal with a constant pulse width and with pulse width modulation information.

[0010] In the driving circuit provided in some embodiments of the present application, the plurality of shift registers include a virtual shift register and n-stage light emitting control shift registers arranged in cascade, where n is a positive integer;

[0011] The virtual shift register is electrically connected to the trigger signal generating subcircuit and the first-stage light-emitting control shift register, respectively, and the n+1-stage light-emitting control shift register is electrically connected to the n-stage light-emitting control shift register, the n+2-stage light-emitting control shift register, and the pixel unit in the n+1-th row, respectively;

[0012] The initial light-emitting control signal is configured to be used as a trigger signal of the virtual shift register, and the virtual shift register is configured to receive the initial light-emitting control signal and process the initial light-emitting control signal to obtain the initial light-emitting control signal with a stable waveform. The initial light-emitting control signal with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register, and the first-level light-emitting control shift register is configured to receive the initial light-emitting control signal with a stable waveform and generate the target light-emitting control signal.

[0013] In the driving circuit provided in some embodiments of the present application, the plurality of shift registers include n-stage light emitting control shift registers arranged in cascade, where n is a positive integer;

[0014] The light emitting control shift register of the first stage is electrically connected to the trigger signal generating sub-circuit, the light emitting control shift register of the second stage and the pixel units of the first row respectively;

[0015] The initial light emitting control signal is configured to be used as a trigger signal of the light emitting control shift register of the first stage, and the light emitting control shift register of the first stage is configured to generate the target light emitting control signal according to the initial light emitting control signal;

[0016] The target light emitting control signal outputted by the light emitting control shift register at the nth stage is used as a trigger signal of the light emitting control shift register at the n+1th stage.

[0017] In the driving circuit provided in some embodiments of the present application, the driving circuit further includes a first clock signal line and a second clock signal line.

[0018] The virtual shift register is electrically connected to the output end of the trigger signal generating sub-circuit, the input end of the first-stage light emitting control shift register, and the first clock signal line respectively;

[0019] The light emitting control shift register of the first stage is electrically connected to the output end of the virtual shift register, the input end of the light emitting control shift register of the second stage, the second clock signal line and the pixel circuit of the first row respectively;

[0020] The second-stage light-emitting control shift register is electrically connected to the output end of the first-stage light-emitting control shift register, the input end of the third-stage light-emitting control shift register, the first clock signal line, and the pixel circuit of the second row respectively;

[0021] The light emitting control shift register of the mth stage is electrically connected to the output end of the light emitting control shift register of the m-1th stage, the input end of the light emitting control shift register of the m+1th stage, the second clock signal line and the pixel circuit of the mth row respectively; m is an odd number, and m>1;

[0022] The m+1th level light control shift register is electrically connected to the output end of the mth level light control shift register, the input end of the m+2th level light control shift register, the first clock signal line and the pixel circuit in the m+1th row.

[0023] In the driving circuit provided in some embodiments of the present application, the trigger signal generating subcircuit includes a first transistor and a second transistor.

[0024] The gate of the first transistor is electrically connected to the first frame start signal input line, the source of the first transistor is electrically connected to the second frame start signal input line, and the drain of the first transistor is electrically connected to the output end of the trigger signal generation subcircuit;

[0025] The gate of the second transistor is electrically connected to the second frame start signal input line, the source of the second transistor is electrically connected to the first frame start signal input line, and the drain of the second transistor is electrically connected to the output end of the trigger signal generating subcircuit.

[0026] In the driving circuit provided in some embodiments of the present application, the first transistor further includes a first stable electrode, and the second transistor further includes a second stable electrode;

[0027] The first stable electrode is electrically connected to the first frame start signal input line, and the second stable electrode is electrically connected to the second frame start signal input line.

[0028] In the driving circuit provided in some embodiments of the present application, the first frame start signal and the second frame start signal are configured not to be high level signals at the same time.

[0029] In the driving circuit provided in some embodiments of the present application, a display frame includes a writing frame and three holding frames.

[0030] In the write frame, in the first time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the second time period, the first frame start signal is a high level signal, and the second frame start signal is a low level signal; in the third time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the fourth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

[0031] In the driving circuit provided in some embodiments of the present application, in the holding frame, in the fifth time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the sixth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

[0032] In the driving circuit provided in some embodiments of the present application, the first frame start signal and the second frame start signal are configured to be provided separately by the driving chip.

[0033] In the driving circuit provided in some embodiments of the present application, the driving circuit also includes a reset shift register, the first frame start signal is configured to be provided by the driving chip, and the reset shift register and the light emitting control shift register share the first frame start signal; the second frame start signal is configured to be provided by the driving chip alone.

[0034] In a second aspect, an embodiment of the present application provides a driving method for driving the driving circuit according to any one of the first aspects, the method comprising:

[0035] Inputting a first frame start signal and a second frame start signal into the trigger generation subcircuit;

[0036] A clock signal is input to the shift register, where the clock signal is a first clock signal or a second clock signal.

[0037] In a third aspect, an embodiment of the present application provides an array substrate, comprising a driving circuit as described in any one of the first aspects, wherein the array substrate comprises:

[0038] substrate, and

[0039] a semiconductor layer, located on one side of the substrate, comprising a semiconductor pattern of a first transistor, a semiconductor pattern of a second transistor, a source and a drain of the first transistor, and a source and a drain of the second transistor in the trigger signal generating subcircuit;

[0040] A first gate layer, located at a side of the semiconductor layer away from the substrate, comprising a gate of the first transistor and a gate of the second transistor;

[0041] The source-drain conductive layer is located at a side of the first gate layer away from the substrate, and includes a first frame start signal input line and a second frame start signal input line.

[0042] In the array substrate provided in some embodiments of the present application, the drain of the first transistor and the drain of the second transistor are shared.

[0043] The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, the source and drain of the first transistor, and the source and drain of the second transistor are an integrated structure.

[0044] In the array substrate provided in some embodiments of the present application, the gate of the first transistor and the gate of the second transistor are centrally symmetrically distributed with the geometric center of the drain of the first transistor as the symmetry point.

[0045] In the array substrate provided in some embodiments of the present application, the first frame start signal input line partially surrounds one side of the first transistor and the second transistor, and the second frame start signal input line partially surrounds the other side of the first transistor and the second transistor.

[0046] In some embodiments of the present application, the array substrate further includes:

[0047] A second gate layer, the second gate layer is located between the first gate layer and the source-drain conductive layer, the second gate layer comprises an initial light emission control signal output line, and the initial light emission control signal output line is configured to output the initial light emission control signal.

[0048] In the array substrate provided in some embodiments of the present application, one of the first frame start signal input line and the second frame start signal input line overlaps with the orthographic projection of the initial light emitting control signal output line on the substrate.

[0049] In some embodiments of the present application, the array substrate further includes:

[0050] A light-shielding conductive layer, the light-shielding conductive layer is located between the substrate and the semiconductor layer, and includes a first stabilizing electrode and a second stabilizing electrode;

[0051] The orthographic projection of the first stabilizing electrode on the substrate covers the gate of the first transistor, and the orthographic projection of the second stabilizing electrode on the substrate covers the gate of the second transistor; the first stabilizing electrode is electrically connected to the first frame start signal input line, and the second stabilizing electrode is electrically connected to the second frame start signal input line.

[0052] The above description is only an overview of the technical solution of the present application. In order to more clearly understand the technical means of the present application, it can be implemented in accordance with the contents of the specification. In order to make the above and other purposes, features and advantages of the present application more obvious and easy to understand, the specific implementation methods of the present application are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0054] Figure 1 A schematic diagram of a pixel circuit structure in a related technology provided in an embodiment of the present application;

[0055] Figure 2 for Figure 1 Timing diagram of

[0056] Figure 3 for Figure 2 Timing diagram for writing frames in one display frame;

[0057] Figure 4 for Figure 2 Timing diagram of holding frames in one display frame;

[0058] Figure 5 A schematic diagram of the structure of a driving circuit provided in an embodiment of the present application;

[0059] Figure 6 and Figure 7 A schematic diagram of the structure of two trigger signal generating sub-circuits provided in an embodiment of the present application;

[0060] Figure 8 for Figure 6 or Figure 7 The timing diagram of the trigger signal generating subcircuit in the writing frame is shown;

[0061] Fig. 9 for Figure 6 or Figure 7 The trigger signal generating subcircuit shown is a timing diagram of the holding frame;

[0062] Fig.10 for Figure 7 The floor plan of the trigger signal generation subcircuit is shown. DETAILED DESCRIPTION

[0063] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0064] In the embodiments of the present application, words such as "first", "second", "third", and "fourth" are used to distinguish between identical or similar items with basically the same functions and effects. This is only for the purpose of clearly describing the technical solutions of the embodiments of the present application and shall not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features.

[0065] In the embodiments of the present application, the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0066] In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiment", "example", "specific example" or "some examples" are intended to indicate that a specific feature, structure, material or characteristic associated with the embodiment or example is included in at least one embodiment or example of the present application. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0067] In the embodiments of the present application, “plurality” means two or more, and “at least one” means one or more, unless otherwise clearly defined.

[0068] The features such as "parallel", "perpendicular", and "same" used in the embodiments of the present application include the features such as "parallel", "perpendicular", and "same" in a strict sense, as well as the cases where "approximately parallel", "approximately perpendicular", "approximately the same", etc. include certain tolerances, taking into account the tolerances related to the measurement of specific quantities (e.g., the limitations of the measurement system), and are expressed as being within the acceptable deviation range for a specific value determined by a person of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within 3% or 5% of the value.

[0069] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0070] The polygon in this specification is not a strict polygon, and may be an approximate triangle, parallelogram, trapezoid, pentagon or hexagon, etc., and there may be some small deformations caused by tolerance.

[0071] In this specification, “electrically connected” and “coupled” include a case where constituent elements are connected together via an element having some kind of electrical function.

[0072] PWM, or Pulse Width Modulation, is a commonly used method for digitally encoding analog signal levels. The PWM mode mainly controls the output signal by controlling the duty cycle of a fixed-frequency pulse signal (the ratio of the high-level duration in one cycle to the total cycle). In a PWM cycle, the longer the high-level time, the greater the duty cycle, the higher the average output voltage (for voltage-type PWM) or average current (for current-type PWM); conversely, the smaller the duty cycle, the lower the average voltage or current. By changing the duty cycle, the brightness can be controlled without changing the data signal (Data) written into the display panel.

[0073] In pixel circuits, oxide TFT (oxide thin film transistor) has emerged in medium and large-sized low-frequency products with its unique performance. Compared with traditional LTPS TFT (low-temperature polycrystalline silicon thin film transistor), oxide TFT has shown significant advantages. From the leakage current characteristics, the leakage current of oxide TFT is significantly smaller. In medium and large-sized low-frequency products, such as some smart TVs and computer monitors, when the screen is in a static display, the high leakage current of LTPS TFT may cause the pixel point charge to leak slowly, thereby affecting the stability and display effect of the picture. However, due to its small leakage current, oxide TFT can maintain the charge state of the pixel point for a long time, so that the picture can still maintain clarity and stability when displaying the same content for a long time, effectively reducing the flicker and noise of the picture. Oxide TFT also has better hysteresis resistance. Hysteresis may cause problems such as signal response delay and unsmooth screen switching in the display panel. In medium and large-sized products, especially in environments with complex application scenarios and possible electromagnetic interference, the hysteresis resistance of oxide TFT is particularly important. It can ensure fast and accurate response to driving signals under different working conditions, achieve fast switching and stable display of pictures, and greatly improve the display quality.

[0074] At present, the main pixel circuit adopts source follower V TH Compensation method, V TH Compensation and data writing are separated. Figure 1This is a schematic diagram of a 6T2C circuit for an example full oxide pixel circuit. Figure 2 yes Figure 1 The circuit diagram shown in the figure corresponds to a 120Hz timing diagram of VRR (Virtual Refresh Rate). VRR is the variable refresh rate (Variable Refresh Rate). This technology is playing an increasingly important role in the display field and is closely related to Oxide TFT technology. Figure 2 In the embodiment, one display frame (1Frame) may include one writing frame and three holding frames. Figure 3 Provided Figure 2 The timing diagram of a write frame in Figure 4 Provided Figure 2 A timing diagram of a hold frame in FIG.

[0075] like Figure 3 As shown, in the write frame, the output waveform of the EM1 signal needs to be a low-level signal VGL in the reset time period ① and the data write time period ③, and a high-level signal VGH in the compensation time period ② between the reset time period ① and the data write time period ③. Figure 4 As shown, in the hold frame, the EM1 signal outputs a VGL signal for a period of time (eg, time period ⑤), and there is no complex output waveform like the write frame.

[0076] For Figure 1 When the pixel circuit shown in the figure is combined with PWM technology, different brightness modes can be obtained by adjusting the pulse width of the EM1 signal. However, since the PWM mode of the current mainstream DIC (the IC that controls the screen Data and GOA signal input) supports the PWM model of equal pulse width, it cannot output Figure 3 The VGL shown in the figure has different widths of EM1. Figure 1 The pixel circuit shown has limited applications.

[0077] Based on this, an embodiment of the present application provides a driving circuit, a driving method, and an array substrate. The driving circuit includes a trigger signal generating subcircuit and a plurality of shift registers arranged in cascade; the trigger signal generating subcircuit is electrically connected to a first frame start signal input line, a second frame start signal input line, and a shift register, respectively, and is configured to generate an initial light-emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light-emitting control signal to the shift register; at least part of the shift register is electrically connected to the pixel circuit, and at least part of the shift register is configured to generate a target light-emitting control signal according to the trigger signal, and transmit the target light-emitting control signal to the pixel circuit; wherein the initial light-emitting control signal is configured to be used as a trigger signal for part of the shift registers; the initial light-emitting control signal is a pulse signal with unequal pulse widths.

[0078] In the present application, by utilizing the existing DIC output signal with equal pulse width and pulse width modulation information (such as the second frame start signal STV2), an initial light control signal is generated in the trigger signal generation subcircuit; the initial light control signal is a pulse signal with different pulse widths. At least part of the shift register generates a target light control signal according to the trigger signal (initial light control signal) and transmits the target light control signal to the pixel circuit, so that the following is obtained: Figure 1 The full oxide pixel circuit shown requires an EM1 driving signal with PWM function.

[0079] The driving circuit, driving method and array substrate provided in the embodiments of the present application will be specifically introduced and described below in conjunction with the accompanying drawings.

[0080] The embodiment of the present application provides a driving circuit, such as Figure 5 As shown, the driving circuit includes a trigger signal generating subcircuit 1 and a plurality of shift registers GOA arranged in cascade;

[0081] The trigger signal generating sub-circuit 1 is electrically connected to the first frame start signal input line STV1, the second frame start signal input line STV2 and the shift register GOA, respectively, and is configured to generate an initial light emitting control signal EM1-STV according to the first frame start signal STV1 and the second frame start signal STV2, and transmit the initial light emitting control signal EM1-STV to the shift register GOA;

[0082] At least part of the shift register GOA is electrically connected to the pixel circuit X, and at least part of the shift register GOA is configured to generate a target light emitting control signal according to the trigger signal, and transmit the target light emitting control signal to the pixel circuit X;

[0083] The initial light-emitting control signal EM1-STV is configured to be used as a trigger signal of a part of the shift register GOA; the initial light-emitting control signal EM1-STV is a pulse signal with different pulse widths.

[0084] Exemplarily, the waveform of the target light emitting control signal is the same as the waveform of the initial light emitting control signal.

[0085] In such a display driving circuit architecture, the design of the trigger signal generating subcircuit 1 is crucial. It works closely with the first frame start signal input line STV1 and the second frame start signal input line STV2 to generate the initial light emitting control signal EM1-STV based on the two start signals. The initial light emitting control signal EM1-STV is a pulse signal with different pulse widths. Its unique pulse characteristics can trigger the subsequent shift register GOA and make the subsequent shift register GOA (n) output the target light emitting control signal EM (y) of the same waveform, where y and n are positive integers.

[0086] In addition, at least part of the shift register GOA is electrically connected to the pixel circuit X, and at least part of the shift register GOA is configured to generate a target light emitting control signal according to the trigger signal, and transmit the target light emitting control signal to the pixel circuit X, including the following two cases:

[0087] The first case: among multiple shift registers GOA arranged in cascade, some shift registers GOA are electrically connected to the pixel circuit X (the virtual shift register described later is not electrically connected to the pixel circuit X), and these shift registers GOA are configured to generate a target light-emitting control signal EM(y) according to a trigger signal, and transmit the target light-emitting control signal EM(y) to the pixel circuit X.

[0088] The second case: all shift registers GOA are electrically connected to the pixel circuit X (without the virtual shift register described later), and each shift register GOA is configured to generate a target light emitting control signal according to the trigger signal and transmit the target light emitting control signal EM(y) to the pixel circuit X.

[0089] Among them, the initial light-emitting control signal EM1-STV is configured to be used as a trigger signal of a partial shift register GOA. It can be understood that the initial light-emitting control signal EM1-STV is used as a trigger signal of a shift register directly electrically connected to the trigger signal generating subcircuit 1.

[0090] In the present application, by utilizing the existing DIC output signal with equal pulse width and pulse width modulation information (such as the second frame start signal STV2), an initial light control signal is generated in the trigger signal generation subcircuit; the initial light control signal is a pulse signal with unequal pulse widths. At least part of the shift register generates a target light control signal according to the trigger signal (initial light control signal) and transmits the target light control signal to the pixel circuit. The waveform of the target light control signal is the same as the waveform of the initial light control signal. In this way, the following is obtained: Figure 1 The EM1 driving signal with PWM function required by the full oxide pixel circuit shown meets the signal requirements of the pixel circuit.

[0091] When applied to display panels equipped with full oxide pixel circuits, this driving circuit has obvious advantages. TH Uniformity enables each pixel to emit light at the same standard when receiving the target light-emitting control signal EM(y) output by the shift register GOA. Because the pulse widths of the initial light-emitting control signals EM1-STV are different, the shift register GOA can flexibly adjust the driving time of the pixel circuit X according to their different pulse widths, thereby more accurately controlling the display state and light-emitting brightness of each pixel. When displaying complex images or high-definition videos, this precise control can avoid the problems of uneven brightness and color deviation caused by driving differences between pixels, give full play to the advantages of Oxide TFT in improving the uniformity of display quality, and present users with a more delicate and realistic picture effect.

[0092] In the driving circuit provided in some embodiments of the present application, Figure 8 and Fig. 9 As shown, the pulse width of the first frame start signal STV1 is fixed, and the second frame start signal STV2 is a frame start signal with a constant pulse width and pulse width modulation information.

[0093] Since the pulse width of the first frame start signal STV1 is fixed, and the second frame start signal STV2 is a frame start signal with equal pulse width and pulse width modulation information, when the trigger signal generation subcircuit 1 receives these two signals, it needs to parse the pulse width modulation information in the second frame start signal. Based on the parsing result, combined with the fixed pulse width of the first frame start signal, the initial light-emitting control signal is generated. Due to the modulation characteristics of the second frame start signal, the pulse width of the initial light-emitting control signal EM1-STV will no longer be a simple fixed value, but a pulse signal with multiple pulse widths of different widths.

[0094] In the driving circuit provided in some embodiments of the present application, Figure 5 As shown, the multiple shift registers GOA include a virtual shift register GOA(0) and n-stage light-emitting control shift registers GOA(n) arranged in cascade, where n is a positive integer;

[0095] The virtual shift register GOA(0) is electrically connected to the trigger signal generating sub-circuit 1 and the first-stage light emitting control shift register GOA(1), respectively; the n+1-th-stage light emitting control shift register GOA(n+1) is electrically connected to the n-th-stage light emitting control shift register GOA(n), the n+2-th-stage light emitting control shift register GOA(n+2) and the n+1-th-row pixel unit X, respectively;

[0096] The initial light-emitting control signal EM1-STV is configured to be used as a trigger signal of the virtual shift register GOA(0), and the virtual shift register GOA(0) is configured to receive the initial light-emitting control signal EM1-STV and process the initial light-emitting control signal EM1-STV to obtain the initial light-emitting control signal EM1-STV with a stable waveform, and the initial light-emitting control signal EM1-STV with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register GOA(1), and the first-level light-emitting control shift register GOA(1) is configured to receive the initial light-emitting control signal EM1-STV with a stable waveform and generate a target light-emitting control signal EM(y), where y is a positive integer.

[0097] Among them, the circuit structure and basic functions of the virtual shift register GOA(0) and the light emitting control shift register GOA(n) are the same, the virtual shift register GOA(0) is directly electrically connected to the trigger signal generating subcircuit 1, and the output end of the virtual shift register GOA(0) is not connected to the pixel circuit in the display area AA. The light emitting control shift register GOA(n) is cascaded, and each level of the light emitting control shift register GOA(n) is connected to a row of pixel circuits and transmits the target light emitting control signal EM(y) to the pixel circuit.

[0098] The light-emitting control shift register GOA(n) is a key component in the display driver system. It is mainly responsible for generating and transmitting light-emitting control signals, thereby regulating the light-emitting process of the pixel circuit.

[0099] The light emission control shift register GOA(n) (generally referred to as EM GOA) described in this application refers to a device for generating and transmitting a light emission control shift register such as Figure 1 The EM1 signal is shown in the shift register. Of course, as Figure 1 As shown in , in actual applications, it may also include a shift register for generating and transmitting an EM2 signal, a shift register for generating and transmitting an RST1 signal, a shift register for generating and transmitting an RST2 signal, and a shift register for generating and transmitting a Gate signal.

[0100] The main function of the virtual shift register GOA(0) is to stabilize the initial light control signal EM1-STV output by the trigger signal generating subcircuit 1, thereby obtaining a target light control signal EM(y) with the same waveform but stable waveform and low noise. This is beneficial for the subsequent light control shift register GOA(n) to transmit a more stable target light control signal EM(y) to the pixel circuit based on it.

[0101] A stable trigger signal is the basis for ensuring high-quality display. Any interference or fluctuation may destroy the synchronization of the signal, resulting in flickering, stripes and other undesirable phenomena on the screen. Since the initial light control signal EM1-STV is used as a trigger signal of the shift register directly electrically connected to the trigger signal generating subcircuit 1, after being stabilized by the virtual shift register GOA(0), the signal output by the virtual shift register GOA(0) can provide a more stable trigger signal to the light control shift register, thereby facilitating improving the quality of the displayed screen.

[0102] In the driving circuit provided in some embodiments of the present application, the plurality of shift registers include n-stage light emitting control shift registers arranged in cascade (but not including the virtual shift register GOA(0)), where n is a positive integer;

[0103] The first-stage light emitting control shift register GOA (1) is electrically connected to the trigger signal generating sub-circuit 1, the second-stage light emitting control shift register GOA (2) and the first-row pixel unit X respectively;

[0104] The initial light emitting control signal EM1-STV is configured to be used as a trigger signal of the first-stage light emitting control shift register EM1-STV, and the first-stage light emitting control shift register GOA(1) is configured to generate a target light emitting control signal EM(y) according to the initial light emitting control signal EM1-STV;

[0105] The target light emission control signal EM(y) output by the n-th stage light emission control shift register GOA(n) is used as a trigger signal of the n+1-th stage light emission control shift register.

[0106] When the driving circuit is applied to a display product with low display quality requirements and insufficient design space for the array substrate, a trigger signal generating subcircuit 1 may be provided in the driving circuit instead of a virtual shift register GOA(0). Figure 1 In the case of the EM1 driving signal with PWM function required by the full oxide pixel circuit shown, the design difficulty and cost can also be reduced.

[0107] In the driving circuit provided in some embodiments of the present application, Figure 5 As shown, the driving circuit further includes a first clock signal line CB and a second clock signal line CK.

[0108] The virtual shift register GOA (0) is electrically connected to the output end of the trigger signal generating sub-circuit 1, the input end (STV) of the first-stage light emitting control shift register GOA (1) and the first clock signal line CB respectively;

[0109] The first-stage light-emitting control shift register GOA (1) is electrically connected to the output end (OUT) of the virtual shift register GOA (0), the input end (STV) of the second-stage light-emitting control shift register GOA (2), the second clock signal line CK and the first-row pixel circuit X respectively;

[0110] The second-stage light-emitting control shift register GOA (2) is electrically connected to the output terminal (OUT) of the first-stage light-emitting control shift register GOA (1), the input terminal (STV) of the third-stage light-emitting control shift register, the first clock signal line CB and the second-row pixel circuit X respectively;

[0111] The m-th level light emitting control shift register GOA(m) is electrically connected to the output terminal (OUT) of the m-1-th level light emitting control shift register GOA(m-1), the input terminal (STV) of the m+1-th level light emitting control shift register GOA(m+1), the second clock signal line CK and the pixel circuit X of the m-th row; m is an odd number, and m>1;

[0112] The m+1th level light emitting control shift register GOA(m+1) is electrically connected to the output end (OUT) of the mth level light emitting control shift register GOA(m), the input end (STV) of the m+2th level light emitting control shift register GOA(m+2), the first clock signal line CB and the m+1th row pixel circuit X respectively.

[0113] It should be noted that in Figure 5 In the figure, only the position of the pixel circuit X is simply indicated by a rectangular frame. In practical applications, each level of the light emitting control shift register transmits the target light emitting control signal EM(y) to the pixel circuits in the same row. Figure 5 In the example, the target light emitting control signal EM(y) is marked as EM1 according to the number of rows. <1> , EM1 <2> , EM1 <3> , EM1 <4> , EM1 <5> , EM1 <6> …

[0114] In addition, the pixel circuit here can be as follows Figure 1 For the pixel circuit shown in , the working principle and driving process of the pixel circuit can be referred to the introduction and description in the relevant technology, which will not be repeated here.

[0115] In the driving circuit provided in some embodiments of the present application, Figure 6 and Figure 7 As shown, the trigger signal generating subcircuit 1 includes a first transistor M1 and a second transistor M2.

[0116] The gate of the first transistor M1 is electrically connected to the first frame start signal input line STV1, the source of the first transistor M1 is electrically connected to the second frame start signal input line STV2, and the drain of the first transistor M1 is electrically connected to the output end (labeled as EM1-STV) of the trigger signal generating sub-circuit 1;

[0117] The gate of the second transistor M2 is electrically connected to the second frame start signal input line STV2, the source of the second transistor M2 is electrically connected to the first frame start signal input line STV1, and the drain of the second transistor M2 is electrically connected to the output end of the trigger signal generating subcircuit 1 (marked as EM1-STV).

[0118] In an exemplary embodiment, the first transistor M1 and the second transistor M2 are both P-type transistors. For a P-type transistor, when a negative voltage is applied to the gate relative to the source, the source and the drain are connected; otherwise, the source and the drain are disconnected.

[0119] In the driving circuit provided in some embodiments of the present application, Figure 7 As shown, the first transistor M1 further includes a first stabilizing electrode BSM1, and the second transistor M2 further includes a second stabilizing electrode BSM2;

[0120] The first stabilizing electrode BSM1 is electrically connected to the first frame start signal input line STV1 , and the second stabilizing electrode BSM2 is electrically connected to the second frame start signal input line STV2 .

[0121] In an exemplary embodiment, the first stabilizing electrode BSM1 and the second stabilizing electrode BSM2 may both be metal materials.

[0122] For example, the first stable electrode BSM1 and the second stable electrode BSM2 can also be called bottom shield metal (BSM). On the one hand, the bottom shield metal can act like a barrier to block the interference of the electromagnetic field generated by other circuits below or the external environment on the transistor; on the other hand, the transistor will generate heat during operation, and excessive heat accumulation will cause the performance of the transistor to deteriorate or even damage it. The bottom shield metal has good thermal conductivity, and it can serve as a heat dissipation channel to quickly conduct the heat generated by the transistor and dissipate it to the surrounding environment; on the other hand, in the substrate where the driving circuit is set, there will be various noise sources, such as noise generated by parasitic capacitance coupling, noise generated by substrate current fluctuation, etc. The bottom shield metal can play an isolation role and reduce the influence of substrate noise on the transistor. When noise current appears in the substrate, the shield metal can guide and shunt it to avoid the noise directly affecting the normal operation of the transistor, thereby improving the signal-to-noise ratio of the transistor and the overall performance of the circuit.

[0123] In the driving circuit provided in some embodiments of the present application, Figure 8 and Fig. 9 According to the timing information in the first frame start signal STV1 and the second frame start signal STV2 are configured not to be high level signals at the same time.

[0124] in, Figure 8 The timing diagram of the first frame start signal STV1 and the second frame start signal STV2 in the writing frame is as follows: Fig. 9 FIG. 1 is a timing diagram of the first frame start signal STV1 and the second frame start signal STV2 in the hold frame.

[0125] Combine the following Figure 6 or Figure 7 The circuit schematic and timing information of the trigger signal generation subcircuit in the figure briefly explain the working principle of the trigger signal generation subcircuit 1:

[0126] 1. When the first frame start signal STV1 is at a low level and the second frame start signal STV2 is at a high level, the first transistor M1 is turned on and the second transistor M2 is turned off, and the output end of the trigger signal generation subcircuit 1 outputs a high-level initial light-emitting control signal EM1-STV;

[0127] 2. When the first frame start signal STV1 is at a high level and the second frame start signal STV2 is at a low level, the first transistor M1 is turned off, the second transistor M2 is turned on, and the output end of the trigger signal generation subcircuit 1 outputs a high level initial light emission control signal EM1-STV;

[0128] 3. When the first frame start signal STV1 is at a low level and the second frame start signal STV2 is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, and the output end of the trigger signal generation subcircuit 1 outputs a low-level initial light-emitting control signal EM1-STV.

[0129] Based on this, in practical applications, since the pulse width of the first frame start signal STV1 is fixed, the second frame start signal STV2 is a frame start signal with equal pulse width and pulse width modulation information, the required initial light control signal EM1-STV can be regulated and generated according to the first frame start signal STV1 and the second frame start signal STV2.

[0130] Figure 8 and Fig. 9 The timing of the initial light emitting control signal EM1-STV generated by the trigger generation subcircuit based on the first frame start signal STV1 and the second frame start signal STV2, wherein: Figure 8 is the timing of the initial light emitting control signal EM1-STV when writing a frame, Fig. 9It is the timing of the initial light emitting control signal EM1-STV when the frame is maintained.

[0131] In the driving circuit provided in some embodiments of the present application, a display frame includes a writing frame and three holding frames.

[0132] like Figure 8 As shown, in the write frame, in the first time period ①, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a low level signal; the initial light emitting control signal EM1-STV is a low level signal;

[0133] In the second time period ②, the first frame start signal STV1 is a high level signal, the second frame start signal STV2 is a low level signal; the initial light emitting control signal EM1-STV is a high level signal;

[0134] In the third time period ③, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a low level signal; the initial light emitting control signal EM1-STV is a low level signal;

[0135] In the fourth time period ④, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a high level signal; and the initial light emitting control signal EM1-STV is a high level signal.

[0136] In the driving circuit provided in some embodiments of the present application, Fig. 9 As shown,

[0137] In the holding frame, in the fifth time period ⑤, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a low level signal, and the initial light emitting control signal EM1-STV is a low level signal;

[0138] In the sixth time period ⑥, the first frame start signal STV1 is a low level signal, the second frame start signal STV2 is a high level signal, and the initial light emitting control signal EM1-STV is a high level signal.

[0139] It should be noted that the specific durations of the above-mentioned first time period ①, second time period ②, third time period ③, fourth time period ④, fifth time period ⑤ and sixth time period ⑥ are not limited here.

[0140] Among them, the durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤ and the sixth time period ⑥ are not completely equal. For example, the durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤ and the sixth time period ⑥ may not be equal; for another example, the durations of the first time period ①, the second time period ②, the third time period ③, the fourth time period ④, the fifth time period ⑤ and the sixth time period ⑥ may be partially equal and partially unequal.

[0141] like Figure 8 As shown, the width of the above-mentioned initial light-emitting control signal EM1-STV in the first time period ① and the third time period ③ is not limited here, and can be designed according to actual needs. Exemplarily, the low-level signal width of the initial light-emitting control signal EM1-STV in the first time period ① can be greater than the low-level signal width of the initial light-emitting control signal EM1-STV in the third time period ③; or, the low-level signal width of the initial light-emitting control signal EM1-STV in the first time period ① can be less than the low-level signal width of the initial light-emitting control signal EM1-STV in the third time period ③. Wherein, when the second frame start signal STV2 is determined, the low-level signal width of the initial light-emitting control signal EM1-STV in the first time period ① and the low-level signal width of the initial light-emitting control signal EM1-STV in the third time period ③ can be adjusted according to the width of the high-level signal of the first frame start signal STV1 in the second time period ② and the position of the rising edge of this high-level signal.

[0142] In addition, the waveform of the target light emitting control signal EM(y) generated by the subsequent light emitting control shift register GOA(n) is the same as that of the target light emitting control signal EM(y) when writing the frame. Figure 8 The waveform of the initial light emitting control signal EM1-STV shown in FIG. 1 is the same as that of the target light emitting control signal EM(y) generated by the subsequent light emitting control shift register GOA(n) when the frame is maintained. Fig. 9 The waveform of the initial light-emitting control signal EM1-STV shown in FIG. 1 is the same; in this way, the target light-emitting control signal EM(y) is input into the pixel circuit of the corresponding row, so that the pixel circuit can also be combined with the PWM mode of the current mainstream DIC (IC that controls the screen Data and GOA signal input), which satisfies the following conditions: Figure 3 The pixel circuit shown in the figure has a demand for EM1 signals of different widths and is also compatible with the current mainstream DIC. This expands the functionality without increasing the cost of DIC, thereby improving the flexibility of the drive circuit application.

[0143] In the driving circuit provided in some embodiments of the present application, the first frame start signal STV1 and the second frame start signal STV2 are configured to be provided separately by the driving chip (DIC). It should be understood that the driving chip (DIC) has multiple transmission channels, one of which is used to send a signal to the first frame start signal STV1 and the second frame start signal STV2. Figure 5 The driving circuit shown in the figure provides a first frame start signal STV1 and a transmission channel for transmitting Figure 5 The driving circuits shown in the two embodiments provide the second frame start signal STV2. In this case, the design of the driving circuit is simple and easy to manufacture.

[0144] In the driving circuit provided in some embodiments of the present application, the driving circuit further includes a reset shift register RSTGOA, a first frame start signal STV1 is configured to be provided by the driving chip (DIC), and the reset shift register RST GOA and the light control shift register EM GOA share the first frame start signal STV1; the second frame start signal STV2 is configured to be provided by the driving chip (DIC) alone. It should be understood that the driving chip (DIC) has multiple transmission channels, one of which simultaneously sends a signal to the driving chip (DIC). Figure 5 The driving circuit shown in the figure and the reset shift register RST GOA driving circuit jointly provide the same first frame start signal STV1, and there is also a transmission channel for transmitting the same signal to the first frame start signal STV1. Figure 5 The driving circuit shown provides the second frame start signal STV2. At this time, since the reset shift register RST GOA and the light control shift register EM GOA share the first frame start signal STV1, the space for designing wiring can be saved, thus improving the utilization of space and facilitating the preparation of small-size products and narrow-frame products.

[0145] The manner in which the first frame start signal STV1 and the second frame start signal STV2 provided by the driving chip (DIC) can be determined according to the requirements of actual products, which can improve the flexibility of circuit design.

[0146] An embodiment of the present application provides a driving method for driving the driving circuit described in any one of the above, the method comprising:

[0147] S1, inputting the first frame start signal STV1 and the second frame start signal STV2 to the trigger generation sub-circuit 1;

[0148] Specifically, when the first frame start signal STV1 is at a low level and the second frame start signal STV2 is at a high level, the first transistor M1 is turned on and the second transistor M2 is turned off, and the output end of the trigger signal generation subcircuit outputs a high level initial light emission control signal EM1-STV;

[0149] When the first frame start signal STV1 is at a high level and the second frame start signal STV2 is at a low level, the first transistor M1 is turned off, the second transistor M2 is turned on, and the output end of the trigger signal generation subcircuit outputs a high level initial light emission control signal EM1-STV;

[0150] When the first frame start signal STV1 is at a low level and the second frame start signal STV2 is at a low level, the first transistor M1 is turned on, the second transistor M2 is turned on, and the output end of the trigger signal generation subcircuit outputs a low-level initial light control signal EM1-STV.

[0151] Based on this, in practical applications, since the pulse width of the first frame start signal STV1 is fixed, the second frame start signal STV2 is a frame start signal with equal pulse width and pulse width modulation information, the required initial light control signal EM1-STV can be regulated and generated according to the first frame start signal STV1 and the second frame start signal STV2.

[0152] S2. Input a clock signal to the shift register GOA. The clock signal is the first clock signal CB or the second clock signal CK.

[0153] At least part of the shift register GOA can generate a target light emitting control signal EM(y) according to the initial light emitting control signal EM1-STV and the clock signal transmitted by the trigger generation sub-circuit 1 and transmit the target light emitting control signal EM(y) to the pixel circuit.

[0154] Specifically, the multiple shift registers GOA include a virtual shift register GOA(0) and n-stage light-emitting control shift registers GOA(n) arranged in cascade, where n is a positive integer;

[0155] The virtual shift register GOA(0) is electrically connected to the trigger signal generating sub-circuit 1 and the first-stage light emitting control shift register GOA(1), respectively; the n+1-th-stage light emitting control shift register GOA(n+1) is electrically connected to the n-th-stage light emitting control shift register GOA(n), the n+2-th-stage light emitting control shift register GOA(n+2) and the n+1-th-row pixel unit X, respectively;

[0156] The initial light-emitting control signal EM1-STV is configured to be used as a trigger signal of the virtual shift register GOA(0), and the virtual shift register GOA(0) is configured to receive the initial light-emitting control signal EM1-STV and process the initial light-emitting control signal EM1-STV to obtain the initial light-emitting control signal EM1-STV with a stable waveform, and the initial light-emitting control signal EM1-STV with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register GOA(1), and the first-level light-emitting control shift register GOA(1) is configured to receive the initial light-emitting control signal EM1-STV with a stable waveform and generate a target light-emitting control signal EM(y), where y is a positive integer.

[0157] An embodiment of the present application provides an array substrate, comprising a driving circuit as described in any one of the above, such as Fig.10 As shown, the array substrate includes:

[0158] substrate, and

[0159] A semiconductor layer (such as LTPS), located on one side of the substrate, including a semiconductor pattern of the first transistor M1, a semiconductor pattern of the second transistor M2, a source and a drain of the first transistor M1, and a source and a drain of the second transistor M2 in the trigger signal generating subcircuit 1;

[0160] A first gate layer Gate1 is located on a side of the semiconductor layer (eg, LTPS) away from the substrate, and includes a gate Gate of the first transistor M1 and a gate Gate of the second transistor M2;

[0161] The source-drain conductive layer SD is located at a side of the first gate layer Gate1 away from the substrate, and includes a first frame start signal input line STV1 and a second frame start signal input line STV2.

[0162] In an exemplary embodiment, the array substrate may be applied to an OLED (Organic Light-Emitting Diode) display panel.

[0163] In an exemplary embodiment, the substrate may be a glass substrate. For example, the thickness of the glass substrate may range from 0.3 mm to 0.7 mm. Specifically, the thickness may be 0.3 mm, 0.4 mm, 0.5 mm or 0.6 mm.

[0164] In an exemplary embodiment, the substrate may be made of one or more materials selected from the group consisting of polyimide, polycarbonate, polyacrylate, polyetherimide, and polyethersulfone, and the present embodiment includes but is not limited thereto.

[0165] The semiconductor layer can be made of silicon material, which can be divided into single crystal silicon, polycrystalline silicon and amorphous silicon according to the crystal form. Polycrystalline silicon is a silicon material composed of many single crystal silicon particles with different orientations. LTPS is a polycrystalline silicon film prepared at a relatively low temperature. Compared with the traditional high temperature process, the low temperature process can use a lower-cost substrate such as glass, and the polycrystalline silicon structure gives the material better electrical properties.

[0166] In addition, if Fig.10 As shown, the semiconductor pattern of the first transistor M1, the semiconductor pattern of the second transistor M2, the source and drain of the first transistor M1, and the source and drain of the second transistor M2 can be an integrated structure. The source and drain of the first transistor M1 and the source and drain of the second transistor M2 can be processed by conductorization to improve their conductivity.

[0167] It should be noted that here Figure 5 The specific circuits of each shift register in the driving circuit shown and the types of transistors included in the circuit are not limited and can be designed differently according to different product types. In addition, since the number of transistors and other components included in the shift register is usually greater than the trigger signal subcircuit, the space occupied by the trigger signal subcircuit in the array substrate is smaller than the space occupied by one shift register.

[0168] The materials of the first gate layer Gate1 and the source-drain conductive layer SD may include metal, for example, the materials of the first gate layer Gate1 and the source-drain conductive layer SD may include at least one of copper (Cu), aluminum (Al), titanium (Ti) or molybdenum (Mo).

[0169] In some embodiments of the present application, in the array substrate provided, Fig.10 As shown, the drain of the first transistor M1 and the drain of the second transistor M2 are shared, and the semiconductor pattern of the first transistor M1, the semiconductor pattern of the second transistor M2, the source and drain of the first transistor M1, and the source and drain of the second transistor M2 are an integrated structure.

[0170] Among them, the drain of the first transistor M1 and the drain of the second transistor M2 are shared, and both are electrically connected to the initial light-emitting control signal output line (marked as EM-STV) through the connecting line SD / LJ set on the source-drain conductive layer SD, and the connecting line SD / LJ is set in the area between the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2, and the connecting line SD / LJ does not overlap with the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2.

[0171] In the present application, by setting the drain of the first transistor M1 and the drain of the second transistor M2 to be shared, on the one hand, the design space can be saved, and on the other hand, the resistance during contact and interconnection can be reduced, thereby improving the stability of signal transmission; and by setting the semiconductor pattern of the first transistor M1, the semiconductor pattern of the second transistor M2, the source and drain of the first transistor M1, and the source and drain of the second transistor M2 to be an integrated structure, the design space of the trigger signal subcircuit is further reduced.

[0172] In some embodiments of the present application, in the array substrate provided, Fig.10 As shown, the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2 are centrally symmetrically distributed with the geometric center of the drain of the first transistor M1 as a symmetric point.

[0173] By setting the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2 to be centrally symmetrically distributed with the geometric center of the drain of the first transistor M1 as a symmetric point, the layout of the first transistor M1 and the second transistor M2 can be made more compact, thereby saving design space.

[0174] In some embodiments of the present application, in the array substrate provided, Fig.10 As shown, the first frame start signal input line STV1 partially surrounds one side of the first transistor M1 and the second transistor M2, and the second frame start signal input line STV2 partially surrounds the other side of the first transistor M1 and the second transistor M2.

[0175] Based on the fact that the gate Gate of the first transistor M1 and the gate Gate of the second transistor M2 are centrally symmetrically distributed as described above, when the first frame start signal input line STV1 and the second frame start signal input line STV2 are subsequently set, the first frame start signal input line STV1 is set close to the side of the gate Gate of the first transistor M1, and the second frame start signal input line STV2 is set close to the side of the gate Gate of the second transistor M2, and the first frame start signal input line STV1 partially surrounds one side of the first transistor M1 and the second transistor M2, and the second frame start signal input line STV2 partially surrounds the other side of the first transistor M1 and the second transistor M2; in this way, while satisfying the first frame start signal input line STV1 and the second frame start signal input line STV2 inputting signals to the trigger generation sub-circuit, the design space is utilized to the maximum extent, so that the space occupied by the trigger generation sub-circuit is as small as possible, leaving sufficient space for the layout of the shift register circuit.

[0176] Among them, "partially surrounded" means that the first frame start signal input line STV1 or the second frame start signal input line STV2 surrounds a part of the peripheral area of ​​the first transistor M1 and the second transistor M2, and this "part" can be half; or, this "part" can be less than half. The line width of the first frame start signal input line STV1 and the second frame start signal input line STV2 is not limited here, and can be determined according to the signal transmission requirements and the conductive properties of the material.

[0177] Exemplarily, when the first frame start signal input line STV1 and the second frame start signal input line STV2 are provided in the same layer and made of the same material, the line widths of the first frame start signal input line STV1 and the second frame start signal input line STV2 may be the same.

[0178] Exemplarily, the line width of the initial light emission control signal output line (labeled as EM-STV) may be set to be smaller than or equal to the line width of the second frame start signal input line STV2.

[0179] In some embodiments of the present application, in the array substrate provided, Fig.10 As shown, the array substrate also includes a second gate layer Gate2, which is located between the first gate layer Gate1 and the source-drain conductive layer SD. The second gate layer Gate2 includes an initial light-emitting control signal output line (marked as EM-STV), and the initial light-emitting control signal output line is configured to output an initial light-emitting control signal.

[0180] The material of the second gate layer Gate2 may be the same as the material of the first gate layer Gate1.

[0181] In the array substrate provided in some embodiments of the present application, one of the first frame start signal input line STV1 and the second frame start signal input line STV2 overlaps with the orthographic projection of the initial light emitting control signal output line (marked as EM-STV) on the substrate 1.

[0182] Exemplarily, the second frame start signal input line STV2 overlaps with the orthographic projection of the initial light emission control signal output line (labeled as EM-STV) on the substrate 1 .

[0183] Among them, when the orthographic projections of the second frame start signal input line STV2 and the initial light-emitting control signal output line (marked as EM-STV) on the substrate 1 overlap, in order to avoid the increased difficulty of the manufacturing process caused by the small distance between the via via2 (used to connect the second frame start signal input line STV2 and the second stable electrode BSM2) on the second frame start signal input line STV2 and the initial light-emitting control signal output line (marked as EM-STV), the length of the second frame start signal input line STV2 can be set to be greater than the length of the first frame start signal input line STV1.

[0184] Exemplarily, the first frame start signal input line STV1 overlaps with the orthographic projection of the initial light emission control signal output line (labeled as EM-STV) on the substrate 1 .

[0185] Of course, when the orthographic projections of the first frame start signal input line STV1 and the initial light-emitting control signal output line (marked as EM-STV) on the substrate 1 overlap, the length of the first frame start signal input line STV1 can also be set to be greater than the length of the second frame start signal input line STV2. The reason is similar to the previous one and will not be repeated here. The via via1 is used to connect the first frame start signal input line STV1 and the first stable electrode BSM1.

[0186] In some embodiments of the present application, in the array substrate provided, Fig.10 As shown, the array substrate also includes a light-shielding conductive layer (e.g., BSM, Bottom shield metal), which is located between the substrate and the semiconductor layer (e.g., LTPS), and includes a first stabilizing electrode BSM1 and a second stabilizing electrode BSM2; wherein, the orthographic projection of the first stabilizing electrode BSM1 on the substrate covers the gate Gate of the first transistor M1, and the orthographic projection of the second stabilizing electrode BSM2 on the substrate covers the gate Gate of the second transistor M2; the first stabilizing electrode BSM1 is electrically connected to the first frame start signal input line STV1, and the second stabilizing electrode BSM2 is electrically connected to the second frame start signal input line STV2.

[0187] Exemplarily, the material of the light-shielding conductive layer may be metal, such as copper (Cu).

[0188] The embodiment of the present application further provides a display panel, comprising the array substrate as described above. The display panel may be an OLED (Organic Light-Emitting Diode) display panel.

[0189] The present application provides a display device, comprising: a display panel as provided in any embodiment; and a driving component connected to the display panel and used to drive the display panel to emit light.

[0190] Those skilled in the art can understand that the display device provided in the present application has the advantages of the display panel of any of the above embodiments.

[0191] The display device provided in the present application can be: a display module, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a car display device, a smart watch, a fitness wristband, a personal digital assistant, or any other product or component with a display function.

[0192] In this application, a transistor refers to a component including at least three terminals: a gate, a drain, and a source. A transistor has a channel region between a drain (drain terminal, a drain region, or a drain) and a source (source terminal, a source region, or a source), and current can flow through the drain, the channel region, and the source. In this application, a channel region refers to a region where current mainly flows.

[0193] In the present application, the transistor may be a thin film transistor or a field effect transistor, etc. The present application is described by taking a thin film transistor as an example.

[0194] The functions of "source" and "drain" may be interchanged when using transistors with opposite polarities or when the direction of current changes during circuit operation. Therefore, in the present application, "source" and "drain" may be interchanged.

[0195] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A driving circuit, wherein: The driving circuit includes a trigger signal generating subcircuit and a plurality of shift registers arranged in cascade connection; The trigger signal generating subcircuit is electrically connected to the first frame start signal input line, the second frame start signal input line and the shift register respectively, and is configured to generate an initial light emitting control signal according to the first frame start signal and the second frame start signal, and transmit the initial light emitting control signal to the shift register; At least part of the shift register is electrically connected to the pixel circuit, and at least part of the shift register is configured to generate a target light emitting control signal according to a trigger signal, and transmit the target light emitting control signal to the pixel circuit; Wherein, the initial light-emitting control signal is configured to be used as a trigger signal for part of the shift register; the initial light-emitting control signal is a pulse signal with different pulse widths.

2. The driving circuit according to claim 1, wherein: The pulse width of the first frame start signal is fixed, and the second frame start signal is a frame start signal with a constant pulse width and pulse width modulation information.

3. The driving circuit according to claim 2, wherein: The multiple shift registers include a virtual shift register and n-stage light emitting control shift registers arranged in cascade, where n is a positive integer; The virtual shift register is electrically connected to the trigger signal generating subcircuit and the first-stage light-emitting control shift register, respectively, and the n+1-stage light-emitting control shift register is electrically connected to the n-stage light-emitting control shift register, the n+2-stage light-emitting control shift register, and the pixel unit in the n+1-th row, respectively; The initial light-emitting control signal is configured to be used as a trigger signal of the virtual shift register, and the virtual shift register is configured to receive the initial light-emitting control signal and process the initial light-emitting control signal to obtain the initial light-emitting control signal with a stable waveform. The initial light-emitting control signal with a stable waveform is configured to be used as a trigger signal of the first-level light-emitting control shift register, and the first-level light-emitting control shift register is configured to receive the initial light-emitting control signal with a stable waveform and generate the target light-emitting control signal.

4. The driving circuit according to claim 2, wherein: The plurality of shift registers include n-stage light emitting control shift registers arranged in cascade, where n is a positive integer; The light emitting control shift register of the first stage is electrically connected to the trigger signal generating sub-circuit, the light emitting control shift register of the second stage and the pixel units of the first row respectively; The initial light emitting control signal is configured to be used as a trigger signal of the light emitting control shift register of the first stage, and the light emitting control shift register of the first stage is configured to generate the target light emitting control signal according to the initial light emitting control signal; The target light emitting control signal outputted by the light emitting control shift register at the nth stage is used as a trigger signal of the light emitting control shift register at the n+1th stage.

5. The driving circuit according to claim 3, wherein: The driving circuit further includes a first clock signal line and a second clock signal line. The virtual shift register is electrically connected to the output end of the trigger signal generating sub-circuit, the input end of the first-stage light emitting control shift register, and the first clock signal line respectively; The light emitting control shift register of the first stage is electrically connected to the output end of the virtual shift register, the input end of the light emitting control shift register of the second stage, the second clock signal line and the pixel circuit of the first row respectively; The second-stage light-emitting control shift register is electrically connected to the output end of the first-stage light-emitting control shift register, the input end of the third-stage light-emitting control shift register, the first clock signal line, and the pixel circuit of the second row respectively; The light emitting control shift register of the mth stage is electrically connected to the output end of the light emitting control shift register of the m-1th stage, the input end of the light emitting control shift register of the m+1th stage, the second clock signal line and the pixel circuit of the mth row respectively; m is an odd number, and m>1; The m+1th level light control shift register is electrically connected to the output end of the mth level light control shift register, the input end of the m+2th level light control shift register, the first clock signal line and the pixel circuit in the m+1th row.

6. The driving circuit according to claim 3 or 4, wherein: The trigger signal generating subcircuit comprises a first transistor and a second transistor, The gate of the first transistor is electrically connected to the first frame start signal input line, the source of the first transistor is electrically connected to the second frame start signal input line, and the drain of the first transistor is electrically connected to the output end of the trigger signal generation subcircuit; The gate of the second transistor is electrically connected to the second frame start signal input line, the source of the second transistor is electrically connected to the first frame start signal input line, and the drain of the second transistor is electrically connected to the output end of the trigger signal generating subcircuit.

7. The driving circuit according to claim 6, wherein: The first transistor further includes a first stabilizing electrode, and the second transistor further includes a second stabilizing electrode; The first stable electrode is electrically connected to the first frame start signal input line, and the second stable electrode is electrically connected to the second frame start signal input line.

8. The driving circuit according to claim 6, wherein: The first frame start signal and the second frame start signal are configured not to be high level signals at the same time.

9. The driving circuit according to claim 8, wherein: A display frame consists of a write frame and three hold frames. In the write frame, in the first time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the second time period, the first frame start signal is a high level signal, and the second frame start signal is a low level signal; in the third time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal; in the fourth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

10. The driving circuit according to claim 9, wherein: In the holding frame, in the fifth time period, the first frame start signal is a low level signal, and the second frame start signal is a low level signal. In the sixth time period, the first frame start signal is a low level signal, and the second frame start signal is a high level signal.

11. The driving circuit according to any one of claims 2 to 10, wherein: The first frame start signal and the second frame start signal are configured to be provided separately by a driving chip.

12. The driving circuit according to any one of claims 2 to 10, wherein: The driving circuit also includes a reset shift register, the first frame start signal is configured to be provided by the driving chip, and the reset shift register and the light emitting control shift register share the first frame start signal; the second frame start signal is configured to be provided by the driving chip alone.

13. A driving method, wherein: Used to drive the driving circuit according to any one of claims 1 to 12, the method comprising: Inputting a first frame start signal and a second frame start signal into the trigger generation subcircuit; A clock signal is input to the shift register, where the clock signal is a first clock signal or a second clock signal.

14. An array substrate, wherein: The driving circuit according to any one of claims 1 to 12, wherein the array substrate comprises: substrate, and a semiconductor layer, located on one side of the substrate, comprising a semiconductor pattern of a first transistor, a semiconductor pattern of a second transistor, a source and a drain of the first transistor, and a source and a drain of the second transistor in the trigger signal generating subcircuit; A first gate layer, located at a side of the semiconductor layer away from the substrate, comprising a gate of the first transistor and a gate of the second transistor; The source-drain conductive layer is located at a side of the first gate layer away from the substrate, and includes a first frame start signal input line and a second frame start signal input line.

15. The array substrate according to claim 14, wherein: The drain of the first transistor and the drain of the second transistor are shared, The semiconductor pattern of the first transistor, the semiconductor pattern of the second transistor, the source and drain of the first transistor, and the source and drain of the second transistor are an integrated structure.

16. The array substrate according to claim 15, wherein: The gate of the first transistor and the gate of the second transistor are centrally symmetrically distributed with the geometric center of the drain of the first transistor as a symmetric point.

17. The array substrate according to claim 16, wherein: The first frame start signal input line partially surrounds one side of the first transistor and the second transistor, and the second frame start signal input line partially surrounds the other side of the first transistor and the second transistor.

18. The array substrate according to claim 16, wherein: The array substrate further includes: A second gate layer, the second gate layer is located between the first gate layer and the source-drain conductive layer, the second gate layer comprises an initial light emission control signal output line, and the initial light emission control signal output line is configured to output the initial light emission control signal.

19. The array substrate according to claim 18, wherein: One of the first frame start signal input line and the second frame start signal input line overlaps with the orthographic projection of the initial light emission control signal output line on the substrate.

20. The array substrate according to claim 19, wherein: The array substrate further includes: A light-shielding conductive layer, the light-shielding conductive layer is located between the substrate and the semiconductor layer, and includes a first stabilizing electrode and a second stabilizing electrode; The orthographic projection of the first stabilizing electrode on the substrate covers the gate of the first transistor, and the orthographic projection of the second stabilizing electrode on the substrate covers the gate of the second transistor; the first stabilizing electrode is electrically connected to the first frame start signal input line, and the second stabilizing electrode is electrically connected to the second frame start signal input line.

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