Training method and system for memory writes

Abstract

A method of training memory write is provided, including: writing a data signal to a memory at a first rate; writing a strobe signal and the data signal to the memory at a second rate, the first rate being less than the second rate; reading the data signal written to the memory at the first rate and the second rate as a first signal and a second signal, respectively; and in response to a difference between the second signal and the first signal, adding at least one delay chain to at least one of the strobe signal and the data signal.

Description

[0001] This application is a divisional application of the patent filed on April 27, 2021, with application number 202110459108.7, entitled "Training Method and System for Writing to Memory". Technical Field

[0002] This application relates to the field of memory, and more particularly to a method and system for memory write training. Background Technology

[0003] With the widespread adoption of the internet, mobile devices such as smartphones, tablets, and portable hard drives have an increasing demand for high-capacity, low-power, and highly reliable non-volatile memory. NAND flash memory, as a high-capacity, fast-read / write, and low-power non-volatile memory, is widely used.

[0004] With the continuous development of flash memory technology, data transfer rates have begun to adopt Double Data Rate (DDR) transmission. DDR uses the rising and falling edges of the data strobe signal (DQS) to sample the data signal (DQ). Therefore, a certain delay adjustment is needed for the sampled data signal and the strobe signal to ensure that the rising and falling edges of the strobe signal are within the effective range of the data signal. Currently, a common method is to add a delay chain to the strobe signal for adjustment. However, the added delay chain is relatively large, resulting in high power consumption. Due to power consumption and internal time limitations, it is difficult to make a delay chain very long. Therefore, there is an urgent need for a solution that can quickly determine the size of the added delay chain while ensuring data read and write accuracy, even with a shorter delay chain. Summary of the Invention

[0005] This application provides a training method for memory writing. By adding a delay chain to at least one of the strobe signal and the data signal, the size of the added delay chain can be quickly determined while ensuring the accuracy of data writing, thereby improving the memory writing speed to a certain extent.

[0006] According to one aspect of this application, a training method for memory writing is provided, which may include: writing a data signal into a memory at a first rate; writing a strobe signal and the data signal into the memory at a second rate, wherein the first rate is less than the second rate; reading the data signals written into the memory at the first rate and the second rate respectively, and using them as a first signal and a second signal respectively; and adding at least one delay chain to at least one of the strobe signal and the data signal in response to a difference between the second signal and the first signal.

[0007] In one implementation, at least one delay chain is selected such that the second signal reads the same as the first signal, and such that the rising and falling edges of the strobe signal are within the high or low level range of the data signal.

[0008] In one embodiment, the step of adding at least one delay chain to at least one of the strobe signal and the data signal may include: adding a delay chain having a predetermined value to the strobe signal; adding a plurality of delay chains having predetermined step size intervals to the data signal respectively; comparing the data signal with the plurality of delay chains added to the first signal respectively to determine a plurality of consecutive adjacent step size intervals such that the data signal with the plurality of delay chains added to the first signal has the same reading result as the first signal; and adding the at least one delay chain to at least one of the strobe signal and the data signal based on the plurality of consecutive adjacent step size intervals.

[0009] In one implementation, the predetermined value may be a default delay value when the strobe signal is written to the memory at a second rate.

[0010] In one implementation, the predetermined value may be the default delay value added to the default delay value when the strobe signal is written to the memory at a second rate.

[0011] In one implementation, the predetermined value may be the default delay value when the strobe signal is written to the memory at a second rate minus the predetermined delay value.

[0012] In one implementation, the number of step intervals can be 2. n There are n, where n is an integer between 3 and 8.

[0013] In one implementation, the size of the at least one delay chain may be the product of the step interval and the time per unit step interval.

[0014] In one embodiment, the step size interval may include a positive step size interval and a negative step size interval.

[0015] In one implementation, the predetermined delay value may be less than 2. n The sum of the absolute values ​​of each delay chain.

[0016] In one implementation, the step of adding at least one delay chain to at least one of the strobe signal and the data signal based on the plurality of consecutive adjacent step intervals may include: determining the size of the at least one delay chain by further selecting any step interval from the plurality of consecutive adjacent step intervals and the product of the time of a unit step interval; and adding the at least one delay chain at the determined position to at least one of the strobe signal and the data signal.

[0017] In one embodiment, the step of adding at least one delay chain to at least one of the strobe signal and the data signal based on the plurality of consecutive adjacent step intervals may include: determining the size of the at least one delay chain by the product of a further selected intermediate step interval from the plurality of consecutive adjacent step intervals and the time of a unit step interval; and adding the determined at least one delay chain to at least one of the strobe signal and the data signal.

[0018] In one embodiment, the step of adding at least one determined delay chain to at least one of the strobe signal and the data signal may include: adding at least one delay chain to the strobe signal in response to the determined at least one delay chain being negative.

[0019] In one embodiment, the step of adding at least one determined delay chain to at least one of the strobe signal and the data signal may include: in response to the determined at least one delay chain being negative, adding the at least one delay chain to the strobe signal and the data signal respectively, wherein the delay chain added to the data signal is smaller than the delay chain added to the strobe signal.

[0020] In one embodiment, the step of adding the determined at least one delay chain to at least one of the strobe signal and the data signal may include: adding the at least one delay chain to the data signal in response to the determined at least one delay chain being a positive value.

[0021] In one embodiment, the step of determining at least one delay chain to be added to at least one of the strobe signal and the data signal may include: in response to the determined at least one delay chain being positive, adding the at least one delay chain to the strobe signal and the data signal respectively, wherein the delay chain added to the data signal is greater than the delay chain added to the strobe signal.

[0022] A system for training memory writes may include a memory and a controller. This system is used to perform the methods described above to train the memory.

[0023] According to the memory writing training method of at least one embodiment of this application, the size of the increased delay chain on at least one of the data signal and / or strobe signal can be quickly confirmed. The increased delay chain is short, resulting in low cost and low power consumption. Accordingly, this reduces the number of comparisons between the data signal written to the memory and the reference data signal to a certain extent, thereby improving efficiency and reducing cost. Attached Figure Description

[0024] Figure 1 This is a schematic diagram of the memory writing training process according to an embodiment of this application;

[0025] Figure 2 This is a further flowchart illustrating step S300 of adding at least one delay chain to at least one of the strobe signal and the data signal according to an embodiment of this application.

[0026] Figure 3 A schematic diagram illustrating ONFI protocol writing training according to an embodiment of this application;

[0027] Figure 4A This is a schematic diagram of data signals and strobe signals during memory writing training according to an embodiment of this application;

[0028] Figure 4B This is a schematic diagram of data signals and strobe signals during memory writing training according to another embodiment of this application;

[0029] Figure 5 This is a schematic diagram showing the results of comparing data signals with multiple delay chains according to an embodiment of this application with a reference data signal; and

[0030] Figure 6 The diagram shown is a schematic of a system for writing to a training memory according to an embodiment of this application. Detailed Implementation

[0031] To better understand this application, various aspects of this application will be described in more detail with reference to the accompanying drawings. It should be understood that these detailed descriptions are merely illustrative of exemplary embodiments of this application and are not intended to limit the scope of this application in any way. Throughout the specification, the same reference numerals refer to the same elements. The expression "and / or" includes any and all combinations of one or more of the associated listed items.

[0032] In the accompanying drawings, the size, dimensions, and shapes of the elements have been slightly adjusted for ease of illustration. The drawings are for illustrative purposes only and are not strictly to scale. As used herein, the terms “approximately,” “about,” and similar terms are used to indicate approximation, not degree, and are intended to illustrate inherent deviations in measured or calculated values ​​that will be recognized by one of ordinary skill in the art. Furthermore, the order in which the steps are described in this application does not necessarily indicate the order in which these steps occur in actual operation, unless otherwise expressly defined or deduced from the context.

[0033] It should also be understood that expressions such as "comprising," "including," "having," "containing," and / or "comprising" are open-ended rather than closed-ended expressions in this specification, indicating the presence of the stated features, elements, and / or components, but not excluding the presence of one or more other features, elements, components, and / or combinations thereof. Furthermore, when expressions such as "at least one of..." appear after a list of listed features, they modify the entire list of features, not just individual elements in the list. Additionally, when describing embodiments of this application, the word "may" is used to mean "one or more embodiments of this application." And the term "exemplary" is intended to refer to examples or illustrations.

[0034] Unless otherwise specified, all terms used herein (including engineering and technical terms) shall have the same meaning as commonly understood by one of ordinary skill in the art to which this application pertains. It should also be understood that, unless expressly stated herein, terms defined in common dictionaries shall be interpreted as having the meaning consistent with their meaning in the context of the relevant art, and not as having an idealized or overly formalized meaning.

[0035] It should be noted that, where there is no conflict, the embodiments and features described in this application can be combined with each other. This application will now be described in detail with reference to the accompanying drawings and embodiments.

[0036] Figure 1 This is a schematic diagram illustrating the memory writing training process according to an embodiment of this application. Figure 1 As shown, the memory writing training method according to this embodiment may include the following steps:

[0037] Step S100: Write the data signal into the memory at a first rate;

[0038] Step S200: Write the strobe signal and the data signal into the memory at a second rate, wherein the first rate is less than the second rate;

[0039] Step S300: Read the data signals written to the memory at the first rate and the second rate respectively, and use them as the first signal and the second signal respectively;

[0040] Step S400: In response to the difference between the second signal and the first signal, at least one delay chain is added to at least one of the strobe signal and the data signal.

[0041] In one implementation, at least one delay chain is selected such that the second signal reads the same result as the first signal, and such that the rising and falling edges of the strobe signal are within the high or low level range of the data signal.

[0042] According to an embodiment of this application, a strobe signal is used to control a write operation to write a data signal into a memory. By adding at least one delay chain to at least one of the strobe signal and the data signal, the added delay chain is small and has low power consumption, which can improve the storage efficiency of the memory to a certain extent.

[0043] The following will refer to Figures 2-5 The following describes specific exemplary implementations of the above steps S100 to S300.

[0044] Step S100

[0045] In step S100, the data signal is first written to the memory at a first rate. For example... Figure 3 The diagram illustrates the ONFI protocol write training according to an embodiment of this application. First, the controller sends a write command to the memory. Upon receiving this command, the memory writes data signals to three ADD CYC address units in a predetermined port at a first rate, which serves as the first signal, i.e., the reference data signal. The first rate is lower than the second rate; for example, the write period at the first rate can be 10ns. The write speed is slow, but the accuracy is high. Therefore, the write data signal at the first rate is used as the first signal, i.e., the reference data signal.

[0046] Step S200

[0047] In this step, the strobe signal and the same data signal used in step S100 above are written to the memory at a second rate. The data signal written to the memory at the second rate is used as the second signal, where the second rate is greater than the first rate. The second rate is called Dual Data Rate (DDR) for data writing. For example, the period for writing at the second rate can be 1 ns or even less. The strobe signal is used to control the write operation to write the data signal to the memory. The strobe signal can be a clock signal. Dual Data Rate (DDR) can transmit the data signal twice within one clock cycle, that is, once on the rising edge and once on the falling edge of the strobe signal. In actual operation, due to the differences in length of PCB traces, package traces, and on-chip traces, the data signal and the strobe signal reading results will be different. This will cause the edge of the strobe signal to not be within the high or low level range of the data signal, or the data signal written to the memory corresponding to the rising and falling edges of the strobe signal will be different from the reading result of the reference data signal, resulting in data transmission errors. Therefore, we need to compare the data signal written at the second rate (i.e., the second signal) with the reference data signal (i.e., the first signal) to determine whether a delay chain needs to be added to the data signal and the strobe signal, and the size of the added delay chain.

[0048] Steps S300 and S400

[0049] Read data signals written to the memory at a first rate and a second rate respectively, which are respectively used as the first signal and the second signal; in response to a difference between the second signal (i.e., the data signal written to the memory at the second rate) and the first signal (i.e., the reference data signal), add at least one delay chain to at least one of the strobe signal and the data signal.

[0050] In one embodiment of this application, after adding at least one delay chain to at least one of the strobe signal and the data signal, the data signal written at the second rate is the same as the reference data signal read result, and the rising edge and falling edge of the strobe signal are within the high level or low level range of the data signal written at the second rate. Figure 2 This is a further flowchart illustrating step S400 of adding at least one delay chain to at least one of the strobe signal and the data signal according to an embodiment of this application. Figure 2 As shown, step S400 includes:

[0051] Step S401: Add a delay chain with a predetermined value to the strobe signal;

[0052] Step S402: Add multiple delay chains with predetermined step intervals to the data signal;

[0053] Step S403: Compare the data signal with multiple delay chains with the first signal to determine multiple consecutive adjacent step intervals that make the data signal with multiple delay chains read the same as the first signal;

[0054] Step S404: Add at least one delay chain to at least one of the strobe signal and the data signal based on multiple consecutive adjacent step size intervals.

[0055] According to the embodiments of this application, by confirming multiple consecutive adjacent step intervals that result in the same reading result of the data signal with multiple delay chains and the reference data signal, the size of the delay chain is further determined. This can reduce the number of comparisons between the data signal with multiple delay chains and the reference data signal, thereby reducing the memory write training time to a certain extent and improving the memory efficiency.

[0056] Figure 4A This is a schematic diagram of data signals and strobe signals during memory writing training according to an embodiment of this application. Figure 4B This is a schematic diagram of data signals and strobe signals during memory writing training according to another embodiment of this application. Figure 4AAs shown, during memory write training, the strobe signal lags behind the data signal. In this case, at least one delay chain can be added on the rising or falling edge of the data signal. The strobe signal can be left unadded or have a small delay chain added, ensuring that the rising and falling edges of the strobe signal are within the high or low level range of the data signal, and that the data signal written at the rising and falling edges of the strobe signal is identical to the reference data signal read result. Optionally, the rising and falling edges of the strobe signal can be in the middle of the high or low level range of the data signal. For example... Figure 4B As shown, during the memory write training process, the strobe signal takes precedence over the data signal. At this time, at least one delay chain can be added to the rising or falling edge of the strobe signal, while the data signal may not have a delay chain added, or a smaller delay chain may be added, so that the rising and falling edges of the strobe signal are within the high or low level range of the data signal, and that the data signal written at the rising and falling edges of the strobe signal is identical to the reference data signal read result. Preferably, the rising and falling edges of the strobe signal are in the middle of the high or low level range of the data signal.

[0057] Figure 5 This is a schematic diagram showing the results of comparing data signals with multiple delay chains added according to an embodiment of this application with a reference data signal. Figure 5 As shown, the shaded areas represent data signals that differ from the reference data signals, while the blank areas represent data signals that are the same as the reference data signals. Select 2. n There are 16 step intervals, where n is an integer between 3 and 8. In this embodiment, n=4 is taken as an example, that is, 16 step intervals are selected, including step intervals in the positive direction and step intervals in the negative direction. Each interval represents the same delay time, and -7 to +8 are used as examples. The size of the delay chain is the product of the step interval and the time of the unit step interval. Taking each step interval as 5ps as an example, -7 means that the data signal should be advanced by 35ps, or the corresponding strobe signal should be delayed by 35ps; +8 means that the data signal should be delayed by 40ps, or the corresponding strobe signal should be advanced by 40ps.

[0058] The data signals after adding delay chains at step intervals can be represented as: DQ[-7], DQ[-6], DQ[-5], DQ[-4], DQ[-3], DQ[-2], DQ[-1], DQ[0], DQ[1], DQ[2], DQ[3], DQ[4], DQ[5], DQ[6], DQ[7], DQ[8]. The data signals DQ[-7]-DQ[8] are compared with the reference data signal to confirm whether the reading results are the same. It is also necessary to confirm whether the rising and falling edges of the strobe signal are within the high or low level range of the data signal to avoid data transmission errors. Through 16 comparisons of the data signal and the reference data signal, the comparison results may be: Figure 5 Any of the modes in the list.

[0059] The comparison results of data signals with multiple delay chains added at step intervals and then compared with reference data signals can be divided into nine modes: Mode 3011, Mode 3012, Mode 3021, Mode 3022, Mode 3031, Mode 3032, Mode 3041, Mode 3042, and Mode 3051. It is worth noting that... Figure 5 The nine modes shown are one of the possible results of comparing the data signal with the reference data signal. They are merely illustrative examples, and those skilled in the art will understand that there are other possible results when comparing the data signal with the reference data signal.

[0060] In this embodiment, a delay chain with a predetermined value is added to the strobe signal, where the predetermined value is the default delay value when the strobe signal is written to memory at a second rate. Multiple delay chains are added to the data signal at step intervals, and the step interval is selected such that the edge of the strobe signal is within the high or low level range of the data signal, and the data signal read result is the same as that of the reference data signal. The selected consecutive step intervals constitute the adjustable range of the data signal. That is, there are multiple delay chains of a certain length; after adding them to the data signal, the data signal read result can be the same as that of the reference data signal.

[0061] by Figure 5The following is an explanation of the comparison results of nine modes of the data signal and the reference data signal. Mode 3011 compares the data signals DQ[-7]-DQ[8] with the reference data signal respectively. The reading results of both are the same. The adjustable range of the data signal is the step size interval -7-8. That is, there are at least 16 delay chains of different sizes added to the data signal and the reading result is the same as the reference data signal. Compared with mode 3011, mode 3012 has some data signals that are different from the reading result of the reference data signal, such as DQ[-4], DQ[-1], DQ[2], and DQ[5]. The step size intervals corresponding to the reading results of the data signal after adding delay chains and the reading results of the reference data signal are alternated. Therefore, the adjustable range of the data signal cannot be confirmed. In mode 3021, there is a continuous step size interval in the middle region of the entire step size range, that is, -2-5, which makes the reading result of the data signal the same as the reference data signal. Therefore, the step size interval of -2-5 can be used as the adjustable range of the data signal. Compared with mode 3021, mode 3022 has some step intervals in the middle region, which makes the data signal and the reference data signal read the same. However, there are also step intervals in the middle region, such as DQ[0], which is different from the reference data signal. Therefore, the adjustable range of the data signal cannot be confirmed. Modes 3031 and 3032 have the same reading result as the reference data signal in DQ[-7]-DQ[-5]. This region can be regarded as the adjustable range of the data signal. Mode 3041 has the same reading result as the reference data signal in DQ[3]-DQ[8]. Mode 3042 has step intervals in this interval that make the reading result of the data signal and the reference data signal different. Therefore, mode 3041 has an adjustable range of the data signal, but mode 3042 cannot confirm the adjustable range of the data signal. Mode 3051 compares the data signal DQ[-7]-DQ[8] with the reference data signal respectively. The reading results of the two are different. Therefore, there is no adjustable range of the data signal in the entire step interval of -7-8.

[0062] In this embodiment, the predetermined value is the default delay value when the strobe signal is written to memory at the second rate. If there is no delay chain that can be added to the data signal to make it the same as the reference data signal read result, optionally, the predetermined value can be the default delay value when the strobe signal is written to memory at the second rate plus the predetermined delay value. Alternatively, the predetermined value can be the default delay value when the strobe signal is written to memory at the second rate minus the predetermined delay value. The predetermined delay value is less than the unit step interval and 2. n The product of these two values ​​means that, taking each step interval as 5 ps, and 16 step intervals as an example, the predetermined delay value is less than 80 ps. The magnitude of the predetermined delay value can be simulated and calculated based on the adjustable range of the data signal and the degree of similarity between the data signal and the data reference signal, which will not be elaborated on here.

[0063] According to an embodiment of this application, by adding multiple delay chains to a data signal at step intervals and comparing the results with a reference data signal, the existence of delay chains in the data signal can be quickly confirmed, ensuring that the data signal reads the same as the reference data signal. If a delay chain exists, its size can be calculated based on the comparison result, adding it to at least one of the data signal and the strobe signal. In one embodiment of this application, at least one delay chain is determined based on selected consecutive adjacent step intervals and added to at least one of the strobe signal and the data signal. By reducing the number of comparisons, the size of the delay chain can be quickly confirmed, saving memory training time to some extent and improving efficiency.

[0064] Specifically, the product of any selected consecutive adjacent step intervals and the time of a unit step interval is chosen as the size of at least one delay chain, and this determined delay chain is added to at least one of the gating signal and the data signal. This reduces the number of comparisons between the data signal and the reference data signal to some extent, improving the efficiency of memory write training. Furthermore, smaller delay chains can be preferentially selected, which reduces system power consumption and better meets the internal time constraints of the memory system.

[0065] In another embodiment of this application, at least one delay chain is determined based on selected consecutive adjacent step intervals and added to at least one of the gating signal and the data signal. Specifically, the product of the middle step interval and the time of a unit step interval is further selected from the selected consecutive adjacent step intervals to determine the size of at least one delay chain, and the determined at least one delay chain is added to at least one of the gating signal and the data signal. By selecting the delay chain corresponding to the middle step interval as the delay chain for the data signal, the error range is increased to a certain extent, the data signal writing accuracy is improved to a certain extent, and the robustness of the system is enhanced.

[0066] Combination Figure 4A , Figure 4B and Figure 5In one embodiment of this application, in response to the determination that at least one delay chain is negative, i.e., the strobe signal takes precedence over the data signal, as an option, at least one delay chain is added to the strobe signal, such that the data signal written at the second rate has the same read result as the reference data signal, and the rising and falling edges of the strobe signal are within the high or low level range of the data signal written at the second rate. Alternatively, the delay chain added to the data signal is smaller than the delay chain added to the strobe signal, such that the data signal written at the second rate has the same read result as the reference data signal, and the rising and falling edges of the strobe signal are within the high or low level range of the data signal written at the second rate. In another embodiment of this application, in response to the determination that at least one delay chain is positive, i.e., the strobe signal lags behind the data signal, as an option, at least one delay chain is added to the data signal, such that the data signal written at the second rate has the same read result as the reference data signal, and the rising and falling edges of the strobe signal are within the high or low level range of the data signal written at the second rate. Alternatively, the delay chain added to the data signal is greater than the delay chain added to the strobe signal, so that the data signal written at the second rate is the same as the reference data signal read result, and the rising and falling edges of the strobe signal are within the high or low level range of the data signal written at the second rate.

[0067] In one embodiment of this application, a delay chain with a default delay value is added to the strobe signal, and multiple delay chains are added to the data signal, each being compared with a reference data signal to obtain a result, thus completing a set of comparisons. If the delay chain with a predetermined delay value added to the strobe signal changes, i.e., it changes to a delay chain with the default delay value plus the predetermined delay value or a delay chain with the default delay value minus the predetermined delay value, a virtual period exists on the strobe signal and the data signal before the next set of comparisons. This virtual period is used to adjust the time provided by the delay chains added to the strobe signal and the data signal in the next set of comparisons. Optionally, the size of the virtual period is 32 bytes.

[0068] Figure 6 The diagram shown is a schematic representation of a system for writing to a training memory according to an embodiment of this application. Figure 6 As shown, the system for writing to the training memory according to this embodiment may include a controller 10 and a memory 20.

[0069] The controller 10 can write data signals to and read data signals stored in the memory 20 according to requests from external sources or the host. The controller 10 can send commands, addresses, and / or control signals to the memory 20 to access the memory 20. The controller 10 can send strobe signals and data signals to the memory 20 via signal lines.

[0070] The controller 10 may also include a data writing module 101, a data sampling module 102, a signal determination module 103, and a delay module 104. The memory 20 includes a data storage cell array 201 formed by a memory cell array.

[0071] In response to a request received from an external source or host to write a data signal into memory 20, data writing module 101 sends an instruction to memory 20 to write the generated signal into the memory's data storage cell array 201 at a first rate as a first signal. Then, data writing module 101 writes the same data signal into the memory's data storage cell array 201 at a second rate as a second signal, wherein the first rate is less than the second rate.

[0072] The data sampling module 102 is configured to send a strobe signal to the memory 20 during data writing to trigger a data write operation to the data storage unit array 201. The rising and falling edges of the sent strobe signal are within the high or low level range of the data signal written to the memory at the second rate.

[0073] The signal determination module 103 determines whether the first signal and the second signal are the same. If they are the same, it means that the data signal written to the memory at the second rate is correct, and the write operation to the memory 20 is accurate, without the need for training to correct it. If they are different, it means that the second signal is written incorrectly. The signal determination module 103 determines that the operation to the memory 20 fails, and then sends an instruction to the delay module 104. The delay module 104 generates at least one delay chain and applies the generated at least one delay chain to at least one of the corresponding strobe signal and data signal, so that the second signal reads the same result as the first signal, and the rising edge and falling edge of the strobe signal are within the high or low level range of the data signal written at the second rate.

[0074] In one embodiment, the controller 10 may issue a computer instruction to the memory 20 to input a delay chain strobe signal having a predetermined value. The predetermined value is a default delay value when the strobe signal is written to the memory at a second rate. Alternatively, the predetermined value may be the default delay value when the strobe signal is written to the memory at a second rate plus the predetermined delay value. Another alternative is that the predetermined value may be the default delay value when the strobe signal is written to the memory at a second rate minus the predetermined delay value.

[0075] In one implementation, the number of step intervals is 2. n There are n values, where n is an integer between 3 and 8. Furthermore, the step size interval includes both positive and negative step size intervals.

[0076] In one implementation, the controller 10 further selects the product of any step interval and the time of a unit step interval from the selected consecutive adjacent step intervals as the size of at least one delay chain. Alternatively, the controller 10 further selects the product of the middle step interval from the selected consecutive adjacent step intervals and the time of a unit step interval as the size of at least one delay chain.

[0077] The specific embodiments described above further illustrate the purpose, technical solution, and beneficial effects of the present invention. It should be understood that the above descriptions are merely specific embodiments of the present invention and are not intended to limit the invention. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A training method of memory write, characterized by, The method comprises: in response to a difference between a first signal and a second signal read, increasing a delay chain of a selection signal by a different predetermined value to obtain a plurality of delayed selection signals; increasing a data signal by a plurality of delay chains with predetermined step intervals respectively to obtain a plurality of delayed data signals; the first signal is the data signal written to the memory at a first rate; the second signal is the data signal written to the memory based on the selection signal at a second rate; the first rate is less than the second rate; based on each of the delayed selection signals, respectively comparing each of the delayed data signals with the first signal to determine a plurality of continuous adjacent predetermined step intervals in which the delayed data signal read is the same as the first signal; based on the plurality of continuous adjacent predetermined step intervals, determining at least one delay chain to be added to the selection signal and / or the data signal; wherein the size of the at least one delay chain is a product of the number of predetermined step intervals included in the at least one delay chain and a unit step interval time.

2. The method of claim 1, wherein, The number of said predetermined step intervals is 2 n wherein n is an integer between 3 and 8.

3. The method of claim 1, wherein, The predetermined step intervals include positive direction step intervals and negative direction step intervals; wherein the delayed data signal obtained based on the positive direction step interval is delayed by a certain time with respect to the data signal; the delayed data signal obtained based on the negative direction step interval is advanced by a certain time with respect to the data signal.

4. The method of claim 1, wherein, The determining at least one delay chain to be added to the selection signal and / or the data signal based on the plurality of continuous adjacent predetermined step intervals comprises: from the plurality of continuous adjacent predetermined step intervals, selecting a product of any step interval and a unit step interval time to determine the size of the at least one delay chain, wherein the any step interval is at least one of the plurality of continuous adjacent predetermined step intervals; adding the at least one delay chain to the selection signal and / or the data signal.

5. The method of claim 1, wherein, The determining at least one delay chain to be added to the selection signal and / or the data signal based on the plurality of continuous adjacent predetermined step intervals comprises: from the plurality of continuous adjacent predetermined step intervals, selecting a product of a middle predetermined step interval and a unit step interval time to determine the size of the at least one delay chain; adding the at least one delay chain to the selection signal and / or the data signal.

6. The method according to claim 4 or 5, characterized in that, The adding the at least one delay chain to the selection signal and / or the data signal comprises: in response to the determined at least one delay chain being negative, adding the at least one delay chain to the selection signal.

7. The method according to claim 4 or 5, characterized in that, The at least one delay chain comprises a first delay chain and a second delay chain, and the adding the at least one delay chain to the selection signal and / or the data signal comprises: in response to the at least one delay chain being negative, adding the first delay chain to the selection signal and adding the second delay chain to the data signal, wherein the size of the second delay chain is smaller than the size of the first delay chain.

8. The method according to claim 4 or 5, characterized in that, The adding of the at least one delay chain to the gate signal and / or the data signal comprises: adding the at least one delay chain to the data signal in response to the determined at least one delay chain being positive.

9. The method of claim 4 or 5, wherein, The at least one delay chain comprises a first delay chain and a second delay chain, and the adding of the at least one delay chain to the gate signal and / or the data signal comprises: adding the first delay chain to the gate signal and adding the second delay chain to the data signal in response to the at least one delay chain being positive, wherein a size of the second delay chain is greater than a size of the first delay chain.

10. A storage system, characterized by comprises: one or more memories, and a controller coupled to the memories and configured to control the memories; The controller comprises a data writing module, a signal determining module and a delay module; wherein The data writing module is configured to, in response to a difference between a first signal and a second signal read, add a delay chain with different predetermined values to a gate signal to obtain a plurality of delayed gate signals, and add a plurality of delay chains with predetermined step intervals to a data signal respectively to obtain a plurality of delayed data signals; the first signal is the data signal written to the memories at a first rate; the second signal is the data signal written to the memories based on the gate signal at a second rate; the first rate is less than the second rate; The signal determining module is configured to, based on each of the delayed gate signals, compare each of the delayed data signals with the first signal respectively to determine a plurality of continuous adjacent predetermined step intervals that make the delayed data signals read the same as the first signal; The delay module is configured to determine at least one delay chain to be added to the gate signal and / or the data signal based on the plurality of continuous adjacent predetermined step intervals, wherein a size of the at least one delay chain is a product of a number of predetermined step intervals included in the at least one delay chain and a time of a unit step interval.

11. The storage system of claim 10, wherein, The delay module is further configured to select a product of a random step interval and a time of a unit step interval to be the size of the at least one delay chain from the plurality of continuous adjacent predetermined step intervals, wherein the random step interval is at least one of the plurality of continuous adjacent predetermined step intervals; The adding of the at least one delay chain to the gate signal and / or the data signal.

12. The storage system of claim 10, wherein, The delay module is further configured to select a product of a predetermined step interval located in the middle and a time of a unit step interval to be the size of the at least one delay chain from the plurality of continuous adjacent predetermined step intervals; The adding of the at least one delay chain to the gate signal and / or the data signal.

13. The storage system of claim 11 or 12, wherein, The delay module is further configured to add the at least one delay chain to the gate signal in response to the determined at least one delay chain being negative.

14. The storage system of claim 11 or 12, wherein, The at least one delay chain includes a first delay chain and a second delay chain, and the delay module is further configured to, in response to the at least one delay chain being negative, add the first delay chain to the gate signal and add the second delay chain to the data signal, wherein a size of the second delay chain is smaller than a size of the first delay chain.

15. The storage system of claim 11 or 12, wherein, The delay module is further configured to, in response to the at least one delay chain being positive, add the at least one delay chain to the data signal.

16. The storage system of claim 11 or 12, wherein, The at least one delay chain includes a first delay chain and a second delay chain, and the delay module is further configured to, in response to the at least one delay chain being positive, add the first delay chain to the gate signal and add the second delay chain to the data signal, wherein a size of the second delay chain is greater than a size of the first delay chain.

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