Modeling method of mos transistor mismatch model

Abstract

The application provides a modeling method of a MOS transistor mismatch model, comprising the following steps: S1, testing mismatch values of a pair of MOS transistors; S2, establishing a relationship between the mismatch values and channel lengths and channel widths of the MOS transistors; S3, repeating steps S1-S2 to obtain relationships between mismatch values of multiple pairs of MOS transistors and channel lengths and channel widths of the MOS transistors; and S4, fitting the actual mismatch values and the relationships of each pair of MOS transistors to obtain a MOS transistor mismatch model. Compared with the prior art, the modeling method of the MOS transistor mismatch model can obtain a MOS transistor mismatch model with higher precision.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a modeling method for a MOS transistor mismatch model. Background Technology

[0002] SPICE is a powerful general-purpose analog circuit simulator, with decades of history since its first version was released in 1972. This program is primarily used in integrated circuit circuit analysis. SPICE's netlist format has become the standard industry standard for describing analog and transistor-level circuits, mainly used for the design and simulation of analog circuits, mixed-signal circuits, power supply circuits, and other electronic systems in IC design. A SPICE model consists of two parts: model equations and model parameters. Because it provides model equations, the SPICE model can be tightly coupled with the simulator's algorithm, resulting in better analysis efficiency and results. SPICE modeling engineers rely on device theory and experience to extract model parameters for use by the SPICE simulation program. Currently, commonly used SPICE models include the BSIM series, PSP, or empirical models (macro models). The analysis accuracy of a SPICE model mainly depends on the source of the model parameters (i.e., the accuracy of the data) and the applicability of the model equations.

[0003] A mature CMOS process technology platform typically includes SPICE modeling of basic components such as MOSFETs, diodes, transistors, MOSFET capacitors, MIM capacitors, resistors, and variable capacitors. Subsequent PDK (Process Design Kit) development, IP libraries, various standard cell libraries, and even customer-customized chip design development are all based on SPICE model libraries. MOS transistor mismatch is a phenomenon in certain manufacturing processes where random fluctuations cause physical quantities of identical MOS transistors to remain unchanged over time. The degree of device mismatch under a specific process determines the final design accuracy and yield of the circuit. Circuit designers need accurate MOS transistor mismatch models to constrain circuit optimization design, and layout designers need corresponding design rules to reduce chip mismatch. Especially as CMOS process device dimensions enter the deep submicron range, device mismatch becomes increasingly severe with decreasing size, limiting the performance of RF / analog integrated circuits. Of course, digital circuits are not entirely unaffected by device mismatch; in the design of large-scale memory, the impact of transistor mismatch on the clock signal of the sub-memory cell must be considered.

[0004] In the existing SPICE process for extracting mismatch models, the extraction method involves fitting an approximate slope using model parameters based on the slope of the test data. This ensures that the extracted mismatch model matches the slope of the test data. However, when the test data is widely distributed, it cannot guarantee consistency between each test point and the simulation data. For example... Figure 1 The x-axis represents 1 / sqrt(W*L), where W is the channel width and L is the channel length. The y-axis represents the threshold voltage mismatch. Data represents the test data of the device's threshold voltage, and model represents the simulation data of the device's threshold voltage. Line 1 is the data line fitted to the simulation data, and line 2 is the data line fitted to the test data. It can be seen that the test data is quite scattered, and the test data and simulation data for some devices differ significantly, indicating that the simulation data generated by existing simulation methods is not very accurate. Figure 2 In the diagram, the horizontal axis is 1 / sqrt(W*L), where W is the channel width and L is the channel length, and the vertical axis is the saturation current mismatch value. "Data" represents the test data of the device's saturation current, and "model" represents the simulated data of the device's saturation current. Line 1 is the data line fitted to the simulated data, and line 2 is the data line fitted to the test data. It can be seen that the test data is quite scattered, and the test data and simulated data for some devices differ significantly, indicating that the simulation data generated by existing technology is not very accurate. Therefore, the accuracy of the mismatch model for MOS transistors formed using existing technology is low. Summary of the Invention

[0005] The purpose of this invention is to provide a modeling method for MOS transistor mismatch models, which can form a MOS transistor mismatch model with high accuracy.

[0006] To achieve the above objectives, the present invention provides a modeling method for a MOS transistor mismatch model, comprising:

[0007] Step S1: Test the mismatch value of a pair of MOS transistors;

[0008] Step S2: Establish the relationship between the mismatch value and the channel length and channel width of the MOS transistor;

[0009] Step S3: Repeat steps S1 to S2 to obtain the relationship between the mismatch values ​​of multiple pairs of MOS transistors and the channel length and channel width of the MOS transistors; and

[0010] Step S4: Fit the actual mismatch value and relationship obtained from the test of each pair of MOS transistors to obtain the mismatch model of the MOS transistor.

[0011] Optionally, in the modeling method for the MOS transistor mismatch model, all the MOS transistors have the same channel length.

[0012] Optionally, in the modeling method for the MOS transistor mismatch model, all the MOS transistors have the same channel width.

[0013] Optionally, in the modeling method of the MOS transistor mismatch model, the mismatch value includes: threshold voltage mismatch value and saturation current mismatch value.

[0014] Optionally, in the modeling method for the MOS transistor mismatch model, the method for obtaining the threshold voltage mismatch value includes:

[0015] Sigma_Vtlin=Vtlin1-Vtlin2;

[0016] Where Sigma_Vtlin is the threshold voltage mismatch value, Vtlin1 is the threshold voltage of one MOS transistor in each pair of MOS transistors, and Vtlin2 is the threshold voltage of the other MOS transistor in each pair of MOS transistors.

[0017] Optionally, in the modeling method for the MOS transistor mismatch model, the method for obtaining the saturation current mismatch value includes:

[0018] Sigma_Idsat=(Idsat1-Idsat2) / (Idsat1+Idsat2) / 2;

[0019] Where Sigma_Idsat is the saturation current mismatch value, Idsat1 is the saturation current of one MOS transistor in each pair of MOS transistors, and Idsat2 is the saturation current of the other MOS transistor in each pair of MOS transistors.

[0020] Optionally, in the modeling method for the MOS transistor mismatch model, the method for obtaining the threshold voltage includes:

[0021] When Ids = Icon * (W / L) and Vds = Vdlin, the voltage between the gate and the source is the threshold voltage; where Icon is the inherent current value of the MOS transistor, Vdlin is the inherent linear region voltage of the MOS transistor, and Vdd is the operating voltage of the MOS transistor.

[0022] Optionally, in the modeling method for the MOS transistor mismatch model, the method for obtaining the saturation current includes:

[0023] When Vds = Vdd, Vgs = Vdd, and Vbs = 0, the current between the drain and source is the saturation current.

[0024] Where Vds is the voltage between the drain and the source, Vgs is the voltage between the gate and the source, Vbs is the voltage between the substrate and the source, and Vdd is the operating voltage of the MOS transistor.

[0025] Optionally, in the modeling method for the MOS transistor mismatch model, the mismatch model of the MOS transistor is:

[0026] mismatch = A + B / W + C / L + D / (W*L) + E / sqrt(W*L); where mismatch is the mismatch value, W is the channel width, L is the channel length, and A, B, C, D, and E are the coefficients of the mismatch model.

[0027] Optionally, in the modeling method of the MOS transistor mismatch model, the coefficients of the mismatch model are obtained by fitting the actual mismatch value and the relationship obtained from the test of each pair of MOS transistors.

[0028] In the modeling method of the MOS transistor mismatch model provided by the present invention, the relationship between the mismatch value of each group of MOS transistors and the channel length and channel width is found based on the mismatch value, channel length and channel width of each group of MOS transistors. All the relationships are fitted to obtain the MOS transistor mismatch model. Compared with the prior art, the modeling method of the MOS transistor mismatch model of the present invention can obtain a more accurate MOS transistor mismatch model. Attached Figure Description

[0029] Figure 1 It is a data graph of threshold voltage mismatch values ​​generated using the existing MOS transistor mismatch modeling method;

[0030] Figure 2 It is a data graph of saturation current mismatch values ​​generated using the existing MOS transistor mismatch modeling method;

[0031] Figure 3 This is a flowchart of the modeling method for the MOS transistor mismatch model according to an embodiment of the present invention.

[0032] Figure 4 This is a data graph of the threshold voltage mismatch value generated using the modeling method of the MOS transistor mismatch model in this embodiment of the invention;

[0033] Figure 5 This is a data graph of saturation current mismatch values ​​generated using the modeling method of the MOS transistor mismatch model in this embodiment of the invention. Detailed Implementation

[0034] The specific embodiments of the present invention will now be described in more detail with reference to the accompanying drawings. The advantages and features of the present invention will become clearer from the following description. It should be noted that the accompanying drawings are all in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present invention.

[0035] In the following text, the terms “first,” “second,” etc., are used to distinguish between similar elements and are not necessarily used to describe a specific order or chronological sequence. It should be understood that these terms, as used herein, may be replaced where appropriate. Similarly, if the methods described herein comprise a series of steps, and the order of these steps presented herein is not necessarily the only possible order in which they can be performed, and some described steps may be omitted and / or other steps not described herein may be added to the method.

[0036] Please refer to Figure 3 This invention provides a modeling method for a MOS transistor mismatch model, comprising:

[0037] Step S1: Test the mismatch value of a pair of MOS transistors;

[0038] Step S2: Establish the relationship between the mismatch value and the channel length and channel width of the MOS transistor;

[0039] Step S3: Repeat steps S1 to S2 to obtain the relationship between the mismatch values ​​of multiple pairs of MOS transistors and the channel length and channel width of the MOS transistors; and

[0040] Step S4: Fit the actual mismatch value and relationship obtained from the test of each pair of MOS transistors to obtain the mismatch model of the MOS transistor.

[0041] In this embodiment of the invention, all MOS transistors have the same channel length and the same channel width. All MOS transistors used in this invention are manufactured using the same process, meaning that theoretically, the parameter values ​​of each MOS transistor should be identical. However, due to various reasons, the final parameters may differ slightly, necessitating the identification of these differences. This embodiment of the invention requires the development of a model based on the actual differences in the parameters. This model can then be used to simulate the parameter differences in subsequent products.

[0042] In this embodiment of the invention, the mismatch value includes: threshold voltage mismatch value and saturation current mismatch value. This embodiment primarily establishes models for the threshold voltage mismatch value and saturation current mismatch value between MOS transistors. In other embodiments of the invention, mismatch models can also be established for the parameters of other MOS transistors.

[0043] In this embodiment of the invention, the method for obtaining the threshold voltage mismatch value includes:

[0044] Sigma_Vtlin=Vtlin1-Vtlin2;

[0045] Here, Sigma_Vtlin represents the threshold voltage mismatch value, Vtlin1 is the threshold voltage of one MOS transistor in each pair, and Vtlin2 is the threshold voltage of the other MOS transistor in each pair. Therefore, each pair of MOS transistors has a mismatch value, and there is a relationship between the mismatch value of each pair and the channel length and channel width (both channel length and channel width are equal). After the mismatch values ​​of all MOS transistors have been tested, there is a relationship between the mismatch value of each pair and the channel length and channel width. Therefore, there are multiple relationships, the specific number of which can be determined based on the actual number of MOS transistors. Some of these relationships may be identical. Next, fitting all these relationships yields a fitted relationship, which is used as the mismatch model.

[0046] In this embodiment of the invention, the method for obtaining the saturation current mismatch value includes:

[0047] Sigma_Idsat=(Idsat1-Idsat2) / (Idsat1+Idsat2) / 2;

[0048] Where Sigma_Idsat is the saturation current mismatch value, Idsat1 is the saturation current of one MOS transistor in each pair of MOS transistors, and Idsat2 is the saturation current of the other MOS transistor in each pair of MOS transistors.

[0049] In this embodiment of the invention, the method for obtaining the threshold voltage (Vtlin) includes: when Ids = Icon * (W / L) and Vds = Vdlin, the voltage value Vgs between the gate and source is the threshold voltage; where Icon is the inherent current value of the MOS transistor, Vdlin is the inherent linear region voltage of the MOS transistor, and Vdd is the operating voltage of the MOS transistor. The inherent current value and inherent linear region voltage are inherent to the MOS transistor and can be obtained through testing or experience in the prior art. The inherent current value and inherent linear region voltage of MOS transistors produced by different processes may vary, and specific values ​​are generally given; therefore, this embodiment of the invention does not elaborate on the method for obtaining them.

[0050] In this embodiment of the invention, the method for obtaining the saturation current (Idsat) includes: when Vds = Vdd, Vgs = Vdd, and Vbs = 0, the current Ids between the drain and source is the saturation current, where Vds is the voltage value between the drain and source, Vgs is the voltage value between the gate and source, Vbs is the voltage value between the substrate and source, and Vdd is the operating voltage of the MOS transistor. Threshold voltage and saturation current are commonly used parameters, and the methods for obtaining them are also commonly used. This embodiment of the invention does not limit the specific methods of obtaining them, but only illustrates them as examples.

[0051] In this embodiment of the invention, the mismatch model of a MOS transistor can be represented by a formula: mismatch=A+B / W+C / L+D / (W*L)+E / sqrt(W*L); where mismatch is the mismatch value, W is the channel width, L is the channel length, and A, B, C, D, and E are coefficients of the mismatch model. In this embodiment, the coefficients of the mismatch model are obtained by fitting the actual mismatch value and the relationship obtained from testing each pair of MOS transistors. Finally, based on the simulation graph established by the mismatch model, the simulation graph is established with reference to the formula Sigma=K / sqrt(W*L); where sigma is the standard deviation, K is a constant coefficient, L is the channel length of the transistor, and W is the channel width of the transistor. Essentially, with sqrt(W*L) as the x-axis and the mismatch value mismatch as the y-axis, the obtained model curve and the actual mismatch value mismatch are relatively close. For example... Figure 4 The x-axis is 1 / sqrt(W*L), where W is the channel width and L is the channel length, and the y-axis is the threshold voltage mismatch value. Data represents the test data of the device's threshold voltage, and model represents the simulated data of the device's threshold voltage. Line 1 is the data line fitted to the simulated data, and line 2 is the data line fitted to the test data. It can be seen that although the test data is relatively scattered, the test data and simulated data for each device are not far apart, indicating that the simulated data obtained using the simulation method of this embodiment is relatively accurate. Figure 5In the diagram, the horizontal axis is 1 / sqrt(W*L), where W is the channel width and L is the channel length, and the vertical axis is the saturation current mismatch value. Data represents the test data of the device's saturation current, and model represents the simulated data of the device's saturation current. Line 1 is the data line fitted to the simulated data, and line 2 is the data line fitted to the test data. It can be seen that although the test data is relatively scattered, the test data and simulated data for each device are not far apart, indicating that the simulation data obtained using the simulation method of this embodiment is relatively accurate. Therefore, it can be concluded that the model data obtained after simulation in this embodiment can not only match the slope of the test data but also match the actual value of the test data for each device well, thereby improving the modeling accuracy of the mismatch for each device.

[0052] In summary, in the modeling method of the MOS transistor mismatch model provided in the embodiments of the present invention, the relationship between the mismatch value of each group of MOS transistors and the channel length and channel width is found based on the mismatch value, channel length and channel width of each group of MOS transistors. All relationships are fitted to obtain the MOS transistor mismatch model. Compared with the prior art, the modeling method of the MOS transistor mismatch model of the present invention can obtain a more accurate MOS transistor mismatch model.

[0053] The above are merely preferred embodiments of the present invention and do not constitute any limitation on the present invention. Any equivalent substitutions or modifications made by those skilled in the art to the technical solutions and content disclosed in the present invention without departing from the scope of the present invention shall be deemed to have remained within the protection scope of the present invention.

Claims

1. A modeling method for a MOS transistor mismatch model, characterized in that, include: Step S1: Test the mismatch value of a pair of MOS transistors; Step S2: Establish the relationship between the mismatch value and the channel length and channel width of the MOS transistor; Step S3: Repeat steps S1 to S2 to obtain the relationship between the mismatch values ​​of multiple pairs of MOS transistors and the channel length and channel width of the MOS transistors; as well as Step S4: Fit the actual mismatch value and relationship obtained from the test of each pair of MOS transistors to obtain the mismatch model of the MOS transistors; The mismatch model of the MOS transistor is as follows: mismatch = A + B / W + C / L + D / (W*L) + E / sqrt(W*L); where mismatch is the mismatch value, W is the channel width, L is the channel length, and A, B, C, D, and E are the coefficients of the mismatch model.

2. The modeling method for the MOS transistor mismatch model as described in claim 1, characterized in that, All of the MOS transistors described herein have the same channel length.

3. The modeling method for the MOS transistor mismatch model as described in claim 1, characterized in that, All of the MOS transistors described herein have the same channel width.

4. The modeling method for the MOS transistor mismatch model as described in claim 1, characterized in that, The mismatch values ​​include: threshold voltage mismatch value and saturation current mismatch value.

5. The modeling method for the MOS transistor mismatch model as described in claim 4, characterized in that, The method for obtaining the threshold voltage mismatch value includes: Sigma_Vtlin = Vtlin1-Vtlin2; Where Sigma_Vtlin is the threshold voltage mismatch value, Vtlin1 is the threshold voltage of one MOS transistor in each pair of MOS transistors, and Vtlin2 is the threshold voltage of the other MOS transistor in each pair of MOS transistors.

6. The modeling method for the MOS transistor mismatch model as described in claim 4, characterized in that, The method for obtaining the saturation current mismatch value includes: Sigma_Idsat = (Idsat1-Idsat2) / (Idsat1+Idsat2) / 2; Where Sigma_Idsat is the saturation current mismatch value, Idsat1 is the saturation current of one MOS transistor in each pair of MOS transistors, and Idsat2 is the saturation current of the other MOS transistor in each pair of MOS transistors.

7. The modeling method for the MOS transistor mismatch model as described in claim 1, characterized in that, Methods for obtaining the threshold voltage include: When Ids = Icon * (W / L) and Vds = Vdlin, the voltage between the gate and the source is the threshold voltage; where Icon is the inherent current value of the MOS transistor, Vdlin is the inherent linear region voltage of the MOS transistor, and Vdd is the operating voltage of the MOS transistor.

8. The modeling method for the MOS transistor mismatch model as described in claim 1, characterized in that, Methods for obtaining saturation current include: When Vds = Vdd, Vgs = Vdd, and Vbs = 0, the current between the drain and source is the saturation current. Where Vds is the voltage between the drain and the source, Vgs is the voltage between the gate and the source, Vbs is the voltage between the substrate and the source, and Vdd is the operating voltage of the MOS transistor.

9. The modeling method for the MOS transistor mismatch model as described in claim 1, characterized in that, The coefficients of the mismatch model are obtained by fitting the actual mismatch value and the relationship obtained from the test of each pair of MOS transistors.

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