Pixel Circuit and Display Device Including the Same

Abstract

A pixel circuit and a display device including the pixel circuit are disclosed. The pixel circuit of the present disclosure includes: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply current to a light-emitting element; a first switching element configured to turn on according to a strobe turn-on voltage and provide a data voltage to the second node; a first capacitor connected between the second node and the third node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the fourth node and the first node, or connected between the fourth node and a power supply line to which the pixel driving voltage is applied.

Description

Technical Field

[0001] The present disclosure relates to a pixel circuit and a display device including the pixel circuit. Background Art

[0002] According to the material of the light-emitting layer, an electroluminescent display device can be classified into an inorganic light-emitting display device and an organic light-emitting display device. An active matrix organic light-emitting display device includes an organic light-emitting diode (hereinafter referred to as "OLED") that emits light by itself, and has advantages such as a fast response speed, high luminous efficiency, high brightness, and a wide viewing angle. In an organic light-emitting display device, an OLED (organic light-emitting diode) is formed in each pixel. The organic light-emitting display device has a fast response speed, excellent luminous efficiency, brightness, and viewing angle, and has excellent contrast and color reproducibility because black gradation can be represented as full black.

[0003] The pixel circuit of an organic light-emitting display device includes a light-emitting element, a driving element for driving the light-emitting element, and one or more switching elements. The switching element is turned on / off according to a gate voltage, thereby connecting or disconnecting a main node of the pixel circuit. The driving element and the switching element can be implemented by transistors.

[0004] Due to process variations and component characteristic variations caused during the manufacturing process of a display panel, there may be differences in the electrical characteristics of driving elements between pixels, and these differences increase as the driving time of the pixels elapses. To compensate for variations in the electrical characteristics of driving elements between pixels, an internal compensation circuit can be embedded in the pixel circuit, or a circuit can be connected to the pixel circuit. The internal compensation circuit can be embedded in the pixel circuit and samples the amount of change in the threshold voltage of the driving element, thereby compensating the gate-source voltage of the driving element through the amount of change in the threshold voltage. The external compensation circuit can generate a compensation value based on the result of sensing the electrical characteristics of the driving element by using an external compensation circuit connected to the pixel circuit, and can compensate for variations in the electrical characteristics of the driving element.

[0005] Due to the limitation of the compensation ability of the internal compensation circuit, image quality may deteriorate. For example, if the amount of change in the threshold voltage of the driving element increases beyond the compensation range, the threshold voltage of the driving element is not compensated, so that a brightness change at low gradation can be visually recognized. Summary of the Invention

[0006] An object of the present disclosure is to solve the above needs and / or problems.

[0007] The present disclosure provides a pixel circuit capable of improving image quality by overcoming compensation limitations in pixels including an internal compensation circuit, and a display device including the pixel circuit.

[0008] The defects solved by the present disclosure are not limited to the above-mentioned defects, and other defects that the present disclosure can solve will become obvious to those skilled in the art from the following description.

[0009] A pixel circuit according to an embodiment of the present disclosure includes: a driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and configured to supply current to a light-emitting element; a first switching element configured to turn on according to a strobe conduction voltage and supply a data voltage to the second node; a first capacitor connected between the second node and the third node; a second capacitor connected between the third node and the fourth node; and a third capacitor connected between the fourth node and the first node, or connected between the fourth node and a power supply line to which the pixel driving voltage is applied.

[0010] The display device of the present disclosure includes the pixel circuit.

[0011] The present disclosure can improve the S factor of the driving element by applying a reverse bias voltage to the driving element and adjusting the capacitance ratio of the capacitor.

[0012] The present disclosure can improve the S factor, thereby overcoming the limitations of the internal compensation circuit, and improving the image quality.

[0013] The effects of the present disclosure are not limited to the above effects, and those skilled in the art will clearly recognize other effects not mentioned above from the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] By referring to the accompanying drawings and describing in detail the exemplary embodiments of the present disclosure, the above and other objects, features, and advantages of the present disclosure will become more apparent to those of ordinary skill in the art. In the drawings:

[0015] Figure 1 is a block diagram showing a display device according to an embodiment of the present disclosure;

[0016] Figure 2 is showing Figure 1 a cross-sectional view of the cross-sectional structure of the display panel shown;

[0017] Figure 3 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure;

[0018] Figure 4 is showing in the display panel Figure 3 a cross-sectional view of the cross-sectional structure of the driving element shown;

[0019] Figure 5 is a view showing the S factor;

[0020] Figure 6 is a simulation result for verifying the effect that the threshold voltage of a driving element deviates from the reverse bias voltage of the driving element;

[0021] Figure 7 is a view showing Figure 3 a waveform diagram of the voltage at the main nodes of the pixel circuit shown in;

[0022] Figure 8 is a view showing the operating characteristics of a driving element and an OLED;

[0023] Figure 9 is a view showing the current change of a light-emitting element based on an increase in the same current according to the S factor;

[0024] Figure 10 is a view showing according to Figure 3 a simulation result of the change of the S factor of the capacitor capacitance of the pixel circuit shown in;

[0025] Figure 11 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure;

[0026] Figure 12 is a view showing the application to Figure 11 a waveform diagram of the strobe signal of the pixel circuit shown in;

[0027] Figures 13A to 13D is a circuit diagram showing step by step Figure 11 the operation of the pixel circuit shown in;

[0028] Figure 14 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure; and

[0029] Figure 15 is a view showing the application to Figure 14 a waveform diagram of the strobe signal of the pixel circuit shown in. Detailed Embodiments

[0030] According to the embodiments described below with reference to the accompanying drawings, the advantages and features of the present disclosure and methods for implementing the same will be more clearly understood. However, the present disclosure is not limited to the following embodiments, but may be implemented in various different forms. On the contrary, the present embodiments will make the disclosure of the present disclosure complete and allow those skilled in the art to fully understand the scope of the present disclosure. The present disclosure is only defined within the scope of the appended claims.

[0031] The shapes, dimensions, ratios, angles, quantities, etc. illustrated in the accompanying drawings for describing the embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. The same reference numerals generally denote the same elements throughout the specification. In addition, when describing the present disclosure, detailed descriptions of known prior arts may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure.

[0032] Terms such as "comprising", "including", "having", and "consisting of" used herein generally mean allowing the addition of other components, unless the term is used together with the term "only". Any singular reference may include the plural unless expressly stated otherwise.

[0033] Even if not explicitly stated, components are construed to include a normal range of errors.

[0034] When using terms such as "on", "above", "below", and "adjacent to" to describe the positional relationship between two components, one or more components may be positioned between the two components unless the terms are used with words such as "immediately" or "directly".

[0035] Terms such as "first", "second", etc. may be used to distinguish components from each other, but the functions or structures of the components are not limited by the serial numbers or component names in front of the components.

[0036] The following embodiments may be partially or fully combined or combined with each other, and may be connected and operated in technically different ways. These embodiments may be executed independently or in association with each other.

[0037] Each pixel may include a plurality of sub-pixels having different colors in order to reproduce the colors of an image on the screen of the display panel. Each sub-pixel includes a transistor serving as a switching element or a driving element. Such a transistor may be implemented as a TFT (thin film transistor).

[0038] The driving circuit of the display device writes the pixel data of the input image to the pixels on the display panel. To this end, the driving circuit of the display device may include a data driving circuit configured to provide data signals to data lines, a gate driving circuit configured to provide gate signals to gate lines, and the like.

[0039] In the display device of the present disclosure, the pixel circuit and the gate driving circuit may include a plurality of transistors. The transistors may be implemented as oxide thin film transistors (oxide TFTs) including oxide semiconductors, low temperature polysilicon (LTPS) TFTs including low temperature polysilicon, and the like. In an embodiment, a description will be given based on an example in which the transistors of the pixel circuit and the gate driving circuit are implemented as n-channel oxide TFTs, but the present disclosure is not limited thereto.

[0040] Generally, a transistor is a three - electrode element including a gate, a source, and a drain. The source is the electrode that supplies carriers to the transistor. In a transistor, carriers start to flow from the source. The drain is the electrode from which carriers leave the transistor. In a transistor, carriers flow from the source to the drain. In the case of an n - channel transistor, since the carriers are electrons, the source voltage is a voltage lower than the drain voltage, enabling electrons to flow from the source to the drain. An n - channel transistor has a direction in which current flows from the drain to the source. In the case of a p - channel transistor, since the carriers are holes, the source voltage is higher than the drain voltage, enabling holes to flow from the source to the drain. In a p - channel transistor, since holes flow from the source to the drain, the current flows from the source to the drain. It should be noted that the source and drain of a transistor are not fixed. For example, the source and drain can change according to the applied voltage. Therefore, the present disclosure is not limited by the source and drain of the transistor. In the following description, the source and drain of the transistor will be referred to as the first electrode and the second electrode.

[0041] The strobe signal swings between a strobe turn - on voltage and a strobe turn - off voltage. The strobe turn - on voltage is set to a voltage higher than the threshold voltage of the transistor, and the strobe turn - off voltage is set to a voltage lower than the threshold voltage of the transistor.

[0042] The transistor turns on in response to the strobe turn - on voltage and turns off in response to the strobe turn - off voltage. In the case of an n - channel transistor, the strobe turn - on voltage can be the strobe high voltage VGH and VEH, and the strobe turn - off voltage can be the strobe low voltage VGL and VEL.

[0043] Hereinafter, exemplary embodiments of the present disclosure will be described with reference to the accompanying drawings. In the following embodiments, the display device will be mainly described with respect to an organic light - emitting display device, but the present disclosure is not limited thereto. In addition, the scope of the present disclosure is not intended to be limited by the names of components or signals in the following embodiments and claims.

[0044] Refer to Figure 1 and Figure 2 , a display device according to an embodiment of the present disclosure includes a display panel 100, a display panel driver for writing pixel data into pixels of the display panel 100, and a power supply 140 for generating power required to drive the pixels and the display panel driver.

[0045] The display panel 100 may be a panel having a rectangular structure, and the rectangular structure has a length in the X-axis direction, a width in the Y-axis direction, and a thickness in the Z-axis direction. The display panel 100 includes a pixel array for displaying an input image on a screen. The pixel array includes a plurality of data lines 102, a plurality of gate lines 103 intersecting the data lines 102, and pixels arranged in a matrix form. The display panel 100 may further include a power supply line commonly connected to the pixels. The power supply line supplies a constant voltage required to drive the pixels 101 to the pixels 101. For example, the display panel 100 may include a VDD line to which a pixel driving voltage ELVDD is applied and a VSS line to which a low-potential power supply voltage ELVSS is applied. Additionally, the power supply line may further include a REF line to which a reference voltage Vref is applied and an INIT line to which an initialization voltage Vinit is applied.

[0046] As Figure 2 shown, the cross-sectional structure of the display panel 100 may include a circuit layer 12, a light-emitting element layer 14, and a packaging layer 16 laminated on a substrate 10.

[0047] The circuit layer 12 may include a TFT (Thin Film Transistor) array, a demultiplexer array 112, a gate driver 120, etc. The TFT array includes pixel circuits connected to wires such as data lines, gate lines, and power supply lines. The wires and circuit elements of the circuit layer 12 may include a plurality of insulating layers, two or more metal layers separated by an insulating layer interposed therebetween, and an active layer including a semiconductor material. All transistors formed in the circuit layer 12 may be implemented as n-channel oxide TFTs.

[0048] The light-emitting element layer 14 may include light-emitting elements EL driven by the pixel circuits. The light-emitting elements EL may include red (R) light-emitting elements, green (G) light-emitting elements, and blue (B) light-emitting elements. In another embodiment, the light-emitting element layer 14 may include white light-emitting elements and color filters. The light-emitting elements EL of the light-emitting element layer 14 may be covered by a plurality of protective layers in which organic layers and inorganic layers are laminated.

[0049] The packaging layer 16 covers the light-emitting element layer 14 to seal the circuit layer 12 and the light-emitting element layer 14. The packaging layer 16 may also have a multi-insulating film structure in which organic films and inorganic films are alternately laminated. The inorganic film prevents the penetration of moisture and oxygen. The organic film flattens the surface of the inorganic film. When the organic layer and the inorganic layer are laminated in multiple layers, the movement path of moisture or oxygen becomes longer than that of a single layer, thereby effectively preventing the penetration of moisture and oxygen that affect the light-emitting element layer 14.

[0050] The touch sensor layer omitted in the drawings may be formed on the encapsulation layer 16, and a polarizer or a color filter layer may be disposed on the touch sensor layer. The touch sensor layer may include a capacitive touch sensor that senses a touch input based on capacitance changes before and after the touch input. The touch sensor layer may include an insulating layer and a metal wire pattern that form the capacitance of the touch sensor. The insulating layer may insulate the crossing portions of the metal wire pattern and may planarize the surface of the touch sensor layer. The polarizer may improve visibility and contrast by converting the polarization of external light reflected by the metals of the touch sensor layer and the circuit layer. The polarizer may be implemented as a polarizer combining a linear polarizer and a phase retardation film or a circular polarizer. A cover glass may be adhered to the polarizer. The color filter layer may include a red color filter, a green color filter, and a blue color filter. The color filter layer may further include a black matrix pattern. The color filter layer absorbs a part of the wavelength of light reflected from the circuit layer and the touch sensor layer, so that it may replace the polarizer and improve the color purity of the image reproduced in the pixel array.

[0051] The pixel array includes a plurality of pixel lines L1 to Ln. Each of the pixel lines L1 to Ln includes a row of pixels arranged in the row direction (X-axis direction) in the pixel array of the display panel 100. The pixels arranged in one pixel row share the gate line 103. The sub-pixels arranged in the column direction Y along the data line direction share the same data line 102. One horizontal period is a time obtained by dividing one frame period by the total number of the pixel lines L1 to Ln.

[0052] The display panel 100 may be implemented as a non-transmissive display panel or a transmissive display panel. The transmissive display panel may be applied to a transparent display device that displays an image on a screen and the actual background is visible. The display panel 100 may be manufactured as a flexible display panel.

[0053] Each pixel 101 may be divided into a red sub-pixel, a green sub-pixel, and a blue sub-pixel to implement colors. Each pixel may further include a white sub-pixel. Each sub-pixel includes a pixel circuit. Hereinafter, a pixel may be interpreted to have the same meaning as a sub-pixel. Each pixel circuit is connected to a data line, a gate line, and a power line.

[0054] Pixels may be arranged as true color pixels and pixel arrangement (pentile) pixels. By driving two sub-pixels having different colors as one pixel 101 using a preset pixel rendering algorithm, the pixel arrangement pixels may achieve a higher resolution than the true color pixels. The pixel rendering algorithm may utilize the colors of light emitted from adjacent pixels to compensate for insufficient color representation in each pixel.

[0055] Power supply 140 generates a direct current (DC) voltage (or constant voltage) required to drive the pixel array and the display panel driver of display panel 100 by using a DC-DC converter. The DC-DC converter may include a charge pump, a regulator, a buck converter, a boost converter, etc. Power supply 140 may generate a DC voltage (or constant voltage), such as a gamma reference voltage VGMA, a gate-on voltage VGH, a gate-off voltage VGL, a pixel driving voltage ELVDD, a low-potential power supply voltage ELVSS, an initialization voltage Vinit, a reference voltage Vref, etc., by adjusting the level of the DC input voltage applied from a host system (not shown). The gamma reference voltage VGMA is supplied to data driver 110. The gate-on voltage VGH and the gate-off voltage VGL are supplied to gate driver 120. Constant voltages such as the pixel driving voltage ELVDD, the low-potential power supply voltage ELVSS, the initialization voltage Vinit, the reference voltage Vref, etc. are supplied to pixel 101 through power lines commonly connected to pixel 101. The constant voltages applied to the pixel circuit may have different voltage levels.

[0056] The display panel driver writes the pixel data of the input image into the pixels of display panel 100 under the control of timing controller 130.

[0057] The display panel driver includes data driver 110 and gate driver 120. The display panel driver may further include a demultiplexer array 112 disposed between data driver 110 and data lines 102.

[0058] The demultiplexer array 112 sequentially supplies the data voltages output from the channels of data driver 110 to data lines 102 by using a plurality of demultiplexers (DEMUX). The demultiplexer may include a plurality of switching elements disposed on display panel 100. When the demultiplexer is disposed between the output terminal of data driver 110 and data lines 102, the number of channels of data driver 110 can be reduced. The demultiplexer array 112 may be omitted.

[0059] The display panel driver may further include a touch sensor driver for driving a touch sensor. Figure 1 The touch sensor driver is omitted. Data driver 110 and the touch sensor driver may be integrated into a single driving integrated circuit (IC). In a mobile device or a wearable device, timing controller 130, power supply 140, data driver 110, etc. may be integrated into one driving IC.

[0060] The display panel driver can operate in a low-speed driving mode under the control of the timing controller 130. The low-speed driving mode can be set to reduce the power consumption of the display device when the input image has not changed for a preset number of frames by analyzing the input image. In the low-speed driving mode, when a still image is input for a predetermined time or longer, the power consumption of the display panel driver and the display panel 100 can be reduced by reducing the refresh rate of the pixels. The low-speed driving mode is not limited to when a still image is input. For example, when the display device is operating in a standby mode, or when a user command or an input image has not been input to the display panel driving circuit for a predetermined time or longer, the display panel driving circuit can operate in the low-speed driving mode.

[0061] The data driver 110 receives pixel data of the input image received as a digital signal from the timing controller 130 and outputs a data voltage. The data driver 110 generates a data voltage Vdata by converting the pixel data of the input image into a gamma-compensated voltage using a digital-to-analog converter (DAC) during each frame period. The gamma reference voltage VGMA is divided into gamma-compensated voltages for each gray level by a voltage divider circuit. The gamma-compensated voltages for each gray level are provided to the DAC of the data driver 110. The data voltage Vdata is output from each channel of the data driver 110 through an output buffer.

[0062] The gate driver 120 can be implemented as an in-panel gate (GIP) circuit formed in the circuit layer 12 on the display panel 100 together with the TFT array and the pixel array wires. The gate driver 120 can be disposed on the bezel BZ which is a non-display area of the display panel 100, or the gate driver 120 can be distributively disposed in the pixel array that reproduces the input image. The gate driver 120 sequentially outputs gate signals to the gate lines 103 under the control of the timing controller 130. The gate driver 120 can sequentially supply the gate signals to the gate lines 103 while shifting the gate signals using a shift register. The gate signals can include various gate pulses, such as a scan pulse, a sense pulse, an initialization pulse, an emission control pulse (hereinafter referred to as an "EM pulse"), etc.

[0063] The timing controller 130 receives digital video data DATA of the input image from the host system and a timing signal synchronized with the digital video data DATA. The timing signal can include a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a clock CLK, a data enable signal DE, etc. Since the vertical period and the horizontal period can be known by counting the data enable signal DE, the vertical synchronization signal Vsync and the horizontal synchronization signal Hsync can be omitted. The data enable signal DE has a period of one horizontal period 1H.

[0064] The host system can be any one of a television (TV) system, a tablet computer, a notebook computer, a navigation system, a personal computer (PC), a home theater system, a mobile device, a wearable device, and a vehicle system. The host system can scale the image signal from the video source to fit the resolution of the display panel 100 and send it to the timing controller 130 together with a timing signal.

[0065] The timing controller 130 can multiply the input frame frequency by i (where i is a natural number) in the normal driving mode, so that the timing controller 130 can control the operation timing of the display panel driver at a frame frequency of input frame frequency × i Hz. The input frame frequency is 60 Hz in the NTSC (National Television System Committee) scheme and 50 Hz in the PAL (Phase Alternating Line) scheme.

[0066] Compared with the normal driving mode, the timing controller 130 reduces the frame frequency (or data refresh rate) at which pixel data is written to the pixels in the low-speed driving mode. For example, in the normal driving mode, the frame frequency at which pixel data is written to the pixels can occur at a frequency of 60 Hz or higher, for example, at a frame frequency of any one of 60 Hz, 120 Hz, and 144 Hz, and the frame frequency in the low-speed driving mode can occur at a frequency lower than the frame frequency in the normal driving mode. For example, the timing controller 130 can reduce the driving frequency of the display panel driver by reducing the frame frequency to a frequency between 1 Hz and 30 Hz in the low-speed driving mode to reduce the refresh rate of the pixels.

[0067] The timing controller 130 generates a data timing control signal for controlling the operation timing of the data driver 110, a control signal for controlling the operation timing of the demultiplexer array 112, and a gate timing control signal for controlling the operation timing of the gate driver 120 based on the timing signals Vsync, Hsync, and DE received from the host system. The timing controller 130 controls the operation timing of the display panel driver to synchronize the data driver 110, the demultiplexer array 112, the touch sensor driver, and the gate driver 120.

[0068] The gate timing control signal generated from the timing controller 130 can be input to the shift register of the gate driver 120 through a level shifter (not shown). The level shifter can receive the gate timing control signal, generate a start pulse and a shift clock, and provide them to the shift register.

[0069] Figure 3 is a circuit diagram showing a pixel circuit according to an embodiment of the present disclosure.

[0070] Refer to Figure 3, the pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a first switching element T1, and a first capacitor Cst, a second capacitor C1, and a third capacitor C2. The driving element DT and the switching element T1 can be implemented by n-channel oxide TFTs.

[0071] The light-emitting element EL can be implemented by an OLED. The OLED includes an organic compound layer formed between an anode and a cathode. The organic compound layer may include, but is not limited to, a hole injection layer HIL, a hole transport layer HTL, a light-emitting layer EML, an electron transport layer ETL, and an electron injection layer EIL. When a voltage is applied to the anode and cathode of the OLED, holes that have passed through the hole transport layer HTL and electrons that have passed through the electron transport layer ETL move to the light-emitting layer EML, and excitons are formed. At this time, visible light is emitted from the light-emitting layer EML. The anode of the light-emitting element EL is connected to the third node DTS. The low-potential power supply voltage EVSS is applied to the cathode of the light-emitting element EL. The OLED used as the light-emitting element EL can be a tandem structure in which a plurality of light-emitting layers are stacked. The tandem-structured OLED can improve the brightness and lifespan of the pixel.

[0072] The driving element DT can be implemented by a double-gate structure including a first gate electrode G1 and a second gate electrode G2. The driving element DT includes a first electrode connected to the first node DTD, a first gate electrode G1 connected to the second node DTG, a second electrode connected to the third node DTS, and a second gate electrode connected to the fourth node DTB. The pixel driving voltage EVDD is applied to the first node DTD connected to the first electrode of the driving element DT. The first electrode can be a drain electrode, and the second electrode can be a source electrode. The second gate electrode G2 can be interpreted as a body electrode or a bottom gate electrode. The first gate electrode G1 and the second gate electrode G2 can overlap each other, and a semiconductor layer is interposed between the first gate electrode G1 and the second gate electrode G2.

[0073] In the driving element DT, the reverse bias voltage V between the second gate electrode G2 and the second electrode BS can shift the threshold voltage Vth of the driving element DT to a desired voltage.

[0074] The first switching element T1 turns on in response to the gate-on voltage VGH, thereby applying the data voltage Vdata of the pixel data to the second node DTG connected to the first gate electrode G1 of the driving element DT. The first switching element T1 turns off in response to the gate-off voltage VGL.

[0075] The first capacitor Cst is connected between the second node DTG and the third node DTS, and stores the gate-source voltage V of the driving element DT GS .

[0076] The second capacitor C1 is connected between the third node DTS and the fourth node DTB. The reverse bias voltage V of the driving element DT BS is charged in the second capacitor C1. The reverse bias voltage V BS is the voltage applied between the third node DTS and the fourth node DTB. The voltage at the fourth node DTB is determined according to the voltage * capacitance transfer rate of the third node DTS. The voltage at the third node DTS changes according to the data voltage Vdata applied to the second node DTG. Therefore, for each gray level of the pixel data, a threshold voltage shift (Vth shift) of the driving element DT occurs, and the S factor (subthreshold slope factor) of the driving element can be improved.

[0077] The third capacitor C2 is connected between the first node DTD and the fourth node DTB. The voltage at the fourth node DTB can be changed by the capacitance transfer rate C1 / (C1 + C2) determined according to the capacitances of the second capacitor C1 and the third capacitor C2.

[0078] The voltage at the third node DTS changes according to the current (or luminance) flowing through the light-emitting element EL. The voltage loss of the reverse bias voltage V of the driving element DT BS is determined according to the capacitance transfer rate. The reverse bias voltage V BS is defined as V BS = C'(Vs) - Vs and has a negative (-) value. Here, C' is the capacitance transfer rate C1 / (C1 + C2), and Vs is the voltage at the third node DTS. As the current amount flowing through the third node DTS increases, the reverse bias voltage V BS becomes larger, and thus the threshold voltage shift of the driving element DT becomes larger.

[0079] Figure 4 is a cross-sectional view showing the cross-sectional structure of the driving element Figure 3 shown in the display panel.

[0080] Referring to Figure 4 , the first metal pattern LS1 is provided on the substrate SUBS of the display panel 100. The first insulating layer BUF is provided on the substrate SUBS to cover the first metal pattern LS1.

[0081] The second metal pattern is provided on the first insulating layer BUF. The second metal pattern includes the second gate electrode G21 of the driving element DT. The second insulating layer BUF2 is provided on the first insulating layer BUF1 to cover the second metal pattern. The second metal pattern overlaps with the first metal pattern LS1, and the first insulating layer BUF1 is interposed between the second metal pattern and the first metal pattern LS1.

[0082] The semiconductor layer is disposed on the second insulating layer BUF2. The semiconductor layer may be formed of an oxide semiconductor. The semiconductor layer includes an active pattern ACT that forms a semiconductor channel of the driving element DT and a metallization pattern AE.

[0083] In the case of IGZO (indium gallium zinc oxide) which is an oxide semiconductor, the conductive characteristics vary according to the oxygen content. When the oxygen content decreases, the conductivity of the oxide semiconductor IGZO increases, resulting in its metallization. As a method of reducing the oxygen content of the oxide semiconductor IGZO, plasma treatment can be employed. For example, if the oxide semiconductor is exposed to plasma (metallization process), the oxygen contained inside the oxide semiconductor can be removed, and the resistance of the oxide semiconductor IGZO can be reduced, causing the oxide semiconductor IGZO to be metallized. Plasma treatment is a method of causing plasma discharge in helium (He), hydrogen (H2), or argon (Ar) gas.

[0084] The active pattern ACT of the semiconductor layer overlaps with the second gate electrode G21 of the driving element, and the second insulating layer BUF2 is interposed between the active pattern ACT and the second gate electrode G21. The second gate electrode G21 can be patterned to a larger size than the active pattern ACT. The pixel driving voltage EVDD can be applied to the metallization pattern AE of the semiconductor layer.

[0085] The third insulating layer GI is disposed on the second insulating layer BUF2 to cover the active pattern ACT made of a semiconductor. A third metal pattern is formed on the third insulating layer GI. The third metal pattern includes a first gate electrode G1 of the driving element DT. The first gate electrode G1 overlaps with the second gate electrode G21, and the active pattern ACT of the semiconductor layer is interposed between the first gate electrode G1 and the second gate electrode G21.

[0086] The fourth insulating layer ILD is disposed on the third insulating layer GI to cover the third metal pattern. A fourth metal pattern is disposed on the fourth insulating layer ILD. The fifth insulating layer PAS is disposed on the fourth insulating layer ILD to cover the fourth metal pattern. The fourth metal pattern includes a first electrode (or drain electrode) DE and a second electrode (or source electrode) SE of the driving element DT. The first electrode DE and the second electrode SE of the driving element DT are connected to the active pattern ACT via contact holes passing through the third insulating layer GI and the fourth insulating layer ILD.

[0087] The fourth metal pattern includes a second gate electrode extension G22. The second gate electrode extension G22 is connected to the second gate electrode G21 via a contact hole passing through the second insulating layer BUF2, the third insulating layer GI, and the fourth insulating layer ILD. In addition, the second gate electrode extension G22 is connected to the first metal pattern LS1 via a contact hole passing through the first insulating layer BUF1, the second insulating layer BUF2, the third insulating layer GI, and the fourth insulating layer ILD.

[0088] The second capacitor C1 may be formed between the second electrode SE of the driving element DT connected to the third node DTS of the pixel circuit and the second gate electrode G21. The third capacitor C2 may be formed between the second gate electrode extension G22 and the metallization pattern AE. The structures of the second capacitor C1 and the third capacitor C2 are not limited to Figure 4 the structures shown. The S factor can be adjusted according to the capacitance transfer rate determined based on the capacitances of the second capacitor C1 and the third capacitor C2. The cross-sectional structures of the second capacitor C1 and the third capacitor C2 may be changed according to the set value of the capacitance transfer rate.

[0089] As Figure 3 and Figure 4 shown, the second gate electrodes G21 and G22 of the driving element DT are separated from the first electrode DE and the second electrode SE of the driving element DT.

[0090] Figure 5 is a diagram showing the S factor of the driving element DT. In Figure 5 , the horizontal axis represents the gate-source voltage V GS of the driving element DT, and the vertical axis represents the drain-source current IDS (logarithmic scale value) of the driving element DT. The S factor is the gate voltage value for increasing the drain current amount of the driving element DT by ten (10) times. As Figure 4 shown, the S factor S can be represented by the reciprocal of the slope value of the I-V conduction curve in the subthreshold region of the driving element DT, that is, . The larger the S factor S, Figure 5 the lower the slope of the I-V conduction curve in

[0091] Figure 6 is a view showing the simulation results for verifying the effect of the reverse bias voltage V BS of the threshold voltage Vth of the driving element on the driving element DT. In Figure 6 , the horizontal axis represents the gate-source voltage V GS [V] of the driving element DT, and the vertical axis represents the drain-source current I DS [A] of the driving element DT. The reverse bias voltage V BSThe threshold voltage of the driving element DT can be shifted into the detectable range. Therefore, even if the shift of the threshold voltage of the driving element DT exceeds the detectable range, the threshold voltage of the driving element DT can be accurately detected. For example, if the threshold voltage of the driving element DT shifts to a voltage of 0 V or lower, the threshold voltage of the driving element DT cannot be detected. However, since a reverse bias voltage V BS is applied to the driving element DT, the threshold voltage Vth of the driving element DT can be shifted to a positive voltage greater than 0 V, and thus the threshold voltage Vth of the driving element DT can be detected. In particular, the lower the voltage Vb at the fourth node DTB applied to the second gate electrode G2 is compared with the voltage Vs at the third node DTS, the more positively shifted the threshold voltage Vth of the driving element DT is.

[0092] Figure 7 is a waveform diagram showing the voltages at the main nodes of the pixel circuit shown Figure 3 therein.

[0093] Referring to Figure 7 , the data voltage Vdata can be applied to the second node DTG of the pixel circuit, and then the second node DTG can be floated. Then, the third node DTS and the fourth node DTB to which the reference voltage Vref is applied can be floated. When these nodes DTG, DTS, and DTB are floated, if the voltage Vs rises due to the current flowing through the third node DTS, the voltage at the second node DTG rises, and the voltage Vb at the fourth node DTB rises. At this time, a voltage loss occurs due to the capacitance transfer rate, so the voltage Vb at the fourth node DTB becomes lower than the voltage Vs at the third node DTS. The voltage Vb of the fourth node DTB is Vb = ΔVs*{C1 / C1 + C2} + Vref, and the reverse bias voltage V BS is V BS = ΔVs*{C1 / C1 + C2} + Vref - Vs. Here, "ΔVs" is the voltage change amount at the third node DTS.

[0094] Figure 8 is a view showing the operating characteristics of the driving element and the OLED.

[0095] Referring to Figure 8 , as the gray value of the pixel data increases, the gate-source voltage V GS of the driving element increases (V GS2 > V GS1 ). At this time, the operating point of the OLED that can be used as the light-emitting element EL moves from V S2 to V S1 (V S2 > V S1) Also, the higher the gray value of the pixel data, the greater the threshold voltage shift (Vth shift) of the driving element. As a result, the slope of the I-V conduction curve decreases. Therefore, as the gray value of the pixel data increases, the S factor S increases. The S factor S is the reciprocal of the slope value of the I-V conduction curve.

[0096] Figure 9 is a view showing the increased current change of the light-emitting element based on the S factor for the same current.

[0097] Referring to Figure 9 , as the S factor S increases, the slope of the I-V conduction curve in the low gray level region decreases. At this time, when the same current flows through the third node DTS in the pixel circuit with a larger S factor and the pixel circuit with a relatively smaller S factor of the driving element DT, when the threshold voltage change ΔVth of the driving element occurs in the low gray level region, the current change ΔI of the OLED OLED is smaller in the driving element DT with a larger S factor. As a result, since even when the cumulative driving time of the pixel increases, the current change of the light-emitting element EL in the low gray level region of the pixel data is small, and thus the threshold voltage shift of the driving element DT becomes large, there is almost no deterioration in the image quality in the low gray level region even when the display device is used for a long time.

[0098] The S factor S can be adjusted by the capacitance ratio of the second capacitor C1 and the third capacitor C2. The capacitance of each of the second capacitor C1 and the third capacitor C2 is set to a value less than the capacitance of the first capacitor Cst. The capacitance of the second capacitor C1 is set to a value greater than the capacitance of the third capacitor C2.

[0099] Figure 10 is a view showing according to Figure 3 the simulation results of the change in the S factor according to the capacitor capacity of the pixel circuit shown in. In Figure 10 , the horizontal axis represents the data voltage Vdata [V] applied to the second node DTG, and the vertical axis represents the current I OLED [A] of the light-emitting element EL. In this simulation, the first capacitor Cst with a capacitance set to 150f and the second capacitor C1 with a capacitance set to 50f are used. The capacitance of the third capacitor C2 becomes 2.5F, 5f, and 10f. As the capacitance value of the third capacitor C2 increases, the slope of the I-V conduction curve decreases, so that the S factor S can increase. Therefore, the S factor for optimally driving the pixel circuit can be adjusted by the capacitance ratio of the second capacitor C1 and the third capacitor C2. In Figure 10 , "REF" is the reference capacitance value.

[0100] Figure 11is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure. Figure 12 is a waveform diagram showing a gate signal applied to Figure 11 the pixel circuit shown in Figures 13A to 13D is a circuit diagram showing the operation of the pixel circuit shown in FIG. 11 step by step.

[0101] Referring to Figures 11 to 13D , the pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements T1 to T5, and a first capacitor Cst, a second capacitor C1, and a third capacitor C2. The driving element DT and the switching elements T1 to T5 may be implemented by n-channel oxide TFTs.

[0102] The pixel circuit is connected to a VDD line to which a pixel driving voltage EVDD is applied, a VSS line to which a low-potential power supply voltage EVSS is applied, an INIT line to which an initialization voltage Vinit is applied, a REF line RL to which a reference voltage Vref is applied, a data line DL to which a data voltage Vdata is applied, and gate lines to which INI, SENSE1, SENSE2, SCAN, and EM are applied. The pixel driving voltage EVDD is a voltage higher than the low-potential power supply voltage EVSS. The initialization voltage Vinit is set to a constant voltage at which the driving element DT can be turned on within the data voltage range. The reference voltage Vref is set to a low-potential constant voltage close to the low-potential power supply voltage EVSS. The gate-on voltages VGH and VEH of the gate signals INI, SENSE1, SENSE2, SCAN, and EM can be set to voltages higher than the pixel driving voltage EVDD. The gate-off voltages VGL and VEL of the gate signals INI, SENSE1, SENSE2, SCAN, and EM can be set to voltages lower than the low-potential power supply voltage EVSS.

[0103] To drive Figure 11 the pixel circuit shown, the gate driver 120 may include a first shift register that sequentially outputs a scan pulse SCAN, a second shift register that sequentially outputs a first sense pulse SENSE1, a third shift register that sequentially outputs a second sense pulse SENSE2, a fourth shift register that sequentially outputs an initialization pulse INI, and a fifth shift register that sequentially outputs pulses of an EM signal EM.

[0104] The driving period of the pixel circuit can be divided into an initialization phase INIT, a sensing phase SENSE, a data writing phase WR, a boosting phase BOOST, and a light-emitting phase EMIS, as Figure 12As shown. In the initialization phase INIT, the pixel circuit is initialized. In the initialization phase INIT, the voltage at the second node DTG is initialized to the initialization voltage Vinit, and the voltages at the third node DTS and the fourth node DTB are initialized to the reference voltage Vref.

[0105] In the sensing phase SENSE, the threshold voltage Vth of the driving element DT that has been offset by the reverse bias voltage V BS is sensed and stored in the first capacitor Cst. In the data writing phase WR, the data voltage Vdata of the pixel data is applied to the second node DTG. In the sensing phase SENSE, the voltage at the second node DTG is maintained at the initialization voltage Vinit, and the voltages at the third node DTS and the fourth node DTB become Vinit - Vth, and the threshold voltage Vth of the driving element DT is sensed. In the data writing phase WR, the data voltage Vdata is applied to the second node DTG, and thus, the voltages at the third node DTS and the fourth node DTB are changed.

[0106] After the voltages at the floating second node DTG, third node DTS, and fourth node DTB rise in the boosting phase BOOST, the light-emitting element EL can emit light at a brightness corresponding to the gray value of the pixel data in the light-emitting phase EMIS. In the boosting phase BOOST, due to the capacitance transfer rate C / (C1 + C2), the voltage Vb at the fourth node DTB becomes lower than the voltage Vs at the third node DTS. In the boosting phase BOOST, assuming the voltage change amount at the third node DTS is "ΔV", the voltage at the fourth node DTB is In the light-emitting phase EMIS, the voltages at the second node DTG, third node DTS, and fourth node DTB can be maintained at the final voltages increased in the boosting phase BOOST. In the light-emitting phase EMIS, the driving element DT generates a current according to the gate-source voltage V GS At this time, the light-emitting element EL can emit light at a brightness corresponding to the gray value of the pixel data according to the current from the driving element DT.

[0107] The EM signal EM can maintain the strobe conduction voltage VEH in the initialization phase INIT, sensing phase SENSE, data writing phase WR, boosting phase BOOST, and light-emitting phase EMIS. Since the fifth switching element T5 is turned on when the EM signal EM is at the strobe conduction voltage VEH, the voltage at the first node DTD is the pixel driving voltage EVDD. In the data writing phase WR, the EM signal EM can be inverted from the strobe conduction voltage VGH to the strobe cutoff voltage VEL. Therefore, the fifth switching element T5 can be kept on or off in the data writing phase WR.

[0108] In the initialization phase INIT, initialization pulses INI, EM signal EM, first sensing pulse SENSE1, and second sensing pulse SENSE2 are generated with the strobe conduction voltages VGH and VEH. The scan pulse SCAN is at the strobe cut-off voltage VGL in the initialization phase INIT.

[0109] In the sensing phase SENSE, initialization pulses INIT, EM signal EM, and second sensing pulse SENSE2 are generated with the strobe conduction voltages VGH and VEH. In the sensing phase SENSE, the first sensing pulse SENSE1 and the scan pulse SCAN are at the strobe cut-off voltage VGL.

[0110] In the data write phase WR, the scan pulse SCAN is generated with the strobe conduction voltage VGH synchronized with the data voltage Vdata of the pixel data. The EM signal EM and the second sensing pulse SENSE2 can maintain the strobe conduction voltage VEH in the data write phase WR. The initialization pulse INI and the first sensing pulse SENSE1 are at the strobe cut-off voltages VGL and VEL in the data write phase WR.

[0111] In the boost phase BOOST, the strobe signals INI, SENSE1, SENSE2, and SCAN other than the EM signal EM are at the strobe cut-off voltage. In the emission phase EMIS, the EM signal EM maintains the strobe conduction voltage VEH, while the other strobe signals INI, SENSE1, SENSE2, and SCAN maintain the strobe cut-off voltage VGL.

[0112] In Figure 11 In the pixel circuit shown, the light-emitting element EL can be implemented with an OLED. The anode of the light-emitting element EL is connected to the third node DTS. The cathode of the light-emitting element EL is connected to the VSS line to which the low-potential power supply voltage EVSS is applied.

[0113] The driving element DT generates a current according to the gate-source voltage V GS to drive the light-emitting element EL. The driving element DT includes a first electrode connected to the first node DTD, a first gate electrode connected to the second node DTG, a second electrode connected to the third node DTS, and a second gate electrode connected to the fourth node DTB.

[0114] The first capacitor Cst is connected between the second node DTG and the third node DTS. The second capacitor C1 is connected between the third node DTS and the fourth node DTB. The third capacitor C2 is connected between the fourth node DTB and the VDD line to which the pixel driving voltage EVDD is applied. The third capacitor C2 can be connected between the first node DTD and the fourth node DTB.

[0115] The first switching element T1 is turned on according to the strobe conduction voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata during the data writing stage WR, and connects the data line DL to the second node DTG. During the data writing stage WR, the data voltage Vdata is applied to the second node DTG. The first switching element T1 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the first gate line to which the scan pulse SCAN is applied, and a second electrode connected to the second node DTG.

[0116] The second switching element T2 is turned on according to the strobe conduction voltage VGH of the initialization pulse INI during the initialization stage INIT and the sensing stage SENSE, and applies the initialization voltage Vinit to the second node DTG. The second switching element T2 includes a first electrode connected to the INIT line to which the initialization voltage Vinit is applied, a gate electrode connected to the second gate line to which the initialization pulse INI is applied, and a second electrode connected to the second node DTG.

[0117] The third switching element T3 is turned on according to the strobe conduction voltage VGH of the first sensing pulse SENSE1 during the initialization stage INIT, and connects the third node DTS to the REF line RL to which the reference voltage Vref is applied. The third switching element T3 includes a first electrode connected to the third node DTS, a gate electrode connected to the third gate line to which the first sensing pulse SENSE1 is applied, and a second electrode connected to the REF line RL.

[0118] The fourth switching element T4 is turned on according to the strobe conduction voltage VGH of the second sensing pulse SENSE2 during the initialization stage INIT, the sensing stage SENSE, and the data writing stage WR, and connects the third node DTS to the fourth node DTB. The fourth switching element T4 includes a first electrode connected to the third node DTS, a gate electrode connected to the fourth gate line to which the second sensing pulse SENSE2 is applied, and a second electrode connected to the fourth node DTB.

[0119] The fifth switching element T5 includes a first electrode connected to the VDD line to which the pixel driving voltage EVDD is applied, a gate electrode connected to the fifth gate line to which the EM signal EM is applied, and a second electrode connected to the first node DTD.

[0120] During the initialization stage INIT, as Figure 13A shown, the second switching element T2 to the fifth switching element T5 and the driving element DT are turned on, and the first switching element T1 is turned off. At this time, the light emitting element EL is not turned on.

[0121] In the sensing stage SENSE, as Figure 13B shown, the second switching element T2, the fourth switching element T4, and the fifth switching element T5 are kept in the on state, and the third switching element T3 is turned off. In the sensing stage SENSE, when the voltage at the third node DTS rises and the gate-source voltage V GS of the driving element DT reaches the threshold voltage Vth, the driving element DT is turned off. At this time, the voltages at the third node DTS and the fourth node DTB become Vinit - Vth, and this voltage is stored in the first capacitor Cst.

[0122] In the data writing stage WR, as Figure 13C shown, the first switching element T1 is turned on, and the second switching element T2 is turned off. At this time, the data voltage Vdata of the pixel data is applied to the second node DTG, so the voltage of the second node DTG changes to the data voltage Vdata. In the data writing stage WR, the fourth switching element T4 and the fifth switching element T5 are kept in the on state, and the third switching element T3 is kept in the off state.

[0123] During the boosting stage BOOST, the strobe signals INI, SCAN, SENSE1, and SENSE2 other than the EM signal EM are at the strobe cut-off voltage VGL. During the boosting stage BOOST, the voltages at the floating second node DTG, third node DTS, and fourth node DTB rise. At this time, because of the voltage loss due to the capacitance transfer rate, the voltage Vb at the fourth node DTB becomes lower than the voltage Vs at the third node DTS.

[0124] In the light emitting stage EMIS, as Figure 13D shown, the fifth switching element T5 is kept in the on state, and the first switching element T1 to the fourth switching element T4 are kept in the off state. At this time, the current generated according to the gate-source voltage Vgs of the driving element DT (i.e., the voltage between the second node and the third node) can be supplied to the light emitting element EL to cause the light emitting element EL to emit light. In the light emitting stage EMIS of driving the light emitting element EL in this way, the voltage Vb at the fourth node DTB is lower than the voltage Vs at the third node DTS.

[0125] Figure 14 is a circuit diagram showing a pixel circuit according to another embodiment of the present disclosure. Figure 15 is a waveform diagram showing the strobe signals applied to the Figure 14 pixel circuit shown in

[0126] Referring to Figure 14 and Figure 15, the pixel circuit includes a light-emitting element EL, a driving element DT for driving the light-emitting element EL, a plurality of switching elements T01 to T03, and a first capacitor Cst, a second capacitor C1, and a third capacitor C2. The driving element DT and the switching elements T01 to T03 can be implemented by n-channel oxide TFTs.

[0127] The pixel circuit is connected to a VDD line to which a pixel driving voltage EVDD is applied, a VSS line to which a low-potential power supply voltage EVSS is applied, a REF line RL to which a reference voltage Vref is applied, a data line DL to which a data voltage Vdata is applied, and a gate line to which a gate signal SENSE and SCAN are applied. The pixel driving voltage EVDD is a voltage higher than the low-potential power supply voltage EVSS. The reference voltage Vref is set to a low-potential constant voltage close to the low-potential power supply voltage EVSS. The gate-on voltage VGH of the gate signals SENSE and SCAN can be set to a voltage higher than the pixel driving voltage EVDD. The gate-off voltage VGL of the gate signals SENSE and SCAN can be set to a voltage lower than the low-potential power supply voltage EVSS.

[0128] To drive Figure 14 the pixel circuit shown, the gate driver 120 may include a shift register that sequentially outputs a scan pulse SCAN and a sense pulse SENSE. In another embodiment, the gate driver 120 may include a first shift register that sequentially outputs a scan pulse SCAN and a second shift register that sequentially outputs a sense pulse SENSE.

[0129] The driving period of the pixel circuit can be divided into a data writing stage WR, a boosting stage BOOST, and a light-emitting stage EMIS, as Figure 15 shown.

[0130] In the data writing stage WR, the data voltage Vdata of the pixel data is applied to the second node DTG. In the data writing stage WR, the data voltage Vdata is applied to the second node DTG, and the reference voltage Vref is applied to the third node DTS and the fourth node DTB.

[0131] After the voltages at the floating second node DTG, third node DTS, and fourth node DTB rise in the boosting stage BOOST, the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data in the light-emitting stage EMIS. In the boosting stage BOOST, due to the capacitance transfer rate C / (C1 + C2), the voltage Vb at the fourth node DTB becomes lower than the voltage Vs at the third node DTS. In the boosting stage BOOST, assuming the voltage change amount at the third node DTS is "ΔV", the voltage at the fourth node DTB is In the emission phase EMIS, the voltages at the second node DTG, the third node DTS, and the fourth node DTB can be maintained at the final voltage increased in the boost phase BOOST. In the emission phase EMIS, the driving element DT generates a current according to the gate-source voltage V GS At this time, the light-emitting element EL can emit light with a brightness corresponding to the gray value of the pixel data according to the current from the driving element DT.

[0132] In the data writing phase WR, the scan pulse SCAN and the sense pulse SENSE are generated simultaneously with the gate-on voltage VGH synchronized with the data voltage Vdata of the pixel data.

[0133] The scan pulse SCAN and the sense pulse SENSE are inverted to the gate-off voltage VGH in the boost phase BOOST and maintain the gate-off voltage VGL in the emission phase EMIS.

[0134] The light-emitting element EL can be implemented with an OLED. The anode of the light-emitting element EL is connected to the third node DTS. The cathode of the light-emitting element EL is connected to the VSS line to which the low-potential power supply voltage EVSS is applied.

[0135] The driving element DT generates a current according to the gate-source voltage V GS to drive the light-emitting element EL. The driving element DT includes a first electrode connected to the first node DTD, a first gate electrode connected to the second node DTG, a second electrode connected to the third node DTS, and a second gate electrode connected to the fourth node DTB.

[0136] The first capacitor Cst is connected between the second node DTG and the third node DTS. The second capacitor C1 is connected between the third node DTS and the fourth node DTB. The third capacitor C2 is connected between the fourth node DTB and the VDD line to which the pixel driving voltage EVDD is applied. The third capacitor C2 can be connected between the first node DTD and the fourth node DTB.

[0137] The first switching element T01 is turned on in the data writing phase WR according to the gate-on voltage VGH of the scan pulse SCAN synchronized with the data voltage Vdata, and connects the data line DL to the second node DTG. The data voltage Vdata is applied to the second node DTG in the data writing phase WR. The first switching element T01 includes a first electrode connected to the data line DL to which the data voltage Vdata is applied, a gate electrode connected to the first gate line to which the scan pulse SCAN is applied, and a second electrode connected to the second node DTG.

[0138] The second switching element T02 is turned on in the data write phase WR according to the strobe conduction voltage VGH of the sense pulse SENSE, and connects the third node DTS to the REF line RL to which the reference voltage Vref is applied. The second switching element T02 includes a first electrode connected to the third node DTS, a gate electrode connected to the second strobe line to which the sense pulse SENSE is applied, and a second electrode connected to the REF line RL.

[0139] The third switching element T03 is turned on in the data write phase WR according to the strobe conduction voltage VGH of the sense pulse SENSE, and connects the fourth node DTB to the REF line RL. The third switching element T03 includes a first electrode connected to the third node DTS, a gate electrode connected to the second strobe line to which the sense pulse SENSE is applied, and a second electrode connected to the REF line RL.

[0140] Figure 14 The pixel circuit shown in can be connected to an external compensation circuit. The external compensation circuit includes an ADC (analog-to-digital converter) that converts the sense voltage stored in the REF line RL connected to the pixel circuit into digital data. The sensed voltage may include electrical characteristics of the driving element DT, such as, for example, a threshold voltage and / or mobility. An integrator can be connected to the input terminal of the ADC. A timing controller 130 that applies the external compensation circuit can generate a compensation value for compensating for changes in the electrical characteristics of the driving element DT based on the sensed data input from the ADC, and add or multiply the compensation value to the pixel data of the input image, thereby compensating for changes in the electrical characteristics of the driving element DT. The ADC can be embedded in the data driver 110.

[0141] The objects to be achieved by the present disclosure, the means for achieving these objects, and the effects of the present disclosure described above do not specify the basic features of the claims, and thus, the scope of the claims is not limited to the disclosure of the present disclosure.

[0142] Although the embodiments of the present disclosure have been described in more detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the embodiments disclosed in the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above embodiments are illustrative in all respects and do not limit the present disclosure. The protection scope of the present disclosure should be interpreted based on the appended claims, and all technical concepts within the equivalent scope thereof should be interpreted as falling within the scope of the present disclosure.

[0143] Cross-reference to related applications

[0144] This application claims the priority and benefit of Korean Patent Application No. 10-2021-0089997, filed on July 8, 2021, and Korean Patent Application No. 10-2021-0166801, filed on November 29, 2021, the disclosures of which are incorporated herein by reference in their entireties.

Claims

1. A pixel circuit, the pixel circuit comprising: A driving element, which includes a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and the driving element is configured to supply current to a light-emitting element; A first switching element, which is configured to turn on according to the strobe conduction voltage of a scan pulse and provide a data voltage to the second node connected to the first gate electrode; A first capacitor, which is connected between the second node and the third node; A second capacitor, which is connected between the third node and the fourth node; And A third capacitor, which is connected between the fourth node and the first node, or connected between the fourth node and a first power supply line to which the pixel driving voltage is applied.

2. The pixel circuit according to claim 1, wherein, The driving element is implemented with a double-gate structure.

3. The pixel circuit according to claim 1, wherein, The capacitance of each of the second capacitor and the third capacitor is less than the capacitance of the first capacitor, and The capacitance of the second capacitor is greater than the capacitance of the third capacitor.

4. The pixel circuit according to claim 3, wherein, The voltage at the fourth node is determined according to the product of the voltage at the third node and the capacitance transfer rate, the capacitance transfer rate is determined according to the capacitances of the second capacitor and the third capacitor, and The voltage at the third node changes according to the data voltage applied to the second node.

5. The pixel circuit according to claim 1, wherein, When driving the light-emitting element, the voltage at the fourth node is lower than the voltage at the third node.

6. The pixel circuit according to claim 5, wherein, The lower the voltage at the fourth node applied to the second gate electrode is compared with the voltage at the third node, the more positively the threshold voltage of the driving element shifts.

7. The pixel circuit according to claim 1, wherein, The first switching element includes a first electrode connected to a data line to which the data voltage is applied, a gate electrode connected to a first gate line to which the scan pulse is applied, and a second electrode connected to the second node.

8. The pixel circuit according to claim 7, the pixel circuit further comprising: A second switching element, which is configured to turn on according to the strobe conduction voltage of an initialization pulse and apply an initialization voltage to the second node; A third switching element, which is configured to turn on according to the strobe conduction voltage of a first sensing pulse and connect the third node to a second power supply line to which a reference voltage is applied; A fourth switching element, which is configured to turn on according to the strobe conduction voltage of a second sensing pulse and connect the third node to the fourth node; And A fifth switching element, which is configured to turn on according to the strobe conduction voltage of a light emission control signal and apply the pixel driving voltage to the first node.

9. The pixel circuit according to claim 8, wherein, The second switching element includes a first electrode connected to a third power supply line to which the initialization voltage is applied, a gate electrode connected to a second gate line to which the initialization pulse is applied, and a second electrode connected to the second node, The third switching element includes a first electrode connected to the third node, a gate electrode connected to a third gate line to which the first sensing pulse is applied, and a second electrode connected to the second power supply line to which the reference voltage is applied, The fourth switching element includes a first electrode connected to the third node, a gate electrode connected to a fourth gate line to which the second sensing pulse is applied, and a second electrode connected to the fourth node, and the fifth switching element includes a first electrode connected to a first power line to which the pixel driving voltage is applied, a gate electrode connected to a fifth gate line to which the light emission control signal is applied, and a second electrode connected to the first node.

10. The pixel circuit according to claim 9, wherein, The driving period of the pixel circuit is divided into an initialization phase, a sensing phase, a data writing phase, a boosting phase, and a light emission phase, in the initialization phase, the initialization pulse, the light emission control signal, the first sensing pulse, and the second sensing pulse are generated at the gate-on voltage, and the voltage of the scan pulse is the gate-off voltage, in the sensing phase, the initialization pulse, the light emission control signal, and the second sensing pulse are generated at the gate-on voltage, and the voltages of the first sensing pulse and the scan pulse are the gate-off voltage, in the data writing phase, the scan pulse is generated at the gate-on voltage synchronized with the data voltage, the light emission control signal and the second sensing pulse are generated at the gate-on voltage, and the initialization pulse and the first sensing pulse are at the gate-off voltage, in the boosting phase, the light emission control signal is generated at the gate-on voltage, and the voltages of the initialization pulse, the first sensing pulse, the second sensing pulse, and the scan pulse are the gate-off voltage, in the light emission phase, the light emission control signal is generated at the gate-on voltage, and the voltages of the initialization pulse, the first sensing pulse, the second sensing pulse, and the scan pulse are the gate-off voltage.

11. The pixel circuit according to claim 10, wherein, The light emitting element emits light with a luminance corresponding to the gray value of the pixel data according to the current from the driving element.

12. The pixel circuit according to claim 7, wherein the pixel circuit further comprises: a second switching element configured to turn on according to the gate-on voltage of the sensing pulse and connect the third node to a second power line to which a reference voltage is applied; and a third switching element configured to turn on according to the gate-on voltage of the sensing pulse and connect the fourth node to the second power line.

13. The pixel circuit according to claim 12, wherein, The second switching element includes a first electrode connected to the third node, a gate electrode connected to a second gate line to which the sensing pulse is applied, and a second electrode connected to the second power line to which the reference voltage is applied, and the third switching element includes a first electrode connected to the fourth node, a gate electrode connected to the second gate line, and a second electrode connected to the second power line.

14. The pixel circuit according to claim 12, wherein, The driving period of the pixel circuit is divided into a data writing phase, a boosting phase, and a light emission phase, in the data writing phase, the scan pulse and the sensing pulse are generated at the gate-on voltage synchronized with the data voltage, and During the boosting stage and the light emitting stage, the voltages of the scan pulse and the sense pulse are gate cut-off voltages.

15. A display device, comprising: A display panel, on which a plurality of data lines, a plurality of gate lines intersecting with the plurality of data lines, a plurality of power supply lines, and a plurality of pixel circuits connected to the data lines, the gate lines, and the power supply lines are provided; A data driver configured to provide a data voltage of pixel data to the data lines; And A gate driver configured to provide a gate signal to the gate lines, wherein each of the pixel circuits includes: A driving element including a first electrode connected to a first node to which a pixel driving voltage is applied, a first gate electrode connected to a second node, a second electrode connected to a third node, and a second gate electrode connected to a fourth node, and the driving element is configured to supply current to a light emitting element; A first switching element configured to turn on according to the gate conduction voltage of the gate signal and provide a data voltage to the second node connected to the first gate electrode; A first capacitor connected between the second node and the third node; A second capacitor connected between the third node and the fourth node; and A third capacitor connected between the fourth node and the first node, or connected between the fourth node and a first power supply line to which the pixel driving voltage is applied.

16. The display device according to claim 15, wherein, The driving element is implemented with a double-gate structure.

17. The display device according to claim 15, wherein, The capacitance of each of the second capacitor and the third capacitor is smaller than the capacitance of the first capacitor, and The capacitance of the second capacitor is larger than the capacitance of the third capacitor.

18. The display device according to claim 17, wherein, The voltage at the fourth node is determined according to the product of the voltage at the third node and the capacitance transfer rate, the capacitance transfer rate is determined according to the capacitances of the second capacitor and the third capacitor, and The voltage at the third node changes according to the data voltage applied to the second node.

19. The display device according to claim 15, wherein, When driving the light emitting element, the voltage at the fourth node is lower than the voltage at the third node.

20. The display device according to claim 19, wherein, The lower the voltage at the fourth node applied to the second gate electrode is compared with the voltage at the third node, the more positively the threshold voltage of the driving element shifts.

21. The display device according to claim 15, wherein, The gate signal includes: An initialization pulse, a first sense pulse, a second sense pulse, a scan pulse, and a light emission control signal, The pixel circuit further includes: A second switching element configured to turn on according to the gate conduction voltage of the initialization pulse and apply an initialization voltage to the second node; A third switching element configured to turn on according to the gate conduction voltage of the first sense pulse and connect the third node to a second power supply line to which a reference voltage is applied; A fourth switching element configured to turn on according to the gate conduction voltage of the second sense pulse and connect the third node to the fourth node; and A fifth switching element configured to turn on according to the gate conduction voltage of the light emission control signal and apply the pixel driving voltage to the first node, and Among them, the first switching element is turned on according to the strobe conduction voltage of the scan pulse, and the data voltage is applied to the second node.

22. The display device according to claim 21, wherein, The driving period of the pixel circuit is divided into an initialization stage, a sensing stage, a data writing stage, a boosting stage, and a light emitting stage. In the initialization stage, the initialization pulse, the light emission control signal, the first sensing pulse, and the second sensing pulse are generated with the strobe conduction voltage, and the voltage of the scan pulse is the strobe cut-off voltage. In the sensing stage, the initialization pulse, the light emission control signal, and the second sensing pulse are generated with the strobe conduction voltage, and the voltages of the first sensing pulse and the scan pulse are the strobe cut-off voltage. In the data writing stage, the scan pulse is generated with the strobe conduction voltage synchronized with the data voltage, the light emission control signal and the second sensing pulse are generated with the strobe conduction voltage, and the initialization pulse and the first sensing pulse are at the strobe cut-off voltage. In the boosting stage, the light emission control signal is generated with the strobe conduction voltage, and the voltages of the initialization pulse, the first sensing pulse, the second sensing pulse, and the scan pulse are the strobe cut-off voltage. In the light emitting stage, the light emission control signal is generated with the strobe conduction voltage, and the voltages of the initialization pulse, the first sensing pulse, the second sensing pulse, and the scan pulse are the strobe cut-off voltage.

23. The display device according to claim 22, wherein, The light emitting element emits light with a brightness corresponding to the gray value of the pixel data according to the current from the driving element.

24. The display device according to claim 15, wherein, The strobe signal includes a scan pulse and a sensing pulse. The pixel circuit further includes: A second switching element configured to be turned on according to the strobe conduction voltage of the sensing pulse and connect the third node to the second power supply line to which a reference voltage is applied; and A third switching element configured to be turned on according to the strobe conduction voltage of the sensing pulse and connect the fourth node to the second power supply line, and Among them, the first switching element is turned on according to the strobe conduction voltage of the scan pulse, and the data voltage is applied to the second node.

25. The display device according to claim 24, wherein, The driving period of the pixel circuit is divided into a data writing stage, a boosting stage, and a light emitting stage. In the data writing stage, the scan pulse and the sensing pulse are generated with the strobe conduction voltage synchronized with the data voltage, and In the boosting stage and the light emitting stage, the voltages of the scan pulse and the sensing pulse are the strobe cut-off voltage.

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