Compilation method, compilation circuit, mode register and memory

Abstract

Embodiments of the present application provide a compilation method, compilation circuit, mode register, and memory. The compilation method includes: receiving a signal to be compiled and a resistance matching signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value. Thus, by presetting compilation rules for the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem of the mode register being unable to operate after receiving the reserved code. In addition, depending on the resistance matching signal, the compilation result of the reserved code varies, allowing the mode register to adjust the resistance value of the resistor in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms.

Description

Technical Field

[0001] The present application relates to the technical field of dynamic random access memory, and in particular to a compilation method, a compilation circuit, a mode register and a memory. Background Art

[0002] The mode register is a key component of dynamic random access memory (DRAM), primarily used to set DRAM parameters. Specifically, each mode register contains multiple code bits, and the levels of different code bits, after decoding, correspond to different parameter values.

[0003] However, the current mode register has poor compatibility with different application environments, resulting in poor DRAM performance. Summary of the Invention

[0004] The present application provides a compilation method, a compilation circuit, a mode register and a memory, which improve the compatibility of the mode register for different application platforms by pre-setting compilation rules of reserved codes related to terminal resistance.

[0005] The technical solution of this application is achieved as follows:

[0006] In a first aspect, an embodiment of the present application provides a compilation method, the method comprising:

[0007] receiving a signal to be compiled and a resistance matching signal;

[0008] Compile the signal to be compiled to obtain a compilation result signal;

[0009] In a case where the signal to be compiled is a reserved code, a compatibility selection process is performed on the compiled result signal based on the resistance matching signal to determine a first compiled value.

[0010] In a second aspect, an embodiment of the present application provides a compilation circuit, the compilation circuit including:

[0011] Signal input terminal, used for receiving the signal to be compiled and the resistance matching signal;

[0012] A compilation unit, used for compiling a signal to be compiled to obtain a compilation result signal;

[0013] The compatible selection unit is configured to perform compatible selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value when the signal to be compiled is a reserved code.

[0014] In a third aspect, an embodiment of the present application provides a mode register, which at least includes the compilation circuit as in the second aspect.

[0015] In a fourth aspect, an embodiment of the present application provides a memory, which at least includes the mode register as described in the third aspect.

[0016] The present application provides a compilation method, a compilation circuit, a mode register, and a memory. The compilation method includes: receiving a signal to be compiled and a resistance matching signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value. The compilation circuit includes a signal input terminal for receiving the signal to be compiled and the resistance matching signal; a compilation unit for compiling the signal to be compiled to obtain a compilation result signal; and a compatibility selection unit for performing compatibility selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value if the signal to be compiled is a reserved code. Thus, by presetting the compilation rules for the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem of the mode register not being able to work after receiving the reserved code. In addition, the compilation results of the reserved code vary depending on the resistance matching signal, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A flowchart of a compilation method provided in an embodiment of the present application;

[0018] Figure 2 A schematic diagram of the structure of a compilation circuit provided in an embodiment of the present application;

[0019] Figure 3 A detailed structural diagram of a compilation circuit provided for related technology;

[0020] Figure 4 A detailed structural diagram of a compilation circuit provided in an embodiment of the present application;

[0021] Figure 5 A detailed structural diagram of another compilation circuit provided for related technology;

[0022] Figure 6 A detailed structural diagram of another compilation circuit provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the structure of a mode register provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of the structure of a memory provided in an embodiment of the present application. DETAILED DESCRIPTION

[0025] The following will be combined with the accompanying drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. It should be understood that the specific embodiments described herein are only used to explain the related applications and are not intended to limit the applications. It should also be noted that for ease of description, only the parts relevant to the related applications are shown in the drawings.

[0026] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those skilled in the art to which this application pertains. The terms used herein are for the purpose of describing the embodiments of this application only and are not intended to limit this application.

[0027] In the following description, reference is made to “some embodiments”, which describes a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0028] It should be pointed out that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged with a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0029] DRAM contains multiple mode registers, which are used to set different DRAM functions and operating modes. Specifically, each mode register contains multiple input bits (also called address codes, address bits, etc.). The level states of different input bits constitute the decoded signal, which is decoded to determine the corresponding parameter value.

[0030] In actual applications, users send a Mode Register Set Command (MRS Command) to the DRAM through the DRAM controller to set each mode register. Because the Basic Input Output System (BIOS) settings in different DRAM controllers vary, the mode registers offer different optional parameters to suit various application platforms.

[0031] The fourth edition of the Double Data Rate SDRAM (DDR SDRAM, DDR4) Technical Standard Specification (SPEC) specifies the compilation rules between input bit combinations and parameter values ​​in the mode register. In addition to the specified input bit combinations, there are also some unused input bit combinations, known as reserved codes, for designers to use when they have special needs.

[0032] Generally speaking, in most cases where there's no special need, reserved codes aren't enabled. Consequently, DRAM doesn't have circuitry to compile these reserved codes. However, because a DRAM controller may need to test and control multiple different DRAMs and isn't designed specifically for a single DRAM, it might issue control commands involving reserved codes. If the DRAM doesn't have circuitry to compile the reserved codes, and the DRAM receives a reserved code from the DRAM controller, the DRAM's mode registers won't function, reducing the DRAM's compatibility with different application platforms.

[0033] Specifically, according to the DDR4 specification, there are two settings related to the resistance value in the mode register, namely: (1) the output driver resistance (Ron) setting item, also known as Output Driver Impedance Control, see Table 1; (2) the terminal resistance (RTT_WR) setting item, see Table 2.

[0034] For example, the DRAM Controller in a company's test platform uses the reserved codes in the Ron or RTT_WR settings to test the DRAM. However, since the mode register in the DRAM does not have the compilation circuit for these reserved codes, the entire test will fail to start.

[0035] Table 1

[0036]

[0037] Table 2

[0038]

[0039]

[0040] In particular, Tables 1 and 2 are all from the SPEC part of DRAM DDR4. A1, A2, A11, A10 and A19 are bits in the corresponding mode register. The meanings of other related parameters can be found in the DDR4 file, and the meanings of the related parameters do not affect the understanding of the embodiments of this application, so they will not be described in detail here.

[0041] Based on this, an embodiment of the present application provides a compilation method, the basic concept of which is: receiving a signal to be compiled and a resistance matching signal; compiling the signal to be compiled to obtain a compilation result signal; when the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value. In this way, by pre-setting the compilation rules for the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem of the mode register not being able to work after receiving the reserved code; in addition, the compilation results of the reserved code are different depending on the resistance matching signal, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms; in addition, because the reserved code provides a more flexible resistance value matching solution, the control solution ultimately delivered to the user can be adjusted based on the test results, thereby providing better read and write performance.

[0042] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0043] In one embodiment of the present application, see Figure 1 , which shows a flow chart of a compilation method provided by an embodiment of the present application. Figure 1 As shown, the method may include:

[0044] S101: Receive a signal to be compiled and a resistance matching signal.

[0045] It should be noted that the compilation method provided in the embodiment of the present application is applied to the mode register of the DRAM.

[0046] In order to match the BIOS settings of the DRAM Controller, the DRAM mode register provides some adjustable parameters, so that the DRAM Controller can send MRS commands to the DRAM to set the mode register in the DRAM. The compilation method provided in the embodiment of the present application is specifically applied to the parameter compilation circuit in the DRAM mode register.

[0047] In the DRAM hardware structure, the output driver circuit and the terminal resistor share a set of pull-up resistors. When the DRAM reads data, this pull-up resistor serves as the output resistor Ron, and its resistance must meet the requirements set by the SPEC for Ron (or Output Driver Impedance). When writing data to the DRAM, it serves as the terminal resistor Rtt_WR, and must meet the requirements set by the SPEC for Rtt_WR. In addition, the resistance values ​​of both the output resistor Ron and the terminal resistor Rtt_WR are not fixed, and multiple optional resistance ranges are required to facilitate matching the DRAM with different DRAM controllers.

[0048] Therefore, the mode register contains some settings related to resistor values, such as the Ron setting and the RTT_WR setting. For these settings, the mode register contains multiple input bits. The DDR4 SPEC specifies detailed encoding rules for these input bits, such as specific input bit value combinations and the corresponding compiled values. These clearly defined input bit value combinations are generally referred to as control codes (or non-reserved codes). In addition, the DDR4 SPEC also contains some unenabled input bit value combinations, meaning that the DDR4 SPEC does not specify the compiled values ​​for these input bit value combinations. These input bit value combinations are generally referred to as reserved codes.

[0049] In related technologies, the mode register hardware system lacks a compilation circuit for reserved codes. Consequently, if a command involving a reserved code is received, the mode register may not function. To address this issue, embodiments of the present application provide a compilation method that pre-encodes and decodes the reserved code in a setting item involving a resistor value, thereby achieving better compatibility with different DRAM controllers.

[0050] The compilation method provided in the embodiment of the present application requires receiving a signal to be compiled and a resistance matching signal. Here, the signal to be compiled is determined based on the MRS command sent by the DRAM Controller, and the resistance matching signal is used to indicate the resistance mode in the DRAM, such as high resistance mode or low resistance mode.

[0051] S102: Compile the signal to be compiled to obtain a compilation result signal.

[0052] It should be noted that the signal to be compiled is compiled to obtain a compilation result signal.

[0053] Here, due to the hardware improvement of the compilation circuit, that is, the compilation part for reserved codes is pre-designed in the compilation circuit, even if the signal to be compiled is a reserved code, the compilation result signal can be obtained without causing direct DRAM shutdown.

[0054] S103: When the signal to be compiled is a reserved code, perform compatibility selection processing on the compiled result signal based on the resistance matching signal to determine a first compiled value.

[0055] It should be noted that in the mode register, there are multiple setting items with different functions, and each setting item may have a reserved code. The reserved codes in the embodiments of the present application particularly relate to those setting items related to the resistance value of the DRAM, such as the first reserved code (output resistance Ron reserved code) and the second reserved code (terminal resistance Rtt_WR reserved code).

[0056] Because the parameter values ​​of these settings are used to adjust the resistance of the resistors for compatibility with the application platform, if the signal to be programmed is a reserved code, the first programming value must be determined based on the resistance matching signal to ensure that the DRAM and DRAM controller are aligned. In other words, if the signal to be programmed is a reserved code, the resistance matching signal must also be considered to determine the final programming value.

[0057] Specifically, depending on the resistance matching signal, the compilation value corresponding to the same reserved code may be different. Therefore, in some embodiments, performing compatibility selection processing on the compilation result signal based on the resistance matching signal to determine the first compilation value may include:

[0058] If the resistance matching signal is a first level signal, determining the first compiled value to be a first preset value corresponding to the reserved code;

[0059] If the resistance matching signal is a second level signal, the first compiled value is determined to be a second preset value corresponding to the reserved code.

[0060] It should be noted that, in the embodiment of the present application, each reserved code corresponds to two compiled values ​​to better enable compatibility with different control platforms.

[0061] If the resistance matching signal is a first level signal, the first compiled value is determined to be a first preset value corresponding to the reserved code; if the resistance matching signal is a second level signal, the first compiled value is determined to be a second preset value corresponding to the reserved code. Here, the first preset value and the second preset value are different.

[0062] Here, the first-level signal and the second-level signal have different level states. For example, the first-level signal can be a high-level signal, also represented by "1," while the second-level signal can be a low-level signal, also represented by "0." Specifically, the level state of the resistance matching signal is used to indicate the desired resistance state of the pull-up resistor. For example, a low-level signal can indicate a high-resistance state, while a high-level signal can indicate a low-resistance state.

[0063] In this way, when the signal to be compiled is a reserved code, the first compiled value can be determined to be the first preset value or the second preset value based on the reserved code itself and the resistance matching signal, thereby providing different output resistance values / terminal resistance values ​​to achieve matching between DRAM and different DRAM Controllers.

[0064] Furthermore, in some embodiments, when the signal to be compiled is a non-reserved code, the method may further include:

[0065] A second compiled value is determined according to the compiled result signal.

[0066] It should be noted that, for those non-reserved codes clearly defined by JEDEC DDR4 SPEC, the second compilation value may be directly determined according to the compilation result signal.

[0067] It should be understood that for non-reserved codes, the coding value only needs to be determined based on the content of the non-reserved code itself; for reserved codes, the coding value needs to be determined based on the resistance matching signal and the reserved code itself.

[0068] Furthermore, the JEDEC DDR4 SPEC does not explicitly define the reserved code's compiled value, so the reserved code's compiled value can be selected and determined based on the actual application scenario. The following is only an exemplary design solution.

[0069] In some embodiments, before receiving the signal to be compiled and the resistance matching signal, the method further includes:

[0070] The value of the first compiled value is determined according to the value of the second compiled value.

[0071] It should be noted that, for a specific setting item, the value of the first compilation value can be designed accordingly according to the compilation value (ie, the value of the second compilation value) clearly specified in the JEDEC DDR4 SPEC.

[0072] In a specific embodiment, determining the value of the first compiled value by taking the value of the second compiled value may include:

[0073] Select from the values ​​of the second compiled value to obtain at least one candidate value;

[0074] At least one candidate value is determined as a value of the first compiled value.

[0075] It should be noted that in some embodiments, candidate values ​​can be selected from the values ​​of the second compiled value and used as the values ​​of the first compiled value. In this way, by using some values ​​of the second compiled value as the values ​​of the first compiled value, the output terminals and some circuits of non-reserved codes can be reused during hardware circuit design, thereby saving circuit layout area.

[0076] Here, the specific selection rules can be determined according to the actual application scenario and are not limited in the embodiments of the present application. For example, the values ​​of the second compiled value that are adapted to extreme conditions can be used as candidate values ​​to maximize the compatibility range of the DRAM. For another example, in some embodiments, when the number of the reserved codes is a, the method can further include:

[0077] Determine a first candidate value and 1 second candidate value according to the at least one candidate value;

[0078] Determining the i-th first candidate value as the first preset value corresponding to the i-th reserved code, and determining the second candidate value as the second preset value corresponding to the i-th reserved code;

[0079] Wherein, i and a are positive integers, and i is less than or equal to a.

[0080] It should be noted that if there are a reserved codes, (a+1) candidate values ​​can be selected from the second compiled value, specifically a first candidate values ​​and 1 second candidate value. Then, the i-th first candidate value is determined as the first preset value corresponding to the i-th reserved code, and the second candidate value is determined as the second preset value corresponding to the i-th reserved code.

[0081] For example, for the RTT_WR setting item, as shown in Table 2 above, the second compiled value is: Dynamic ODT Off, RZQ / 2, RZQ / 1, Hi-Z, RZQ / 3. The meanings of the above parameters can be found in the JEDEC DDR4 standard document and will not be described in detail here. At this time, the following candidate values ​​are selected from the second compiled value: Dynamic ODT Off, RZQ / 2, RZQ / 1 and RZQ / 3; then, the first preset values ​​corresponding to the three different reserved codes in the RTT_WR setting item are respectively determined to be RZQ / 2, RZQ / 1 and RZQ / 3 (the specific corresponding relationship can be flexibly determined), and the second preset values ​​corresponding to the three different reserved codes are all determined to be Dynamic ODT Off. The details are shown in Table 3 below.

[0082] Table 3

[0083] A11 A10 A9 RTT_WR 0 0 0 Dynamic ODT Off 0 0 1 RZQ / 2 0 1 0 RZQ / 1 0 1 1 Hi-Z 1 0 0 RZQ / 3 1 0 1 RZQ / 2 or Dynamic ODT Off 1 1 0 RZQ / 1 or Dynamic ODT Off 1 1 1 RZQ / 3 or Dynamic ODT Off

[0084] In another specific embodiment, determining the value of the first compiled value according to the value of the second compiled value may include:

[0085] Selecting from the values ​​of the second compiled value to obtain at least one candidate value;

[0086] Adjusting the at least one candidate value to obtain at least one adjusted value;

[0087] The at least one candidate value and the at least one adjusted value are determined as values ​​of the first compiled value.

[0088] It should be noted that after determining the candidate value from the second compiled value, the candidate value can be adjusted to obtain the adjusted value, and the candidate value and the adjusted value are determined as the first compiled value. In this way, the compiled values ​​of the setting item are actually more than those specified by the JEDEC DDR4 SPEC, thus providing more resistor matching solutions.

[0089] Here, the specific adjustment method can be determined according to the actual application scenario and is not specifically limited in the embodiments of the present application. For example, in some embodiments, when the number of the reserved codes is a, the number of the at least one candidate value is a, and the number of the at least one adjusted value is a;

[0090] Accordingly, the method may further include:

[0091] Determining the i-th candidate value as the first preset value corresponding to the i-th reserved code, and determining the i-th adjusted value as the second preset value corresponding to the i-th reserved code;

[0092] Wherein, i and a are positive integers, and i is less than or equal to a.

[0093] It should be noted that if there are a reserved codes, a candidate values ​​can be selected from the second compiled value, and the a candidate values ​​can be adjusted to obtain a adjusted values. At this time, the a candidate values ​​are respectively determined as the first preset values ​​of the a reserved codes, and the a adjusted values ​​are respectively determined as the second preset values ​​of the a reserved codes.

[0094] In particular, for the Ron setting item, as shown in Table 1 above, the second compiled value is RZQ / 5 or RZQ / 7. RZQ represents a calibrated standard resistance value, which is 240 ohms in the DDR4 JEDEC SPEC. RZQ / 5 represents the standard resistance value divided by 5, and RZQ / 7 represents the standard resistance value divided by 7. Based on this, in some embodiments, when the reserved code is the first reserved code (Ron reserved code), adjusting the at least one candidate value to obtain at least one adjusted value may include:

[0095] If the i-th candidate value is the ratio of the preset resistance value to n, then the i-th adjustment value is determined to be the ratio of the preset resistance value to (n+1); wherein i and n are positive integers.

[0096] It should be noted that a specific adjustment method is as follows: if the candidate value is the ratio of the preset resistance value to n, then the corresponding adjustment value of the candidate value is the ratio of the preset resistance value to (n+1).

[0097] That is, for the Ron setting item, as shown in Table 1 above, the second coding value is RZQ / 5 or RZQ / 7, and the Ron setting item also includes two reserved codes. In this case, the second coding value is actually a candidate value. Next, the adjusted value corresponding to RZQ / 5 is determined to be RZQ / 6, and the adjusted value corresponding to RZQ / 7 is determined to be RZQ / 8. Finally, the first and second preset values ​​of one reserved code are determined to be RZQ / 5 and RZQ / 6, respectively; and the first and second preset values ​​of the other reserved code are determined to be RZQ / 7 and RZQ / 8, respectively. This is shown in Table 4 below.

[0098] Table 4

[0099]

[0100] Here, the feasibility analysis of adjusting RZQ / n to RZQ / (n+1) is as follows.

[0101] When reading data from the DRAM, the output driver resistance Ron is reduced within the allowable range specified by the DDR4 specification, thereby enhancing drive capability and improving output signal integrity. The DDR4 JEDEC specification specifies two output resistor Ron values: 34 ohms (Ω) and 48 Ω. Furthermore, the calibrated standard resistance RZQ in DRAM is 240 Ω.

[0102] For the 34 ohm output resistance Ron range, within the allowable deviation range, the minimum Ron resistance value is ≥ 34 × 0.83 = 28.22 Ω. Although the SPEC recommended parameter is RZQ / 7 = 240 / 7 = 34.29 Ω, RZQ / 8 = 240 / 8 = 30 Ω also meets the allowable deviation requirements of SPEC.

[0103] For the 48-ohm output resistance Ron range, within the allowable deviation range, the minimum Ron resistance value is ≥ 48 × 0.83 = 39.84 Ω. Although the SPEC recommended parameter is RZQ / 5 = 240 / 5 = 48 Ω, RZQ / 6 = 240 / 6 = 40 Ω also meets the allowable deviation requirements of SPEC.

[0104] Here, 0.83 is the coefficient of the minimum Ron resistance value within the allowable deviation range specified in the DDR4 JEDEC SPEC compared to the recommended resistance value.

[0105] From the above, it can be seen that the Ron resistance value obtained by RZQ / (N+1) complies with the requirements of SPEC.

[0106] In particular, in DRAM manufacturing processes, the calibrated standard resistance value RZQ may not be exactly 240Ω. Therefore, during testing, RZQ / (N+1) may be closer to the SREC standard than RZQ / N. In this case, you can enable reserved code, such as modifying the preset control program or hardware circuit to provide a better resistance matching solution.

[0107] In this way, by pre-setting the compilation rules of the reserved code, the mode register can compile the reserved code sent by the application platform, avoiding the problem that the mode register does not work after receiving the reserved code. In addition, the compilation results of the reserved code are different according to the different resistance matching signals, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms. In addition, because the reserved code provides a more flexible resistance value matching solution, the control solution finally delivered to the user can be adjusted according to the test results, thereby providing better read and write performance.

[0108] The compilation method is further described below in conjunction with a specific compilation circuit structure.

[0109] In some embodiments, the compiling circuit may include a first compiling unit, a second compiling unit, and a compatible selection unit. The method may further include:

[0110] In a case where the signal to be coded is a reserved code, determining a first coding value by the first coding unit and the compatible selection unit;

[0111] In a case where the signal to be coded is a non-reserved code, a second coding value is determined by the second coding unit.

[0112] It should be noted that the compilation circuit can be divided into a first compilation unit, a second compilation unit, and a compatible selection unit. The first compilation unit is a unit that compiles for reserved codes. Since the compilation value of a reserved code depends on the compilation result signal and the resistance matching signal, if the signal to be compiled is a reserved code, the first compilation value is determined by the first compilation unit and the compatible selection unit. The second compilation unit is a unit that compiles for non-reserved codes. If the signal to be compiled is a non-reserved code, the second compilation unit directly determines the second compilation value.

[0113] Furthermore, in some embodiments, the method may further include:

[0114] Determining a first category of non-reserved codes and a second category of non-reserved codes; wherein the first category of non-reserved codes includes non-reserved codes having the same compiled value as the reserved code, and the second category of non-reserved codes includes remaining non-reserved codes in the non-reserved codes except the first category of non-reserved codes;

[0115] Accordingly, the second compilation unit includes a second-first compilation unit and a second-second compilation unit. The method may further include:

[0116] When the signal to be coded is a reserved code or a first type of non-reserved code, determining the first coding value by the first coding unit, the second-first coding unit, and the compatible selection unit;

[0117] When the signal to be coded is a second-type non-reserved code, a third coding value is determined by the second second coding unit; wherein the third coding value is the remaining coding value of the second coding value except the first coding value.

[0118] It should be noted that, to achieve circuit reuse, non-reserved codes are divided into a first category of non-reserved codes and a second category of non-reserved codes. The first category of non-reserved codes includes non-reserved codes that have the same programming value as a reserved code, and the second category of non-reserved codes includes non-reserved codes other than the first category of non-reserved codes. In other words, the programming value of the first category of non-reserved codes is also the programming value of the reserved code, while the programming value of the second category of non-reserved codes merely serves as the programming value of the non-reserved code.

[0119] Correspondingly, the second coding value can also be categorized as a first coding value and a third coding value. The third coding value refers to the portion of the second coding value excluding the first coding value. In other words, the first coding value serves as a coding value for both the first-category non-reserved code and the reserved code, while the third coding value serves only as a coding value for the non-reserved code.

[0120] On this basis, the second compilation unit is divided into a second-first compilation unit and a second-second compilation unit; wherein the second-first compilation unit is used to compile the first type of non-reserved code, and the second-second compilation unit is used to compile the second type of non-reserved code. In this case, the compilation process may specifically include:

[0121] For the reserved code or the first type of non-reserved code, the first coding value is determined by the first coding unit, the second-first coding unit, and the compatible selection unit; for the second type of non-reserved code, the third coding value is directly determined by the second-second coding unit.

[0122] In this way, the compilation circuit of the reserved code reuses part of the compilation circuit and output end of the first type of non-reserved code, which can save circuit area.

[0123] Furthermore, in some embodiments, determining the first coding value by the first coding unit, the second-first coding unit, and the compatible selection unit may include:

[0124] Compiling the signal to be compiled by the first compiling unit to obtain a first compiled signal;

[0125] performing compilation processing on the signal to be compiled by the second-first compilation unit to obtain a second-first compiled signal;

[0126] The compatible selection unit performs a logic calculation on the first compilation processing signal, the second-first compilation processing signal, and the resistance matching signal, and determines the first compilation value according to the logic calculation result.

[0127] It should be noted that an example of a circuit processing process for determining the first compiled value is as follows:

[0128] (1) The first compiling unit compiles the signal to be compiled to obtain a first compiling signal. Here, the first compiling signal can indicate which reserved code the signal to be compiled belongs to (because the compiling value of the reserved code needs to be determined based on the reserved code itself and the resistance matching signal).

[0129] (2) The second-first coding unit compiles the signal to be compiled to obtain a second-first coding signal. Here, the second-first coding signal can not only indicate whether the signal to be compiled is a first-class non-reserved code, but also indicate which first-class non-reserved code it is (because the coding value of the non-reserved code needs to be determined based on the non-reserved code itself).

[0130] (3) Performing a logic calculation on the first compilation signal, the second compilation signal, and the resistance matching signal, and determining a specific value based on the logic calculation result. Here, the logic calculation algorithm needs to be designed accordingly according to different application scenarios.

[0131] In this way, through the compilation method provided in the embodiment of the present application, both reserved codes and non-reserved codes can be decoded. Even if instructions related to reserved codes are received, the DRAM can still operate normally and will not crash. In addition, for the reserved codes, it is necessary to determine the final compilation value based on the resistance matching signal so that the DRAM can match different DRAM Controllers, ultimately improving the compatibility of the DRAM and providing optimal read and write performance.

[0132] In summary, the embodiments of the present application belong to the field of synchronous dynamic random access memory (SDRAM) DDR4 design, and are specifically applied to mode registers in DRAM. In the latest version of JEDEC DDR4 SPEC, there are still reserved code definitions for some mode registers, and these reserved codes are also available setting codes for different DRAM Controller designers. Therefore, different DRAM Controller design schemes may apply the reserved codes to different coding environments, resulting in some DRAMs being incompatible with the DRAM Controller. In order to improve the compatibility of DDR4 circuits and to adapt to more DRAM Controller design schemes, these reserved codes can be encoded and decoded in advance in the design of DRAM.

[0133] Specifically, in DDR4, the output driver circuit and the termination resistor share a set of pull-up resistors. When the DRAM reads data, it functions as the output driver circuit, and the output resistor Ron must meet the requirements set by the specification. When writing data to the DRAM, it functions as the termination resistor Rtt_WR, which must also meet the requirements set by the specification for Rtt_WR.

[0134] That is to say, the purpose of the embodiment of the present application is to preset the resistor-related reserved codes defined in different mode registers in the DDR4 JEDEC SPEC, so as to be more compatible with the BIOS settings of different DRAM Controllers; at the same time, each reserved code will have two compilation values, which are selected and compiled through the compatible selection circuit to match different DRAM Controller platforms; in addition, since there may be some errors in the DRAM process, according to different chip test results, if the compilation value of the reserved code is closer to the standard value of DDR4, then the reserved code can be enabled, and the specified compilation value can be selected through the compatible selection circuit to provide the optimal terminal matching resistance, thereby obtaining better read and write signal integrity.

[0135] In addition, the embodiment of the present application also provides a specific compilation rule. For the first reserved code (Ron reserved code), each reserved code can correspond to RZQ / N or RZQ / (N+1) at the same time. The final decision on whether to correspond to RZQ / N or RZQ / (N+1) can be made based on the final chip test results, through a compatible selection circuit, and the selection is made based on the best data output signal performance. For the second reserved code (Rtt_WR reserved code), each reserved code can correspond to RZQ / N or Dynamic ODT Off at the same time. For details, please refer to the above content.

[0136] In this way, by presetting the reserved codes related to the resistor values ​​defined in different mode registers in the DDR4 JEDEC SPEC, better compatibility with BIOS settings of different DRAM controllers can be achieved.

[0137] An embodiment of the present application provides a compilation method, comprising receiving a signal to be compiled and a resistance matching signal; compiling the signal to be compiled to obtain a compilation result signal; and, if the signal to be compiled is a reserved code, performing compatibility selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value. Thus, by presetting compilation rules for the reserved code, a mode register can compile the reserved code sent by the application platform, thereby avoiding the problem of the mode register being unable to operate after receiving the reserved code. Furthermore, depending on the resistance matching signal, the compilation result of the reserved code varies, allowing the mode register to adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms. Furthermore, because the reserved code provides a more flexible resistance matching solution, the control solution ultimately delivered to the user can be adjusted based on test results, thereby providing better read and write performance.

[0138] In another embodiment of the present application, see Figure 2 , which shows a schematic diagram of the structure of a compiling circuit 20 provided in an embodiment of the present application. Figure 2 As shown, the compiling circuit 20 includes:

[0139] The signal input terminal 201 is used to receive the signal to be compiled and the resistance matching signal;

[0140] A compiling unit 202 is configured to compile a signal to be compiled to obtain a compilation result signal;

[0141] The compatible selection unit 203 is configured to perform compatible selection processing on the coding result signal based on the resistance matching signal to determine a first coding value when the signal to be coded is a reserved code.

[0142] It should be noted that if Figure 2As shown, the compiling circuit 20 includes a signal input terminal 201, a compiling unit, and a compatibility selection unit 203. The signal input terminal 201 is used to receive a signal to be compiled and a resistance matching signal. The compiling unit 202 is used to compile the signal to be compiled and output a compilation result signal. The compatibility selection unit 203 is connected to both the compiling unit 202 and the signal input terminal 201. When the signal to be compiled is a reserved code, compatibility selection is performed on the compilation result signal based on the resistance matching signal to obtain a first compilation value.

[0143] Here, the reserved code includes at least a first reserved code and a second reserved code, the first reserved code is an output drive resistor (Ron) reserved code, and the second reserved code is a terminal resistor (RTT_WR) reserved code.

[0144] Furthermore, in some embodiments, the compatibility selection unit 203 is specifically configured to, when the signal to be compiled is a reserved code and the resistance matching signal is a first level signal, determine that the first compilation value is a first preset value corresponding to the reserved code; and, when the signal to be compiled is a reserved code and the resistance matching signal is a second level signal, determine that the first compilation value is a second preset value corresponding to the reserved code.

[0145] It should be noted that each reserved code corresponds to two preset values. If the resistance matching signal is a first level signal, the compatibility selection unit 203 determines the first compilation value to be the first preset value corresponding to the reserved code. If the resistance matching signal is a second level signal, the compatibility selection unit 203 determines the first compilation value to be the second preset value corresponding to the reserved code. The first level signal can be designed as a low level signal, and the second level signal can be designed as a high level signal.

[0146] Furthermore, in some embodiments, the compiling circuit 20 is further configured to determine a second compiling value according to the compiling result signal when the signal to be compiled is a non-reserved code.

[0147] It should be noted that, for non-reserved codes, the compiling circuit 20 directly determines the second compiling value according to the compiling result signal.

[0148] Furthermore, in some embodiments, the compilation unit 202 includes a first compilation unit and a second compilation unit; wherein,

[0149] The first compiling unit is configured to compile the signal to be compiled to obtain a first compilation result signal;

[0150] The second compiling unit is configured to compile the signal to be compiled to obtain a second compilation result signal.

[0151] It should be noted that the compilation unit 202 can be divided into a first compilation unit and a second compilation unit. The first compilation unit is used to compile the reserved code to obtain a first compilation result signal; the second compilation unit is used to compile the non-reserved code to obtain a second compilation result signal.

[0152] Further, in some embodiments, the non-reserved code includes a first type of non-reserved code, and the second coding unit includes a second-first coding unit;

[0153] The second-first compiling unit is configured to compile the signal to be compiled to obtain a second-first compiling result signal;

[0154] The compatible selection unit 203 is specifically configured to perform a logical calculation on the first compilation result signal, the second-first compilation result signal, and the resistance matching signal when the signal to be compiled is a first-type non-reserved code or when the signal to be compiled is a reserved code, and determine the first compilation value according to the logical operation result.

[0155] as well as,

[0156] In some embodiments, the non-reserved code further includes a second type of non-reserved code, and the second coding unit further includes a second second coding unit;

[0157] The second-second coding unit is configured to perform coding processing on the signal to be coded to obtain a second-second coding result signal; and when the signal to be coded is a second-type non-reserved code, directly determine a third coding value according to the second-second coding result signal.

[0158] It should be noted that, to save circuit area, non-reserved codes can be divided into two categories: Category 1 non-reserved codes and Category 2 non-reserved codes. Category 1 non-reserved codes include non-reserved codes with the same compiled value as a reserved code; Category 2 non-reserved codes correspond to all non-reserved codes except Category 1 non-reserved codes.

[0159] Accordingly, the second compiled value can be divided into the first compiled value and the third compiled value, and the third compiled value includes the portion of the second compiled value excluding the first compiled value.

[0160] At this time, the compilation process of the reserved code can be combined with part of the first type of reserved codes, thereby saving circuit area. Therefore, the second compilation unit can be divided into a second-first compilation unit and a second-second compilation unit.

[0161] For the first type of non-reserved code or reserved code, the first compilation unit 201 and the second-first compilation unit perform compilation processing to obtain a first compilation result signal and a second-first compilation result signal. Then, the compatible selection unit 203 performs a logical calculation on the first compilation result signal and the second-first compilation result signal to determine a first compilation value.

[0162] The second coding unit performs coding processing on the second type of non-reserved codes to obtain a second coding result signal, and directly determines the third coding value according to the second coding result signal.

[0163] In summary, to better adapt to the use of DRAM reserved codes in different DRAM controller designs, the two resistor-related mode setting reserved codes are pre-compiled in the DDR4 design, further improving DRAM compatibility with different system platforms. Furthermore, a compatible selection circuit is used to perform multiple circuit selections, ensuring better DRAM system read and write signal performance during final chip testing.

[0164] The technical solution provided by the embodiment of the present application includes: on the one hand, the reserved codes for the two resistance-related mode settings defined in DDR4 SPEC are pre-encoded during design; on the other hand, the compilation circuit includes three parts, (1) a compilation circuit for the coding clearly specified by SPEC (equivalent to the aforementioned second encoding unit); (2) a compilation circuit for the reserved code (equivalent to the aforementioned first encoding unit); (3) a DFT selection circuit for improving compatibility (equivalent to the aforementioned compatibility selection unit); on the other hand, the above three circuit parts are all used to achieve the improved SPEC compilation truth table (such as Table 3 to Table 4), including a variety of specific circuit structures and circuit logic; on the other hand, through the compatibility selection circuit, more terminal resistance matching schemes can be provided when the final chip is tested after it is completed, so as to obtain better signal reading and writing performance.

[0165] An embodiment of the present application provides a compilation circuit, comprising a signal input terminal for receiving a signal to be compiled and a resistance matching signal; a compilation unit for compiling the signal to be compiled to obtain a compilation result signal; and a compatibility selection unit for performing compatibility selection processing on the compilation result signal based on the resistance matching signal when the signal to be compiled is a reserved code, thereby determining a first compilation value. Thus, by presetting compilation rules for the reserved code, a mode register can compile the reserved code sent by the application platform, thereby avoiding the problem of the mode register being unable to operate after receiving the reserved code. In addition, the compilation results of the reserved code vary depending on the resistance matching signal, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms. Furthermore, because the reserved code provides a more flexible resistance matching solution, the control solution ultimately delivered to the user can be adjusted based on test results, thereby providing better read and write performance.

[0166] In another embodiment of the present application, taking the Ron setting item as an example, a specific example of a compilation circuit is provided.

[0167] Table 1 above shows the SPEC original definition table of Ron setting items in the related art, and its specific compilation circuit is as follows: Figure 3 The aforementioned Table 4 shows the SPEC improved definition table of the Ron setting item in the embodiment of the present application, and its specific compilation circuit is as follows Figure 4 shown.

[0168] As can be seen from Table 4, when the signal to be compiled is a reserved code, the compiled value needs to be determined based on the reserved code itself and the resistance matching signal. Specifically, if the resistance matching signal is 1, the compiled value of the reserved code is RZQ / N; conversely, if the resistance matching signal is 0, the compiled value of the reserved code is RZQ / (N+1). Here, the mapping relationship between the resistance matching signal and the specific compiled value can be determined based on the actual application scenario and is not limited in the embodiments of the present application.

[0169] like Figure 4 As shown, the compiling circuit 20 includes an arithmetic unit 301, an arithmetic unit 302, an arithmetic unit 303, an arithmetic unit 304, an arithmetic unit 305, an arithmetic unit 306, a data selector 307, a data selector 308, a data selector 309, and a data selector 310. Among them, the arithmetic units 301 to 304 are all two-input AND gates, and the arithmetic units 305 to 306 are all two-input OR gates. For the specific connections of the above devices, please refer to Figure 4 , I will not go into details here.

[0170] like Figure 4 As shown, from a functional perspective, the compilation circuit 20 can be divided into three parts: (1) the compilation circuit for the encoding clearly defined by SPEC (SPEC Defined Decode Block); (2) the compilation circuit for the reserved code (SPEC Reserved Decode Block); (3) the DFT selection circuit for improving compatibility (DFT Block For Better Compatibility).

[0171] (1) The decoder circuit for the SPEC-defined encoding (SPEC Defined Decode Block) includes an operator 301 and an operator 302. In particular, for the Ron setting item, all non-reserved codes are essentially first-class non-reserved codes. Therefore, there is no further division for the decoder circuit for the SPEC-defined encoding.

[0172] (2) The compilation circuit for the reserved code (SPEC Reserved Decode Block) includes an operator 303 and an operator 304.

[0173] (3) DFT selection circuit for improving compatibility (DFT Block For Better Compatibility): operator 305, operator 306, data selector 307, data selector 308, data selector 309 and data selector 310.

[0174] based on Figure 4 The specific compilation principle of the compilation circuit is as follows. Specifically, according to DDR4 specifications, the Ron setting is encoded by the three input bits A2 and A1 of the mode register MR1. A1_T represents the signal value of A1, and A1_B represents the signal value of A1 after the negation operation. The following two-digit value describes the Ron input bit combination. For example, 10 represents A2 as a logic 1 and A1 as a logic 0.

[0175] If the signal to be compiled is a non-reserved code, such as 00, then operator 301 outputs logic 1, operator 302 outputs logic 0, operator 303 outputs logic 0, operator 304 outputs logic 0, operator 305 outputs logic 1, operator 306 outputs logic 0, and both input terminals of data selector 307 are logic 1. Then, output terminal RZQ / 7 is high, and other output terminals are low, and the final compiled value is RZQ / 7.

[0176] If the signal to be compiled is a reserved code, such as 10, operator 301 outputs a logic 0, operator 302 outputs a logic 0, operator 303 outputs a logic 1, operator 304 outputs a logic 0, and operator 305 outputs a logic 1. At this point, the two input ports of data selector 307 are logic 0 and logic 1, respectively. Since one input port of data selector 309 is grounded to signal VSS and is thus always logic 0, the two input ports of data selector 309 are also logic 0 and logic 1, respectively. At this point, if the resistance matching signal is a logic 0, data selector 307 selects to output a logic 0, data selector 309 selects to output a logic 1, output terminal RZQ / 8 is high, and all other output terminals are low, resulting in a final compiled value of RZQ / 8. Conversely, if the resistance matching signal is a logic 1, data selector 307 outputs a logic 1, data selector 309 outputs a logic 0, output terminal RZQ / 7 is high, and all other output terminals are low, resulting in a final compiled value of RZQ / 7.

[0177] It should be understood that for the compilation circuit, Figure 5This is only one circuit implementation method in Table 4. Due to the diversity of logic devices, even for the same compiled truth table, it can be implemented through a variety of circuit structures, and the embodiments of this application are not exhaustive. Therefore, as long as it conforms to the concept of the embodiments of this application, that is, the reserved code is pre-encoded and decoded based on the resistance matching signal, then the corresponding circuit structure is within the scope of protection of the embodiments of this application.

[0178] In addition, the application scenarios of the embodiments of the present application generally occur during testing before delivery to users. During user use, the reserved code is generally not used for control. Therefore, before delivery to the user, the resistance matching signal can be preset to a low-level signal or a high-level signal. Since the user will not send commands related to the reserved code, it will not affect the user experience. Of course, if the user sends a control command involving the reserved code, it can also ensure that the DRAM can perform the relevant decoding and operate normally.

[0179] In summary, the embodiments of the present application preset the reserved codes related to the output resistance Ron defined in different mode registers in the DDR4 JEDEC SPEC, thereby achieving better compatibility with BIOS settings of different DRAM controllers.

[0180] An embodiment of the present application provides a compilation circuit, and this embodiment describes in detail the specific implementation method of the aforementioned embodiment. It can be seen that by pre-setting the compilation rules of the reserved code, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem of the mode register not being able to work after receiving the reserved code; in addition, according to different resistance matching signals, the compilation results of the reserved code are different, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms.

[0181] In yet another embodiment of the present application, taking the Rtt_WR setting item as an example, another specific example of a compilation circuit is provided.

[0182] Table 2 above shows the SPEC original definition table of the Rtt_WR setting item in the related art, and its specific compilation circuit is as follows: Figure 5 The aforementioned Table 3 shows the SPEC improved definition table of the Rtt_WR setting item in the embodiment of the present application, and its specific compilation circuit is as follows: Figure 6 shown.

[0183] As can be seen from Table 3, when the signal to be compiled is a reserved code, the compiled value needs to be determined based on the reserved code itself and the resistance matching signal. Specifically, if the resistance matching signal is 1, the compiled value of the reserved code is RZQ / N; conversely, if the resistance matching signal is 0, the compiled value of the reserved code is Dynamic ODT Off. The mapping relationship between the resistance matching signal and the specific compiled value can be determined based on the actual application scenario and is not limited in this embodiment of the application.

[0184] like Figure 6 As shown, the compiling circuit 20 includes an operator 401, an operator 402, an operator 403, an operator 404, an operator 405, an operator 406, an operator 407, an operator 408, an operator 409, an operator 410, an operator 411, an operator 412, an operator 413, an operator 414, an operator 415, a data selector 416, a data selector 417, a data selector 418, and a data selector 419. Operators 401 to 405 and 409 to 411 are all three-input AND gates, operators 406 to 408 are all two-input NAND gates, and operators 12 to 415 are all two-input OR gates. For the specific connections of the above devices, please refer to FIG. Figure 6 , I will not go into details here.

[0185] like Figure 6 As shown, from a functional perspective, the compilation circuit 20 can be divided into three parts: (1) the compilation circuit for the encoding clearly defined by SPEC (SPEC Defined Decode Block); (2) the compilation circuit for the reserved code (SPEC Reserved Decode Block); (3) the DFT selection circuit for improving compatibility (DFT Block For Better Compatibility).

[0186] (1) The decoder circuit for the SPEC-defined encoding (SPEC Defined Decode Block) includes operators 401 to 405. Operators 401, 402, 403, and 405 are used to decode the first type of non-reserved codes, forming a second-first decoder circuit; operator 404 is used to decode the second type of non-reserved codes, forming a second-second decoder circuit.

[0187] (2) The compilation circuit for the reserved code (SPEC Reserved Decode Block) includes operators 406 to 411.

[0188] (3) DFT selection circuit for improving compatibility (DFT Block For Better Compatibility): operators 412 to 415 and data selectors 416 to 419.

[0189] based on Figure 6 The compilation circuit in [1] operates as follows. Specifically, according to DDR4 specifications, the Rtt_WR setting is encoded by the three input bits A11, A10, and A9 of mode register MR2. The following describes the Rtt_WR input bit combination using three-bit values. For example, 110 represents A11 as a logic 1, A10 as a logic 1, and A9 as a logic 0.

[0190] If the signal to be compiled is a first-class non-reserved code, such as 000, then operator 401 outputs logic 1, operators 406 and 407 both output logic 1, and operator 408 outputs logic 0. Consequently, operator 412 outputs logic 1, and both input ports of data selector 416 are logic 1. Regardless of whether the resistor matching signal is 0 or 1, data selector 416 outputs logic 1, so the output terminal Dynamic ODT Off is high. The remaining operators output logic 0, and the other output ports are all low. The final compiled value is Dynamic ODT off.

[0191] If the signal to be compiled is a second-class non-reserved code, such as 011, then operator 404 outputs logic 1, and the output terminal Hi-Z is high. Operators 406 and 407 both output logic 1, and the remaining operators output logic 0, and the other output terminals are all low. The final compiled value is Hi-Z.

[0192] If the signal to be encoded is a reserved code, such as 101, on the one hand, operators 401 to 405 output logic 0, operator 406 outputs logic 1, operator 407 outputs logic 0, and operator 408 outputs logic 1. Consequently, operator 412 outputs logic 1, and the two input ports of data selector 416 are logic 0 and logic 1, respectively. On the other hand, operator 402 outputs logic 0, operator 409 outputs logic 1, and operator 413 outputs logic 1. Therefore, the two input ports of data selector 417 are logic 1 and logic 0, respectively. The remaining operators output logic 0. At this time, if the resistance matching signal is logic 0, the data selector 416 selects to output logic 0, the data selector 417 selects to output logic 1, the output terminal RZQ / 2 is high, and the other output terminals are all low, and the final compiled value is RZQ / 2; conversely, if the resistance matching signal is logic 1, the data selector 416 outputs logic 1, the data selector 417 outputs logic 0, the output terminal Dynamic ODT Off is high, and the other output terminals are all low, and the final compiled value is Dynamic ODT Off.

[0193] It should be understood that for the compilation circuit, Figure 6 This is only one circuit implementation method in Table 3. Due to the diversity of logic devices, even for the same compiled truth table, it can be implemented through a variety of circuit structures, and the embodiments of this application are not exhaustive. Therefore, as long as it conforms to the concept of the embodiments of this application, that is, the reserved code is pre-encoded and decoded based on the resistance matching signal, then the corresponding circuit structure is within the scope of protection of the embodiments of this application.

[0194] In addition, the application scenarios of the embodiments of the present application generally occur during testing before delivery to users. During user use, the reserved code is generally not used for control. Therefore, before delivery to the user, the resistance matching signal can be preset to a low-level signal or a high-level signal. Since the user will not send commands related to the reserved code, it will not affect the user experience. Of course, if the user sends a control command involving the reserved code, it can also ensure that the DRAM can perform the relevant decoding and operate normally.

[0195] In summary, the embodiments of the present application preset reserved codes related to the terminal resistors defined in different mode registers in the DDR4 JEDEC SPEC, thereby achieving better compatibility with BIOS settings of different DRAM controllers.

[0196] An embodiment of the present application provides a compilation circuit, and this embodiment describes in detail the specific implementation method of the aforementioned embodiment. It can be seen that by pre-setting the compilation rules of the reserved code, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem of the mode register not being able to work after receiving the reserved code; in addition, according to different resistance matching signals, the compilation results of the reserved code are different, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms.

[0197] In yet another embodiment of the present application, see Figure 7 , which shows a schematic diagram of the structure of a mode register 50 provided in an embodiment of the present application. Figure 7 As shown, the mode register 50 at least includes the aforementioned compilation circuit 20 .

[0198] Since the mode register 50 includes the aforementioned compilation circuit 20, by pre-setting the compilation rules of the reserved code, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem that the mode register cannot work after receiving the reserved code; in addition, according to the different resistance matching signals, the compilation results of the reserved code are different, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms.

[0199] In yet another embodiment of the present application, see Figure 8 , which shows a schematic diagram of the structure of a memory 60 provided in an embodiment of the present application. Figure 8 As shown, the memory 60 at least includes the aforementioned mode register 50 .

[0200] Since the memory 60 includes the aforementioned mode register 50, by pre-setting the compilation rules of the reserved code, the mode register can compile the reserved code sent by the application platform, thereby avoiding the problem that the mode register cannot work after receiving the reserved code; in addition, according to the different resistance matching signals, the compilation results of the reserved code are different, so that the mode register can adjust the resistance value in the DRAM to match different application platforms, thereby improving the compatibility of the mode register with different application platforms.

[0201] Furthermore, the memory 50 at least includes a dynamic random access memory DRAM and complies with DDR4 memory specifications.

[0202] The above are merely preferred embodiments of the present application and are not intended to limit the scope of protection of the present application.

[0203] It should be noted that, in this application, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0204] The serial numbers of the above embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0205] The methods disclosed in the several method embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments.

[0206] The features disclosed in the several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0207] The features disclosed in the several method or device embodiments provided in this application can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0208] The above are only specific embodiments of the present application, but the scope of protection of this application is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A compilation method, characterized in that: Applied to a compiling circuit, the method includes: receiving a signal to be compiled and a resistance matching signal; Compiling the signal to be compiled to obtain a compilation result signal; When the signal to be compiled is a reserved code, performing compatibility selection processing on the compiled result signal based on the resistance matching signal to determine a first compiled value; In a case where the signal to be compiled is a non-reserved code, the method further includes: determining a second compiled value according to the compiled result signal; Before receiving the signal to be compiled and the resistance matching signal, the method further includes: determining a value of the first compiled value according to a value of the second compiled value; The determining the value of the first compiled value according to the value of the second compiled value includes: Selecting from the values ​​of the second compiled value to obtain at least one candidate value; The at least one candidate value is determined as a value of the first compiled value.

2. The compiling method according to claim 1, wherein: In a case where the signal to be compiled is a reserved code, performing compatibility selection processing on the compiled result signal based on the resistance matching signal to determine a first compiled value includes: If the resistance matching signal is a first level signal, determining that the first compiled value is a first preset value corresponding to the reserved code; If the resistance matching signal is a second level signal, determining that the first compiled value is a second preset value corresponding to the reserved code; The first level signal is different from the second level signal, and the first preset value corresponding to the reserved code is different from the second preset value corresponding to the reserved code.

3. The compiling method according to claim 2, wherein: The first level signal is a high level signal, and the second level signal is a low level signal.

4. The compiling method according to claim 1, wherein: When the number of the reserved codes is a, the method further includes: Determine a first candidate value and 1 second candidate value according to the at least one candidate value; Determining the i-th first candidate value as the first preset value corresponding to the i-th reserved code, and determining the second candidate value as the second preset value corresponding to the i-th reserved code; Wherein, i and a are positive integers, and i is less than or equal to a.

5. The compiling method according to claim 1, wherein: The determining the value of the first compiled value according to the value of the second compiled value includes: Selecting from the values ​​of the second compiled value to obtain at least one candidate value; Adjusting the at least one candidate value to obtain at least one adjusted value; The at least one candidate value and the at least one adjusted value are determined as values ​​of the first compiled value.

6. The compiling method according to claim 5, characterized in that When the number of the reserved codes is a, the number of the at least one candidate value is a, and the number of the at least one adjusted value is a; Accordingly, the method further comprises: Determining the i-th candidate value as the first preset value corresponding to the i-th reserved code, and determining the i-th adjusted value as the second preset value corresponding to the i-th reserved code; Wherein, i and a are positive integers, and i is less than or equal to a.

7. The compiling method according to any one of claims 1 to 6, characterized in that: The reserved code includes at least one of the following: a first reserved code and a second reserved code; wherein the first reserved code is an output drive resistance (Ron) reserved code, and the second reserved code is a terminal resistance (RTT_WR) reserved code.

8. The compiling method according to claim 5, wherein: When the reserved code is the first reserved code, adjusting the at least one candidate value to obtain at least one adjusted value includes: If the i-th candidate value is the ratio of the preset resistance value to n, then the i-th adjustment value is determined to be the ratio of the preset resistance value to (n+1); wherein i and n are positive integers.

9. The compiling method according to claim 1, wherein: The compiling circuit includes a first compiling unit, a second compiling unit, and a compatibility selection unit, and the method further includes: When the signal to be coded is a reserved code, determining the first coding value by the first coding unit and the compatible selection unit; In a case where the signal to be coded is a non-reserved code, the second coding value is determined by the second coding unit.

10. The compiling method according to claim 9, wherein: The method further comprises: Determining a first category of non-reserved codes and a second category of non-reserved codes; wherein the first category of non-reserved codes includes non-reserved codes having the same compiled value as the reserved code, and the second category of non-reserved codes includes remaining non-reserved codes in the non-reserved codes except the first category of non-reserved codes; Accordingly, the second compilation unit includes a second-first compilation unit and a second-second compilation unit, and the method further includes: When the signal to be coded is a reserved code or a first type of non-reserved code, determining the first coding value by the first coding unit, the second-first coding unit, and the compatible selection unit; When the signal to be coded is a second-type non-reserved code, a third coding value is determined by the second second coding unit; wherein the third coding value is the remaining coding value of the second coding value except the first coding value.

11. The compiling method according to claim 10, wherein: The determining the first coding value by using the first coding unit, the second-first coding unit, and the compatible selection unit includes: Compiling the signal to be compiled by the first compiling unit to obtain a first compiled signal; performing compilation processing on the signal to be compiled by the second-first compilation unit to obtain a second-first compiled signal; The compatible selection unit performs a logic calculation on the first compilation processing signal, the second-first compilation processing signal, and the resistance matching signal, and determines the first compilation value according to the logic calculation result.

12. A compiling circuit, characterized in that: The compiling circuit comprises: Signal input terminal, used for receiving the signal to be compiled and the resistance matching signal; A compiling unit, configured to compile the signal to be compiled to obtain a compilation result signal; a compatible selection unit, configured to, when the signal to be compiled is a reserved code, perform compatible selection processing on the compilation result signal based on the resistance matching signal to determine a first compilation value; The compiling circuit is further configured to determine a second compiling value according to the compiling result signal when the signal to be compiled is a non-reserved code; The compilation unit includes a first compilation unit and a second compilation unit; wherein, The first compiling unit is configured to compile the signal to be compiled to obtain a first compilation result signal; The second compiling unit is configured to compile the signal to be compiled to obtain a second compilation result signal; The non-reserved code includes a first type of non-reserved code, and the second coding unit includes a second-first coding unit; The second-first compiling unit is configured to compile the signal to be compiled to obtain a second-first compiling result signal; The compatible selection unit is specifically configured to perform a logic operation on the first compilation result signal, the second-first compilation result signal, and the resistance matching signal when the signal to be compiled is a first type non-reserved code or the signal to be compiled is a reserved code, and determine the first compilation value according to the logic operation result; The first type of non-reserved codes includes non-reserved codes having the same coding value as the reserved code.

13. The compiling circuit according to claim 12, wherein: The compatible selection unit is specifically configured to, when the signal to be compiled is a reserved code and the resistance matching signal is a first level signal, determine that the first compiling value is a first preset value corresponding to the reserved code; and, when the signal to be compiled is a reserved code and the resistance matching signal is a second level signal, determine that the first compiling value is a second preset value corresponding to the reserved code; The first level signal is different from the second level signal, and the first preset value of the reserved code is different from the second preset value of the reserved code.

14. The compiling circuit according to claim 12, wherein: The non-reserved code further includes a second type of non-reserved code, and the second coding unit further includes a second second coding unit; The second-second coding unit is configured to perform coding processing on the signal to be coded to obtain a second-second coding result signal; and when the signal to be coded is a second-type non-reserved code, directly determine a third coding value according to the second-second coding result signal; The second type of non-reserved codes includes the remaining non-reserved codes in the non-reserved codes except the first type of non-reserved codes, and the third coding value includes the remaining coding values ​​in the second coding value except the first coding value.

15. The compiling circuit according to any one of claims 12 to 14, characterized in that: The reserved code includes at least one of the following: a first reserved code and a second reserved code; wherein the first reserved code is an output drive resistance (Ron) reserved code, and the second reserved code is a terminal resistance (RTT_WR) reserved code.

16. A mode register, characterized in that: The mode register at least includes the compilation circuit according to any one of claims 12 to 15.

17. A memory, characterized in that: The memory includes at least the mode register according to claim 16.

18. The memory according to claim 17, wherein: The memory at least includes a dynamic random access memory (DRAM), and the DRAM complies with DDR4 memory specifications.

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