High-maintenance high-failure bidirectional thyristor electrostatic protection device and manufacturing method thereof

Abstract

The embodiment of the application provides a high-maintenance high-failure bidirectional thyristor electrostatic protection device and a manufacturing method thereof, a P-type substrate, an N-type buried layer, a first N-type deep well, a second N-type deep well and a third N-type deep well; the left side of the second N-type deep well is provided with a third P+ injection area, and the right side is provided with a fourth P+ injection area; the left side of the second N-type deep well is provided with a first P well, and the right side is provided with a second P well; the first P well is provided with a first P-type drift area and a second P-type drift area, and the second P well is provided with a third P-type drift area and a fourth P-type drift area; the first P-type drift area is provided with a first P+ injection area, and the second P-type drift area is provided with a first N+ injection area; the third P-type drift area is provided with a second N+ injection area, and the fourth P-type drift area is provided with a sixth P+ injection area; the first N+ injection area, the first P+ injection area and the second P+ injection area are connected together to serve as an anode of the device, and the second N+ injection area, the fifth P+ injection area and the sixth P+ injection area are connected together to serve as a cathode of the device.

Description

Technical Field

[0001] This invention relates to the field of electrostatic discharge (ESD) protection, and more particularly to a high-sustainment, high-failure bidirectional thyristor ESD protection device and its manufacturing method. Background Technology

[0002] With advancements in semiconductor manufacturing processes, ESD-induced failures of integrated circuit chips and electronic products have become increasingly severe. ESD protection for electronic products and integrated circuit chips has become one of the major challenges faced by product engineers.

[0003] ESD-induced failure modes include hard failure, soft failure, and latent failure. The causes of these failures can be categorized into electrical failure and thermal failure. Thermal failure refers to the generation of a current of several to tens of amperes in a localized area of ​​the chip when an ESD pulse occurs. This current is short-lived but generates a large amount of heat, causing localized metal interconnects to melt or hot spots to form on the chip, leading to secondary breakdown. Electrical failure occurs when the electric field strength created by the voltage applied to the gate oxide layer exceeds the dielectric strength, causing surface breakdown or dielectric breakdown. As the threat posed by ESD to chips becomes increasingly serious, the study of its physical mechanisms is receiving increasing attention.

[0004] Compared to other ESD devices, traditional thyristor devices have a dual-conductance modulation mechanism, resulting in high discharge efficiency per unit area, low parasitic capacitance, and the best robustness. However, due to their high trigger voltage and low sustaining voltage, they are prone to latch-up, which needs to be carefully considered during the design process. Bidirectional thyristor devices are an improvement on traditional thyristors and can be considered as an integration of several anti-parallel connected ordinary thyristors. Their working principle is the same as that of traditional unidirectional thyristors, allowing for voltage clamping in both forward and reverse directions.

[0005] A cross-sectional view of a traditional bidirectional silicon controlled rectifier (SCR) electrostatic discharge (ESD) device is shown below. Figure 1 Its equivalent circuit diagram is shown in Figure 2When an ESD pulse is applied to the anode of a bidirectional SCR, the N-type deep well and the third P+ injection region form a reverse-biased PN junction. When this pulse voltage exceeds the avalanche breakdown voltage of this PN junction, a large avalanche current is generated inside the device. The current flows through the parasitic resistance of the second P-well to the other end, the cathode. When the voltage across this parasitic well resistor exceeds the forward conduction voltage of the cb junction of the vertical NPN transistor (composed of the second P-well and the second N-injection), this transistor turns on. After this transistor turns on, it provides base current to the lateral PNP transistor, and the lateral PNP transistor, when also turned on, also provides base current to the vertical NPN transistor, forming a positive feedback loop. Therefore, even if there is no avalanche current afterward, static electricity can still be discharged due to the transistor's conduction. The bidirectional SCR has a symmetrical structure. When an ESD pulse occurs at the cathode, the PN junction formed by the N-type deep well and the second P+ injection region undergoes avalanche breakdown, causing the PNP transistor and the NPN transistor to conduct sequentially to discharge static electricity. However, SCRs have high trigger voltages and low sustaining voltages, which can easily exceed the design window and cause latch-up. Therefore, it is necessary to increase their sustaining voltage. However, increasing the sustaining voltage will reduce the robustness of the device, so robustness still needs to be carefully considered. Summary of the Invention

[0006] This invention provides a simple, high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method.

[0007] To achieve the above objectives, the technical solution of this invention is implemented as follows:

[0008] This invention provides a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device, comprising: a P-type substrate;

[0009] The P-type substrate has an N-type buried layer;

[0010] Above the N-type buried layer are a first N-type deep well, a second N-type deep well, and a third N-type deep well;

[0011] The second N-type deep trap has a third P+ injection region on its left side;

[0012] A fourth P+ injection region is provided on the right side of the second N-type deep well;

[0013] The second type N deep well has a first P well on the left and a second P well on the right.

[0014] The first P-well contains a first P-type drift region and a second P-type drift region, and the second P-well contains a third P-type drift region and a fourth P-type drift region;

[0015] The first P-type drift region is provided with a first P+ injection region, and the second P-type drift region is provided with a first N+ injection region;

[0016] The third P-type drift region is provided with a second N+ injection region, and the fourth P-type drift region is provided with a sixth P+ injection region;

[0017] The first N+ injection region, the first P+ injection region, and the second P+ injection region are connected together and serve as the anode of the device, while the second N+ injection region, the fifth P+ injection region, and the sixth P+ injection region are connected together and serve as the cathode of the device.

[0018] Specifically, a first field oxygen isolation region is provided between the left side of the first P+ implantation region and the left edge of the P-type substrate; a second field oxygen isolation region is provided between the right side of the first P+ implantation region and the left side of the second P+ implantation region; a third field oxygen isolation region is provided between the right side of the second P+ implantation region and the left side of the first N+ implantation region; a fourth field oxygen isolation region is provided between the right side of the first N+ implantation region and the left side of the third P+ implantation region; a fifth field oxygen isolation region is provided between the right side of the third P+ implantation region and the left side of the fourth P+ implantation region; a sixth field oxygen isolation region is provided between the right side of the fourth P+ implantation region and the left side of the second N+ implantation region; a seventh field oxygen isolation region is provided between the right side of the second N+ implantation region and the left side of the fifth P+ implantation region; an eighth field oxygen isolation region is provided between the right side of the fifth P+ implantation region and the left side of the sixth P+ implantation region; and a ninth field oxygen isolation region is provided between the right side of the sixth P+ implantation region and the right edge of the P-type substrate.

[0019] Wherein, the left portion of the first field oxygen isolation region is located on the surface of the P-type substrate, and the right portion is located on the surface of the first P-type drift region; the left portion of the second field oxygen isolation region is located on the surface of the first P-type drift region, and the right portion is located on the surface of the first P-well; the left portion of the third field oxygen isolation region is located on the surface of the first P-well, and the right portion is located on the surface of the second P-type drift region; the left portion of the fourth field oxygen isolation region is located on the surface of the second P-type drift region, and the right portion is located on the surface of the first P-well; the left portion of the fifth field oxygen isolation region is located on the surface of the N-type deep well; the left portion of the sixth field oxygen isolation region is located on the surface of the second P-well, and the right portion is located on the surface of the third P-type drift region; the left portion of the seventh field oxygen isolation region is located on the surface of the third P-type drift region, and the right portion is located on the surface of the second P-well; the left portion of the eighth field oxygen isolation region is located on the surface of the second P-well, and the right portion is located on the surface of the fourth P-type drift region; the left portion of the ninth field oxygen isolation region is located on the surface of the fourth P-type drift region, and the right portion is located on the surface of the P-type substrate.

[0020] When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the second N+ injection region, the third P-type drift region / second P-well, and the N-type buried layer constitute a vertical NPN transistor, the first P-well, the N-type deep well, and the second P-well constitute a horizontal PNP transistor structure, and the first P+ injection region / first P-type drift region / first P-well, the N-type buried layer, the second P-well / fourth P-type drift region / sixth P+ injection region constitute a horizontal PNP transistor structure.

[0021] This invention also includes a method for fabricating a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device, characterized in that the method comprises:

[0022] Step 1: Form an N-type buried layer in a P-type substrate;

[0023] Step 2: Generate a P-well above the N-type buried layer;

[0024] Step 3: Generate three N-type deep wells in the P-well, forming the first P-well and the second P-well;

[0025] Step 4: Generate the first P-type drift region and the second P-type drift region in the first P-well;

[0026] Step 5: Generate the third and fourth P-type drift regions in the second P-well;

[0027] Step Six: Form a first P+ injection region within the first P-type drift region; form a second P+ injection region within the first P-well to the right of the first P-type drift region; form a first N+ injection region within the second P-type drift region; form a third P+ injection region at the junction of the first P-well and the second deep N-well; form a fourth P+ injection region at the junction of the second deep N-well and the second P-well; form a second N+ injection region within the third P-type drift region; form a fifth P+ injection region within the second P-well to the right of the third P-type drift region; and form a sixth P+ injection region within the fourth P-type drift region.

[0028] Step 7: Form field oxygen isolation regions between all implantations. Form the first field oxygen isolation region between the left side of the first P+ implantation region and the left edge of the P-type substrate, and form the ninth field oxygen isolation region between the right side of the sixth P+ implantation region and the right edge of the P-type substrate.

[0029] Step 8: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0030] Step 9: Connect the first N+ injection region, the first P+ injection region, and the second P+ injection region together as the anode of the device, and connect the second N+ injection region, the fifth P+ injection region, and the sixth P+ injection region together as the cathode of the device.

[0031] The method further includes the following steps:

[0032] A silicon dioxide thin film is grown on a P-type substrate, followed by the deposition of a silicon nitride layer. A photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop the wafer to form a shallow isolation trench. The silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, and a silicon dioxide layer is deposited. Then, chemical polishing is performed until the silicon nitride layer is removed.

[0033] This invention provides a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device and its fabrication method, with the following advantages:

[0034] 1. Due to the presence of the first P-type drift region, the anode current flows through the first P+ injection region, through the first P-type drift region and the first P-well to reach the N-type buried layer. The parasitic resistance of the N-type buried layer carries the current, which enables the lateral PNP structure formed by the first P+ injection region / first P-type drift region / first P-well, N-type buried layer, second P-well / third P-type drift region / second N+ injection region to open and discharge the current, thereby making the current in the device uniformly distributed. The presence of the first P-type drift region enables the realization of the second discharge path that was originally difficult to open.

[0035] 2. In this invention, the presence of the third and fourth P+ injection regions transforms the breakdown surface from the original N-type deep well and P-well into an N-type deep well and P+ injection region, thereby reducing the device's trigger voltage. The presence of the second and third P-type drift regions increases the concentration of the P-well where the N+ injection region is located, thereby increasing the base concentration of the emitter stage of the parasitic NPN transistor, reducing the injection efficiency of the emitter stage, and increasing the sustaining voltage.

[0036] 3. The distance D3 between the first N+ injection region and the second P+ injection region, and the distance D1 between the second N+ injection region and the fourth P+ injection region of the present invention are adjustable. When D1 increases, the base region width of the vertical NPN transistor also increases, which reduces the amplification factor of the vertical NPN transistor and increases the holding voltage accordingly. Attached Figure Description

[0037] Figure 1 This is a cross-sectional view of a currently known bidirectional SCR electrostatic discharge protection device;

[0038] Figure 2 The equivalent circuit diagram of the currently known bidirectional SCR electrostatic discharge protection device;

[0039] Figure 3 A cross-sectional view of a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device provided in an embodiment of the present invention;

[0040] Figure 4The equivalent circuit diagram of a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device provided in an embodiment of the present invention is shown. Detailed Implementation

[0041] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of the invention and are not intended to limit the invention.

[0042] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this invention pertains. The terminology used herein in the description of the invention is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention.

[0043] like Figure 3 As shown, a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device includes a P-type substrate 101; an N-type buried layer 201 is disposed in the substrate; above the N-type buried layer 201 are N-type deep wells 301, 302, and 303; a first P-well 401 is disposed between the N-type deep wells 301 and 302, and a second P-well 402 is disposed between the N-type deep wells 301 and 303; the first P-well 401 contains a second P+ injection region 602, a first P-type drift region 501, and a second P-type drift region 502; the second P-well 402 contains a second P+ injection region 607, a third P-type drift region 503, and a fourth P-type drift region 504; the first P-type drift region 501 contains... A first P+ injection region 601, a first N+ injection region 603 within a second P-type drift region 502, a first N+ injection region 606 within a third P-type drift region 503, and a first P+ injection region 608 within a fourth P-type drift region 504; a third P+ injection region 604 is located at the junction of the first P-well 401 and the second N-type deep well 302, and a fourth P+ injection region 605 is located at the junction of the second P-well 401 and the second N-type deep well 302; the first P+ injection region 601, the second P+ injection region 602, and the first N+ injection region 603 are connected together and serve as the anode of the device; the second N+ injection region 606, the fifth P+ injection region 607, and the sixth P+ injection region 608 are connected together and serve as the cathode of the device.

[0044] A first field oxygen isolation region 701 is provided between the left side of the first P+ implantation region 601 and the left edge of the P-type substrate 101; a second field oxygen isolation region 702 is provided between the right side of the first P+ implantation region 601 and the left side of the second P+ implantation region 602; a third field oxygen isolation region 703 is provided between the right side of the second P+ implantation region 602 and the left side of the first N+ implantation region 603; a fourth field oxygen isolation region 704 is provided between the right side of the first N+ implantation region 603 and the left side of the third P+ implantation region 604; and a fourth field oxygen isolation region 704 is provided between the right side of the third P+ implantation region 604 and the left side of the fourth P+ implantation region 604. A fifth field oxygen isolation region 705 is provided between the left and right sides of region 605; a sixth field oxygen isolation region 706 is provided between the right side of the fourth P+ implantation region 605 and the left side of the second N+ implantation region 606; a seventh field oxygen isolation region 707 is provided between the right side of the second N+ implantation region 606 and the left side of the fifth P+ implantation region 607; an eighth field oxygen isolation region 708 is provided between the right side of the fifth P+ implantation region 607 and the left side of the sixth P+ implantation region 608; and a ninth field oxygen isolation region 709 is provided between the right side of the sixth P+ implantation region 608 and the right edge of the P-type substrate 101.

[0045] The left portion of the first field oxygen isolation region 701 is located on the surface of the P-type substrate 101, and the right portion is located on the surface of the first P-type drift region 501; the left portion of the second field oxygen isolation region 702 is located on the surface of the first P-type drift region 501, and the right portion is located on the surface of the first P-well 401; the left portion of the third field oxygen isolation region 703 is located on the surface of the first P-well 401, and the right portion is located on the surface of the second P-type drift region 502; the left portion of the fourth field oxygen isolation region 704 is located on the surface of the second P-type drift region 502, and the right portion is located on the surface of the first P-well 401; the fifth field oxygen isolation region 705... The left portion is located on the surface of the N-type deep well 302; the left portion of the sixth field oxygen isolation region 706 is located on the surface of the second P-well 402, and the right portion is located on the surface of the third P-type drift region 503; the left portion of the seventh field oxygen isolation region 707 is located on the surface of the third P-type drift region 503, and the right portion is located on the surface of the second P-well 402; the left portion of the eighth field oxygen isolation region 708 is located on the surface of the second P-well 402, and the right portion is located on the surface of the fourth P-type drift region 504; the left portion of the ninth field oxygen isolation region 709 is located on the surface of the fourth P-type drift region 504, and the right portion is located on the surface of the P-type substrate 101.

[0046] like Figure 4As shown, when the high-voltage ESD pulse reaches the anode of the device and the cathode of the device is connected to a low potential, the first N+ injection region 603, the second P-type drift region 502 / first P-well 401, and the N-type deep well 301 constitute a vertical NPN transistor, the first P-well 401, the N-type deep well 302, and the second P-well 402 constitute a horizontal PNP transistor structure, and the first P+ injection region 601 / first P-type drift region 501 / first P-well 401, N-type buried layer 201, second P-well 402 / fourth P-type drift region 504 / sixth P+ injection region constitute a horizontal PNP transistor structure.

[0047] When the ESD high-voltage pulse reaches the anode of the device, the first P+ injection region 601, the second P+ injection region 602, and the first N+ injection region 603 are at high potential, while the second N+ injection region 606, the fifth P+ injection region 607, and the sixth P+ injection region 608 at the other end are at low potential. The N-type deep well 302 and the fourth P+ injection region 605 are reverse biased. When the pulse voltage exceeds the avalanche breakdown voltage of the junction, a large avalanche current is generated inside the device. The avalanche current flows through the parasitic resistance of the second P-well 402 into the cathode, and is processed by the equivalent circuit. Figure 4 It can be seen that the avalanche current increases the voltage across the parasitic resistance in the second P-well 402, causing the vertical NPN transistor to conduct first. After the NPN transistor conducts, a large current is injected into the N-type buried layer 201. The injection of current increases the voltage across the parasitic resistance in the N-type buried layer 201, triggering the lateral PNP transistor. The lateral and vertical NPN transistors form positive feedback, creating the first current path. After the first current path is formed, the presence of the first P-type drift region 501 causes the anode current to flow through the first P+ injection region 60. The current flows through the first P-type drift region 501 and the first P-well 401 to the N-type buried layer. The parasitic resistance of the N-type buried layer 201 carries the current, which causes the lateral PNP structure formed by the first P+ injection region 601 / first P-type drift region 501 / first P-well 401, N-type buried layer 201, second P-well 402 / third P-type drift region 503 / second N+ injection region 606 to open and discharge the current, thereby making the current in the device uniformly distributed. The existence of the first P-type drift region 501 enables the second discharge path, which was originally difficult to open, to be realized.

[0048] When the ESD high-voltage pulse reaches the anode of the device, the presence of the fourth P+ injection region 605 causes the breakdown surface to change from the original N-type deep well 302 and P-well 402 to N-type deep well 302 and the fourth P+ injection region 605, reducing the device's trigger voltage. The presence of the second P-type drift region 502 increases the concentration of the first N+ injection region 603 in the first P-well 401, which increases the base concentration of the emitter stage of the parasitic NPN transistor, reduces the injection efficiency of the emitter stage, and increases the sustaining voltage.

[0049] When the ESD high voltage pulse reaches the anode of the device, the distance D1 between the second N+ injection region 606 and the fourth P+ injection region 605 of the device is adjustable. When D1 increases, the base width of the vertical NPN transistor also increases, which reduces the amplification factor of the vertical NPN transistor and increases the holding voltage accordingly.

[0050] A method for fabricating a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device includes the following steps:

[0051] Step 1: A silicon dioxide thin film is grown on a P-type substrate 101, followed by the deposition of a silicon nitride layer; a photoresist layer is spin-coated onto the wafer, and a mask is used for exposure and development to form isolation trenches; the silicon dioxide, silicon nitride, and isolation trenches are etched to remove the photoresist layer, a silicon dioxide layer is deposited, and then chemical polishing is performed until the silicon nitride layer is reached, after which the silicon nitride layer is removed.

[0052] Step 2: Form an N-type buried layer 201 in the P-type substrate 101;

[0053] Step 3: Generate a P-well above the N-type buried layer 201;

[0054] Step 4: Generate three N-type deep wells 301, 302, and 303 in the P-well to generate the first P-well 401 and the second P-well 402;

[0055] Step 5: Generate a first P-type drift region 501 and a second P-type drift region 502 in the first P-well 401;

[0056] Step 6: Generate the third P-type drift region 503 and the fourth P-type drift region 504 in the second P-trap 402;

[0057] Step 7: A first P+ injection region 601 is formed within the first P-type drift region 501; a second P+ injection region 602 is formed within the first P-well 401 to the right of the first P-type drift region 501; a first N+ injection region 603 is formed within the second P-type drift region 502; a third P+ injection region 604 is formed at the junction of the first P-well 401 and the second deep N-well 302; a fourth P+ injection region 605 is formed at the junction of the second deep N-well 302 and the second P-well 402; a second N+ injection region 606 is formed within the third P-type drift region 503; a fifth P+ injection region 607 is formed within the second P-well 402 to the right of the third P-type drift region 503; and a sixth P+ injection region 608 is formed within the fourth P-type drift region 504.

[0058] Step 8: Form field oxygen isolation regions between all implantations. A first field oxygen isolation region 701 is formed between the left side of the first P+ implantation region 601 and the left edge of the P-type substrate 101. A ninth field oxygen isolation region 709 is formed between the right side of the sixth P+ implantation region 608 and the right edge of the P-type substrate 101.

[0059] Step 9: Anneal all injection zones to eliminate the migration of impurities within the injection zones;

[0060] Step 10: Connect the first N+ injection region 603, the first P+ injection region 601, and the second P+ injection region 602 together as the anode of the device, and connect the second N+ injection region 606, the fifth P+ injection region 607, and the sixth P+ injection region 608 together as the cathode of the device.

[0061] Optionally, the method further includes:

[0062] A silicon dioxide thin film is grown on a P-type substrate 101, followed by the deposition of a silicon nitride layer. A photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop the wafer to form a shallow isolation trench. The silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, and a silicon dioxide layer is deposited. Then, chemical polishing is performed until the silicon nitride layer is removed.

[0063] The fabrication method of this invention for a high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device is simple and easy to operate. The fabricated bidirectional thyristor ESD device structure increases the current path by adding a P+ injection region and wrapping it with a P-type drift region to guide the current downwards, thus increasing the failure current of the device and sharing the main path current. Simultaneously, adding a P+ injection region to the breakdown surface alters the breakdown voltage, thereby reducing the trigger voltage. The emitter of the parasitic NPN transistor is wrapped with a P-type drift region to increase the base region concentration of the parasitic transistor, reducing emitter efficiency and thus improving the sustaining voltage. Furthermore, the distance between diodes D1 and D2 is adjustable; as D1 increases, the base region width of the vertical NPN transistor also increases, reducing the amplification factor of the vertical NPN transistor and increasing the sustaining voltage. This allows the device to be used in ESD protection designs, effectively protecting the internal chip and avoiding the risk of latch-up. The example device of this invention uses a 0.25μm BCDMOS process.

[0064] The above description is merely a preferred embodiment of the present invention and is not intended to limit the scope of protection of the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention are included within the scope of protection of the present invention.

Claims

1. A high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) protection device, characterized in that, include: P-type substrate; The P-type substrate has an N-type buried layer; Above the N-type buried layer are a first N-type deep well, a second N-type deep well, and a third N-type deep well; The second N-type deep trap has a third P+ injection region on its left side; A fourth P+ injection region is provided on the right side of the second N-type deep well; The second type N deep well has a first P well on the left and a second P well on the right. The first P-well contains a first P-type drift region and a second P-type drift region, and the second P-well contains a third P-type drift region and a fourth P-type drift region; The first P-type drift region is provided with a first P+ injection region, and the second P-type drift region is provided with a first N+ injection region; The third P-type drift region is provided with a second N+ injection region, and the fourth P-type drift region is provided with a sixth P+ injection region; The first N+ injection region, the first P+ injection region, and the second P+ injection region are connected together and serve as the anode of the device; the second N+ injection region, the fifth P+ injection region, and the sixth P+ injection region are connected together and serve as the cathode of the device. A first field oxygen isolation region is provided between the left side of the first P+ implantation region and the left edge of the P-type substrate; a second field oxygen isolation region is provided between the right side of the first P+ implantation region and the left side of the second P+ implantation region; a third field oxygen isolation region is provided between the right side of the second P+ implantation region and the left side of the first N+ implantation region; a fourth field oxygen isolation region is provided between the right side of the first N+ implantation region and the left side of the third P+ implantation region; a fifth field oxygen isolation region is provided between the right side of the third P+ implantation region and the left side of the fourth P+ implantation region; a sixth field oxygen isolation region is provided between the right side of the fourth P+ implantation region and the left side of the second N+ implantation region; a seventh field oxygen isolation region is provided between the right side of the second N+ implantation region and the left side of the fifth P+ implantation region; an eighth field oxygen isolation region is provided between the right side of the fifth P+ implantation region and the left side of the sixth P+ implantation region; and a ninth field oxygen isolation region is provided between the right side of the sixth P+ implantation region and the right edge of the P-type substrate.

2. The high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, The left portion of the first field oxygen isolation region is located on the surface of the P-type substrate, and the right portion is located on the surface of the first P-type drift region; the left portion of the second field oxygen isolation region is located on the surface of the first P-type drift region, and the right portion is located on the surface of the first P-well; the left portion of the third field oxygen isolation region is located on the surface of the first P-well, and the right portion is located on the surface of the second P-type drift region; the left portion of the fourth field oxygen isolation region is located on the surface of the second P-type drift region, and the right portion is located on the surface of the first P-well; the left portion of the fifth field oxygen isolation region is located on the surface of the N-type deep well; the left portion of the sixth field oxygen isolation region is located on the surface of the second P-well, and the right portion is located on the surface of the third P-type drift region; the left portion of the seventh field oxygen isolation region is located on the surface of the third P-type drift region, and the right portion is located on the surface of the second P-well. The left part of the eighth field oxygen isolation region is located on the surface of the second P-well, and the right part is located on the surface of the fourth P-type drift region; the left part of the ninth field oxygen isolation region is located on the surface of the fourth P-type drift region, and the right part of the ninth field oxygen isolation region is located on the surface of the P-type substrate.

3. The high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device according to claim 1, characterized in that, When a high-voltage ESD pulse reaches the anode of the device and the cathode is connected to a low potential, the second N+ injection region, the third P-type drift region / second P-well, and the N-type buried layer constitute a vertical NPN transistor, the first P-well, the N-type deep well, and the second P-well constitute a horizontal PNP transistor structure, and the first P+ injection region / first P-type drift region / first P-well, the N-type buried layer, the second P-well / fourth P-type drift region / sixth P+ injection region constitute a horizontal PNP transistor structure.

4. A method for fabricating a high-holding-time, high-failure bidirectional thyristor electrostatic discharge (ESD) device, characterized in that, include: Step 1: Form an N-type buried layer in a P-type substrate; Step 2: Generate a P-well above the N-type buried layer; Step 3: Generate three N-type deep wells in the P-well, forming the first P-well and the second P-well; Step 4: Generate the first P-type drift region and the second P-type drift region in the first P-well; Step 5: Generate the third and fourth P-type drift regions in the second P-well; Step Six: Form a first P+ injection region within the first P-type drift region; form a second P+ injection region within the first P-well to the right of the first P-type drift region; form a first N+ injection region within the second P-type drift region; form a third P+ injection region at the junction of the first P-well and the second deep N-well; form a fourth P+ injection region at the junction of the second deep N-well and the second P-well; form a second N+ injection region within the third P-type drift region; form a fifth P+ injection region within the second P-well to the right of the third P-type drift region; and form a sixth P+ injection region within the fourth P-type drift region. Step 7: Form field oxygen isolation regions between all implantations. Form the first field oxygen isolation region between the left side of the first P+ implantation region and the left edge of the P-type substrate, and form the ninth field oxygen isolation region between the right side of the sixth P+ implantation region and the right edge of the P-type substrate. Step 8: Anneal all injection zones to eliminate the migration of impurities within the injection zones; Step 9: Connect the first N+ injection region, the first P+ injection region, and the second P+ injection region together as the anode of the device, and connect the second N+ injection region, the fifth P+ injection region, and the sixth P+ injection region together as the cathode of the device.

5. The method for manufacturing the high-sustainment, high-failure bidirectional thyristor electrostatic discharge (ESD) device according to claim 4, characterized in that, The method is preceded by: A silicon dioxide thin film is grown on a P-type substrate, followed by the deposition of a silicon nitride layer. A photoresist layer is spin-coated onto the wafer, and a mask is used to expose and develop the wafer to form a shallow isolation trench. The silicon dioxide, silicon nitride, and shallow isolation trench are etched to remove the photoresist layer, and a silicon dioxide layer is deposited. Then, chemical polishing is performed until the silicon nitride layer is removed.

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