Transimpedance amplifier and control method for a transimpedance amplifier

Abstract

The embodiment of the application discloses a trans-impedance amplifier and a control method thereof, and is applied to the technical field of circuits. The trans-impedance amplifier TIA comprises an inverting amplifier circuit and a voltage clamping circuit. The inverting amplifier circuit and the voltage clamping circuit are connected in parallel. The inverting amplifier circuit comprises a first PMOS tube and a first NMOS tube with a common gate. The source of the first PMOS tube is connected with the drain of a second NMOS tube. The voltage clamping circuit comprises a second PMOS tube and a second NMOS tube with a common gate. The gates of the two are connected with the input end of the TIA. The source of the second NMOS tube and the drain of the second PMOS tube are connected with the output end of the TIA. The voltage clamping circuit can provide a compensation current, so as to avoid that the output voltage of the trans-impedance amplifier is too high or too low. In this way, the voltage difference between the source and the drain of the first PMOS tube and the first NMOS tube can be controlled, so as to avoid overvoltage phenomenon, thereby prolonging the service life of the first PMOS tube and the first NMOS tube.

Description

Technical Field

[0001] This application relates to the field of circuit technology, and in particular to a transimpedance amplifier and its control method. Background Technology

[0002] A transimpedance amplifier (TIA) is a front-end amplifier in a photodetector (such as a photodiode), used to convert the current signal output by the photodetector into a voltage signal. The working principle of a TIA is as follows: a feedback resistor is added across the operational amplifier, and the feedback resistor converts the current into a voltage and outputs it according to Ohm's law.

[0003] Existing TIAs use a CMOS structure, consisting of a PMOS transistor and an NMOS transistor connected in series. The input terminals of the TIA are connected to the gates of the PMOS and NMOS transistors, respectively. The input voltage is used to control the conduction or cutoff of the PMOS and NMOS transistors, thereby controlling the output voltage of the transimpedance amplifier.

[0004] Because the current signal received by the TIA is a burst signal, a large current may momentarily flow into the TIA's input terminal before the TIA reaches a steady state, causing the input voltage to be too high and consequently the output voltage to be too low. In this case, the voltage between the source and drain of the NMOS transistor may exceed the NMOS transistor's breakdown voltage, thus damaging the NMOS transistor. Therefore, solving the overvoltage problem of the TIA is crucial to improving its performance and lifespan. Summary of the Invention

[0005] This application provides a transimpedance amplifier and a control method for the transimpedance amplifier.

[0006] A first aspect of this application provides a transimpedance amplifier (TIA). The TIA includes an inverting amplifier circuit and a voltage clamping circuit. The inverting amplifier circuit and the voltage clamping circuit are connected in parallel. The inverting amplifier circuit includes a common-gate first PMOS transistor and a first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are connected to form the input terminal of the TIA. The source of the first PMOS transistor is connected to the drain of a second NMOS transistor to form the output terminal of the inverting amplifier circuit. The voltage clamping circuit includes a common-gate second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to the input terminal of the TIA. The source of the second NMOS transistor and the drain of the second PMOS transistor are connected to the output terminal of the TIA. The drain of the second NMOS transistor is connected to a DC power supply, and the source of the second PMOS transistor is grounded.

[0007] The voltage clamping module compensates for the load current based on the input voltage to control the output voltage. When the input voltage (gate voltage) is too low, the first and second NMOS transistors are cut off, while the first and second PMOS transistors are turned on. At this time, the compensation current is supplied to the first PMOS transistor by the second PMOS transistor. This reduces the output voltage, ensuring it doesn't become too high. The voltage difference between the drain and source of the first NMOS transistor is also prevented from becoming too high, thus avoiding overvoltage in the first NMOS transistor. This structure ensures the first NMOS transistor operates safely.

[0008] When the input voltage is too high, the first and second PMOS transistors are cut off, while the first and second NMOS transistors are turned on. At this time, the compensation current is supplied by the second NMOS transistor to the first NMOS transistor. This increases the output voltage, ensuring it doesn't become too low. The voltage difference between the drain and source of the first PMOS transistor is also prevented from becoming too high, avoiding overvoltage and ensuring the first PMOS transistor operates safely.

[0009] In the aforementioned TIA, the voltage clamping module compensates the load circuit based on the input voltage, protecting the output voltage and keeping it within the normal range. This prevents excessive voltage difference between the drain and source of the CMOS transistor, which could cause overvoltage and ensure the CMOS transistor operates safely. It also prevents damage to the CMOS transistor caused by sudden changes in current signals that could deviate from the breakdown point. This significantly improves the performance of the transimpedance amplifier. Furthermore, the voltage clamping module offers advantages such as fast response speed, handling instantaneous voltage changes at various nodes caused by sudden signals. This further enhances the stability of the transimpedance amplifier.

[0010] In one optional implementation, the turn-on voltages of both the first PMOS and the first NMOS transistors are lower than those of the second PMOS and the second NMOS transistors. Thus, if the input voltage is within the normal swing range, the gate voltages of both the second NMOS and the second PMOS transistors do not reach their turn-on voltages. Since both the second NMOS and the second PMOS transistors are in the off state, the voltage clamping circuit is ineffective, ensuring that the reverse amplification performance of the TIA is not affected.

[0011] In one alternative implementation, the TIA further includes a feedback resistor circuit. The feedback resistor circuit is connected in parallel with the inverting amplifier circuit. The feedback resistor circuit is used to convert the input current signal of the TIA into a voltage signal. The feedback resistor enables the conversion of a current signal into a voltage signal. Simultaneously, the introduction of the feedback resistor allows the inverting amplifier circuit to form a closed system. This improves the stability of the inverting amplifier circuit and also increases its gain.

[0012] In one optional implementation, the feedback resistor circuit includes a first feedback branch, a second feedback branch, and a third feedback branch connected in parallel. The first feedback branch includes a first resistor, a second resistor, and a first switch. The first and second resistors are connected in series, and the first switch is connected in parallel across the second resistor. The second feedback branch includes a third resistor and a second switch, which are connected in series. The third feedback branch includes a fourth resistor and a third switch, which are connected in series. The feedback resistor circuit includes three parallel feedback branches, and each feedback branch has a switch. The conduction state of the switch in the first feedback branch affects the slew rate of the inverting amplifier circuit. The closing and opening of the switches in the second and third feedback branches affect whether the third and fourth resistors are connected in parallel. This affects the resistance value of the feedback resistor circuit, ultimately affecting the gain of the transimpedance amplifier. Using the above feedback resistor circuit, the transimpedance amplifier can switch between two slew rates and three gain modes, improving the flexibility of the transimpedance amplifier.

[0013] In one alternative implementation, the third feedback branch further includes a feedback capacitor. The feedback capacitor is connected in parallel across the fourth resistor to compensate for phase margin. When the TIA is in low-gain mode, the signal phase difference will increase. At this time, a feedback capacitor is needed to compensate for the phase margin and restore the signal, thereby improving the TIA's performance.

[0014] In an optional implementation, a second voltage clamping circuit can be connected in parallel across the feedback resistor circuit. This second voltage clamping circuit includes a common-gate third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to the input terminal of the feedback resistor circuit. The source of the third NMOS transistor and the drain of the third PMOS transistor are connected to the output terminal of the feedback resistor circuit. The drain of the third NMOS transistor is connected to a DC power supply, and the source of the third PMOS transistor is grounded. Because a voltage clamping circuit is also added to the feedback resistor circuit, the voltage at the input terminal can be clamped after the output voltage is fed back to the input terminal. This controls the magnitude of the input voltage, preventing it from being too high or too low. This avoids overvoltage phenomena in the CMOS transistor, maintaining the source-drain voltage difference of the CMOS transistor at its normal operating state, further improving the lifespan and performance of the CMOS transistor.

[0015] In one alternative implementation, the TIA further includes a load circuit. The input of the load circuit is connected to the output of the inverting amplifier circuit. The output of the load circuit is the output of the transimpedance amplifier (TIA). The load circuit is used to adjust the gain of the inverting amplifier module, thereby improving the performance of the TIA.

[0016] In one alternative implementation, the load circuit includes a load PMOS transistor and a load NMOS transistor. The gates of the load PMOS transistor and the load NMOS transistor are connected to form the input terminal of the load circuit. The source and drain of the load PMOS transistor are connected. The gates of the load PMOS transistor and the load NMOS transistor are connected to the source and drain of the load PMOS transistor and the load NMOS transistor, respectively. Alternatively, the load circuit may use a load CMOS transistor, which acts as a variable-resistance resistor. By changing the resistance value, the parameters of the transimpedance amplifier (TIA) can be adjusted, thereby improving the flexibility of the transimpedance amplifier.

[0017] In an optional implementation, the load circuit further includes a load capacitor. A first terminal of the load capacitor is connected to the output terminal of the load circuit. A second terminal of the load capacitor is grounded. The load capacitor is used to adjust the open-loop bandwidth of the inverting amplifier circuit.

[0018] A second aspect of this application provides another transimpedance amplifier (TIA). The TIA includes a first inverting amplifier, a second inverting amplifier, a third inverting amplifier, a first voltage clamping circuit, a second voltage clamping circuit, and a third voltage clamping circuit. The first, second, and third inverting amplifiers are connected in series. The first voltage clamping circuit is connected in parallel across the first inverting amplifier. The second voltage clamping circuit is connected in parallel across the second inverting amplifier. The third voltage clamping circuit is connected in parallel across the third inverting amplifier.

[0019] The first inverting amplifier includes a common-gate first PMOS transistor and a first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are connected to form the input terminal of the TIA. The source of the first PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the first inverting amplifier. The second inverting amplifier includes a common-gate second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to form the input terminal of the second inverting amplifier. The input terminal of the second inverting amplifier is connected to the output terminal of the first inverting amplifier. The source of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the second inverting amplifier. The third inverting amplifier includes a common-gate third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to form the input terminal of the third inverting amplifier. The input terminal of the third inverting amplifier is connected to the output terminal of the second inverting amplifier. The source of the third PMOS transistor is connected to the drain of the third NMOS transistor to form the output terminal of the TIA.

[0020] The first voltage clamping circuit includes a common-gate fourth PMOS transistor and a fourth NMOS transistor. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input terminal of the TIA. The source of the fourth NMOS transistor and the drain of the fourth PMOS transistor are connected to the output terminal of the first inverting amplifier. The drain of the fourth NMOS transistor is connected to a DC power supply, and the source of the fourth PMOS transistor is grounded. The second voltage clamping circuit includes a common-gate fifth PMOS transistor and a fifth NMOS transistor. The gates of the fifth PMOS transistor and the fifth NMOS transistor are connected to the input terminal of the second inverting amplifier. The source of the fifth NMOS transistor and the drain of the fifth PMOS transistor are connected to the output terminal of the second inverting amplifier. The drain of the fifth NMOS transistor is connected to a DC power supply, and the source of the fifth PMOS transistor is grounded. The third voltage clamping circuit includes a common-gate sixth PMOS transistor and a sixth NMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the input terminal of the third inverting amplifier. The source of the sixth NMOS transistor and the drain of the sixth PMOS transistor are connected to the output terminal of the TIA. The drain of the sixth NMOS transistor is connected to the DC power supply, and the source of the sixth PMOS transistor is grounded.

[0021] In one optional implementation, the turn-on voltages of the fourth PMOS and the fourth NMOS are both lower than the turn-on voltages of the first PMOS and the first NMOS. The turn-on voltages of the fifth PMOS and the fifth NMOS are both lower than the turn-on voltages of the second PMOS and the second NMOS. The turn-on voltages of the sixth PMOS and the sixth NMOS are both lower than the turn-on voltages of the third PMOS and the third NMOS.

[0022] In one alternative implementation, the TIA further includes a feedback resistor circuit. A first terminal of the feedback resistor circuit is connected to the output terminal of the TIA. A second terminal of the feedback resistor circuit is connected to the input terminal of the TIA. The feedback resistor circuit is used to convert the input current signal of the TIA into a voltage signal.

[0023] In one optional embodiment, the feedback resistor circuit includes a first feedback branch, a second feedback branch, and a third feedback branch connected in parallel. The first feedback branch includes a first resistor, a second resistor, and a first switch. The first and second resistors are connected in series. The first switch is connected in parallel across the second resistor. The second feedback branch includes a third resistor and a second switch. The third resistor and the second switch are connected in series. The third feedback branch includes a fourth resistor and a third switch. The fourth resistor and the third switch are connected in series.

[0024] In an alternative implementation, the third feedback branch further includes a feedback capacitor. The feedback capacitor is connected in parallel across the fourth resistor. The feedback capacitor is used to compensate for phase margin.

[0025] In an optional implementation, a fourth voltage clamping circuit can be connected in parallel across the feedback resistor circuit. This fourth voltage clamping circuit includes a common-gate third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to the input terminal of the feedback resistor circuit. The source of the third NMOS transistor and the drain of the third PMOS transistor are connected to the output terminal of the feedback resistor circuit. The drain of the second NMOS transistor is connected to a DC power supply, and the source of the second PMOS transistor is grounded.

[0026] In one optional embodiment, the TIA further includes a first load circuit, a second load circuit, and a third load circuit. The first load circuit includes a first load PMOS transistor, a first load NMOS transistor, a fourth switch, and a fifth switch. The gates of the first load PMOS transistor and the first load NMOS transistor are connected. The source and drain of the first load PMOS transistor are connected. The gates of the first load PMOS transistor and the first load NMOS transistor are connected to the source and drain of the first load PMOS transistor and the first load NMOS transistor, respectively.

[0027] The gates of the first load PMOS transistor and the first load NMOS transistor are connected to the output of the first inverting amplifier. The source and drain of the first load PMOS transistor and the first load NMOS transistor are connected to the input of the second inverting amplifier. One end of the fourth switch is connected to a DC power supply, and the other end is connected to the drain of the first load PMOS transistor. One end of the fifth switch is connected to the source of the first load NMOS transistor, and the other end is grounded.

[0028] The second load circuit includes a second load PMOS transistor, a second load NMOS transistor, a third load PMOS transistor, a third load NMOS transistor, a sixth switch, and a seventh switch. The gate of the second load PMOS transistor is connected to the gate of the second load NMOS transistor. The source of the second load PMOS transistor is connected to the drain of the second load NMOS transistor. The gate of the second load PMOS transistor and the gate of the second load NMOS transistor are connected to the source and drain of the second load PMOS transistor and the second load NMOS transistor, respectively.

[0029] The gate of the third load PMOS transistor is connected to the gate of the third load NMOS transistor. The source of the third load PMOS transistor is connected to the drain of the third load NMOS transistor. The gates of the third load PMOS transistor and the third load NMOS transistor are connected to the source and drain of the third load PMOS transistor and the third load NMOS transistor, respectively.

[0030] The gates of the second load PMOS transistor and the second load NMOS transistor are connected to the output of the second inverting amplifier. The source and drain of the second load PMOS transistor and the second load NMOS transistor are connected to the gates of the third load PMOS transistor and the third load NMOS transistor. One end of the sixth switch is connected to a DC power supply, and the other end is connected to the drain of the second load PMOS transistor. One end of the seventh switch is connected to the source of the second load NMOS transistor, and the other end is grounded. The source and drain of the third load PMOS transistor and the third load NMOS transistor are connected to the input of the third inverting amplifier.

[0031] The third load circuit includes a fourth load PMOS transistor and a fourth load NMOS transistor. The gates of the fourth load PMOS transistor and the fourth load NMOS transistor are connected together. The source and drain of the fourth load PMOS transistor are connected together. The gates of the fourth load PMOS transistor and the fourth load NMOS transistor are connected to the output of the third inverting amplifier. The source and drain of the fourth load PMOS transistor are the output of TIA.

[0032] In an optional embodiment, the first load circuit further includes a first load capacitor and an eighth switch. The second load circuit further includes a second feedback capacitor and a ninth switch. One end of the eighth switch is connected to the source of the first load PMOS transistor and the drain of the first load NMOS transistor. The other end is connected to one end of the first load capacitor. The other end of the first load capacitor is grounded. One end of the ninth switch is connected to the source of the third load PMOS transistor and the drain of the third load NMOS transistor. The other end is connected to one end of the second load capacitor, and the other end of the second load capacitor is grounded.

[0033] A third aspect of this application provides a control method for a transimpedance amplifier (TIA). The control method includes the following steps: When the slew rate corresponding to the TIA is a first slew rate, a first switch in the feedback resistor circuit is closed. When the slew rate corresponding to the TIA is a second slew rate, the first switch in the feedback resistor circuit is opened. The TIA includes a first inverting amplifier, a second inverting amplifier, and a third inverting amplifier, as well as a first voltage clamping circuit, a second voltage clamping circuit, and a third voltage clamping circuit.

[0034] A first inverting amplifier, a second inverting amplifier, and a third inverting amplifier are connected in series. A first voltage clamping circuit is connected in parallel across the first inverting amplifier. A second voltage clamping circuit is connected in parallel across the second inverting amplifier. A third voltage clamping circuit is connected in parallel across the third inverting amplifier. The first inverting amplifier includes a common-gate first PMOS transistor and a first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are connected to form the input terminal of the TIA. The source of the first PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the first inverting amplifier.

[0035] The second inverting amplifier includes a common-gate second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to form the input terminal of the second inverting amplifier. The input terminal of the second inverting amplifier is connected to the output terminal of the first inverting amplifier. The source of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the second inverting amplifier.

[0036] The third inverting amplifier includes a third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to form the input terminal of the third inverting amplifier. The input terminal of the third inverting amplifier is connected to the output terminal of the second inverting amplifier. The source of the third PMOS transistor is connected to the drain of the third NMOS transistor to form the output terminal of the TIA.

[0037] The first voltage clamping circuit includes a fourth PMOS transistor and a fourth NMOS transistor. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input terminal of the TIA. The source of the fourth NMOS transistor and the drain of the fourth PMOS transistor are connected to the output terminal of the first inverting amplifier. The drain of the fourth NMOS transistor is connected to a DC power supply, and the source of the fourth PMOS transistor is grounded.

[0038] The second voltage clamping circuit includes a common-gate fifth PMOS transistor and a fifth NMOS transistor. The gates of the fifth PMOS transistor and the fifth NMOS transistor are connected to the input terminal of the second inverting amplifier. The source of the fifth NMOS transistor and the drain of the fifth PMOS transistor are connected to the output terminal of the second inverting amplifier. The drain of the fifth NMOS transistor is connected to a DC power supply, and the source of the fifth PMOS transistor is grounded.

[0039] The third voltage clamping circuit includes a sixth PMOS transistor and a sixth NMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the input terminal of the third inverting amplifier. The source of the sixth NMOS transistor and the drain of the sixth PMOS transistor are connected to the output terminal of the TIA. The drain of the sixth NMOS transistor is connected to the DC power supply, and the source of the sixth PMOS transistor is grounded.

[0040] The TIA may also include a feedback resistor circuit. The first terminal of the feedback resistor circuit is connected to the output terminal of the TIA. The second terminal of the feedback resistor circuit is connected to the input terminal of the TIA. This is used to convert the input current signal of the TIA into a voltage signal. The feedback resistor circuit includes a first feedback branch, a second feedback branch, and a third feedback branch connected in parallel.

[0041] The first feedback branch includes a first resistor, a second resistor, and a first switch. The first and second resistors are connected in series, and the first switch is connected in parallel across the second resistor. The second feedback branch includes a third resistor and a second switch, which are connected in series. The third feedback branch includes a fourth resistor and a third switch, which are connected in series.

[0042] In one optional embodiment, the TIA further includes a first load circuit, a second load circuit, and a third load circuit. The first load circuit includes a first load PMOS transistor, a first load NMOS transistor, a first load switch, and a second load switch. The gates of the first load PMOS transistor and the first load NMOS transistor are connected. The source and drain of the first load PMOS transistor are connected. The gates of the first load PMOS transistor and the first load NMOS transistor are connected to the source and drain of the first load PMOS transistor. The gates of the first load PMOS transistor and the first load NMOS transistor are connected to the output terminal of a first inverting amplifier. The source and drain of the first load PMOS transistor are connected to the input terminal of a second inverting amplifier. One end of the first load switch is connected to a DC power supply, and the other end is connected to the drain of the first load PMOS transistor. One end of the second load switch is connected to the source of the first load NMOS transistor, and the other end is grounded.

[0043] The second load circuit includes a second load PMOS transistor, a second load NMOS transistor, a third load PMOS transistor, a third load NMOS transistor, a third load switch, and a fourth load switch. The gates of the second load PMOS transistor and the second load NMOS transistor are connected. The sources and drains of the second load PMOS transistor and the second load NMOS transistor are connected. The gates of the second load PMOS transistor and the second load NMOS transistor are connected to their respective sources and drains. The gates of the third load PMOS transistor and the third load NMOS transistor are connected. The sources and drains of the third load PMOS transistor and the third load NMOS transistor are connected. The gates of the second load PMOS transistor and the second load NMOS transistor are connected to their respective sources and drains. The gates of the second load PMOS transistor and the second load NMOS transistor are connected to the output of the second inverting amplifier. The sources and drains of the second load PMOS transistor and the second load NMOS transistor are connected to the gates of the third load PMOS transistor and the third load NMOS transistor. One end of the third load switch is connected to the DC power supply, and the other end is connected to the drain of the second load PMOS transistor. One end of the fourth load switch is connected to the source of the second load NMOS transistor, and the other end is grounded.

[0044] The source of the third load PMOS transistor and the drain of the third load NMOS transistor are connected to the input of the third inverting amplifier. The third load circuit includes a fourth load PMOS transistor and a fourth load NMOS transistor. The gates of the fourth load PMOS transistor and the fourth load NMOS transistor are connected. The source of the fourth load PMOS transistor and the drain of the fourth load NMOS transistor are connected. The gates of the fourth load PMOS transistor and the fourth load NMOS transistor are connected to the output of the third inverting amplifier. The source of the fourth load PMOS transistor and the drain of the fourth load NMOS transistor are the output of TIA.

[0045] When TIA corresponds to high-gain mode, the second and third switches are opened. The first, second, third, and fourth load switches are also opened. When TIA corresponds to medium-gain mode, the second switch is closed and the third switch is open. The first and second load switches are open, and the third and fourth load switches are closed. When TIA corresponds to low-gain mode, the second and third switches are closed. The first, second, third, and fourth load switches are also closed.

[0046] A fourth aspect of this application provides a photoelectric converter, which includes a photodetector and a TIA provided by any one of the first aspects described above. Alternatively, it may include a photodetector and a TIA provided by any one of the second aspects described above. The output terminal of the photodetector is connected to the input terminal of the TIA. The photodetector receives an optical signal and converts the optical signal into a current signal. The TIA amplifies the current signal and converts the current signal into a voltage signal.

[0047] The technical solution disclosed in this application adjusts the output voltage of the transimpedance amplifier by connecting a voltage clamping circuit in parallel across the operational amplifier terminals of the transimpedance amplifier. This prevents overvoltage problems in the MOSFETs within the operational amplifier caused by excessively high or low input voltage. This controls the voltage difference between the source and drain of the MOSFETs, ensuring they operate safely and improving the lifespan and performance of the transimpedance amplifier. Attached Figure Description

[0048] Figure 1 This is a system architecture diagram of a passive optical network;

[0049] Figure 2A This is a schematic diagram of the structure of a first type of transimpedance amplifier provided in an embodiment of this application;

[0050] Figure 2B This is a schematic diagram of the structure of a second type of inverting amplifier provided in an embodiment of this application;

[0051] Figure 3 The output voltage variation curve provided in the embodiments of this application;

[0052] Figure 4A This is a schematic diagram of the structure of the first feedback resistor circuit provided in the embodiments of this application;

[0053] Figure 4B This is a schematic diagram of the structure of the second feedback resistor circuit provided in the embodiments of this application;

[0054] Figure 5 This is a schematic diagram of the structure of a third type of transimpedance amplifier provided in the embodiments of this application;

[0055] Figure 6 This is a schematic diagram of the structure of the fourth transimpedance amplifier provided in the embodiments of this application;

[0056] Figure 7 This is a schematic diagram of the structure of the fifth transimpedance amplifier provided in the embodiments of this application;

[0057] Figure 8 This is a flowchart illustrating a control method for a transimpedance amplifier provided in an embodiment of this application. Detailed Implementation

[0058] This application provides a transimpedance amplifier and its control method. By connecting a voltage clamping circuit in parallel across the operational amplifier (op-amp) of the TIA, the voltage at the output of the transimpedance amplifier is adjusted. This prevents overvoltage problems in the CMOS transistor of the op-amp due to excessively high or low input voltage. This controls the voltage difference between the source and drain of the CMOS transistor, ensuring the CMOS transistor operates safely. This improves the lifespan and performance of the TIA.

[0059] A Transducer Amplifier (TIA) is a type of amplifier, a crucial component used to convert and amplify current signals into voltage signals. Based on Ohm's law, the TIA achieves this conversion through a feedback resistor, effectively functioning as a resistor. Due to its high bandwidth, the TIA is generally used in high-speed circuits. For example, it is frequently used in optoelectronic transmission and communication systems.

[0060] Taking passive optical network (PON) as an example, TIA is often used in the receiver of PON to capture the optical signals transmitted in the network. Figure 1 This is a system architecture diagram for a passive optical network. (Example:) Figure 1 As shown, a PON consists of an optical distribution network (ODN), an optical line terminal (OLT) at the central office, and optical network units (ONUs) at the user side. If the ONU directly provides user port functionality, such as the Ethernet user port functionality used by a personal computer (PC) for internet access, then the ONU is called an optical network terminal (ONT). It should be understood that the ONU mentioned below refers to both ONU and ONT, without specific limitations.

[0061] In a PON system, the OLT provides the network-side interface, while the ONU provides the user-side interface. The Optical Distribution Network (ODN) connects the OLT and ONU. The ODN is a network composed of optical fibers and passive optical splitters, used to distribute or multiplex data signals between the OLT and ONU. In a PON system, data transmission from the OLT to the ONU is called downlink, and data transmission from the ONU to the OLT is called uplink.

[0062] PON primarily employs a point-to-multipoint access method. The OLT establishes communication with all ONUs in the PON network through an optical splitter. During uplink transmission, the ONU communicates with the OLT using time-division multiplexing. The ONU is in an off state when no signal is being transmitted, and quickly turns on when a signal is being transmitted. Thus, each communication signal from each ONU is a burst optical signal. This requires the receiver on the OLT side to have the ability to quickly capture burst optical signals within a certain dynamic range. The insertion loss of each link between the OLT and ONUs is different. Therefore, the average power and phase of multiple burst optical signals arriving at the OLT will be different. This necessitates converting the burst optical signals into voltage signals and amplifying the voltage signals to the same level before subsequent signal processing can proceed.

[0063] Existing transimpedance amplifiers (TIAs) consist of a common-gate PMOS transistor and an NMOS transistor. The source of the PMOS transistor and the drain of the NMOS transistor are connected to form the output terminal. When a large current signal is injected into the TIA, the input voltage becomes too high. This results in an excessively low output voltage. This leads to an excessively large voltage difference between the source and drain of the PMOS transistor, causing overvoltage in the PMOS transistor. This voltage difference may exceed the breakdown voltage of the PMOS transistor, damaging it. Similarly, when the input voltage is too low, the output voltage will be very high. This will create a large voltage difference between the source and drain of the NMOS transistor, causing overvoltage in the NMOS transistor. The voltage between the source and drain will exceed the breakdown voltage of the NMOS transistor, damaging it. This severely affects the lifespan and performance of the transimpedance amplifier.

[0064] To address the aforementioned issues, this application embodiment adds a voltage clamping circuit to the original TIA structure. This voltage clamping circuit controls the range of the output voltage, limiting it to a reasonable range. This prevents overvoltage of the PMOS and NMOS transistors due to excessively high or low input voltage, ensuring the safe operation of the CMOS transistors within the TIA. This improves the lifespan and performance of the TIA.

[0065] Figure 2A This is a schematic diagram of the structure of a first type of TIA provided in an embodiment of this application. Figure 2A As shown, the TIA includes an inverting amplifier circuit, a voltage clamping circuit, and a feedback resistor circuit. The TIA can serve as a front-end amplifier for a photodetector. The two ends of the inverting amplifier circuit are the input and output terminals of the TIA, respectively. The input terminal can be connected to a photodiode to receive current signals. The other input terminal can be connected to a signal processing circuit to perform subsequent signal processing on the converted voltage signal. In essence, this TIA is a single-stage amplifier, performing the first amplification of the signal.

[0066] In this circuit, a voltage clamping circuit and a feedback resistor circuit are connected in parallel across the inverting amplifier circuit. The voltage clamping circuit controls the amplitude of the output voltage. The feedback resistor forms a feedback system, converting the current signal into a voltage signal. The inverting amplifier circuit can be a CMOS structure. The feedback resistor is connected in parallel between the input and output terminals of the inverting amplifier circuit. According to the principle of "virtual short and virtual open," if the input current is i and the corresponding resistance of the feedback resistor circuit is RF, then the output voltage Vout is equal to -Rf*i. The inverting amplifier circuit can internally consist of a series-connected PMOS transistor and an NMOS transistor. The PMOS and NMOS transistors share a common gate, which serves as the input terminal of the inverting amplifier. The drain of the PMOS transistor is connected to the power supply, which provides the drain voltage. The source of the PMOS transistor is connected to the drain of the NMOS transistor, forming the output terminal of the inverting amplifier. The drain of the NMOS transistor can be grounded, or resistors, inductors, or other components can be connected to increase the current capability; there are no specific limitations.

[0067] The amplification factor of the inverting amplifier is (gmN + gmP) * (roN / / roP). gmN and gmP are the transconductances of the NMOS and PMOS, respectively. roN and roP are the drain output impedances of the NMOS and PMOS, respectively. If the feedback resistor is RF1, then the amplification factor of the entire transimpedance amplifier is A * Rf1 / (1 + A), where A = (gmN + gmP) * (roN / / roP). It can be understood that the above transimpedance amplifier is a single-stage amplifier structure, and a multi-stage amplifier structure can also be constructed based on this structure. That is, the transimpedance amplifier can include multiple inverting amplifier circuits connected in series. The output of the previous inverting amplifier circuit is connected to the input of the next inverting amplifier circuit. Finally, by adding a feedback resistor across the series-connected inverting amplifiers, a multi-stage transimpedance amplifier TIA can be obtained.

[0068] Figure 2B This is a circuit diagram of a second type of transimpedance amplifier provided in an embodiment of this application. It is understood that... Figure 2B The structure shown is Figure 2A The diagram shows the internal circuitry of the inverting amplifier and voltage clamping circuit. The inverting amplifier includes a common-gate first PMOS transistor P1 and a first NMOS transistor N1. The gates of P1 and N1 are connected to form the input terminal of the inverting amplifier. This input terminal is also the input terminal of the transimpedance amplifier TIA. The source of P1 and the drain of N1 are connected to form the output terminal of the inverting amplifier. This output terminal is also the output terminal of the transimpedance amplifier TIA. The drain of P1 is connected to the power supply, providing the drain voltage VDD12. The source of N1 can be designed according to specific circumstances. It can be directly grounded, or connected to a resistor or capacitor, etc., to achieve other circuit functions; the specific design is not limited.

[0069] The voltage clamping circuit is connected in parallel across the inverting amplifier circuit. It includes a common-gate second PMOS transistor PC1 and a second NMOS transistor PC2. The gates of PC1 and PC2 are connected together and to the input of the inverting amplifier circuit. The drain of NC1 is connected to the power supply, providing the drain voltage VDD. Clamp The source of NC1 is connected to the drain of PC1, and then connected to the output of the inverting amplifier circuit. Finally, the source of PC1 is grounded.

[0070] In this circuit, the turn-on voltages of NC1 and PC1 are higher than those of P1 and N1. Therefore, when the input voltage Vin is within its normal swing range, the gate voltages of NC1 and PC1 do not reach their turn-on voltages and are thus in the off state. At this time, the voltage clamping circuit is inactive and does not affect the inverting amplification performance of the TIA. However, if Vin becomes too high or too low, the conduction state of the CMOS transistor in the voltage clamping circuit will change. This allows for the adjustment of the Vout voltage value.

[0071] Specifically, the voltage clamping module compensates for the load current based on Vin, thereby controlling the value of Vout. As shown in the figure, when Vin (gate voltage) is too low, transistors N1 and NC1 are cut off, while transistors P1 and PC1 are turned on. The compensation current i... H The current is supplied to P1 by PC1. The current direction is from P1 to PC1 and then to ground. This reduces the Vout voltage value, ensuring that Vout does not become too high. This prevents the voltage difference between the drain and source of N1 from becoming too high, avoiding overvoltage in N1 and ensuring that N1 operates safely. When Vin is too high, P1 and PC1 are cut off, while N1 and NC1 are turned on. The compensation current i... L The current is supplied to N1 by NC1, flowing from NC1 to N1 and then to ground. This increases the Vout voltage, preventing it from becoming too low. This also prevents excessive voltage difference between the drain and source of P1, thus avoiding overvoltage and ensuring P1 operates safely.

[0072] In the aforementioned TIA, the voltage clamping module compensates the load circuit based on the input voltage. This protects the output voltage, keeping it within the normal range. It prevents excessive voltage differences between the drain and source of the CMOS transistor, thus avoiding overvoltage and ensuring the CMOS transistor operates safely. It also prevents sudden changes in current signals from causing the operating point to deviate from the breakdown point, which could damage the CMOS transistor, thereby improving the TIA's performance. Furthermore, the voltage clamping module offers advantages such as fast response speed, handling instantaneous voltage changes at various nodes caused by sudden signals, thus enhancing the TIA's stability.

[0073] Figure 3 A graph showing the change in output voltage provided in an embodiment of this application. Figure 3 As shown, the horizontal axis represents the input voltage Vin, and the vertical axis represents the output voltage Vout. Curve 1 shows the variation of Vout with Vin without a voltage clamping circuit. Curve 2 shows the variation of Vout with Vin after the voltage clamping circuit is connected.

[0074] Depend on Figure 3 It can be seen that when the input voltage Vin is at the normal operating point of 600mV, the Vout corresponding to curves 1 and 2 remains unchanged. That is, when Vin is within the normal operating swing, the voltage clamping circuit does not affect the gain of the TIA. Then, as the range of the input voltage Vin increases (becomes larger or smaller), the range of Vout corresponding to the TIA without the voltage clamping circuit becomes very large, easily causing overvoltage of the CMOS transistors. However, the Vout of the TIA with the voltage clamping circuit is limited to between 300mV and 900mV. This voltage is neither too high nor too low, ensuring that all transistors inside the transimpedance amplifier are in a safe operating state.

[0075] The following section describes the effect of the feedback resistor circuit on the gain of the transimpedance amplifier (TIA). The feedback resistor circuit is used to convert the input current signal into a voltage signal. As described above, the amplification factor (gain) of the transimpedance amplifier is A*Rf1 / (1+A), where A = (gmN+gmP)*(roN / / roP). From the formula, it can be seen that the gain is related to the resistance value of the feedback resistor, the transconductance of the CMOS transistor, and the drain-off output impedance. The larger the resistance value of the feedback resistor, the higher the gain of the transimpedance amplifier. Therefore, the gain of the transimpedance amplifier can be changed by designing a feedback resistor circuit to control the value of the feedback resistor.

[0076] The slew rate of a transimpedance amplifier can also be adjusted by designing a feedback resistor circuit. Slew rate is a crucial performance indicator (SRI) for operational amplifiers, measuring their ability to reproduce details accurately. It is defined as the rate of rise of the op-amp's output when a large signal is input to the op-amp in a closed-loop system. When the input signal changes too rapidly, the output cannot keep pace with the input due to the op-amp's internal RC time constant. The slew rate can typically be adjusted by designing a feedback resistor circuit.

[0077] Figure 4A This is a schematic diagram of the structure of a first type of feedback resistor circuit provided in an embodiment of this application. Figure 4AAs shown, the feedback resistor circuit is connected in parallel across the inverting amplifier, specifically between the input and output terminals of the TIA. The feedback resistor circuit comprises three parallel feedback branches. The first feedback branch includes resistors RF1 and RF4 connected in series. A switch M1 is connected in parallel across RF4. The second feedback branch includes resistor RF2 and switch M2, connected in series. The third feedback branch includes resistor RF3 and switch M3, connected in series.

[0078] This feedback resistor circuit can provide switching between two slew rates and three gain modes. For example, when it is necessary to control the slew rate of the transimpedance amplifier to a first slew rate, such as 10G, the switch M1 on the first feedback branch can be closed. In this case, only RF1 exists in the first feedback branch. When it is necessary to control the slew rate of the transimpedance amplifier to a second slew rate, such as 2.5G, the switch M1 on the first feedback branch is opened. In this case, both RF1 and RF4 exist in the first feedback branch, enabling switching between the two slew rates.

[0079] Simultaneously, the conduction states of switches M2 and M3 in the second and third feedback branches are controlled to achieve switching between different gain modes. If the transimpedance amplifier requires a high-gain mode, switches M2 and M3 in both the second and third feedback branches can be kept in the off state. In this way, the resistance of the entire feedback loop is the resistance of RF1 or the resistance of RF1 and RE4 in series. At this time, the feedback resistor value is the maximum, and its corresponding gain is the highest.

[0080] If the transimpedance amplifier requires a medium-gain mode, switch M2 in the second feedback branch can be closed, and switch M3 in the third feedback branch can be opened. In this way, the resistance of the entire feedback loop is either the resistance of RF1 and RF2 connected in parallel, or the resistance of RF1 and RE4 connected in series first and then in parallel with RF2. Understandably, the more resistors are connected in parallel, the smaller the resistance value. Therefore, the parallel connection of RF2 in the second feedback branch will cause the feedback resistor value to decrease, and its corresponding gain will also decrease.

[0081] When the transimpedance amplifier requires a low-gain mode, both switch M2 in the second feedback branch and switch M3 in the third feedback branch can be kept closed. In this case, the resistance of the entire feedback loop is the resistance of RF1, RF2, and RF3 connected in parallel, or the resistance of RF1 and RE4 connected in series first and then in parallel with RF2 and RF3. At this point, the feedback resistor is at its minimum, and the corresponding gain is lowest. During the gain reduction process, the open-loop dominant pole rises due to the decrease in feedback resistance, which leads to a decrease in loop stability. Therefore, a feedback capacitor C3 can be added to the third feedback branch, increasing the feedback capacitance. C3 is connected in parallel across RF3 to compensate for the phase margin.

[0082] In a preferred embodiment, a voltage clamping circuit can also be connected across the feedback resistor circuit to control the input voltage. Figure 4B This is a schematic diagram of the structure of a second type of feedback resistor circuit provided in an embodiment of this application. Figure 4B As shown, another voltage clamping circuit is connected across the feedback resistor circuit. This voltage clamping circuit consists of an NMOS transistor NC2 and a PMOS transistor PC2. The gates of NC2 and PC2 are connected together and to the input of the feedback resistor circuit. The source of NC2 is connected to the drain of PC2 and to the output of the feedback resistor circuit. The drain of NC2 is connected to the drain power supply, and the source of PC2 is grounded.

[0083] Since this voltage clamping circuit is connected to the feedback branch, it can clamp the input voltage Vin. The specific principle is similar to that of the voltage clamping circuit described above, and will not be elaborated here. By clamping the input voltage Vin, the value of Vin can be controlled. This effectively controls the value of Vout, preventing the source-drain voltage difference between the PMOS and NMOS transistors from becoming too large. This avoids breakdown of both transistors, thereby improving their lifespan and performance.

[0084] The load circuit of the transimpedance amplifier is described below. It should be understood that the output of the op-amp can also be connected to a load circuit to adjust the gain of the TIA. For example, the load circuit can be composed of a resistor to change the drain-off output impedance. Preferably, the resistor can also be replaced by a load CMOS transistor, which is equivalent to an adjustable resistor. For example, the load circuit includes a load PMOS transistor and a load NMOS transistor. The gates of the load PMOS transistor and the load NMOS transistor are connected to form the input of the load circuit. The source and drain of the load PMOS transistor are connected. The gates of the load PMOS transistor and the load NMOS transistor are connected to the source and drain of the load PMOS transistor and the load NMOS transistor, respectively, thus forming a parallel connection. The gain of the inverting amplifier circuit can be adjusted through the load PMOS transistor and the load NMOS transistor.

[0085] The load circuit may also include a load capacitor to adjust the open-loop bandwidth of the inverting amplifier circuit. Specifically, one end of the load capacitor is connected to the source of the load PMOS transistor and the drain of the load NMOS transistor. The other end of the load capacitor is grounded to improve the performance of the entire transimpedance amplifier.

[0086] The transimpedance amplifiers described in the above embodiments are all single-stage amplifiers. Based on the above structure, multi-stage transimpedance amplifiers can also be constructed. A three-stage amplifier is described below as an example. It is understood that the structures of five-stage amplifiers, seven-stage amplifiers, and other multi-stage amplifiers can all refer to the three-stage amplifier structure, and their working principles are similar; therefore, they will not be elaborated upon here.

[0087] Figure 5 This is a schematic diagram of the structure of a third type of transimpedance amplifier provided in an embodiment of this application. Figure 5 As shown, the TIA is a three-stage amplification structure, consisting of three inverting amplifiers connected in series. The output of the first inverting amplifier becomes the input of the next. When a current signal is transmitted to the first-stage inverting amplifier, it converts the current signal into a voltage signal and transmits it to the second-stage inverting amplifier for inverse amplification. Then, it is transmitted through the second-stage inverting amplifier to the third-stage inverting amplifier for further inverse amplification. The total gain of the transimpedance amplifier is the product of the amplification factors of each inverting amplifier.

[0088] Each stage of the inverting amplifier has a corresponding voltage clamping circuit. That is, this transimpedance amplifier includes three voltage clamping circuits. Each voltage clamping circuit is connected in parallel across each stage of the inverting amplifier to limit the output voltage of each stage. This ensures that the CMOS transistors in each stage of the inverting amplifier are in a safe operating state, preventing damage to the CMOS transistors due to overvoltage. The control of the output voltage of each stage of the inverting amplifier by the voltage clamping circuits can be understood by referring to the limiting principle of the voltage clamping circuit in the single-stage amplifier described above, and will not be elaborated upon here.

[0089] The three-stage transimpedance amplifier also includes a feedback resistor circuit. This feedback resistor circuit is connected in parallel between the output of the first-stage inverting amplifier and the input of the third-stage inverting amplifier to convert the current signal into a voltage signal. For example, the internal structure of this feedback resistor circuit can be similar to... Figure 4A and Figure 4B The feedback resistor circuits in the illustrated embodiments have the same structure, including multiple feedback branches connected in parallel. The resistance value of the feedback resistor circuit is controlled by connecting and disconnecting the feedback branches, thereby affecting the gain of the entire cross-group amplifier and providing multiple gain modes.

[0090] Each stage of the inverting amplifier can also be connected to a load circuit. The output of the first-stage inverting amplifier is connected to the input of the first load circuit, and the output of the first load circuit is connected to the input of the second-stage inverting amplifier. The output of the second-stage inverting amplifier is connected to the input of the second load circuit, and the output of the second load circuit is connected to the input of the third-stage inverting amplifier. The output of the third-stage inverting amplifier is connected to the input of the third load circuit, and the output of the third load circuit is the output of the entire transimpedance amplifier.

[0091] In a three-stage transimpedance amplifier, the load circuit in each stage is also used to adjust the gain of the transimpedance amplifier. Similarly, the load circuit can be composed of resistors to change the out-of-drain output impedance. The load circuit can also be composed of load CMOS transistors, which act as adjustable resistors to adjust the gain of the transimpedance amplifier. The load circuit can also include load capacitors to adjust the bandwidth of the transimpedance amplifier.

[0092] Based on the above description, the circuit structure of each stage of a three-stage transimpedance amplifier can be exactly the same. Figure 6 This is a schematic diagram of the structure of a fourth type of transimpedance amplifier provided in an embodiment of this application. Figure 6 As shown, TIA is a three-stage amplification structure. In each stage, the inverting amplifier consists of a PMOS transistor and an NMOS transistor. The load circuit consists of a switch, a PMOS transistor, an NMOS transistor, and a load capacitor, and the structure of each stage is identical.

[0093] In the first-stage amplification structure, the first inverting amplifier includes a common-gate PMOS transistor P1 and an NMOS transistor N1. The gates of P1 and N1 are connected to form the input terminal of the transimpedance amplifier. The drain of P1 is connected to the power supply, which provides a drain voltage. The source of P1 is connected to the drain of N1, forming the output terminal of the first inverting amplifier. The source of N1 can be grounded.

[0094] The output of the first inverting amplifier is used to connect to the first load circuit. For example, the first load circuit includes a load PMOS transistor P4 and a load NMOS transistor N4. The gates of P4 and N4 are interconnected and connected to the output of the first inverting amplifier. The source of P4 and the drain of N4 are connected, and also connected to the gates of P4 and N4, thus forming a parallel structure. Simultaneously, the drain of P4 is connected to switch M4, which connects it to the drain power supply. The source of N4 is connected to switch M5, which grounds it.

[0095] Simultaneously, the first load circuit also includes a load capacitor C1. One end of the load capacitor C1 is grounded, and the other end is connected to the source of P4. The source of P4 and the drain of N4 are connected to form the output terminal of the first load circuit, which is connected to the input terminal of the second-stage amplification structure. Furthermore, the first-stage amplification mechanism includes a first voltage clamping circuit, which is connected in parallel across the first-stage amplification structure to address overvoltage issues in the circuit. Its internal structure is referenced [reference needed]. Figure 2B The structure of the voltage clamping circuit in the illustrated embodiment will not be described in detail here.

[0096] Similarly, the second-stage amplification structure is exactly the same as the first-stage amplification structure. It also includes a second inverting amplifier, a second load circuit, and a second voltage clamping circuit. The second voltage clamping circuit is connected in parallel between the input of the second inverting amplifier and the output of the second load circuit. For the specific internal structure of each component, please refer to the structure of each part in the first-stage amplification structure; it will not be repeated here. The third-stage amplification structure is also exactly the same as the first and second-stage amplification structures, including a third inverting amplifier, a third load circuit, and a third voltage clamping circuit. The third voltage clamping circuit is connected in parallel between the input of the third inverting amplifier and the output of the third load circuit. Its internal structure is also as described in the first-stage amplification structure; it will not be repeated here.

[0097] It should be understood that a feedback resistor circuit is connected in parallel between the output and input terminals of the aforementioned transimpedance amplifier. This feedback resistor circuit... Figure 4A or Figure 4B The feedback resistor circuit shown has the same structure. By controlling the switches in the feedback resistor circuit and the switches in the three load circuits, the two conversion rates and three gain modes of the transimpedance amplifier can be switched.

[0098] When the three-stage transimpedance amplifier needs to switch to the first slew rate, such as 10 GHz, switch M1 on the first feedback branch can be closed. In this case, only RF1 exists in the first feedback branch. When the slew rate of the transimpedance amplifier needs to be controlled to the second slew rate, such as 2.5 GHz, switch M1 on the first feedback branch is opened. In this case, RF1 and RF4 exist in the first feedback branch, enabling switching between the two slew rates.

[0099] When the transimpedance amplifier is at the first slew rate, switch M1 in the first feedback branch is open. At this time, the conduction state of other switches can be controlled to switch the gain mode at the first slew rate. Specifically, if the transimpedance amplifier needs to switch to a high-gain mode, switches M2 in the second feedback branch and M3 in the third feedback branch can be kept open. Furthermore, switches M4 and M5 in the first-stage load circuit, switches M6 and M7 in the second-stage load circuit, and switches M8 and M9 in the third-stage load circuit can all be kept open. In this way, the resistance of the load circuit is at its maximum, and the feedback resistor in the feedback circuit is also at its maximum, resulting in the highest gain, corresponding to the high-gain mode.

[0100] If the transimpedance amplifier needs to be switched to medium gain mode, switch M2 in the second feedback branch can be closed, switch M3 in the third feedback branch can be opened, and switches M4 and M5 in the first load circuit can be opened. Switches M6 and M7 in the second load circuit and switches M8 and M9 in the third load circuit can be closed. This reduces the feedback resistor value because RF2 and RF1 are connected in parallel. Simultaneously, the PMOS and NMOS transistors in the second and third load circuits are connected in parallel, further reducing the load circuit resistance. This results in a decrease in the TIA gain, corresponding to medium gain mode.

[0101] If the transimpedance amplifier needs to be switched to low-gain mode, switches M2 in the second feedback branch and M3 in the third feedback branch can be closed. Furthermore, switches M4 and M5 in the first load circuit, switches M6 and M7 in the second load circuit, and switches M8 and M9 in the third load circuit can all be closed. This brings RF3 back into the feedback circuit, causing the feedback resistor value to decrease again. Simultaneously, in the load circuit, the PMOS and NMOS transistors in the first load circuit are connected in parallel, further reducing the load circuit resistance. This results in the lowest TIA gain, corresponding to low-gain mode. Additionally, load capacitors C1 and C2 can be added in low-gain mode to adjust the bandwidth.

[0102] Similarly, when the transimpedance amplifier is at the second slew rate, i.e., when switch M1 on the first feedback branch is closed, the switching of the three gain modes at this slew rate can also be achieved using the above method. The control method is similar to the control method for gain mode switching at the first slew rate, and will not be elaborated upon here.

[0103] In the aforementioned transimpedance amplifier, switching between two conversion rates and three gain modes can be achieved by controlling the switches in the feedback resistor circuit and the load circuit. This greatly improves the operational flexibility of the TIA, allowing its parameters to be adjusted according to specific needs and thus enhancing its performance.

[0104] In the aforementioned TIA, switches M7 and M8 correspond to P6 and N6 in the third load circuit. The connection between P6 and N6 can be controlled by adjusting the conduction states of M7 and M8. However, changing the connection method will also affect the resistance value of the third load circuit. Since the control circuit is connected to the third load circuit, its resistance value directly affects the steady state of the control circuit. Resistance fluctuations can cause instability in the next stage of the circuit. To solve this problem, Figure 7 This is a schematic diagram of the structure of the fifth transimpedance amplifier provided in the embodiments of this application. Figure 7 As shown, the transimpedance amplifier has a three-stage amplification structure, including three inverting amplifiers (first to third inverting amplifiers), three voltage clamping circuits (first to third voltage clamping circuits), and three load circuits (first to third load circuits).

[0105] In this circuit, the input terminal of the first inverting amplifier is also the input terminal of the transimpedance amplifier. The output terminal of the first inverting amplifier is connected to the input terminal of the first load circuit. The output terminal of the first load circuit is connected to the input terminal of the second inverting amplifier. The output terminal of the second load circuit is connected to the input terminal of the third inverting amplifier. The output terminal of the third inverting amplifier is also connected to the input terminal of the third load circuit. The output terminal of the third load circuit is the output terminal of the transimpedance amplifier.

[0106] The first voltage clamping circuit is connected in parallel between the input of the first inverting amplifier and the output of the first load circuit. The second voltage clamping circuit is connected in parallel between the input of the second inverting amplifier and the output of the second load circuit. The third voltage clamping circuit is connected in parallel between the input of the third inverting amplifier and the output of the third load circuit.

[0107] Among them, the structures of the first to third inverting amplifiers are similar to Figure 6 The structures of the first to third inverting amplifiers in the illustrated embodiment are similar and will not be described in detail here. The first, second, and third voltage clamping circuits are also used to limit the output voltage of each inverting amplifier stage, ensuring that the CMOS transistors in each stage are in a safe operating state and preventing damage to the CMOS transistors due to overvoltage. It is understood that the structure of the voltage clamping circuits and the control of the output voltage of each inverting amplifier stage can refer to the limiting principle of the voltage clamping circuit in the single-stage amplifier described above, and will not be elaborated upon here.

[0108] Figure 7 The illustrated embodiments and Figure 6 Compared to the illustrated embodiment, the corresponding load circuit structure is slightly different. Specifically, in Figure 7In the illustrated embodiment, the first load circuit includes a load PMOS transistor P4 and a load NMOS transistor N4. The gates of P4 and N4 are interconnected and connected to the output of the first inverting amplifier. The source of P4 and the drain of N4 are connected, and also connected to the gates of P4 and N4. Simultaneously, the drain of P4 is connected to switch M4, which connects it to the drain power supply. The source of N4 is connected to switch M5, which grounds it. The first load circuit also includes a load capacitor C1. One end of the load capacitor C1 is grounded, and the other end is connected to the source of P4. The connection between the source of P4 and the drain of N4 forms the output of the first load circuit. This output is connected to the input of the second inverting amplifier.

[0109] The second load circuit includes load PMOS transistor P5 and load NMOS transistor N5, as well as load PMOS transistor P7 and load NMOS transistor N7. The gates of P5 and N5 are interconnected and connected to the output of the second inverting amplifier. The source of P5 and the drain of N5 are connected, and also connected to the gates of both P5 and N5. Simultaneously, the drain of P5 is connected to switch M6, which connects it to the drain power supply. The source of N5 is connected to switch M7, which grounds it.

[0110] In this circuit, the gates of P7 and N7 are interconnected and connected to the source of P5 and the drain of N5. The source of P7 and the drain of N7 are connected, and also connected to the gates of P7 and N7. The drain of P7 is connected to the drain power supply, and N7 is grounded. The second load circuit also includes a load capacitor C2, one end of which is grounded, and the other end is connected to the source of P7 and the drain of N7. The connection between the source of P7 and the drain of N7 forms the output terminal of the second load circuit. This output terminal is connected to the input terminal of the third-stage amplifier structure.

[0111] The third load circuit includes a load PMOS transistor P6 and a load NMOS transistor N6. The gates of P6 and N6 are interconnected and connected to the output of the third inverting amplifier. The source of P6 and the drain of N6 are connected, and also connected to the gates of P6 and N6, forming a parallel structure. Simultaneously, P6 is connected to its drain power supply, and the source of N6 is grounded. The connection between the source of P6 and the drain of N6 forms the output of the third load circuit. This output is also the output of the entire transimpedance amplifier.

[0112] In the above structure, the resistance value of the third load circuit is fixed. Therefore, if the TIA needs to switch to high-gain mode, both switch M2 in the second feedback branch and switch M3 in the third feedback branch can be controlled to be in the open state. Furthermore, switches M4 and M5 in the first-stage load circuit, and switches M6 and M7 in the second-stage load circuit, can also be controlled to be in the open state. In this way, the resistance value of the load circuit is at its maximum, and the feedback resistor value of the feedback circuit is also at its maximum. Therefore, the gain is the highest, corresponding to the high-gain mode.

[0113] If the TIA needs to switch to medium gain mode, switch M2 on the second feedback branch can be closed, and switch M3 on the third feedback branch can be opened. Simultaneously, switches M4 and M5 in the first load circuit are opened, while switches M6 and M7 in the second load circuit are closed. This reduces the feedback resistor value because RF2 and RF1 are connected in parallel. Furthermore, in the load circuits, the PMOS and NMOS transistors in the second and third load circuits are connected in parallel. This further reduces the resistance of the load circuit, thus lowering the gain, corresponding to the medium gain mode.

[0114] If the TIA needs to switch to low-gain mode, switches M2 in the second feedback branch and M3 in the third feedback branch can be closed. Furthermore, switches M4 and M5 in the first load circuit, and switches M6 and M7 in the second-stage load circuit, are also closed. This brings RF3 back into the feedback circuit, causing the feedback resistor value to decrease again. Simultaneously, in the load circuit, the PMOS and NMOS transistors in the first load circuit are connected in parallel, further reducing the load circuit resistance. This results in the lowest gain, corresponding to low-gain mode. Additionally, load capacitors C1 and C2 can be added in low-gain mode to adjust the bandwidth.

[0115] In the three-stage amplification structure of the TIA described above, since the load PMOS and load NMOS transistors in the third load circuit are fixed, their corresponding output impedances are also fixed. This is beneficial for the subsequent control circuit to maintain a steady state. Furthermore, by controlling the switching of the first and second load circuits, three gain modes can be achieved. Therefore, the TIA offers superior performance and improves the stability of the transimpedance amplifier.

[0116] In combination with the above Figure 7 The circuit diagram of the transimpedance amplifier shown is as follows. Figure 8 This is a flowchart illustrating a control method for a transimpedance amplifier provided in an embodiment of this application. Figure 8 As shown, the control method includes:

[0117] 801. When the slew rate corresponding to the transimpedance amplifier is the first slew rate, the first switch in the control feedback resistor circuit is closed.

[0118] The structure of the transimpedance amplifier can be referenced. Figure 7 The illustrated embodiment shows the structure of the transimpedance amplifier. The structure of the feedback resistor circuit can be found in [reference needed]. Figure 4A or Figure 4BThe embodiment shown illustrates the structure of the feedback resistor. The first slew rate is greater than the second slew rate. For example, the first slew rate can be 10G, and the second slew rate can be 2.5G. The slew rate switching can be achieved using switch M1 on the first feedback branch of the feedback resistor circuit. Specifically, when the slew rate corresponding to the transimpedance amplifier is 10G, M1 can be closed, so that only the feedback resistor RF1 exists on the first feedback branch.

[0119] 802. When the transimpedance amplifier switches to high gain mode, in the first conversion rate state, the second and third switches in the control feedback resistor circuit are opened.

[0120] When the slew rate of the transimpedance amplifier is fixed, the gain mode can be switched by controlling the switches in the second and third feedback branches, as well as the switch in the load circuit. When the transimpedance amplifier switches to high-gain mode, the resistance of the feedback resistor circuit must reach its maximum. Therefore, both switch M2 in the second feedback branch and switch M3 in the third feedback branch need to be disconnected, so that only RF1 exists in the feedback resistor circuit.

[0121] 803. Control the first load switch and the second load switch in the first load circuit to disconnect, and control the third load switch and the fourth load switch in the second load circuit to disconnect, thereby completing the high-gain mode switching.

[0122] Simultaneously, it is also necessary to control the switches in the first and second load circuits. Specifically, switches M4 and M5 in the first load circuit need to be disconnected, and switches M6 and M7 in the second load circuit need to be disconnected. This ensures that the load in each stage of the load circuit reaches its maximum value. In this way, the overall transimpedance amplifier achieves its highest gain, reaching high-gain mode.

[0123] 804. When the transimpedance amplifier switches to gain mode, the second switch in the control feedback resistor circuit is open and the third switch is closed.

[0124] In medium-gain mode, the gain of TIA is less than that of TOA in high-gain mode. Therefore, it is necessary to reduce the resistance value of the feedback resistor circuit and the load circuit. To do this, switch M2 on the second feedback branch of the feedback resistor circuit can be closed, and switch M3 on the third feedback branch can be opened, causing RF1 and RF2 to be connected in parallel. This will decrease the resistance value of the feedback resistor circuit, thus reducing the gain.

[0125] 805. Control the first load switch and the second load switch in the first load circuit to open, and control the third load switch and the fourth load switch in the second load circuit to close, thus completing the medium gain mode switching.

[0126] Simultaneously, the switches in the load circuit also need to be adjusted. Specifically, switches M4 and M5 in the first load circuit need to be disconnected, and switches M6 and M7 in the second load circuit need to be closed. This reduces the load in the second load circuit, thereby reducing the gain of the entire transimpedance amplifier and achieving a medium gain mode.

[0127] 806. When the transimpedance amplifier switches to gain mode, the second and third switches in the control feedback resistor circuit are closed.

[0128] In low-mode, the transimpedance amplifier has the lowest gain. Therefore, it is necessary to further reduce the resistance of the feedback resistor circuit and the load circuit. At this point, both switch M2 on the second feedback branch and switch M3 on the third feedback branch of the feedback resistor circuit can be closed. This connects RF1 to RF3 in parallel, reducing the resistance of the feedback resistor circuit and thus lowering the gain.

[0129] 807. Control the first load switch and the second load switch in the first load circuit to close, and control the third load switch and the fourth load switch in the second load circuit to close, thereby completing the low gain mode switching.

[0130] Simultaneously, the switches in the load circuit also need to be adjusted. Specifically, switches M4 and M5 in the first load circuit and switches M6 and M7 in the second load circuit need to be closed. This reduces the load in the first load circuit, thereby further reducing the gain of the entire transimpedance amplifier and reaching a low-gain mode.

[0131] 808. When the slew rate corresponding to the transimpedance amplifier is the second slew rate, the first switch in the control feedback resistor circuit is turned off.

[0132] Since the slew rate can be switched using switch M1 on the first feedback branch of the feedback resistor circuit, when the slew rate of the transimpedance amplifier needs to switch from the first slew rate to the second slew rate, for example, from 10G to 2.5G, M1 can be disconnected. This allows RF1 and RF4 to exist on the first feedback branch. It is understandable that once the slew rate of the transimpedance amplifier is the second slew rate, the gain mode switching at the second slew rate can also be completed according to the above steps. The control method is similar and will not be elaborated here.

[0133] The control method described above for the transimpedance amplifier can achieve multiple switching rates by controlling the switches in the feedback resistor circuit and the load circuit, thereby improving the flexibility and performance of the transimpedance amplifier.

[0134] This application also provides a photoelectric converter, including a transimpedance amplifier and a photodetector. The structure of the transimpedance amplifier can refer to the structure of the transimpedance amplifier described in any of the above embodiments, and is not specifically limited.

[0135] The output of the photodetector is connected to the input of the TIA. The photodetector receives optical signals and converts them into current signals. The TIA amplifies the current signals and converts them into voltage signals.

[0136] The technical terminology used in the embodiments of this invention is for illustrative purposes only and is not intended to limit the invention. In this document, the singular forms “a,” “the,” and “the” are used to include the plural forms as well, unless the context clearly indicates otherwise. Furthermore, the use of “comprising” and / or “including” in the specification means the presence of the stated feature, integral, step, operation, element, and / or component, but does not preclude the presence or addition of one or more other features, integrals, steps, operations, elements, and / or components.

[0137] The equivalents (if any) of the corresponding structures, materials, actions, and all means or steps and functional elements in the appended claims are intended to include any structure, material, or action used in conjunction with other expressly claimed elements to perform the function. The description of the invention is given for the purposes of illustration and description, but is not intended to be exhaustive or to limit the invention to the forms disclosed.

Claims

1. A transimpedance amplifier (TIA), characterized in that, The TIA includes an inverting amplifier circuit and a first voltage clamping circuit; wherein: The inverting amplifier circuit and the first voltage clamping circuit are connected in parallel. The inverting amplifier circuit includes a first PMOS transistor and a first NMOS transistor with a common gate. The gates of the first PMOS transistor and the first NMOS transistor are connected to form the input terminal of the TIA. The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the inverting amplifier circuit. The first voltage clamping circuit includes a common-gate second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to the input terminal of the TIA, and the source of the second NMOS transistor and the drain of the second PMOS transistor are connected to the output terminal of the TIA. The drain of the second NMOS transistor is connected to a DC power supply, and the source of the second PMOS transistor is grounded. The turn-on voltages of the first PMOS transistor and the first NMOS transistor are both lower than the turn-on voltages of the second PMOS transistor and the second NMOS transistor.

2. The TIA according to claim 1, characterized in that, The TIA also includes a feedback resistor circuit, which is connected in parallel with the inverting amplifier circuit; the feedback resistor circuit is used to convert the input current signal of the TIA into a voltage signal.

3. The TIA according to claim 2, characterized in that, The feedback resistor circuit includes a first feedback branch, a second feedback branch, and a third feedback branch connected in parallel; The first feedback branch includes a first resistor, a second resistor, and a first switch. The first resistor and the second resistor are connected in series, and the first switch is connected in parallel across the two ends of the second resistor. The second feedback branch includes a third resistor and a second switch, wherein the third resistor and the second switch are connected in series; The third feedback branch includes a fourth resistor and a third switch, which are connected in series.

4. The TIA according to claim 3, characterized in that, The third feedback branch also includes a feedback capacitor, which is connected in parallel across the fourth resistor and is used to compensate for the phase margin.

5. The TIA according to claim 3, characterized in that, A second voltage clamping circuit is also connected in parallel across the two ends of the feedback resistor circuit; the second voltage clamping circuit includes a common-gate third PMOS transistor and a third NMOS transistor, the gates of the third PMOS transistor and the third NMOS transistor are connected to the input terminal of the feedback resistor circuit, the source of the third NMOS transistor and the drain of the third PMOS transistor are connected to the output terminal of the feedback resistor circuit; the drain of the third NMOS transistor is connected to a DC power supply, and the source of the third PMOS transistor is grounded.

6. The TIA according to any one of claims 1-5, characterized in that, The TIA also includes a load circuit, the input of which is connected to the output of the inverting amplifier circuit, and the output of which is the output of the transimpedance amplifier TIA; the load circuit is used to adjust the gain of the inverting amplifier circuit.

7. The TIA according to claim 6, characterized in that, The load circuit includes a load PMOS transistor and a load NMOS transistor; wherein: The gate of the load PMOS transistor and the gate of the load NMOS transistor are connected to form the input terminal of the load circuit. The drain of the load PMOS transistor and the drain of the load NMOS transistor are connected. The gate of the load PMOS transistor and the gate of the load NMOS transistor are connected to the source of the load PMOS transistor and the drain of the load NMOS transistor.

8. The TIA according to claim 7, characterized in that, The load circuit also includes a load capacitor, the first end of which is connected to the output terminal of the load circuit, and the second end of which is grounded. The load capacitor is used to adjust the open-loop bandwidth of the inverting amplifier circuit.

9. A transimpedance amplifier (TIA), characterized in that, The TIA includes a first inverting amplifier, a second inverting amplifier, and a third inverting amplifier, as well as a first voltage clamping circuit, a second voltage clamping circuit, and a third voltage clamping circuit; wherein: The first inverting amplifier, the second inverting amplifier, and the third inverting amplifier are connected in series in sequence. The first voltage clamping circuit is connected in parallel across the first inverting amplifier, the second voltage clamping circuit is connected in parallel across the second inverting amplifier, and the third voltage clamping circuit is connected in parallel across the third inverting amplifier. The first inverting amplifier includes a common-gate first PMOS transistor and a first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are connected to form the input terminal of the TIA. The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the first inverting amplifier. The second inverting amplifier includes a common-gate second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to form the input terminal of the second inverting amplifier, and the input terminal of the second inverting amplifier is connected to the output terminal of the first inverting amplifier. The source of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the second inverting amplifier. The third inverting amplifier includes a common-gate third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to form the input terminal of the third inverting amplifier, and the input terminal of the third inverting amplifier is connected to the output terminal of the second inverting amplifier. The source of the third PMOS transistor and the drain of the third NMOS transistor are connected to form the output terminal of the TIA. The first voltage clamping circuit includes a common-gate fourth PMOS transistor and a fourth NMOS transistor. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input terminal of the TIA. The source of the fourth NMOS transistor and the drain of the fourth PMOS transistor are connected to the output terminal of the first inverting amplifier. The drain of the fourth NMOS transistor is connected to a DC power supply, and the source of the fourth PMOS transistor is grounded. The second voltage clamping circuit includes a common-gate fifth PMOS transistor and a fifth NMOS transistor. The gates of the fifth PMOS transistor and the fifth NMOS transistor are connected to the input terminal of the second inverting amplifier. The source of the fifth NMOS transistor and the drain of the fifth PMOS transistor are connected to the output terminal of the second inverting amplifier. The drain of the fifth NMOS transistor is connected to a DC power supply, and the source of the fifth PMOS transistor is grounded. The third voltage clamping circuit includes a sixth PMOS transistor and a sixth NMOS transistor with a common gate. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the input terminal of the third inverting amplifier. The source of the sixth NMOS transistor and the drain of the sixth PMOS transistor are connected to the output terminal of the TIA. The drain of the sixth NMOS transistor is connected to a DC power supply, and the source of the sixth PMOS transistor is grounded.

10. The TIA according to claim 9, characterized in that, The turn-on voltages of the fourth PMOS transistor and the fourth NMOS transistor are both lower than the turn-on voltages of the first PMOS transistor and the first NMOS transistor. The turn-on voltages of the fifth PMOS transistor and the fifth NMOS transistor are both lower than the turn-on voltages of the second PMOS transistor and the second NMOS transistor. The turn-on voltages of the sixth PMOS transistor and the sixth NMOS transistor are both lower than the turn-on voltages of the third PMOS transistor and the third NMOS transistor.

11. The TIA according to claim 9 or 10, characterized in that, The TIA also includes a feedback resistor circuit, with a first terminal connected to the output terminal of the TIA and a second terminal connected to the input terminal of the TIA; the feedback resistor circuit is used to convert the input current signal of the TIA into a voltage signal.

12. The TIA according to claim 11, characterized in that, The feedback resistor circuit includes a first feedback branch, a second feedback branch, and a third feedback branch connected in parallel; The first feedback branch includes a first resistor, a second resistor, and a first switch. The first resistor and the second resistor are connected in series, and the first switch is connected in parallel across the two ends of the second resistor. The second feedback branch includes a third resistor and a second switch, wherein the third resistor and the second switch are connected in series; The third feedback branch includes a fourth resistor and a third switch, which are connected in series.

13. The TIA according to claim 12, characterized in that, The third feedback branch also includes a feedback capacitor, which is connected in parallel across the fourth resistor and is used to compensate for phase margin.

14. The TIA according to claim 12 or 13, characterized in that, A fourth voltage clamping circuit is also connected in parallel across the two ends of the feedback resistor circuit. The fourth voltage clamping circuit includes a common-gate third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to the input terminal of the feedback resistor circuit. The source of the third NMOS transistor and the drain of the third PMOS transistor are connected to the output terminal of the feedback resistor circuit. The drain of the third NMOS transistor is connected to a DC power supply, and the source of the third PMOS transistor is grounded.

15. The TIA according to claim 9, characterized in that, The TIA also includes a first load circuit, a second load circuit, and a third load circuit; The first load circuit includes a first load PMOS transistor, a first load NMOS transistor, a fourth switch, and a fifth switch; the gate of the first load PMOS transistor is connected to the gate of the first load NMOS transistor; the source of the first load PMOS transistor is connected to the drain of the first load NMOS transistor; and the gates of the first load PMOS transistor and the first load NMOS transistor are connected to the source and the drain of the first load PMOS transistor. The gates of the first load PMOS transistor and the first load NMOS transistor are connected to the output terminal of the first inverting amplifier, and the source and drain of the first load PMOS transistor are connected to the input terminal of the second inverting amplifier; one end of the fourth switch is connected to a DC power supply, and the other end is connected to the drain of the first load PMOS transistor; one end of the fifth switch is connected to the source of the first load NMOS transistor, and the other end is grounded. The second load circuit includes a second load PMOS transistor, a second load NMOS transistor, a third load PMOS transistor, a third load NMOS transistor, a sixth switch, and a seventh switch; the gate of the second load PMOS transistor and the gate of the second load NMOS transistor are connected; the source of the second load PMOS transistor and the drain of the second load NMOS transistor are connected; the gate of the second load PMOS transistor and the gate of the second load NMOS transistor are connected to the source of the second load PMOS transistor and the drain of the second load NMOS transistor. The gate of the third load PMOS transistor is connected to the gate of the third load NMOS transistor; the source of the third load PMOS transistor is connected to the drain of the third load NMOS transistor; and the gates of the third load PMOS transistor and the third load NMOS transistor are connected to the source and the drain of the third load PMOS transistor. The gates of the second load PMOS transistor and the second load NMOS transistor are connected to the output terminal of the second inverting amplifier. The source and drain of the second load PMOS transistor and the second load NMOS transistor are connected to the gates of the third load PMOS transistor and the third load NMOS transistor. One end of the sixth switch is connected to a DC power supply, and the other end is connected to the drain of the second load PMOS transistor. One end of the seventh switch is connected to the source of the second load NMOS transistor, and the other end is grounded. The source of the third load PMOS transistor and the drain of the third load NMOS transistor are connected to the input terminal of the third inverting amplifier. The third load circuit includes a fourth load PMOS transistor and a fourth load NMOS transistor; the gate of the fourth load PMOS transistor and the gate of the fourth load NMOS transistor are connected; the source of the fourth load PMOS transistor and the drain of the fourth load NMOS transistor are connected; the gate of the fourth load PMOS transistor and the gate of the fourth load NMOS transistor are connected to the output terminal of the third inverting amplifier; the source of the fourth load PMOS transistor and the drain of the fourth load NMOS transistor are the output terminals of the TIA.

16. The TIA according to claim 15, characterized in that, The first load circuit further includes a first load capacitor and an eighth switch; the second load circuit further includes a second feedback capacitor and a ninth switch. One end of the eighth switch is connected to the source of the first load PMOS transistor and the drain of the first load NMOS transistor, and the other end is connected to one end of the first load capacitor; the other end of the first load capacitor is grounded. One end of the ninth switch is connected to the source of the third load PMOS transistor and the drain of the third load NMOS transistor, and the other end is connected to one end of the second load capacitor; the other end of the second load capacitor is grounded.

17. A control method for a transimpedance amplifier (TIA), characterized in that, The control method includes: When the conversion rate corresponding to the TIA is the first conversion rate, the first switch in the control feedback resistor circuit is closed. When the conversion rate corresponding to the TIA is the second conversion rate, the first switch in the feedback resistor circuit is turned off. The TIA includes a first inverting amplifier, a second inverting amplifier, and a third inverting amplifier, as well as a first voltage clamping circuit, a second voltage clamping circuit, and a third voltage clamping circuit. The first inverting amplifier, the second inverting amplifier, and the third inverting amplifier are connected in series in sequence. The first voltage clamping circuit is connected in parallel across the first inverting amplifier, the second voltage clamping circuit is connected in parallel across the second inverting amplifier, and the third voltage clamping circuit is connected in parallel across the third inverting amplifier. The first inverting amplifier includes a common-gate first PMOS transistor and a first NMOS transistor. The gates of the first PMOS transistor and the first NMOS transistor are connected to form the input terminal of the TIA. The drain of the first PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the first inverting amplifier. The second inverting amplifier includes a common-gate second PMOS transistor and a second NMOS transistor. The gates of the second PMOS transistor and the second NMOS transistor are connected to form the input terminal of the second inverting amplifier, and the input terminal of the second inverting amplifier is connected to the output terminal of the first inverting amplifier. The source of the second PMOS transistor is connected to the drain of the second NMOS transistor to form the output terminal of the second inverting amplifier. The third inverting amplifier includes a common-gate third PMOS transistor and a third NMOS transistor. The gates of the third PMOS transistor and the third NMOS transistor are connected to form the input terminal of the third inverting amplifier, and the input terminal of the third inverting amplifier is connected to the output terminal of the second inverting amplifier. The source of the third PMOS transistor and the drain of the third NMOS transistor are connected to form the output terminal of the TIA. The first voltage clamping circuit includes a common-gate fourth PMOS transistor and a fourth NMOS transistor. The gates of the fourth PMOS transistor and the fourth NMOS transistor are connected to the input terminal of the TIA. The source of the fourth NMOS transistor and the drain of the fourth PMOS transistor are connected to the output terminal of the first inverting amplifier. The drain of the fourth NMOS transistor is connected to a DC power supply, and the source of the fourth PMOS transistor is grounded. The second voltage clamping circuit includes a common-gate fifth PMOS transistor and a fifth NMOS transistor. The gates of the fifth PMOS transistor and the fifth NMOS transistor are connected to the input terminal of the second inverting amplifier. The source of the fifth NMOS transistor and the drain of the fifth PMOS transistor are connected to the output terminal of the second inverting amplifier. The drain of the fifth NMOS transistor is connected to a DC power supply, and the source of the fifth PMOS transistor is grounded. The third voltage clamping circuit includes a common-gate sixth PMOS transistor and a sixth NMOS transistor. The gates of the sixth PMOS transistor and the sixth NMOS transistor are connected to the input terminal of the third inverting amplifier. The source of the sixth NMOS transistor and the drain of the sixth PMOS transistor are connected to the output terminal of the TIA. The drain of the sixth NMOS transistor is connected to a DC power supply, and the source of the sixth PMOS transistor is grounded. The TIA also includes a feedback resistor circuit, with a first terminal connected to the output terminal of the TIA and a second terminal connected to the input terminal of the TIA; the feedback resistor circuit is used to convert the input current signal of the TIA into a voltage signal. The feedback resistor circuit includes a first feedback branch, a second feedback branch, and a third feedback branch connected in parallel; The first feedback branch includes a first resistor, a second resistor, and a first switch. The first resistor and the second resistor are connected in series, and the first switch is connected in parallel across the two ends of the second resistor. The second feedback branch includes a third resistor and a second switch, wherein the third resistor and the second switch are connected in series; The third feedback branch includes a fourth resistor and a third switch, which are connected in series.

18. The control method according to claim 17, characterized in that, The TIA also includes a first load circuit, a second load circuit, and a third load circuit; The first load circuit includes a first load PMOS transistor, a first load NMOS transistor, a first load switch, and a second load switch; the gate of the first load PMOS transistor is connected to the gate of the first load NMOS transistor; the source of the first load PMOS transistor is connected to the drain of the first load NMOS transistor; and the gates of the first load PMOS transistor and the first load NMOS transistor are connected to the source and the drain of the first load PMOS transistor. The gates of the first load PMOS transistor and the first load NMOS transistor are connected to the output terminal of the first inverting amplifier, and the source and drain of the first load PMOS transistor are connected to the input terminal of the second inverting amplifier; one end of the first load switch is connected to a DC power supply, and the other end is connected to the drain of the first load PMOS transistor; one end of the second load switch is connected to the source of the first load NMOS transistor, and the other end is grounded. The second load circuit includes a second load PMOS transistor, a second load NMOS transistor, a third load PMOS transistor, a third load NMOS transistor, a third load switch, and a fourth load switch; the gate of the second load PMOS transistor and the gate of the second load NMOS transistor are connected; the source of the second load PMOS transistor and the drain of the second load NMOS transistor are connected; the gate of the second load PMOS transistor and the gate of the second load NMOS transistor are connected to the source of the second load PMOS transistor and the drain of the second load NMOS transistor. The gate of the third load PMOS transistor is connected to the gate of the third load NMOS transistor; the source of the third load PMOS transistor is connected to the drain of the third load NMOS transistor; and the gates of the third load PMOS transistor and the third load NMOS transistor are connected to the source and the drain of the third load PMOS transistor. The gates of the second load PMOS transistor and the second load NMOS transistor are connected to the output terminal of the second inverting amplifier. The source and drain of the second load PMOS transistor and the second load NMOS transistor are connected to the gates of the third load PMOS transistor and the third load NMOS transistor. One end of the third load switch is connected to a DC power supply, and the other end is connected to the drain of the second load PMOS transistor. One end of the fourth load switch is connected to the source of the second load NMOS transistor, and the other end is grounded. The source of the third load PMOS transistor and the drain of the third load NMOS transistor are connected to the input terminal of the third inverting amplifier. The third load circuit includes a fourth load PMOS transistor and a fourth load NMOS transistor; the gate of the fourth load PMOS transistor and the gate of the fourth load NMOS transistor are connected; the source of the fourth load PMOS transistor and the drain of the fourth load NMOS transistor are connected; the gates of the fourth load PMOS transistor and the fourth load NMOS transistor are connected to the output terminal of the third inverting amplifier; the source of the fourth load PMOS transistor and the drain of the fourth load NMOS transistor are the output terminals of the TIA. When the TIA corresponds to the high-gain mode, the second switch and the third switch are controlled to be disconnected, and the first load switch, the second load switch, the third load switch and the fourth load switch are controlled to be disconnected. When the TIA corresponds to the medium gain mode, the second switch is closed, the third switch is opened, and the first load switch and the second load switch are opened, while the third load switch and the fourth load switch are closed. When the TIA corresponds to the low gain mode, the second switch and the third switch are controlled to close, and the first load switch, the second load switch, the third load switch and the fourth load switch are controlled to close.

19. A photoelectric converter, characterized in that, The photoelectric converter includes a photodetector and a transimpedance amplifier (TIA) as described in any one of claims 1 to 8; or a TIA as described in any one of claims 9 to 16; wherein: The output terminal of the photodetector is connected to the input terminal of the TIA; The photodetector is used to receive optical signals and convert the optical signals into current signals; The TIA is used to amplify the current signal and convert it into a voltage signal.

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