Data receiving device and method for blind deconvolution mechanism

Abstract

A data receiving device with a blind deconvolution mechanism. A descrambling circuit descrambles the received data based on a single-antenna assumption and N data position assumptions within a transmission period, generating N sets of soft-bit data. A soft information processing circuit extracts bit position information to determine invariant and variable bit positions for a blind deconvolution process, including: cyclically storing and superimposing N sets of soft-bit data to generate N sets of superposition results, corresponding to N data position assumptions in N buffers of a buffer circuit; and retaining data corresponding to invariant bit positions at the start of a new transmission period. A post-processing circuit deinterleaves and decodes the N sets of superposition results corresponding to each data sub-block to generate N sets of decoded results for verification. When any N sets of decoded results pass verification, the soft information processing circuit terminates the blind deconvolution process.

Description

Technical Field

[0001] This invention relates to data receiving technology, and more particularly to a data receiving device and method with a blind deconvolution mechanism. Background Technology

[0002] In low-power wide-area networks (LPWANs), users have increasingly higher demands for low power consumption. This is especially true in IoT applications, where a large number of devices need to connect to the network. Some of these devices require low-data-volume transmissions coupled with long waiting times. When a device begins receiving data, it needs to perform blind decoding. The longer the blind decoding takes, the more power the device consumes. Therefore, if a device could possess a more efficient and faster blind decoding mechanism, it would help reduce device power consumption. Summary of the Invention

[0003] In view of the problems of the prior art, the present application provides a data receiving apparatus and method with an accelerated blind deconvolution mechanism to improve the prior art.

[0004] To solve the above-mentioned technical problems, this application is implemented as follows:

[0005] This application provides a data receiving apparatus with a blind deconvolution mechanism, including: a descrambler circuit, a buffer circuit, a soft information processing circuit, and a post-processing circuit. The descrambler circuit is configured to descramble received data from the antenna based on the antenna and N data position assumptions within a transmission period to generate N sets of soft bit data. The received data is generated via a convolutional coding procedure, and each of the N sets of soft bit data has N data sub-blocks within a transmission period. The N data position assumptions sequentially assume that the first data sub-block of the received data is the first original data sub-block to the Nth original data sub-block. The buffer circuit includes N circular buffers, each with a unit coding length. The soft information processing circuit is configured to extract bit position information corresponding to a unit encoding length to determine multiple invariant bit positions and multiple variable bit positions for a blind decoding process. This includes: assuming N data positions corresponding to N circular buffers in the buffer circuit, cyclically storing and superimposing N sets of soft bit data to generate N sets of superposition results; and at the start of the assumed new transmission cycle, retaining data corresponding to the invariant bit positions in the N circular buffers and clearing data corresponding to the variable bit positions in the N circular buffers. The post-processing circuit is configured to deinterleave and decode the N sets of superposition results corresponding to each data sub-block to generate N sets of decoding results for verification, thereby generating N verification results. When the N verification results show that all N sets of decoding results fail verification, the soft information processing circuit continues the blind decoding process to superimpose N sets of soft bit data in the N circular buffers. When the N verification results show that any one of the N sets of decoding results passes verification, the soft information processing circuit terminates the blind decoding process.

[0006] This application further provides a data receiving method with a blind deconvolution mechanism, applied in a data receiving device, comprising: descrambling the received data received from the antenna by a descrambling circuit according to the antenna and N data position assumptions within the transmission period to generate N sets of soft bit data, characterized in that the received data is generated by a convolutional coding procedure, each of the N sets of soft bit data has N data sub-blocks within the transmission period, and the N data position assumptions sequentially assume the first data sub-block of the received data as the first original data sub-block to the Nth original data sub-block; a soft information processing circuit extracts bit position information corresponding to a unit coding length to determine multiple invariant bit positions and multiple variable bit positions; and a blind deconvolution procedure is performed by the soft information processing circuit, including: the soft information processing circuit causing each of the buffer circuits to have N circular buffers of unit encoding length correspond to N data position assumptions. N sets of soft bit data are cyclically stored and superimposed to generate N sets of superposition results. At the start of a new assumed transmission cycle, the N circular buffers retain data at the corresponding invariant bit positions and clear data at the corresponding variable bit positions. The post-processing circuit deinterleaves and decodes the N sets of superposition results corresponding to each data sub-block to generate N sets of decoding results for verification, thus generating N verification results. When the N verification results show that all N sets of decoding results have failed verification, the soft information processing circuit continues the blind decoding process to superimpose N sets of soft bit data onto the N circular buffers. When the N verification results show that any one of the N sets of decoding results has passed verification, the soft information processing circuit terminates the blind decoding process. Attached Figure Description

[0007] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments of this application and are configured to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0008] Figure 1 This shows a block diagram of a data receiving device with an accelerated blind deconvolution mechanism according to an embodiment of the present invention.

[0009] Figure 2 This diagram illustrates how, in another embodiment of the present invention, raw data is encoded into encoded data via an encoding process.

[0010] Figure 3 This diagram illustrates the structure of the data to be transmitted in one embodiment of the present invention.

[0011] Figure 4A This diagram illustrates different received data corresponding to different data location assumptions in one embodiment of the present invention.

[0012] Figure 4B This diagram illustrates soft bit data in one embodiment of the present invention.

[0013] Figures 5A to 5D The following diagrams respectively illustrate soft bit data and a circular buffer in one embodiment of the present invention; and

[0014] Figure 6 This diagram shows a flowchart of a data receiving method with an accelerated blind deconvolution mechanism according to an embodiment of the present invention. Detailed Implementation

[0015] The embodiments of the present invention will be described below with reference to the accompanying drawings. In these drawings, the same reference numerals denote the same or similar components or method flows.

[0016] It must be understood that the use of terms such as "including" or "comprising" in this specification is configured to indicate the presence of specific technical features, values, method steps, work processes, and / or components, but does not preclude the addition of more technical features, values, method steps, work processes, components, or any combination thereof.

[0017] It is important to understand that when a component is described as "connected" or "coupled" to another component, it can be a direct connection or coupling to other components, and intermediate components may be involved. Conversely, when a component is described as "directly connected" or "directly coupled" to another component, it is characterized by the absence of any intermediate components.

[0018] One objective of this invention is to provide a data receiving device and method with an accelerated blind deconvolution mechanism, which performs blind deconvolution by using information from fixed bit positions in accumulated data, thereby reducing the time required to complete the blind deconvolution.

[0019] Please refer to Figure 1 . Figure 1 This diagram shows a block diagram of a data receiving device 100 with an accelerated blind deconvolution mechanism according to an embodiment of the present invention.

[0020] The data receiving device 100 can receive received data RD transmitted from the data transmitting device (not shown) via, for example but not limited to, the narrowband physical broadcast channel (NPBCH) or the narrowband physical downlink shared channel (NPDSCH) of a narrowband Internet of Things (NB-IoT) system.

[0021] The received data RD can be generated by a convolutional coding program executed by the data transmission device. The data receiving device 100 will blindly decode the received data RD after initially receiving it.

[0022] Since the operation of the data receiving device 100 is related to the convolutional coding program executed by the data transmitting device, the following will use the characteristics of tail-biting convolutional code (TBCC) encoding technology as an example to explain how the convolutional coding program is performed. However, the present invention is not limited to this encoding method.

[0023] Please refer to Figure 2 . Figure 2 This diagram illustrates an embodiment of the present invention, showing how raw data A is encoded into encoded data E via an encoding process.

[0024] like Figure 2 As shown, the original data A is a vector of length NA×1, that is, it is data with NA bits, and includes the first and second bit segments to be encoded, SE1 and SE2.

[0025] In one numerical example, the first bit segment to be encoded, SE1, is 6 bits long and includes, for example, but not limited to, a 4-bit system frame number (SFN) and a 2-bit hyper-SFN, the contents of which are variable bits that change with different periods. The second bit segment to be encoded, SE2, is 28 bits long, and its contents remain unchanged over a long period of time. Therefore, NA is 34.

[0026] In step S210, the original data A is augmented by a check code addition procedure to add a third bit segment SE3, such as error detection data B of length NB, becoming data C of length NC×1. The error detection data B can be implemented by, for example, but not limited to, cyclic redundancy check, to verify the correctness of the original data A.

[0027] In one embodiment, the error detection data segment B is generated by operations on the first and second bit segments to be encoded, SE1 and SE2, and its content varies with different periods. In this case, NC = NA + NB. In a numerical example, the length of the third bit segment to be encoded, SE3, is 16 bits. Therefore, NB is 16 and NC is 50.

[0028] In step S220, data C is channel encoded by a channel encoding procedure to combat channel effects.

[0029] In one embodiment, the data transmission device may include L (e.g., 6) buffers and adders, and use these elements to implement tail-biting convolution encoding with a coding rate of, for example, 1 / 3, to generate 3×NC data D that can be represented by a vector. However, the coding rate used in this invention is not limited to this. Therefore, a data with an original length of 50 bits will be encoded to produce data with a total length of 150 bits, and this 150-bit length is defined herein as the unit coding length.

[0030] In one embodiment, the encoding is generated from the first bit segment SE1 (6 bits) to be encoded and the first portion (6 bits) of the second bit segment SE2 adjacent to the first bit segment SE1 and with a length equivalent to the buffer length L. For each of the three encoded data streams (D0, D1, and D2), the variable bits corresponding to the first bit segment SE1 (6 bits) and the second bit segment SE2 will become 6 + 6 = 12 bits, while the unchanged bits will become 28 - 6 = 22. The variable bits corresponding to the third bit segment SE3 will remain 16 bits.

[0031] In step S230, the data D undergoes an interleaving process.

[0032] In one embodiment, the narrowband IoT system interleaves data D using a fixed interleaving algorithm and employs the same interleaving method for all three coded data streams to produce one-dimensional data V with a length of 3NC×1 (still a unit coding length of 150 bits) that can be represented by a vector [V0,V1,V2]. For example, section 5.1.4.2 of the document "Evolved Universal Terrestrial Radio Access (E-UTRA); Multiplexing and channel coding" defines an interleaving method suitable for narrowband IoT systems.

[0033] Although the positions of the changing and invariant bits change and are no longer continuous due to interleaving, the interleaving algorithm is fixed. Therefore, the positions of the changing and invariant bits after interleaving are the same for data from different periods. Furthermore, since encoding and interleaving are performed in three separate paths, the changing and invariant bits also have the same corresponding positions in the three 50-bit vectors V0, V1, and V2 mentioned above. For example, if the 22 invariant bits corresponding to the first vector V0 are represented as UnChangedPos_V = [U0, U1, ..., U20, U21], then the invariant bits corresponding to the second vector V1 and the third vector V2 will be UnChangedPos_V+50 and UnChangedPos_V+100, respectively. The three vectors will contain a total of 66 invariant bits.

[0034] In step S240, the data V undergoes a rate matching procedure and a scrambling procedure to evenly distribute the data to all available resource units, forming a data E to be transmitted with a length of NE×1.

[0035] Please refer to Figure 3 . Figure 3 This diagram shows a structural schematic of the data E to be transmitted in one embodiment of the present invention. Figure 3 The data E to be transmitted shown is illustrated using the data structure of a narrowband physical broadcast channel as an example. However, the present invention is not limited to this.

[0036] One transmission cycle of the data E to be transmitted is 640 milliseconds, corresponding to 64 frames. Every 8 frames constitute a raw data sub-block, and there are 8 raw data sub-blocks SBO0 to SBO7 in one transmission cycle. The aforementioned data D with a unit code length of 150 bits is interleaved to generate data V, and then rate-matched to 1600 bits. Each raw data sub-block SBO0 to SBO7 corresponds to 200 bits of this 1600 bits, and different frames in the same raw data sub-block have different scrambling codes.

[0037] The received data RD received by the data receiving device 100 will be the data to be transmitted, E. However, the data receiving device 100 cannot know which original data sub-block of the data to be transmitted, E, the initially received data RD belongs to, and must first perform blind decoding.

[0038] Please refer to this again. Figure 1 The following will describe the components included in the data receiving device 100 and their operation. Figure 1 As shown, the data receiving device 100 includes: an antenna 110, a channel estimation circuit 120, an equalization circuit 130, a descrambler circuit 140, a buffer circuit 150, a soft information processing circuit 160, and a post-processing circuit 170.

[0039] Antenna 110 receives received data RD from the wireless channel. Channel estimation circuit 120 and equalization circuit 130 are respectively configured to perform channel estimation and equalization on the received data RD before transmitting it to descrambling circuit 140.

[0040] The descrambling circuit 140 is configured to descramble the received data RD based on the antenna 110 and N data position assumptions within the transmission period to generate N sets of soft-bit data. In one embodiment, the soft-bit data are log-likelihood ratios (LLRs).

[0041] Each N soft bits of data has N data sub-blocks within a transmission period. The N data positions are assumed sequentially to be the first original data sub-block to the Nth original data sub-block within the transmission period of the received data RD.

[0042] Please refer to Figure 4A . Figure 4A This diagram illustrates different received data RDs corresponding to different data location assumptions in one embodiment of the present invention.

[0043] correspond Figure 2 In the example where N is 8, Figure 4A The received data RD is plotted in 8 columns, each corresponding to one of the 8 data location assumptions, and labeled with assumptions 1 through 8. The received data RD has 8 data sub-blocks SBD0 to SBD7.

[0044] The first assumption corresponding to the first column is that the first data sub-block SBD0 of the received data RD is... Figure 2 The first raw data subblock SBO0. The second assumption corresponding to the second column is that the first data subblock SBD0 of the received data RD is... Figure 2 The second raw data sub-block SBO1.

[0045] Similarly, the 8th assumption corresponding to the 8th column is that the first data sub-block SBD0 of the received data RD is... Figure 2 The 8th raw data sub-block SBO7.

[0046] Since the data receiving device 100 will receive the received data RD for the new transmission cycle after the end of one transmission cycle, according to the second assumption, the received data RD shown in the second column, in the 8th data sub-block SBD8, will correspond to the first original data sub-block SBO0 of the next transmission cycle. According to the third assumption, the received data RD shown in the third column, starting from the 7th data sub-block SBD6, will correspond to the first and second original data sub-blocks SBO0 and SBO1 of the next transmission cycle.

[0047] Similarly, according to the 8th assumption, the received data RD shown in column 8, starting from the 2nd data sub-block SBD1, will correspond to the 1st to 7th raw data sub-blocks SBO0 to SBO6 of the next transmission cycle. Here, the assumed raw data sub-blocks of the next transmission cycle are drawn with dashed borders to distinguish them from the solid borders of the raw data sub-blocks of the previous transmission cycle.

[0048] Since each original data sub-block is scrambled in a different way, the descrambling circuit 140 will descramble the received data RD according to the 8 data position assumptions to generate 8 sets of soft bit data SD0 to SD7.

[0049] Please refer to Figure 4B . Figure 4B This diagram illustrates the soft bit data SD0 to SD7 in one embodiment of the present invention.

[0050] The soft bit data SD0 to SD7 are respectively based on Figure 4A The received data RD is generated from one of the eight assumed data locations. For example... Figure 4B As shown, each soft bit data SD0 to SD7 includes eight 200-bit soft bit data sub-blocks DS0 to DS7 after descrambling.

[0051] Taking soft-bit data SD5 as an example, its corresponding data position is assumed to be... Figure 4A The sixth assumption is that the soft bit data sub-block DS0 of soft bit data SD5 is also assumed to be the sixth original data sub-block SBO5. Soft bit data sub-blocks DS3 to DS7 will correspond to the first to fifth original data sub-blocks SBO0 to SB04 of the next transmission cycle, and are shown with dashed borders. The structure of other soft bit data can be understood in the same way, and will not be elaborated further here.

[0052] Please refer to this again. Figure 1 The cache circuit 150 includes N circular buffers, each with a unit code length. Correspondingly... Figure 2 In the embodiment where N is 8, the cache circuit 150 includes 8 circular buffers RB0 to RB7, each with a unit encoding length of 150 bits.

[0053] The soft information processing circuit 160 is configured to extract bit position information BP corresponding to a unit code length to determine multiple constant bit positions and multiple variable bit positions.

[0054] Bit location information BP is generated by Figure 2 The interleaving algorithm used in step S230 generates the interleaving process. Taking invariant bit positions as an example, the bit position information BP may include the position information of 66 invariant bits, namely UnChangedPos_V, UnChangedPos_V+50, and UnChangedPos_V+100.

[0055] In one embodiment, the data receiving device 100 may be provided with a computation circuit (not shown) to calculate the bit position information BP according to the interleaving algorithm, and then the soft information processing circuit 160 retrieves it. In another embodiment, the data receiving device 100 may be provided with a storage circuit (not shown) to store the calculated bit position information BP, and then the soft information processing circuit 160 retrieves it. The present invention is not limited thereto.

[0056] The soft information processing circuit 160 is configured to perform a blind decoding procedure. The blind decoding procedure first assumes that the eight cyclic buffers RB0 to RB7 of the buffer circuit 150 correspond to eight data positions, and then cyclically stores and superimposes eight sets of soft bit data SD0 to SD7 to produce superposition results AR0 to AR7.

[0057] Since the soft bit data SD0 to SD7 are log-likelihood ratios, the superposition results AR0 to AR7 are the combination of information from these log-likelihood ratios. The soft information processing circuit 160 then, at the start of the assumed new transmission cycle, causes the N circular buffers to retain data at the corresponding invariant bit positions and clears the data at the corresponding variable bit positions from the N circular buffers.

[0058] The following will use soft bit data SD5 and circular buffer RB5 as examples to explain the process of circularly storing and superimposing soft bit data in a circular buffer.

[0059] Please refer to Figures 5A to 5D . Figures 5A to 5D The diagrams show the soft bit data SD5 and the circular buffer RB5 in one embodiment of the present invention.

[0060] The soft-bit data SD5 consists of eight 200-bit soft-bit data sub-blocks, DS0 to DS7. The circular buffer RB5 is a buffer with a length of 150 bits.

[0061] like Figure 5A As shown, the circular buffer RB5 with a unit encoding length of 150 bits will first store the first 50 bits of the first soft bit data subblock DS0 from the 101st position, and then cyclically store and superimpose the last 150 bits of the soft bit data subblock DS0 from the beginning.

[0062] like Figure 5B As shown, the circular buffer RB5 continues to store and overlay the first 150 bits of the second soft bit data sub-block DS1 from the beginning, and then stores and overlays the last 50 bits of the soft bit data sub-block DS1 from the beginning.

[0063] like Figure 5C As shown, the circular buffer RB5 continues to store and superimpose the first 100 bits of the third soft bit data sub-block DS2 from the 51st position, and then stores and superimposes the last 100 bits of the soft bit data sub-block DS2 from the beginning.

[0064] like Figure 5D As shown, at this point, the assumed next transmission cycle has begun. At the start of the new transmission cycle, the blind decoding procedure causes the circular buffer RB5 to retain the data at the corresponding invariant bit positions, and clears the data at the corresponding variable bit positions from the N circular buffers.

[0065] Since the soft bit data sub-block DS3 marks the start of a new transmission cycle under the assumption corresponding to the soft bit data SD5, it will be stored starting from the beginning of the circular buffer RB5. The circular buffer RB5 will store and overlay the first 150 bits of the soft bit data sub-block DS3 from the beginning, and then repeat the process of storing and overlaying the last 50 bits of DS3 from the beginning. Subsequent soft bit data sub-blocks DS4 to DS7 can be stored and overlaid by the buffer circuit 150 in the same manner, which will not be elaborated further here.

[0066] It should be noted that since soft bit data SD5 corresponds to the sixth assumption, which assumes that soft bit data sub-block DS3 is the start of the next transmission cycle, the corresponding circular buffer RB5 is cleared. For other soft bit data (corresponding to other assumptions), since soft bit data sub-block DS3 is not the start of the next transmission cycle under other assumptions, the corresponding circular buffer does not need to be cleared when processing soft bit data sub-block DS3. Instead, the corresponding circular buffer is cleared at the start of the new transmission cycle under the aforementioned assumptions.

[0067] Please refer to this again. Figure 1 The post-processing circuit 170 includes a deinterleaving circuit 180, a decoding circuit 190, and a verification circuit 195.

[0068] The deinterleaving circuit 180 is configured to deinterleave the superposition results AR0 to AR7 corresponding to each data sub-block to generate deinterleaving results DI0 to DI7. The decoding circuit 190 is configured to decode the deinterleaving results DI to generate decoding results DO0 to DO7.

[0069] The verification circuit 195 verifies the decoding results DR0 to DR7 to generate verification results CR0 to CR7, which are then transmitted to the soft information processing circuit 160. The soft information processing circuit 160 determines whether the decoding results DR0 to DR7 pass the verification based on the verification results CR0 to CR7.

[0070] When the verification results CR0-CR7 show that all decoding results DR have failed the verification, the soft information processing circuit 160 continues the blind decoding process to superimpose N sets of soft bit data onto the N circular buffers. When the verification results CR0-CR7 show that any one of the decoding results DR0-DR7 has passed the verification, the soft information processing circuit 160 terminates the blind decoding process and outputs the decoding result that has passed the verification. For example, when the decoding result DR5 passes the verification, the soft information processing circuit 160 will determine the corresponding... Figure 4A The sixth assumption is correct, and the blind solution procedure is terminated.

[0071] In different embodiments, the post-processing circuit 170 may perform deinterleaving, decoding, and verification in different ways. This invention is not limited to specific deinterleaving, decoding, and verification techniques.

[0072] It should be noted that the above embodiments are all illustrated using the single antenna assumption 110 as an example. In one embodiment, when the possible number of antenna assumptions is M, the number of buffer circuits 150 included in the data receiving device 110 will be M. The descrambling circuit 140 must descramble the M antenna assumptions and N data position assumptions to generate M×N sets of soft bit data. The soft information processing circuit 160 then causes the N cyclic buffers of the M buffer circuits 150 to cyclically store and superimpose the M×N sets of soft bit data to generate the superposition result AR.

[0073] In some technologies, the soft information processing circuitry clears all information from the buffer circuitry at the start of a new transmission cycle without performing cross-cycle information merging. In such cases, the blind decoding process often requires more iterations to complete the blind decoding.

[0074] The data receiving device of the present invention can retain data at the corresponding unchanged bit position at the beginning of a new transmission cycle by a soft information processing circuit, thereby improving the probability of successful blind decoding by cross-cycle information merging, and thus reducing the time required for blind decoding.

[0075] Please refer to Tables 1 and 2. During simulation, the possible number of antennas M is assumed to be 2, the channel type is ETU, and the Doppler spread is 5Hz. Tables 1 and 2 show the number of iterations required for successful blind decoding in one embodiment of the present invention, with and without cross-cycle information combining. Table 1 shows the minimum number of iterations required to achieve a 5% block error rate (BLER). Table 2 shows the average number of iterations required to achieve a 5% BLER. The actual position of the starting frame of the narrowband physical broadcast channel within a 640-millisecond transmission period and the signal-to-noise ratio both affect performance.

[0076] Table 1

[0077]

[0078] Table 2

[0079]

[0080] For a true location of 40 and a signal-to-noise ratio (SNR) of -12dB, even with the maximum number of iterations, the data block error rate of the technique without cross-period information merging can only be reduced to 5.6%. Table 1 shows that the lower the SNR, the more significant the improvement of the cross-period information merging technique of this invention. This is because at a high SNR, only a few iterations are needed to solve the problem correctly, making it less likely to trigger the cross-period boundary conditions. The true location also affects the improvement, as different true locations result in different probabilities of triggering the cross-period boundary. Furthermore, the proportion of frames from historical periods also varies. In the cases described in Tables 1 and 2, the minimum number of iterations required by this invention is reduced by a maximum of a dozen iterations compared to the technique without cross-period information merging, and by a minimum of 0 iterations.

[0081] Compared to techniques that do not perform cross-cycle information merging, the additional cost of this invention is the memory space used to store information at invariant bit positions. At low signal-to-noise ratios, the minimum number of iterations required to achieve a 5% data block error rate can be reduced by up to a dozen, and the average number of iterations can be reduced by up to 1.76. For the blind decoding process of narrowband physical broadcast channels, if the possible assumptions for the number of antennas are 2 and the data position is 8, then 16 assumptions must be tried per iteration. Reducing one iteration means a significant saving of 16 decoding operations.

[0082] Figure 6 This diagram shows a flowchart of a data receiving method 600 with an accelerated blind deconvolution mechanism according to an embodiment of the present invention.

[0083] In addition to the aforementioned apparatus, the present invention also discloses a flowchart of a data receiving method 600 with an accelerated blind deconvolution mechanism, applicable to, for example, but not limited to, [various applications]. Figure 1 In the data receiving device 100. An embodiment of the data receiving method 600 is, for example... Figure 6 As shown, it includes the following steps.

[0084] In step S610, the descrambling circuit 140 descrambles the received data RD received from the antenna 110 according to the antenna 110 and the N data position assumptions in the transmission period to generate N sets of soft bit data (e.g., soft bit data SD0 to SD7).

[0085] In step S620, the soft information processing circuit 160 extracts bit position information BP corresponding to the unit encoding length to determine multiple fixed bit positions and multiple variable bit positions.

[0086] In step S630, the soft information processing circuit 160 performs a blind decoding procedure.

[0087] In step S640, the blind decoding program first uses the soft information processing circuit 160 to make the N circular buffers with each unit encoding length in the buffer circuit 150 correspond to the N data positions, cyclically store and superimpose N sets of soft bit data to generate N sets of superposition results (e.g., superposition results AR0 to AR7).

[0088] In step S650, the blind decoding program then determines, by the soft information processing circuit 160, the start of the assumed new transmission cycle, to retain the data at the corresponding unchanged bit positions in the N circular buffers and to clear the data at the corresponding changed bit positions in the N circular buffers.

[0089] In step S660, the post-processing circuit 170 deinterleaves and decodes the N sets of superposition results corresponding to each data sub-block to generate N sets of decoding results (e.g., decoding results DO0 to DO7) for verification, thereby generating N verification results (e.g., verification results CR0 to CR7).

[0090] In step S670, determine whether any N sets of decoding results pass the verification.

[0091] When N verification results show that all N sets of decoding results have failed the verification, the soft information processing circuit 160 returns to step S630 to continue the blind decoding process so that N sets of soft bit data are superimposed on the N circular buffers.

[0092] In step S680, when any N sets of decoding results show that the N verification results have passed the verification, the soft information processing circuit 160 terminates the blind decoding program.

[0093] It should be noted that the above-described implementation is merely an example. In other embodiments, those skilled in the art can make modifications without departing from the spirit of the invention.

[0094] In summary, the data receiving apparatus and method of the present invention with an accelerated blind deconvolution mechanism performs blind deconvolution by using information from fixed bit positions in accumulated data, thereby reducing the time required to complete blind deconvolution.

[0095] Although the embodiments of this case are described above, these embodiments are not intended to limit this case. Those skilled in the art can make changes to the technical features of this case based on the express or implied content of this case. All such changes may fall within the scope of patent protection sought in this case. In other words, the scope of patent protection in this case shall be determined by the scope of the patent application in this specification.

Claims

1. A data receiving apparatus of a convolution mechanism, characterized by, The data receiving device comprises: a descrambling circuit configured to descramble received data received from an antenna according to the antenna and N data position hypotheses in a transmission period to generate N sets of soft bit data, wherein the received data is generated by a convolutional encoding procedure and has N data subblocks in the transmission period, and the N data position hypotheses sequentially assume a first data subblock of the received data to be a first original data subblock to an Nth original data subblock; a buffer circuit comprising N circular buffers each having a unit encoding length; a soft information processing circuit configured to extract bit position information corresponding to the unit encoding length to determine a plurality of fixed bit positions and a plurality of variable bit positions, and to perform a blind decoding procedure, comprising: causing the N circular buffers of the buffer circuit to cyclically store and superimpose N sets of the soft bit data corresponding to the N data position hypotheses to generate N sets of superimposed results; and causing the N circular buffers to retain data corresponding to the plurality of fixed bit positions and to clear data corresponding to the plurality of variable bit positions at the beginning of a new transmission period assumed; a post-processing circuit configured to deinterleave and decode the N sets of superimposed results corresponding to each data subblock to generate N sets of decoded results and to perform checking to generate N check results; wherein when the N check results show that none of the decoded results passes the checking, the soft information processing circuit continues to perform the blind decoding procedure to cause the N circular buffers to superimpose N sets of the soft bit data, wherein when the N check results show that any one of the N sets of decoded results passes the checking, the soft information processing circuit outputs the decoded result that passes the checking.

2. The data receiving apparatus of claim 1, wherein The N sets of soft bit data are log-likelihood ratios respectively.

3. The data receiving apparatus of claim 1, wherein When the number of antennas is M, the number of buffer circuits included in the data receiving device is M, the descrambling circuit descrambles M antennas and the N data position hypotheses to generate M×N sets of soft bit data, and the soft information processing circuit causes the N circular buffers of the M buffer circuits to cyclically store and superimpose M×N sets of the soft bit data to generate M×N sets of superimposed results.

4. The data receiving apparatus of claim 1, wherein The convolutional encoding procedure comprises a check code adding procedure, a channel encoding procedure, an interleaving procedure, a rate matching procedure and a scrambling procedure performed by a data transmitting device that transmits the received data, and the bit position information is generated according to an interleaving algorithm of the interleaving procedure.

5. The data receiving apparatus of claim 1, wherein The post-processing circuit comprises: a deinterleaving circuit configured to deinterleave the sets of superimposed results corresponding to each data subblock to generate N sets of deinterleaved results; a decoding circuit configured to decode the N sets of deinterleaved results to generate N sets of decoded results; and a checking circuit configured to check the N sets of decoded results to generate N check results transmitted to the soft information processing circuit.

6. The data receiving apparatus of claim 1, wherein The data receiving device comprises a channel estimation circuit and an equalization circuit configured to perform channel estimation and equalization on the received data and then transmit the received data to the descrambling circuit.

7. The data receiving apparatus of claim 1, wherein The length of the transmission period is 640 milliseconds, including 8 data sub-blocks each having 200 bits, and the unit code length is 150 bits.

8. A data receiving method of a blind deconvolution mechanism, characterized by, The data receiving device comprises: The received data received from the antennas is descrambled by the descrambling circuit according to the antennas and N data position hypotheses in a transmission period to generate N sets of soft bit data, wherein the received data is generated via a convolutional encoding procedure, each of the N sets of soft bit data has N data sub-blocks in the transmission period, and the N data position hypotheses sequentially assume that a first data sub-block of the received data is a first original data sub-block to an Nth original data sub-block; The soft information processing circuit extracts bit position information corresponding to the unit code length to determine a plurality of fixed bit positions and a plurality of variable bit positions; The soft information processing circuit performs a blind decoding procedure, comprising: The soft information processing circuit causes N circular buffers each having the unit code length in the buffer circuit to correspond to the N data position hypotheses, circularly store and superimpose N sets of the soft bit data to generate N sets of superimposed results; and The N circular buffers retain data corresponding to the plurality of fixed bit positions at the start of a new transmission period assumed, and clear data corresponding to the plurality of variable bit positions in the N circular buffers; The post-processing circuit de-interleaves and decodes the N sets of superimposed results corresponding to each of the data sub-blocks to generate N sets of decoding results for checking to generate N check results; When the N check results show that the N sets of decoding results all fail to pass the check, the soft information processing circuit continues to perform the blind decoding procedure to cause the N circular buffers to superimpose N sets of the soft bit data; and When the N check results show that any of the N sets of decoding results passes the check, the decoding result that passes the check is output.

9. The data receiving method of claim 8, wherein, When the number of antennas is M, the number of buffer circuits included in the data receiving device is M, the descrambling circuit descrambles M antennas and the N data position hypotheses to generate M×N sets of soft bit data, and the soft information processing circuit causes N circular buffers of M buffer circuits to circularly store and superimpose M×N sets of the soft bit data to generate M×N sets of superimposed results.

10. The data receiving method of claim 8, wherein, The length of the transmission period is 640 milliseconds, including 8 data sub-blocks each having 200 bits, and the unit code length is 150 bits. The data receiving device comprises: The received data received from the antennas is descrambled by the descrambling circuit according to the antennas and N data position hypotheses in a transmission period to generate N sets of soft bit data, wherein the received data is generated via a convolutional encoding procedure, each of the N sets of soft bit data has N data sub-blocks in the transmission period, and the N data position hypotheses sequentially assume that a first data sub-block of the received data is a first original data sub-block to an Nth original data sub-block; The soft information processing circuit extracts bit position information corresponding to the unit code length to determine a plurality of fixed bit positions and a plurality of variable bit positions; The soft information processing circuit performs a blind decoding procedure, comprising: The soft information processing circuit causes N circular buffers each having the unit code length in the buffer circuit to correspond to the N data position hypotheses, circularly store and superimpose N sets of the soft bit data to generate N sets of superimposed results; and The N circular buffers retain data corresponding to the plurality of fixed bit positions at the start of a new transmission period assumed, and clear data corresponding to the plurality of variable bit positions in the N circular buffers; The post-processing circuit de-interleaves and decodes the N sets of superimposed results corresponding to each of the data sub-blocks to generate N sets of decoding results for checking to generate N check results; When the N check results show that the N sets of decoding results all fail to pass the check, the soft information processing circuit continues to perform the blind decoding procedure to cause the N circular buffers to superimpose N sets of the soft bit data; and When the N check results show that any of the N sets of decoding results passes the check, the decoding result that passes the check is output. When the number of antennas is M, the number of buffer circuits included in the data receiving device is M, the descrambling circuit descrambles M antennas and the N data position hypotheses to generate M×N sets of soft bit data, and the soft information processing circuit causes N circular buffers of M buffer circuits to circularly store and superimpose M×N sets of the soft bit data to generate M×N sets of superimposed results.

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