An excitatory-inhibitory neuromorphic transistor, a manufacturing method and a working method

Abstract

The present invention relates to the field of semiconductor devices, and in particular to an excitation-inhibition neuromorphic transistor, a manufacturing method and a working method. The present invention uses a metal-gate dielectric-inert electrode to form a volatile memristor, and couples the volatile memristor and the field effect transistor together through the inert electrode, so as to complete the construction of the excitation-inhibition neuromorphic transistor device at a low cost, and generally forms an excitation-inhibition neuromorphic transistor with a compact structure that can be used to simultaneously accept excitation and inhibition input regulation functions. The present invention also includes an excitation-inhibition neuromorphic transistor with multiple drains, which can realize the regulation of accepting multi-terminal excitatory stimulation inputs at the same time. The channel layer and the inert electrode involved in the present invention are respectively made of two-dimensional materials to achieve the ultimate miniaturization of the device size, so that the excitation-inhibition neuromorphic transistor has a compact structure and strong miniaturization, while reducing the power consumption of the device.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and in particular to an excitation-inhibition neuromorphic transistor, a manufacturing method and a working method. Background Art

[0002] The neuromorphic computing architecture has the characteristics of high parallelism and low power consumption, and is expected to break through the computing efficiency and energy consumption bottlenecks of the traditional von Neumann architecture. Neuron devices are the basic components of the neuromorphic computing architecture. They transmit information through discrete pulses similar to those in biological neurons. In addition to receiving excitatory inputs, another important feature of neurons is that they can be regulated by inhibitory inputs. This mechanism allows specific neurons in the nervous system to be activated, thereby generating relatively sparse neural activity, which is also a key factor in the low power consumption of the mammalian brain. How to efficiently simulate the behavior of biological brain neurons is the key issue of the current neuromorphic computing architecture.

[0003] There is currently related work on using analog circuits based on traditional silicon to realize the functions of neurons, but such designs usually require dozens of transistors and components such as capacitors to simulate the functions of a single biological neuron, which consumes high power and is difficult to miniaturize.

[0004] Some new memristors or transistors can also simulate the leakage-integration-release characteristics of biological neurons, but they generally lack the inhibitory function or the ability to simultaneously accept excitatory and inhibitory input regulation, and cannot fully realize the functions of biological neurons. Summary of the invention

[0005] In order to achieve the purpose of simultaneously accepting excitation and inhibition input regulation functions, the present invention provides an excitation-inhibition neuromorphic transistor, comprising:

[0006] Substrate, channel layer, inert electrode, gate dielectric layer, source, drain, gate;

[0007] The substrate surface has a channel layer, the substrate surfaces on both sides of the channel layer have an inert electrode and a source electrode respectively, a portion of the inert electrode and a portion of the source electrode are superimposed on the surface of the channel layer, the exposed surface of the channel layer and the inert electrode surface have a gate dielectric layer, the surface of the gate dielectric layer has a gate and a drain electrode, the drain electrode is located directly above the inert electrode, the gate is located directly above the channel layer, and the gate is located between the source electrode and the drain electrode;

[0008] The source, the gate and the inert electrode constitute a field effect transistor, the drain, the inert electrode and the gate dielectric layer therebetween constitute a volatile memristor, and the volatile memristor and the field effect transistor are coupled together through the inert electrode.

[0009] Optionally, the channel layer material is a layered two-dimensional material with semiconductor properties, and the inert electrode is an inert metal or a layered two-dimensional material with inert metal properties.

[0010] Optionally, the gate dielectric layer under the drain has the same thickness as the gate dielectric layer under the gate.

[0011] Optionally, the gate serves as an inhibitory input port of the excitation-inhibition neuromorphic transistor, and the drain serves as an excitatory input port of the excitation-inhibition neuromorphic transistor.

[0012] Optionally, it further includes: a plurality of discrete drain electrodes, wherein the plurality of discrete drain electrodes are all located directly above the inert electrode.

[0013] Optionally, each discrete drain electrode and inert electrode and the gate dielectric layer therebetween constitute a volatile memristor, and the multiple volatile memristors are connected in parallel and then connected to the field effect transistor.

[0014] A method for manufacturing an excitatory-inhibitory neuromorphic transistor, comprising:

[0015] providing a substrate;

[0016] forming a channel layer on the surface of the substrate;

[0017] forming an inert electrode on the surface of the substrate and one side of the channel layer, wherein a portion of the inert electrode is superimposed on the surface of the channel layer;

[0018] forming a source electrode on the surface of the substrate and the other side of the channel layer, wherein a portion of the source electrode is superimposed on the surface of the channel layer;

[0019] The exposed surface of the channel layer and the surface of the inert electrode form a gate dielectric layer;

[0020] A gate and a drain are formed on the surface of the gate dielectric layer. The drain is located directly above the inert electrode. The gate is located directly above the channel layer and between the source and the drain.

[0021] Optionally, it further includes: a plurality of discrete drain electrodes, wherein the plurality of discrete drain electrodes are formed on the surface of the gate dielectric layer, and the plurality of discrete drain electrodes are all located directly above the inert electrode.

[0022] A method for operating an excitatory-inhibitory neuromorphic transistor, comprising:

[0023] Providing the excitatory-inhibitory neuromorphic transistor as claimed in claim 1;

[0024] An excitatory voltage pulse is input to the drain of the excitation-inhibition neuromorphic transistor, and the source outputs a first current pulse; or an excitatory voltage pulse is input to the drain of the excitation-inhibition neuromorphic transistor and an inhibitory voltage pulse is input to the gate at the same time, and the source outputs a second current pulse.

[0025] Optionally, under the stimulation of a voltage pulse of a certain frequency input to the drain, if the gate input inhibitory voltage pulse is 0V, the source output current pulse emission rate is X; if the gate input inhibitory voltage is less than 0V, the source output current pulse emission rate is less than X.

[0026] In summary, the advantages and beneficial effects of the present invention are:

[0027] Since a single volatile memristor has the characteristic of being able to simulate the basic leakage-integration-discharge of biological neurons when working, the present invention uses metal-gate dielectric-inert electrode to form a volatile memristor, and utilizes the volatile memristor to simulate the basic leakage-integration-discharge of biological neurons. The volatile memristor and the field effect transistor are coupled together through the inert electrode, and the construction of an excitation-inhibition neuromorphic transistor device can be completed at a low cost, and an excitation-inhibition neuromorphic transistor with a compact structure that can be used to simultaneously accept excitation and inhibition input regulation functions is formed as a whole.

[0028] The present invention also includes an excitatory-inhibitory neuromorphic transistor with multiple discrete drains, which can realize the regulation of receiving multi-terminal excitatory stimulation inputs at the same time.

[0029] The channel layer and the inert electrode involved in the present invention respectively use two-dimensional materials such as molybdenum disulfide and graphene, which can perform extreme miniaturization of the device size, so that the excitation-inhibition neuromorphic transistor has a compact structure and strong miniaturization, while reducing the power consumption of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] Figure 1 It is a schematic cross-sectional structure diagram of an excitatory-inhibitory neuromorphic transistor structure according to the first embodiment of the present invention;

[0031] Figure 2A FIG. 1 is an equivalent circuit diagram of a volatile memristor of an excitation-inhibition neuromorphic transistor according to the first embodiment of the present invention when in operation;

[0032] Figure 2B The figure shows a voltage-time image of a volatile memristor of an excitation-inhibition neuromorphic transistor according to the first embodiment of the present invention when it is working;

[0033] Figure 2CIt is a schematic structural diagram of the longitudinal growth principle of metal conductive filaments of a volatile memristor of an excitation-inhibition neuromorphic transistor according to the first embodiment of the present invention;

[0034] Figure 2D It is a schematic structural diagram of the lateral growth principle of metal conductive filaments of a volatile memristor of an excitation-inhibition neuromorphic transistor according to the first embodiment of the present invention;

[0035] Figure 2E It is a structural schematic diagram of the lateral dissolution principle of a volatile memristor metal conductive filament of an excitation-inhibition neuromorphic transistor according to the first embodiment of the present invention;

[0036] Figure 2F It is a structural schematic diagram of the longitudinal dissolution principle of a volatile memristor metal conductive filament of an excitation-inhibition neuromorphic transistor according to the first embodiment of the present invention;

[0037] Figure 3 It is a flow chart showing a process of manufacturing an excitatory-inhibitory neuromorphic transistor according to the first embodiment of the present invention;

[0038] Figure 4A to Figure 4I FIG. 1 is a cross-sectional structural schematic diagram of a manufacturing process of an excitatory-inhibitory neuromorphic transistor according to a first embodiment of the present invention;

[0039] Figure 5 FIG. 1 is a schematic cross-sectional view of a plurality of discrete drain structures of an excitation-inhibition neuromorphic transistor according to a first embodiment of the present invention;

[0040] Fig. 6A It is a structural schematic diagram of a test circuit connection of an excitation-inhibition neuromorphic transistor working method according to a second embodiment of the present invention;

[0041] Figure 6B It is a schematic diagram showing a gate inhibition input frequency of an excitation-inhibition neuromorphic transistor operation method according to a second embodiment of the present invention;

[0042] Figure 6C FIG. 1 is a schematic diagram of a source output current pulse of an excitation-inhibition neuromorphic transistor operation method according to a second embodiment of the present invention. DETAILED DESCRIPTION

[0043] In order to facilitate understanding by those skilled in the art, the present invention will be further described in detail below with reference to specific embodiments.

[0044] The first embodiment of the present invention provides an excitatory-inhibitory neuromorphic transistor, please refer to Figure 1 ,include:

[0045] Substrate 100, channel layer 30, inert electrode 40, gate dielectric layer 50, source 63, drain 62, gate 61;

[0046] The surface of the substrate 100 has a channel layer 30, and the surfaces of the substrate 100 on both sides of the channel layer 30 have an inert electrode 40 and a source 63 respectively, a portion of the inert electrode 40 and a portion of the source 63 are superimposed on the surface of the channel layer 30, and the exposed surface of the channel layer 30 and the surface of the inert electrode 40 have a gate dielectric layer 50, and the surface of the gate dielectric layer 50 has a gate 61 and a drain 62, the drain 62 is located directly above the inert electrode 40, the gate 61 is located directly above the channel layer 30, and the gate 61 is located between the source 63 and the drain 62;

[0047] The source 63 , the gate 61 and the inert electrode 40 constitute a field effect transistor 200 , the drain 62 , the inert electrode 40 and the gate dielectric layer 50 therebetween constitute a volatile memristor 300 , and the volatile memristor 300 is coupled with the field effect transistor 200 through the inert electrode 40 .

[0048] In the first embodiment of the present invention, the substrate 100 includes a silicon substrate 10 and a silicon dioxide layer 20 located on the surface of the silicon substrate 100 .

[0049] In the first embodiment of the present invention, the silicon substrate 10 is a heavily doped P-type silicon substrate.

[0050] In the first embodiment of the present invention, the silicon dioxide layer 20 on the surface of the silicon substrate 10 is formed of a 285 nm silicon dioxide sheet.

[0051] In the first embodiment of the present invention, the channel layer 30 and the inert electrode 40 are made of two-dimensional semiconductor materials.

[0052] In the first embodiment of the present invention, the material of the channel layer 30 is a layered two-dimensional material with semiconductor properties.

[0053] In the first embodiment of the present invention, the material of the channel layer 30 is molybdenum disulfide or tungsten diselenide.

[0054] In the first embodiment of the present invention, the inert electrode is an inert metal or a layered two-dimensional material having inert metal properties.

[0055] In the first embodiment of the present invention, the inert electrode is two-dimensional graphene.

[0056] In other embodiments, the channel layer material is other suitable two-dimensional semiconductor materials.

[0057] The two-dimensional semiconductor material can be used to perform extreme miniaturization of device size, so that the excitation-inhibition neuromorphic transistor has a compact structure and strong miniaturization, while reducing the power consumption of the device.

[0058] In the first embodiment of the present invention, the gate dielectric layer under the drain electrode and the gate dielectric layer under the gate electrode have the same thickness and are formed at the same time.

[0059] In other embodiments, the gate dielectric layer under the drain and the gate dielectric layer under the gate have different thicknesses and can be formed separately.

[0060] In the first embodiment of the present invention, the gate dielectric layer 50 is a high-K dielectric layer, and the channel layer 30 and the volatile memristor 300 share the gate dielectric layer 50 , which simplifies the device preparation process and reduces the device manufacturing cost.

[0061] The high-K dielectric layer can reduce the thickness of the excitation-inhibition neuromorphic transistor to continuously improve the performance of the excitation-inhibition neuromorphic transistor.

[0062] In the first embodiment of the present invention, the gate dielectric layer 50 is specifically aluminum oxide, and the gate dielectric layer 50 enables the volatile memristor 300 to stably switch electrochemical properties.

[0063] In the first embodiment of the present invention, the source electrode 63 and the gate electrode 61 are made of metal chromium or metal gold.

[0064] In the first embodiment of the present invention, the material of the drain electrode 62 is an active metal material, which is beneficial to the growth of the metal conductive filament.

[0065] In the first embodiment of the present invention, the drain electrode 62 is made of metal silver or metal copper.

[0066] In the first embodiment of the present invention, the gate 61 serves as an inhibitory input port of the excitation-inhibition neuromorphic transistor, and the drain 62 serves as an excitatory input port of the excitation-inhibition neuromorphic transistor.

[0067] The excitatory-inhibitory neuromorphic transistor can be used to simultaneously receive excitatory and inhibitory input regulation functions.

[0068] In the first embodiment of the present invention, the source 63 , the gate 61 and the inert electrode 40 constitute a field effect transistor 200 , the drain 62 , the inert electrode 40 and the gate dielectric layer 50 therebetween constitute a volatile memristor 300 , and the volatile memristor 300 is coupled with the field effect transistor 200 through the inert electrode 40 .

[0069] The formation of the excitatory-inhibitory neuromorphic transistor allows the device structure to be more compact and reduces the manufacturing cost.

[0070] In the first embodiment of the present invention, the drain electrode 62 serves as the top electrode TE of the volatile memristor 300 , and the inert electrode 40 serves as the bottom electrode BE of the volatile memristor 300 .

[0071] In the first embodiment of the present invention, the device further comprises: a plurality of discrete drain electrodes 62 , each of which is located directly above the inert electrode 40 .

[0072] In the first embodiment of the present invention, each discrete drain electrode 62 and the inert electrode 40 and the gate dielectric layer 50 therebetween form a volatile memristor 300 , and a plurality of volatile memristors 300 are connected in parallel and then connected to the field effect transistor 200 .

[0073] In the first embodiment of the present invention, the plurality of drains 62 are specifically four drains 62 .

[0074] In the first embodiment of the present invention, the excitation-inhibition neuromorphic transistor having one field effect transistor 200 and multiple volatile memristors 300 is a multi-port excitation-inhibition neuromorphic transistor, wherein the gate 61 of the multi-port excitation-inhibition neuromorphic transistor is a common inhibitory input port, and the multiple discrete drains 62 are multiple discrete excitatory input ports of the multi-port excitation-inhibition neuromorphic transistor.

[0075] Biological neurons can receive excitatory stimulation inputs from multiple terminals. By extending the inert electrode 40 and the drain 62 to form a multi-port excitatory-inhibitory neuromorphic transistor, the function of biological neurons receiving excitatory stimulation inputs from multiple terminals is realized.

[0076] In the first embodiment of the present invention, the bottom electrode BE of the volatile memristor 300 is an inert electrode 40 , which is beneficial to accelerate the dissolution and rupture of the metal conductive filaments of the volatile memristor 300 .

[0077] In the first embodiment of the present invention, please refer to Figure 2A The circuit diagram of a single volatile memristor 300 when in operation and Figure 2B The moment t0-t1 in the voltage-time image when the single volatile memristor 300 is working is:

[0078] Please refer to Figure 2CWhen a voltage pulse is directly applied across the top electrode TE and the bottom electrode BE of the volatile memristor 300 , the metal atoms in the top electrode TE of the volatile memristor 300 will move under the drive of the voltage, which corresponds to the integration process of biological neurons.

[0079] Please refer to Figure 2D The metal atoms in the top electrode TE of the volatile memristor 300 move to form a metal conductive filament between the top electrode TE and the bottom electrode BE of the volatile memristor 300. The metal conductive filament grows longitudinally. Once the top electrode TE and the bottom electrode BE of the volatile memristor 300 are connected, the top electrode TE and the bottom electrode BE of the volatile memristor 300 are directly connected by the metal conductive filament. At this time, the resistance of the volatile memristor 300 is instantly reduced from the off-state resistance Roff to the on-state resistance Ron, so that the output current of the volatile memristor 300 suddenly increases, corresponding to the discharge function of biological neurons.

[0080] In the first embodiment of the present invention, please refer to Figure 2A The circuit diagram of a single volatile memristor 300 when in operation and Figure 2B The time t1-t2 in the voltage-time image when the single volatile memristor 300 is working, that is:

[0081] Please refer to Figure 2E After the voltage across the volatile memristor 300 is removed, the metal conductive filament formed between the top electrode TE and the bottom electrode BE will spontaneously dissolve and rupture under the action of minimized interface energy and irregular thermal motion, corresponding to the leakage of biological neurons.

[0082] Please refer to Figure 2F If the metal conductive filament no longer connects the top electrode TE and the bottom electrode BE, the resistance of the volatile memristor 300 instantly increases from the on-state resistance Ron to the off-state resistance Roff, so that the output current of the volatile memristor 300 suddenly decreases, corresponding to the reset of the biological neuron.

[0083] The present invention also provides a method for manufacturing an excitatory-inhibitory neuromorphic transistor, please refer to Figure 3 , is a flow chart of a method for manufacturing an excitatory-inhibitory neuromorphic transistor according to the first embodiment of the present invention, and the specific steps include:

[0084] Step S10, providing a substrate;

[0085] Step S20, forming a channel layer on the surface of the substrate;

[0086] Step S30, forming an inert electrode on the surface of the substrate and one side of the channel layer, wherein a portion of the inert electrode is superimposed on the surface of the channel layer;

[0087] Step S40, forming a source electrode on the surface of the substrate and the other side of the channel layer, wherein a portion of the source electrode is superimposed on the surface of the channel layer;

[0088] Step S50, forming a gate dielectric layer on the exposed surface of the channel layer and the surface of the inert electrode;

[0089] Step S60: forming a gate and a drain on the surface of the gate dielectric layer, wherein the drain is located directly above the inert electrode, and the gate is located directly above the channel layer and between the source and the drain.

[0090] Specifically, step S10 is performed to provide a substrate 100 , and the specific steps include: providing a silicon substrate 10 , and growing a silicon dioxide layer 20 on the surface of the silicon substrate 10 .

[0091] In the first embodiment of the present invention, the silicon substrate 10 is a heavily doped P-type silicon substrate, and the silicon dioxide layer 20 is a 285 nm silicon dioxide wafer.

[0092] Step S20 is performed, referring to 4A-4B, to form a channel layer 30 on the surface of the substrate 100 .

[0093] A channel layer 30 is formed on the surface of the substrate 100 , and an inert electrode 40 and a source electrode 63 are formed on the surface of the substrate 100 and on both sides of the channel layer 30 , respectively. Parts of the inert electrode 40 and the source electrode 63 are superimposed on the surface of the channel layer 30 .

[0094] In the first embodiment of the present invention, the channel layer 30 is formed by transferring the material of the channel layer 30 to the surface of the substrate 100 using PDMS (polydimethylsiloxane).

[0095] Execute step S30, please refer to Figures 4C to 4D , forming an inert electrode 40 on the surface of the substrate 100 and one side of the channel layer 30, wherein a portion of the inert electrode 40 is superimposed on the surface of the channel layer 30;

[0096] In the first embodiment of the present invention, the inert electrode 40 is transferred to a target position by using PDMS and a micro-transfer platform, and the inert electrode 40 is in van der Waals contact with the channel layer 30 .

[0097] Execute step S40, please refer to Figure 4E , forming a source electrode 63 on the surface of the substrate 100 and the other side of the channel layer 30, wherein a portion of the source electrode 63 is superimposed on the surface of the channel layer 30;

[0098] In the first embodiment of the present invention, the formation of the source 63 includes the following specific steps: spin coating photoresist on the exposed surfaces of the inert electrode 40, the channel layer 30 and the substrate 100, performing post-baking and then using laser direct writing, and then performing thermal evaporation of metal to form the source 63, and finally forming the source 63 after stripping off the photoresist.

[0099] The inert electrode 40 , the channel layer 30 and the photoresist on the surface of the substrate 100 are dried through a post-baking process to prepare for subsequent processes.

[0100] By using the laser direct writing technology, a laser beam is applied to expose the photoresist at the position of the source electrode 63 on the surface of the channel layer 30 and the substrate 100 after post-baking, and the contour of the source electrode 63 is formed after development.

[0101] The thermal evaporation metal technology allows the metal material of the source electrode 63 to adhere to the surface of the substrate 100 and the channel layer 30 in a vacuum environment, and gradually accumulate to finally form the source electrode 63 .

[0102] In other embodiments, the photoresist is post-baked and then exposed using an electron beam, and then metal is thermally evaporated to form the source 63 .

[0103] Execute step S50, please refer to Figures 4F to 4G The exposed surface of the channel layer 30 and the surface of the inert electrode 40 form a gate dielectric layer 50 .

[0104] In the first embodiment of the present invention, the gate dielectric layer 50 is prepared using an atomic deposition process (ALD), and the specific steps include: first pre-depositing a metal layer using a thermal evaporation process, and then growing a metal oxide corresponding to the metal layer on the surface of the metal layer using an atomic layer deposition process.

[0105] Since the channel layer 30 is a two-dimensional semiconductor material, there are no dangling bonds on the surface of the two-dimensional semiconductor material. By pre-depositing a metal layer on the exposed surface of the channel layer 30 and the surface of the inert electrode 40 as a contact for the growth of the gate dielectric layer 50, it is helpful to grow a high-quality oxide layer as the gate dielectric layer 50 on the two-dimensional semiconductor material without dangling bonds.

[0106] In the first embodiment of the present invention, the gate dielectric layer 50 is a high-K dielectric.

[0107] In the first embodiment of the present invention, the thickness of the pre-deposited metal layer is in the range of 1-2 nm.

[0108] In the first embodiment of the present invention, the thickness of the metal oxide is 10 nm.

[0109] In the first embodiment of the present invention, the material of the metal layer is metal aluminum, and the material of the gate dielectric layer 50 is aluminum oxide.

[0110] In other embodiments, the formation order of the gate dielectric layer 50 and the source electrode 63 is adjustable.

[0111] Execute step S60, please refer to Figures 4H to 4I A gate 61 and a drain 62 are formed on the surface of the gate dielectric layer 50 . The drain 62 is located directly above the inert electrode 40 . The gate 61 is located directly above the channel layer 30 and between the source 63 and the drain 62 .

[0112] The specific steps of forming the gate 61 and the drain 62 include: first forming the drain 62 by laser direct writing and thermal evaporation metal process, and then forming the gate 61 by laser direct writing and thermal evaporation metal process. The formation process of the gate 61 and the drain 62 is adjustable.

[0113] In other embodiments, the drain electrode 62 and the gate electrode 61 may be formed by electron beam exposure and thermal evaporation metal processes, respectively.

[0114] In other embodiments, the source is formed after the drain and the gate are formed, or the source, the drain and the gate can be formed at the same time.

[0115] In the first embodiment of the present invention, please refer to Figure 5 , further comprising: a plurality of discrete drain electrodes 62 , wherein the plurality of discrete drain electrodes 62 are formed on the surface of the gate dielectric layer 50 , and the plurality of discrete drain electrodes 62 are all located directly above the inert electrode 40 .

[0116] In the first embodiment of the present invention, the plurality of separate drain electrodes 62 are four drain electrodes 62 , and are formed simultaneously.

[0117] In the first embodiment of the present invention, the excitation-inhibition neuromorphic transistor having a plurality of discrete drains 62 is a multi-port excitation-inhibition neuromorphic transistor, which uses a relatively large area of ​​two-dimensional graphene as an inert electrode 40 and forms any plurality of discrete drains 62 by laser direct writing or electron beam exposure and thermal evaporation of metal.

[0118] In the first embodiment of the present invention, the source 63, the gate 61 and the inert electrode 40 constitute a field effect transistor 200, the drain 62, the inert electrode 40 and the gate dielectric layer 50 therebetween constitute a volatile memristor 300, the volatile memristor 300 and the field effect transistor 200 are coupled together through the inert electrode 40, the gate voltage is used to control the resistance of the channel layer, and the inert electrode 40 competes for the source-drain voltage of the neuromorphic transistor after the channel is connected in series, thereby realizing the function of biological neurons being regulated by both excitatory input and inhibitory input at the same time.

[0119] The volatile memristor 300 is composed of metal-gate dielectric-inert electrode. The volatile memristor 300 has the basic leakage-integration-release characteristics of simulating biological neurons. The volatile memristor 300 and the field effect transistor 200 are coupled together through the inert electrode 40 to complete the construction of the excitation-inhibition neuromorphic transistor, forming an excitation-inhibition neuromorphic transistor with a compact overall structure. At the same time, the channel layer 30 and the inert electrode 40 are respectively made of two-dimensional materials such as molybdenum disulfide and graphene, so as to achieve extreme miniaturization of the device size, so that the overall structure of the neuromorphic transistor is compact and has strong miniaturization.

[0120] In a second embodiment of the present invention, a method for operating an excitation-inhibition neuromorphic transistor is provided, further comprising:

[0121] providing the excitatory-inhibitory neuromorphic transistor described above;

[0122] An excitatory voltage pulse is input to the drain of the excitation-inhibition neuromorphic transistor, and the source outputs a first current pulse; or an excitatory voltage pulse is input to the drain of the excitation-inhibition neuromorphic transistor and an inhibitory voltage pulse is input to the gate at the same time, and the source outputs a second current pulse.

[0123] In the second embodiment of the present invention, please refer to Fig. 6A , an excitatory voltage pulse is input to the drain 62 of the excitatory-inhibitory neuromorphic transistor, specifically an excitatory voltage pulse excitation with an amplitude of 3V, a period of 10ms, and a pulse width of 5ms, and the source 63 outputs a first current pulse, and the source output current pulse emission rate is X.

[0124] When an excitatory voltage pulse is input to the drain port 62 of the excitation-inhibition neuromorphic transistor, the gate 61 voltage Vg=0V, and the volatile memristor 300 in the excitation-inhibition neuromorphic transistor is in an off state, the off-state resistance Roff of the volatile memristor 300 is much larger than the channel resistance Rzero, and the volatile memristor 300 can almost share all the source-drain voltages at both ends of the excitation-inhibition neuromorphic transistor. Therefore, the excitation-inhibition neuromorphic transistor responds to the excitatory input voltage pulse at the drain port 62, so that the metal conductive filaments of the top electrode TE in the volatile memristor 300 grow, realizing the integration process of biological neurons; when the metal conductive filaments convert the volatile When the top electrode TE and the bottom electrode BE of the memristor 300 are connected, the volatile memristor 300 is in the on state, and the circuit current suddenly increases, realizing the discharge function of the biological neuron; since the on-state resistance Ron of the volatile memristor 300 is much smaller than the channel resistance Rzero of the field effect transistor 200, the voltage division of the volatile memristor 300 will suddenly decrease, and the metal conductive filaments of the volatile memristor 300 will immediately undergo lateral and longitudinal dissolution processes, so that the volatile memristor 300 returns to the off state, realizing the leakage process of the biological neuron, and realizing the excitability regulation function of the drain 62 of the excitatory-inhibitory neuromorphic transistor by the excitatory input of the excitatory-inhibitory neuromorphic transistor.

[0125] In the second embodiment of the present invention, please refer to Figure 6B , while inputting an excitatory voltage pulse to the drain 62 port of the excitation-inhibition neuromorphic transistor, an inhibitory voltage pulse is input to the gate 61 of the excitation-inhibition neuromorphic transistor, and during the process in which the gate 61 voltage Vg gradually decreases from 0V to -7V, the source 63 outputs a second current pulse, and the source output current pulse emission rate is less than X.

[0126] The channel layer resistance Rneg of the field effect transistor 200 is equal to or even much larger than the off-state resistance Roff of the volatile memristor 300, so that the voltage division obtained by the off-state resistance Roff of the volatile memristor 300 is reduced or even almost zero, thereby slowing down the growth rate of the metal conductive filaments of the volatile memristor 300 or even making the diffusion rate faster than the growth rate, thereby realizing the reset function of the biological neurons and realizing the inhibitory regulation function of the gate inhibitory input of the excitation-inhibition neuromorphic transistor on the excitation-inhibition neuromorphic transistor.

[0127] Please refer to Figure 6CThe current pulse emission rate of the output of the excitation-inhibition neuromorphic transistor gradually decreases until no pulses are emitted, and the amplitude of the pulses also continues to decrease, which clearly reflects the working process of the excitation-inhibition neuromorphic transistor and realizes that the excitation-inhibition neuromorphic transistor has complete excitation-inhibition artificial neuron functions.

[0128] In the second embodiment of the present invention, the current pulse emission rate is calculated as follows: the number of current pulses output by the source within a certain period of time / the number of voltage pulses input by the drain.

[0129] In the second embodiment of the present invention, the method for detecting the current pulse is: when the voltage input to the drain is at a high level during a pulse cycle, the source output current is higher than 1 μA, that is, it is detected as a current pulse.

[0130] The volatile memristor 300 is coupled with the field effect transistor 200, and the resistance of the channel layer is controlled by the gate voltage to achieve voltage division competition between the gate and the volatile memristor 300, thereby realizing the function of biological neurons being regulated by both excitatory input and inhibitory input at the same time.

[0131] In other embodiments, when the excitatory-inhibitory neuromorphic transistor is a multi-port excitatory-inhibitory neuromorphic transistor, an excitatory voltage pulse is input to one or more drains of the excitatory-inhibitory neuromorphic transistor having the plurality of discrete drains, thereby realizing the function of the biological neuron receiving multi-terminal excitatory stimulation inputs.

[0132] An excitatory voltage pulse is input to one or more drains of the excitatory-inhibitory neuromorphic transistor having the plurality of discrete drains, and an inhibitory voltage pulse is input to the gate of the excitatory-inhibitory neuromorphic transistor having the plurality of discrete drains, thereby realizing the function of biological neurons receiving multi-terminal inhibitory stimulation inputs.

[0133] Finally, it is to be noted that any modification or equivalent replacement of part or all of the technical features based on the device structure of the present invention and the technical solution of the described embodiment, which does not deviate from the essence of the corresponding technical solution of the present invention, belongs to the patent scope of the device structure of the present invention and the described implementation scheme.

Claims

1. An excitatory-inhibitory neuromorphic transistor, characterized in that include: Substrate, channel layer, inert electrode, gate dielectric layer, source, drain, gate; The substrate surface has a channel layer, the substrate surfaces on both sides of the channel layer have an inert electrode and a source electrode respectively, a portion of the inert electrode and a portion of the source electrode are superimposed on the surface of the channel layer, the exposed surface of the channel layer and the inert electrode surface have a gate dielectric layer, the surface of the gate dielectric layer has a gate and a drain electrode, the drain electrode is located directly above the inert electrode, the gate is located directly above the channel layer, and the gate is located between the source electrode and the drain electrode; The source, the gate and the inert electrode constitute a field effect transistor, the drain, the inert electrode and the gate dielectric layer therebetween constitute a volatile memristor, and the volatile memristor and the field effect transistor are coupled together through the inert electrode.

2. An excitatory-inhibitory neuromorphic transistor as claimed in claim 1, characterized in that: The channel layer material is a layered two-dimensional material with semiconductor properties, and the inert electrode is an inert metal or a layered two-dimensional material with inert metal properties.

3. The excitatory-inhibitory neuromorphic transistor according to claim 1, characterized in that: The gate dielectric layer under the drain has the same thickness as the gate dielectric layer under the gate.

4. The excitatory-inhibitory neuromorphic transistor of claim 1, wherein: The gate serves as an inhibitory input port of the excitatory-inhibitory neuromorphic transistor, and the drain serves as an excitatory input port of the excitatory-inhibitory neuromorphic transistor.

5. The excitatory-inhibitory neuromorphic transistor of claim 1, wherein: Also includes: A plurality of discrete drain electrodes are disposed directly above the inert electrode.

6. An excitatory-inhibitory neuromorphic transistor as claimed in claim 5, characterized in that: Each of the discrete drain electrodes and the inert electrode and the gate dielectric layer therebetween constitutes a volatile memristor, and a plurality of the volatile memristors are connected in parallel and then connected to the field effect transistor.

7. A method for manufacturing an excitatory-inhibitory neuromorphic transistor, characterized in that: include: providing a substrate; forming a channel layer on the surface of the substrate; forming an inert electrode on the surface of the substrate and one side of the channel layer, wherein a portion of the inert electrode is superimposed on the surface of the channel layer; forming a source electrode on the surface of the substrate and the other side of the channel layer, wherein a portion of the source electrode is superimposed on the surface of the channel layer; The exposed surface of the channel layer and the surface of the inert electrode form a gate dielectric layer; A gate and a drain are formed on the surface of the gate dielectric layer. The drain is located directly above the inert electrode. The gate is located directly above the channel layer and between the source and the drain.

8. The method for manufacturing an excitatory-inhibitory neuromorphic transistor according to claim 7, characterized in that: Also includes: A plurality of discrete drain electrodes are formed on the surface of the gate dielectric layer, and the plurality of discrete drain electrodes are all located directly above the inert electrode.

9. A method for operating an excitatory-inhibitory neuromorphic transistor, characterized in that: include: Providing the excitatory-inhibitory neuromorphic transistor as claimed in claim 1; Inputting an excitatory voltage pulse to the drain of the excitatory-inhibitory neuromorphic transistor, and outputting a first current pulse to the source; Alternatively, an excitatory voltage pulse is input to the drain of the excitatory-inhibitory neuromorphic transistor, an inhibitory voltage pulse is input to the gate, and a second current pulse is output to the source.

10. The method for operating an excitatory-inhibitory neuromorphic transistor according to claim 9, characterized in that: Under the stimulation of a voltage pulse of a certain frequency input to the drain, if the gate input inhibitory voltage pulse is 0V, the source output current pulse emission rate is X; if the gate input inhibitory voltage is less than 0V, the source output current pulse emission rate is less than X; the current pulse emission rate is calculated as: the number of current pulses output by the source within a certain period of time / the number of voltage pulses input by the drain.

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