One-time programmable antifuse physical unclonable function

Abstract

A method includes performing a first read operation on memory cells of a programmed first one-time programmable (OTP) antifuse to determine a state of the memory cells based on a first parameter level, performing a second read operation on the programmed memory cells of the first OTP antifuse to determine a state of the memory cells based on a second parameter level, identifying the memory cells of the first OTP antifuse as indeterminate bits when the state determined during the first read operation is different from the state determined during the second read operation, and programming one or more memory cells of a second OTP antifuse based on a bit position of the identified indeterminate bits of the first OTP antifuse.

Description

Technical Field

[0001] The present disclosure relates generally to one-time programmable systems and, more particularly, to one-time programmable antifuse physically unclonable functionality. Background Art

[0002] A physically unclonable function (PUF) is a physically defined keyword that serves as a unique identifier for semiconductor devices such as microprocessors. A PUF is a physical entity implemented in a physical structure. A PUF is based on unique physical changes that occur naturally during semiconductor manufacturing or post-processing. PUFs are typically implemented in integrated circuits and are often used in applications with high security requirements, more specifically in cryptography. Summary of the Invention

[0003] In one aspect, a method includes performing a first read operation on memory cells of a programmed first one-time programmable (OTP) antifuse based on a first parameter level to determine a state of the memory cells, performing a second read operation on the memory cells of the programmed first OTP antifuse based on a second parameter level to determine a state of the memory cells, identifying the memory cells of the programmed first OTP antifuse as indeterminate bits when the state determined during the first read operation is different from the state determined during the second read operation, and programming one or more memory cells of the second OTP antifuse based on a bit position of the identified indeterminate bits of the programmed first OTP antifuse.

[0004] In one aspect, a method includes performing a first read operation on memory cells of a first one-time programmable (OTP) antifuse, performing a second read operation on memory cells of a second OTP antifuse to determine a programmed / unprogrammed state of the memory cells of the second OTP antifuse, and masking a portion of the memory cells of the first OTP antifuse based on the second read operation, wherein the masked memory cells correspond to indeterminate bits of the first OTP antifuse.

[0005] In one aspect, a system includes a memory storing instructions and a processor coupled to the memory and executing the instructions. The instructions, when executed, cause the processor to perform operations including: performing a first read operation on memory cells of a programmed first OTP antifuse to determine a state of the memory cells based on a first parameter level, performing a second read operation on the memory cells of the programmed first OTP antifuse to determine a state of the memory cells based on a second parameter level, identifying the programmed memory cells of the first OTP antifuse as an indeterminate bit when the state determined during the first read operation differs from the state determined during the second read operation, and programming one or more memory cells of a second OTP antifuse based on the bit position of the identified indeterminate bit of the first OTP antifuse.

[0006] Other features of the present disclosure and the structure and operation of various embodiments are described in detail below with reference to the accompanying drawings. It should be noted that the present invention is not limited to the specific embodiments described herein. These embodiments are presented herein for illustrative purposes only. Based on the teachings contained herein, other embodiments will be apparent to those skilled in the relevant art(s). BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of embodiments of the present disclosure. The accompanying drawings are used to provide knowledge and understanding of the embodiments of the present disclosure and do not limit the scope of the present disclosure to these specific embodiments. In addition, the drawings are not necessarily drawn to scale.

[0008] Figure 1 A physically unclonable function (PUF) key according to an embodiment of the present disclosure is shown.

[0009] Figure 2 An example graph illustrating a normalized programming cell current distribution function according to an embodiment of the present invention is shown.

[0010] Figure 3 Depicted is a flow chart of a process for generating a PUF key according to an embodiment of the present disclosure.

[0011] Figure 4 An example of normalized programmed cell current for a one-time programmable (OTP) PUF keyword according to an embodiment of the present disclosure is shown.

[0012] Figure 5 The readout of the OTP PUF keyword during programming according to an embodiment of the present disclosure is shown.

[0013] Figure 6 The readout of the OTP PUF pairing word during programming according to an embodiment of the present disclosure is shown.

[0014] Figure 7 Depicted is a flow chart of a process for reading a PUF key according to an embodiment of the present disclosure.

[0015] Figure 8 The reading of the OTP PUF keyword and the OTP PUF pairing word during application reading according to an embodiment of the present disclosure is shown.

[0016] Figure 9 The readout of the PUF key during application reading according to an embodiment of the present disclosure is shown.

[0017] Figure 10 An abstract diagram depicts an example computer system in which embodiments of the present disclosure may operate. DETAILED DESCRIPTION

[0018] Aspects of the present disclosure relate to a one-time programmable (OTP) antifuse physically unclonable function (PUF).

[0019] To be physically unclonable, a PUF key includes the following properties: physical inspection of the silicon die (e.g., imaging and reverse engineering) does not reveal the key information, and the key is physically available when the chip is powered on. Using other protection techniques during chip power-up, an adversary may not be able to retrieve the key.

[0020] PUF keys can be implemented using one-time programmable (OTP) antifuses. OTP antifuses are a type of non-volatile memory (NVM). Typically, a relatively high programming voltage (e.g., from about 5V to about 10V) is applied to the OTP antifuse to break down the gate oxide of the antifuse cell transistor, thereby creating a conductive channel between the gate and the channel for data writing. This type of gate oxide breakdown is permanent and irreversible physical damage. OTP antifuses have the advantages of small area, low power consumption, high reliability, and fast read speed.

[0021] OTP antifuse memory products can generate programmed cells with breakdown transistor gate oxides that exhibit stable and sufficiently high conductivity that can be used to distinguish programmed cells from unprogrammed cells. The conductivity of a well-programmed OTP cell can be represented by a programmed cell current that generally exhibits a normal distribution. Due to the nature of silicon and silicon manufacturing, relatively low or relatively high conductivity of the breakdown transistor gate oxide occurs randomly at each cell location. In addition, PUF keywords can be generated using programmed OTP cells because low or high conductivity of the breakdown transistor gate cannot be detected by physical inspection. In a PUF keyword, a low conductivity cell can represent a binary 0 (or low state) and a high conductivity cell can represent a binary 1 (or high state), and vice versa.

[0022] The conductivity of programmed OTP antifuse cells is subject to variations in die-to-die processing, power supply, temperature, aging, and so on. This variation can affect the stability of the OTP PUF word. Therefore, improvements in OTP PUF stability are desirable. The OTP antifuse PUF scheme described herein provides high stability performance.

[0023] The method described herein provides a solution for generating a PUF key with a fully programmed OTP PUF keyword (OTP antifuse) and a partially programmed OTP PUF companion word by using multiple read operations with different read conditions to define a PUF with binary 0s and 1s, and mask all uncertain bits on the OTP PUF keyword. Utilizing a well-developed design and programming / reading method for the OTP word, a desired conductivity level is defined to increase the margin of application reads of the PUF key, as will be further described below. With this increased margin, those skilled in the art will appreciate that the OTP antifuse PUF scheme described herein can achieve improved stability of the PUF key across all silicon and operational variations (such as die-to-die variations, supply power variations, temperature variations, etc.).

[0024] In one embodiment, a PUF key is generated by first programming all cells or bits of an OTP antifuse or word by applying a relatively high programming voltage on the gates of the cell transistors of the OTP word and a relatively low voltage at the transistor channels to break down the gate oxide. After programming, each cell on the OTP word exhibits a certain degree of conductivity. Thus, with a desired read voltage on the cell gates and a desired read time length, all programmed cells read as high or binary 1 when compared to a relatively low conductivity level, L0. For example, the desired read time length may be in the range of approximately 10 ns to approximately 1000 ns. Compared to the low conductivity level, L0, unprogrammed cells read as low or binary 0. As discussed above, due to the nature of silicon and silicon manufacturing, each programmed cell with gate oxide breakdown randomly exhibits different conductivity levels at different cell locations on the OTP word.

[0025] Furthermore, two read operations are performed on the programmed OTP word. During the first read operation, all programmed cells are compared to a high conductivity level, L1, selected to be higher than L0. As a result, programmed cells with relatively low conductivity are read as a low state, or binary 0, while cells with relatively high conductivity are read as a high state, or binary 1. Cells read as binary 0 during the first read are considered 0s for the PUF key. During the second read operation, all programmed cells are compared to another high conductivity level, L3, selected to be higher than L1. As a result, programmed cells with relatively high conductivity are read as a high state, or binary 1, while cells with relatively low conductivity are read as a low state, or binary 0. Cells read as binary 1s during the second read operation are considered 1s for the PUF key. All cells read as 1s during the first read and as 0s during the second read are considered as indeterminate bits that need to be masked during the application read of the PUF key. Therefore, after two read operations, all programmed cells on the OTP word can be divided into three groups: one with low conductivity, one with medium conductivity, and one with high conductivity. To generate the PUF key, cells with low conductivity are assigned as 0s in the PUF key, while cells with high conductivity are assigned as 1s in the PUF key. At the same time, cells with medium conductivity are assigned as uncertain bits, and their corresponding cell positions on the OTP word are recorded and used to apply a read mask for the PUF key. The programmed OTP word is called the OTP PUF key.

[0026] To mask the uncertain bits of the OTP PUF keyword, a second OTP word is programmed as a companion word to the OTP PUF keyword programmed in the first step. On the companion word, all cells at the same cell position as the uncertain bit of the OTP PUF keyword are programmed, while all other cells are not programmed. In one embodiment, all cells at the same cell position as the uncertain bit of the OTP PUF keyword are not programmed, while all other cells are programmed. As described above, when compared to the low conductivity level L0, all programmed cells on the companion OTP word read as a high state or binary 1, and all unprogrammed cells read as a low state or binary 0. Therefore, during a PUF keyword application read, the bit positions of all uncertain bits of the OTP PUF keyword can be identified by reading the companion OTP word with a conductivity level of L0. As a result, all uncertain bits of the OTP PUF keyword can be masked. Therefore, one PUF keyword includes two OTP words (OTP antifuse), the first OTP word representing the OTP PUF keyword and the second OTP word representing the OTP PUF pairing word.

[0027] During an application read of a PUF word, two read operations are performed to read the PUF key. During the first read operation, all cells in the OTP PUF key are compared to a predetermined high conductivity level, L2, which is selected to be higher than conductivity level L1 but lower than conductivity level L3. With good margins between L1 and L2, and between L2 and L3, all 0s in the OTP PUF key are read as binary 0s, while all 1s in the OTP PUF key are read as binary 1s. For example, the read margin improvement can be from approximately 10% to approximately 30%. Simultaneously, the uncertain bits of the OTP PUF key are read as either binary 0 or 1. All of these uncertain bits are masked based on a second read operation performed on the OTP PUF partner word. During the second read operation, all cells in the OTP PUF partner word are compared to a low conductivity level, L0, which is selected to be lower than conductivity level L1. After the second read operation, the bit position information of all 1s on the OTP PUF pairing word is used to mask all uncertain bits of the OTP PUF keyword. In one embodiment, the OTP PUF pairing word is read before the OTP PUF keyword.

[0028] Figure 1A physical unclonable function key according to an embodiment of the present disclosure is shown. In one embodiment, a PUF key 100 can be generated from two OTP words. The first word can be referred to as an OTP PUF keyword 102, which contains all the 0s and 1s of the PUF keyword, and the second word is referred to as an OTP PUF pairing word 104, which is used to mask the uncertain bits on the OTP PUF keyword. All cells of the OTP PUF keyword 102 are programmed. Programmed cells with relatively low conductivity on the OTP PUF keyword 102 are designated as 0s of the PUF keyword, while programmed cells with relatively high conductivity on the OTP PUF keyword 102 are designated as 1s of the PUF keyword, as previously described herein. Programmed cells with medium conductivity are designated as uncertain bits, and the cell positions of the uncertain bits on the OTP PUF keyword 102 are recorded in the OTP PUF pairing word 104 through programming. To program the OTP PUF pairing word 104, all cells with the same cell position as the uncertain bit of the OTP PUF key 102 are programmed. During an application read of the PUF key 100, the PUF key information can be read from the OTP PUF key 102, and the uncertain bits of the OTP PUF key 102 are masked by the cell position information read from the programmed bits on the OTP PUF pairing word 104. In the OTP PUF scheme described herein, the stability of the OTP PUF key is improved by introducing the OTP PUF pairing word 104 to mask the programmed cells with medium conductivity on the OTP PUF key 102.

[0029] In the following description, the normalized programmed cell current I cell is used as an example to represent the conductivity of an OTP programmed cell and the threshold value for the OTP read operation. A person skilled in the art will appreciate that other OTP read parameters (such as read voltage level or read pulse time length or all combinations) can also be utilized in the read operation of the OTP PUF word.

[0030] Figure 2 An example graph 200 of a normalized programmed cell current distribution function (NDF) according to an embodiment of the present disclosure is shown. OTP antifuse memory products can generate programmed cells with stable and relatively high cell currents. The cell current of a well-programmed OTP cell typically has a normal distribution as shown in waveform 202. The programmed cell current level occurs randomly across OTP words or cell locations in an OTP memory array.

[0031] Figure 3 Depicted is a flow diagram of a process 300 for generating a PUF key, according to an embodiment of the present disclosure.

[0032] At 302, a PUF key is generated based on programming all cells (memory cells) or bits of the OTP word (first OTP antifuse) by applying a relatively high programming voltage on the gates of the cell transistors of the OTP word and a relatively low voltage at the transistor channels to break down the gate oxide. In one embodiment, one or more programmed cells of the OTP word may be read as unprogrammed if the cell current of the programmed cells is below L0.

[0033] Figure 4 An example of normalized programmed cell currents for an OTP PUF keyword according to an embodiment of the present disclosure is shown. Due to the nature of silicon and silicon manufacturing, cell current levels occur randomly at each cell location. Table 400 shows OTP PUF keyword current levels 402 and corresponding cell locations 404.

[0034] At 304, all programmed cells of the PUF keyword are read. The system performs a first comparison of the parameter value of each programmed cell with a first parameter level. The parameter value may be a parameter associated with the conductivity of the memory cell. The first parameter level may include a first conductivity level or a current level representing the first conductivity level. For example, the current level of each programmed cell is compared to the first current level I cell_1 were compared.

[0035] At 306, all programmed cells of the PUF keyword are read again. The system performs a second comparison of the parameter value of each programmed cell with the second parameter level. For example, the current level is compared with the second current level I cell_3 are compared. In this example, I cell_1 Equal to 0.55 and I cell_3 is equal to 0.75. Both are normalized current numbers. I cell_1 and I cell_3 like Figure 2 shown.

[0036] At 308, a state is associated with each cell of the PUF key based on the first comparison and the second comparison. cell_1 The programmed cell having a cell current of 0 is designated as a binary 0 of the PUF key and has a current level higher than the second current level I cell_3 The programmed cell with a cell current of I is designated as a binary 1 of the PUF key. cell_1 and the second current level I cell_3 The cells between the cell currents are designated as indeterminate bits or 0 / 1. Figure 5The reading of the OTP PUF key during programming according to an embodiment of the present disclosure is shown. Table 500 shows the OTP PUF key state 502 and cell location 504.

[0037] The second OTP antifuse (ie, the OTP PUF pairing word) is programmed to the OTP PUF pairing word of the programmed OTP PUF keyword at 310. All cells of the OTP PUF pairing word having the same cell position designated as an indeterminate bit on the OTP PUF keyword are programmed.

[0038] Figure 6 6 shows the reading of the OTP PUF pairing word during programming according to an embodiment of the present disclosure. Table 600 shows the OTP PUF pairing word 602 and the cell position 604. The cells with the same cell position as the uncertain bit of the OTP PUF keyword are programmed, as shown in FIG. Figure 6 All other cells are not programmed, as indicated by the "P" in Figure 6 As indicated by the "U" in Figure 2 As shown, the programmed and unprogrammed cells on the OTP PUF pairing word can be controlled by comparing their respective cell currents to a value below I cell_1 In one embodiment, the third current level is I cell_0 .

[0039] During application, as described below, reading of the PUF key is performed.The PUF key consists of two programmed OTP words, one as the OTP PUF keyword and the other as the OTP PUF pairing word.

[0040] Figure 7 Depicted is a flow diagram of a process 700 for reading a PUF key, according to an embodiment of the present disclosure.

[0041] At 702, all cells on the OTP PUF key (ie, the first OTP antifuse) are read and compared to the fourth current level I cell_2 The fourth current level I cell_2 You can Figure 2 As shown in cell_2 In this example it is equal to 0.65.

[0042] At 704, all cells on the OTP PUF pairing word (ie, the second OTP antifuse) are read and compared to the third current level I cell_0 For comparison, such as Figure 2 As indicated in . Figure 8The reading of the OTP PUF keyword and the OTP PUF pairing word during an application read according to an embodiment of the present disclosure is shown. Table 800 shows the reading of the OTP PUF keyword 802 and the reading of the OTP PUF pairing word 804. For the OTP PUF keyword 802, all cell positions with the OTP PUF keyword state 502 as binary 0 are read as binary 0, cells with the OTP PUF keyword state 502 as binary 1 are read as binary 1, and cells with the OTP PUF keyword state 502 as binary 0 / 1 are read as binary 0 or 1. For the OTP PUF pairing word 804, all unprogrammed cells are read as binary 0 and all programmed cells are read as binary 1, as shown in FIG. Figure 6 As expected.

[0043] At 706 , the uncertain bits on the OTP PUF key are masked based on the reading of the OTP PUF pairing word. Figure 9 900 shows an OTP PUF keyword 902 and a cell location 904. Table 900 is derived from Table 800. For example, for cell location cell0, the OTP PUF keyword is read as binary 1 and the corresponding OTP PUF pairing word is read as binary 0 (from Table 800). Therefore, the binary 0 for the OTP PUF pairing word indicates that the OTP PUF keyword at cell location cell0 is not masked. For cell location cell3, the OTP PUF keyword is read as binary 1 and the corresponding OTP PUF pairing word is read as binary 1. Figure 9 As shown, the binary 1 for the OTP PUF pairing word indicates that the cell position cell3 is masked.

[0044] As discussed above, the cell current of a programmed OTP antifuse cell may shift over the course of user usage and vary with changes in power supply and ambient temperature. cell The current may also have variations in die to die processing, power supply, temperature, aging, etc., as understood by one of ordinary skill in the art. cell_1 and I cell_2 The margin between cell_3 and I cell_2 The overall stability of the current OTP PUF keyword is improved by increasing the margin between them.

[0045] In one embodiment, as will be appreciated by one of ordinary skill in the art, a PUF key may require a balance of 0s and 1s. In one embodiment, balancing can be easily achieved by generating more PUF bits than required on an OTP PUF key and then masking the unbalanced bits (unwanted cells) using an OTP pairing word associated with the OTP PUF key. Unbalanced bits or unneeded cells correspond to memory cells that have a balance of more than 0s and 1s. If desired, multiple OTP PUF keys and their OTP pairing words can be used to generate a PUF key. For example, to create a 256-bit PUF key, all cells on multiple OTP PUF keys are programmed to obtain more than 128 PUF 0s and more than 128 PUF 1s. On the OTP pairing words of these multiple OTP PUF keys, only the 256 cells that share the same cell position as any 128 PUF 0s and any 128 PUF 1s are not programmed, while all other cells are programmed. Therefore, the programmed cells on the OTP pairing word represent not only the uncertain bits of the OTP PUF key, but also the unnecessary PUF key bits. Therefore, the number of 0s and 1s of the PUF key can be generated in a balanced manner.

[0046] In one embodiment, two or more OTP pairing words are assigned to a single OTP PUF key to improve the read stability of the OTP PUF pairing word. For example, the third OTP antifuse can be programmed at step 310. During the reading of the PUF key, the two or more OTP PUF pairing words can be used together to identify the uncertain bits of the OTP PUF key.

[0047] In one embodiment, a memory cell may have a data storage element constructed around an ultra-thin dielectric (such as a gate oxide), and the data storage element is used to store information by stressing the ultra-thin dielectric to breakdown to set the memory cell's leakage current level. The memory cell is read by sensing the current drawn by the cell.

[0048] The OTP antifuse described herein can be part of a memory integrated circuit that includes many other well-known elements, such as sense amplifiers, pull-up circuits, word line amplifiers, decoders, voltage amplifiers, and the like.

[0049] The memory incorporating the OTP antifuse is preferably fabricated using any advanced process for fabricating n-type gated devices, p-type gated devices, or both types of devices.

[0050] Figure 10An exemplary computer system 1000 is shown within which a set of instructions for causing the machine to perform any one or more of the methodologies discussed herein may be executed. In alternative implementations, the machine may be connected (e.g., networked) to other machines in a local area network (LAN), an intranet, an extranet, and / or the Internet. The machine may operate in the capacity of a server or a client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or a client machine in a cloud computing infrastructure or environment.

[0051] The machine may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a web appliance, a server, a network router, a switch or a bridge, or any machine capable of executing a set of instructions (sequential or otherwise) that specify actions to be taken by the machine. Furthermore, while a single machine is illustrated, the term "machine" should also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0052] The example computer system 1000 includes a processing device 1002, a main memory 1004 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) such as synchronous DRAM (SDRAM), static memory 1006 (e.g., flash memory, static random access memory (SRAM), etc.), and a data storage device 1018 that communicate with each other via a bus 1030.

[0053] The processing device 1002 represents one or more processors such as a microprocessor, a central processing unit, or the like. More specifically, the processing device may be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor that implements other instruction sets, or a processor that implements a combination of instruction sets. The processing device 1002 may also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 1002 may be configured to execute instructions 1026 for performing the operations and steps described herein.

[0054] The computer system 1000 may further include a network interface device 1008 for communicating over a network 1020. The computer system 1000 may also include a video display unit 1010 (e.g., a liquid crystal display (LCD) or a cathode ray tube (CRT)), an alphanumeric input device 1012 (e.g., a keyboard), a cursor control device 1014 (e.g., a mouse), a graphics processing unit 1022, a signal generating device 1016 (e.g., a speaker), the graphics processing unit 1022, a video processing unit 1028, and an audio processing unit 1032.

[0055] The data storage device 1018 may include a machine-readable storage medium 1024 (also referred to as a non-transitory computer-readable medium) on which is stored one or more sets of instructions 1026 or software implementing any one or more of the methodologies or functions described herein. During execution of the instructions 1026 by the computer system 1000, the instructions 1026 may also reside, completely or at least partially, within the main memory 1004 and / or within the processing device 1002, the main memory 1004 and the processing device 1002 also constituting machine-readable storage media.

[0056] In some implementations, the instructions 1026 include instructions for implementing functionality corresponding to the present disclosure. Although the machine-readable storage medium 1024 is shown as a single medium in the example implementation, the term "machine-readable storage medium" should be understood to include a single medium or multiple media (e.g., a centralized or distributed database, and / or associated caches and servers) that store one or more sets of instructions. The term "machine-readable storage medium" should also be understood to include any medium that can store or encode a set of instructions for execution by a machine and enable the machine and processing device 1002 to perform any one or more methods of the present disclosure. Therefore, the term "machine-readable storage medium" should be understood to include, but is not limited to, solid-state memory, optical media, and magnetic media.

[0057] Some portions of the foregoing detailed description are presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are used by those skilled in the art of data processing to most effectively convey the substance of their work to others skilled in the art. An algorithm may be a sequence of operations leading to a desired result. These operations are those requiring physical manipulation of physical quantities. These quantities may take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. Such signals may be referred to as bits, values, elements, symbols, characters, terms, numbers, etc.

[0058] It should be remembered, however, that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. Unless otherwise indicated, as will be apparent from this disclosure, it should be understood that throughout this specification certain terms refer to actions and processes of computer systems or similar electronic computing devices that manipulate and transform data represented as physical (electronic) quantities within the computer system's registers and memories into other data similarly represented as physical quantities within the computer system's memories or registers or other such information storage devices.

[0059] The present disclosure also relates to an apparatus for performing the operations herein. The apparatus may be specially constructed for the intended purpose, or it may comprise a computer selectively activated or reconfigured by a computer program stored in the computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, magnetic or optical cards, or any type of medium suitable for storing electronic instructions, each coupled to a computer system bus.

[0060] The algorithms and displays presented herein do not inherently relate to any particular computer or other device. According to the teachings herein, various other systems may be used with the program, or it may prove convenient to construct a more specialized device to perform the method. In addition, the present disclosure is not described with reference to any particular programming language. It will be appreciated that a variety of programming languages ​​may be used to implement the teachings of the present invention described herein.

[0061] The present disclosure can be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon, and the instructions may be used to program a computer system (or other electronic device) to perform a process according to the present disclosure. Machine-readable media includes any mechanism for storing information in a form readable by a machine (e.g., a computer). For example, a machine-readable (e.g., computer-readable) medium includes a machine (e.g., computer) readable storage medium such as a read-only memory ("ROM"), a random access memory ("RAM"), a magnetic disk storage medium, an optical storage medium, a flash memory device, etc.

[0062] In the foregoing disclosure, the implementation of the present disclosure has been described with reference to its specific example implementations. Obviously, various modifications may be made thereto without departing from the scope of the implementation of the present disclosure set forth in the appended claims. Where the present disclosure refers to some elements in the singular, more than one element may be depicted in the accompanying drawings, and the same elements are marked with the same numerals. Therefore, the present disclosure and the accompanying drawings are to be considered illustrative rather than restrictive.

Claims

1. A method for a one-time programmable system, comprising: performing, by one or more computer devices, a first read operation on a memory cell of the programmed first one-time programmable (OTP) antifuse to determine a state of the memory cell based on a first parameter level; performing, by the one or more computer devices, a second read operation on the memory cells of the programmed first OTP antifuse to determine states of the memory cells based on a second parameter level; identifying, by the one or more computer devices, the memory cell of the programmed first OTP antifuse as an indeterminate bit when the state determined during the first read operation is different from the state determined during the second read operation; as well as One or more memory cells of a second OTP antifuse are programmed by the one or more computer devices based on the identified bit position of the indeterminate bit of the first OTP antifuse. 2 . The method of claim 1 , wherein the parameter value of the memory cell identified as the indeterminate bit is between the first parameter level and the second parameter level. 3 . The method of claim 2 , wherein the parameter value corresponds to conductivity of the memory cell, the first parameter level comprises a first conductivity level, and the second parameter level comprises a second conductivity level. The method of claim 2 , wherein the first parameter level comprises a first voltage level and the second parameter level comprises a second voltage level.

5. The method of claim 2, wherein the first parameter level and the second parameter level are threshold current levels selected based on a normalized memory cell current distribution of memory cells of the programmed first OTP antifuse. 6 . The method of claim 1 , wherein a programmed memory cell of the second OTP antifuse has a same bit position in the second OTP antifuse as the indeterminate bit in the first OTP antifuse.

7. The method of claim 1, wherein a number of programmed memory cells of the programmed first OTP antifuse is greater than a number of bits required in a physically unclonable (PUF) key.

8. The method according to claim 7, further comprising: A plurality of memory cells of the second OTP antifuse corresponding to unwanted memory cells that exceed a balance between high state and low state memory cells of the first OTP antifuse based on a desired number of bits are programmed.

9. The method according to claim 1, further comprising: One or more cells of a third OTP antifuse are programmed based on the identified bit position of the indeterminate bit of the first OTP antifuse.

10. A method for a one-time programmable system, comprising: performing, by one or more computer devices, a first read operation on a memory cell of a first one-time programmable (OTP) antifuse; performing, by the one or more computer devices, a second read operation on the memory cells of the second OTP antifuse to determine programming states of the memory cells of the second OTP antifuse; as well as A portion of the memory cells of the first OTP antifuse is masked by the one or more computer devices based on the second read operation, wherein the masked memory cells are determined based on the programmed states of the memory cells in the second OTP antifuse.

11. The method of claim 10, wherein performing the first read operation comprises: A low state is associated with the memory cell of the first OTP antifuse when the parameter value is below a first parameter level. 12 . The method of claim 11 , wherein the parameter value corresponds to conductivity of the memory cell, and the first parameter level comprises a first conductivity level.

13. The method of claim 12, wherein the first conductivity level is greater than a second conductivity level and lower than a third conductivity level, wherein the second conductivity level and the third conductivity level are based on a normalized memory cell current distribution of the first OTP antifuse.

14. The method of claim 13, wherein performing the second read operation comprises: associating a high state with the memory cell of the second OTP antifuse when the conductivity of the memory cell of the second OTP antifuse is greater than the second conductivity level; as well as The indeterminate bit of the first OTP antifuse is identified as the memory cell in the first OTP antifuse having the same position as the memory cell in the second OTP antifuse having a high state.

15. The method according to claim 10, further comprising: A third read operation is performed on the memory cells of a third OTP antifuse, wherein the masking of the portion of the memory cells of the first OTP antifuse is further based on the third read operation.

16. A one-time programmable system comprising: a memory for storing instructions; The first one-time programmable OTP antifuse; Second OTP antifuse; as well as a processor coupled to the memory and configured to execute the instructions, wherein the instructions, when executed, cause the processor to perform operations comprising: programming memory cells of the first OTP antifuse to provide a programmed first OTP antifuse; performing a first read operation on the memory cells of the programmed first OTP antifuse to determine states of the memory cells based on a first parameter level, performing a second read operation on the memory cells of the programmed first OTP antifuse to determine states of the memory cells based on a second parameter level, identifying the memory cell of the programmed first OTP antifuse as an indeterminate bit when the state determined during the first read operation is different from the state determined during the second read operation, and One or more memory cells of the second OTP antifuse are programmed based on the identified bit position of the indeterminate bit of the programmed first OTP antifuse.

17. The system of claim 16, wherein the parameter value of the memory cell identified as the indeterminate bit is between the first parameter level and the second parameter level.

18. The system of claim 16, wherein a programmed memory cell of the second OTP antifuse has a same bit position in the second OTP antifuse as the indeterminate bit in the first OTP antifuse.

19. The system of claim 16, wherein the processor is further configured to perform operations comprising: A plurality of memory cells of the second OTP antifuse corresponding to unwanted memory cells corresponding to memory cells exceeding a balance between high-state memory cells and low-state memory cells of the first OTP antifuse are programmed.

20. The system of claim 16, wherein the processor is further configured to perform operations comprising: One or more cells of a third OTP antifuse are programmed based on the identified bit position of the indeterminate bit of the first OTP antifuse.

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