Encoding representation method suitable for topology generation and parameter optimization of analog integrated circuits

By encoding analog integrated circuits into adjacency matrices, the problem of representing topological structure and parameter information in analog integrated circuit design is solved, realizing automated circuit design and optimization, and improving design efficiency and accuracy.

CN115618784BActive Publication Date: 2026-06-30GUANGZHOU UNIVERSITY
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
GUANGZHOU UNIVERSITY
Filing Date
2022-10-08
Publication Date
2026-06-30

AI Technical Summary

Technical Problem

Existing technologies are insufficient to effectively describe the topology and parameter information of analog integrated circuits, resulting in a significant expenditure of human and material resources in the design and verification process.

Method used

By employing an encoding representation method, analog integrated circuits are transformed into adjacency matrices, supporting topology generation and parameter optimization. By defining component types, pin counts, parameter ranges, and adjacency matrix construction, a complete representation and optimization of the circuit topology can be achieved.

Benefits of technology

It enables automated design of analog integrated circuits, improving design efficiency and accuracy, and supports complete descriptions of topology generation and parameter optimization, making it suitable for circuit simulation and automated verification.

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Abstract

This invention relates to the field of integrated circuit technology, specifically to an encoding representation method suitable for analog integrated circuit topology generation and parameter optimization. The method includes the following steps: encoding the analog integrated circuit; converting the circuit encoding into an adjacency matrix to represent circuit connection relationships; extending the encoding to support analog integrated circuit topology generation; and extending the encoding to support analog integrated circuit parameter optimization. This encoding representation method for analog integrated circuit topology generation and parameter optimization, while fully representing the analog integrated circuit, proposes an adjacency matrix to represent the circuit topology structure and serve as the input and output of the topology generation algorithm. It is applicable to analog integrated circuit topology generation and parameter optimization, and can fully represent the information required for circuit topology generation and parameter optimization. This invention has the advantages of strong integration integrity, support for mutual conversion with netlists, and adaptability to circuit topology generation and parameter optimization.
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Description

Technical Field

[0001] This invention relates to the field of integrated circuit technology, specifically to a coding representation method applicable to topology generation and parameter optimization of analog integrated circuits. Background Technology

[0002] Analog integrated circuit design is a demanding task that requires a lot of manpower and resources. Designing or verifying a new circuit structure often requires a team to spend a lot of effort and cost, which is why automated design of analog integrated circuits has emerged.

[0003] In practical applications of analog integrated circuit automation, converting real circuit topology into computer-readable data requires a specific encoding method to act as a bridge between the two, establishing a one-to-one mapping between the circuit topology and parameter information and the circuit code. This encoding method, while representing the circuit's topology and parameter information, also needs to be applicable to topology generation and parameter optimization. Therefore, the functionality of the encoding needs to be expanded to fully represent the information required for automated circuit design. Summary of the Invention

[0004] The purpose of this invention is to provide an encoding representation method suitable for topology generation and parameter optimization of analog integrated circuits, so as to solve the problems mentioned in the background art.

[0005] To achieve the above objectives, the present invention provides the following technical solution: a coding representation method suitable for analog integrated circuit topology generation and parameter optimization, comprising the following steps:

[0006] S1: Encode the analog integrated circuit.

[0007] S2: Convert the circuit code into an adjacency matrix to represent the circuit connection relationship.

[0008] S3: Extended coding to support analog integrated circuit topology generation.

[0009] S4: Extended coding to support parameter optimization for analog integrated circuits.

[0010] Preferably, the steps in S1 can be refined as follows:

[0011] S1.1: Define the number, number of pins, and number of parameters for each component type, and specify the physical meaning of the corresponding index pins and parameters, as well as the definition range of the parameters.

[0012] S1.2: Initialize and add circuit components, and allocate storage space for the corresponding components.

[0013] S1.3: The physical meaning of the pins corresponding to the component type. Set the value of the pin space corresponding to the component. If several pins have the same value, it means that the pins are connected to each other.

[0014] S1.4: The physical meaning of the parameters corresponding to the component type. Set the value of the parameter space corresponding to the component. If the parameter range exceeds the limit range, set it to the highest or lowest value of the parameter range.

[0015] S1.5: Convert the final code into a netlist for circuit simulation.

[0016] Preferably, the steps in S2 can be refined as follows:

[0017] S2.1: Starting from the first pin of the first component, traverse all components in the circuit and record the component number and pin number connected to each pin of each component.

[0018] S2.2: Construct an adjacency matrix by assigning component numbers and pin numbers according to the relationship between components and pins.

[0019] Preferably, the steps in S3 can be refined as follows:

[0020] S3.1: Determine the number of ports in the circuit section to be optimized. According to step 1.1, define the type of circuit to be optimized, where the initial value of the number of parameters in the circuit section to be optimized is 0.

[0021] S3.2: Add the circuit elements to be optimized to the circuit according to S1.2 and S1.3, and connect them to the corresponding ports.

[0022] S3.3: The computer identifies the circuit element to be optimized and divides the circuit part corresponding to the element to be optimized into the part to be optimized, while the rest is the fixed part.

[0023] S3.4: Using an analog integrated circuit topology generation algorithm, a new generated circuit with the corresponding number of ports is generated based on the number of ports of the circuit element to be optimized, and represented in the form of an adjacency matrix.

[0024] S3.5: The computer replaces the components of the newly generated circuit with those of the circuit to be optimized, and performs automated simulation verification to verify the feasibility and performance of the newly generated circuit. If the circuit does not meet the requirements, a new round of topology generation is performed; otherwise, the corresponding circuit is saved.

[0025] Preferably, the steps in S4 can be refined as follows:

[0026] S4.1: When performing parameter optimization, parameters can be divided into optimizable parameters, variable parameters, and fixed parameters. The definitions of these three types of parameters are as follows:

[0027] Optimizable parameters: In parameter optimization, the parameters of some circuit components need to be optimized. During the optimization process, the value of the parameters will change with the output of the optimization algorithm.

[0028] Variable parameters: In parameter optimization, some circuit components have certain functional relationships between their parameters. Therefore, parameters can be set as variables. Based on the optimizable parameters, special symbols are added to declare the parameter as a variable parameter. During the optimization process, the variable parameters will be calculated according to mathematical relationships. When the value of a variable changes, the value of the variable with the same variable name will also change.

[0029] Fixed parameters: In parameter optimization, we do not want to optimize the parameters of some circuit components. Therefore, we use a character type to set the value of the parameter. Based on the optimizable parameters, we add special symbols to declare the parameter as a fixed parameter. The value of the parameter will not change during the optimization process.

[0030] S4.2: When setting component parameters in S1.4, set the parameter type for each component according to the physical meaning of the circuit to be optimized.

[0031] S4.3: The computer reads the circuit code, identifies the parameter type, and optimizes the parameters according to the rules of each parameter type. If the performance does not meet the requirements during the optimization process, the next round of optimization is performed; otherwise, the corresponding circuit is saved.

[0032] Compared with the prior art, the beneficial effects of the present invention are:

[0033] This coding representation method, applicable to topology generation and parameter optimization of analog integrated circuits, fully describes the analog integrated circuit while proposing an adjacency matrix to represent the circuit topology and serve as the input and output of the topology generation algorithm. It is applicable to topology generation and parameter optimization of analog integrated circuits and can fully describe the information required for circuit topology generation and parameter optimization. This invention has the advantages of strong integration integrity, support for mutual conversion with netlists, and adaptability to circuit topology generation and parameter optimization. Attached Figure Description

[0034] Figure 1 This is a schematic diagram illustrating the definition of component information in this invention;

[0035] Figure 2 This is a schematic diagram of the circuit storage structure of the present invention;

[0036] Figure 3 This is a schematic representation of the adjacent circuit topology of the present invention;

[0037] Figure 4 This is a schematic diagram of the circuit type to be optimized in this invention. Detailed Implementation

[0038] like Figure 1-4 As shown, the present invention provides a technical solution: an encoding representation method suitable for topology generation and parameter optimization of analog integrated circuits, comprising the following steps:

[0039] S1: Encode the analog integrated circuit.

[0040] S1.1: Define the number, number of pins, and number of parameters for each component type, and specify the physical meaning of the corresponding index pins and parameters, as well as the definition range of the parameters.

[0041] S1.2: Initialize and add circuit components, and allocate storage space for the corresponding components.

[0042] S1.3: The physical meaning of the pins corresponding to the component type. Set the value of the pin space corresponding to the component. If several pins have the same value, it means that the pins are connected to each other.

[0043] S1.4: The physical meaning of the parameters corresponding to the component type. Set the value of the parameter space corresponding to the component. If the parameter range exceeds the limit range, set it to the highest or lowest value of the parameter range.

[0044] S1.5: Convert the final code into a netlist for circuit simulation.

[0045] S2: Convert the circuit code into an adjacency matrix to represent the circuit connection relationship.

[0046] S2.1: Starting from the first pin of the first component, traverse all components in the circuit and record the component number and pin number connected to each pin of each component.

[0047] S2.2: Construct an adjacency matrix based on the component numbers and pin numbers according to the relationship between components and pins.

[0048] S3: Extended coding to support analog integrated circuit topology generation.

[0049] S3.1: Determine the number of ports in the circuit section to be optimized. According to step 1.1, define the type of circuit to be optimized, where the initial value of the number of parameters in the circuit section to be optimized is 0.

[0050] S3.2: Add the circuit elements to be optimized to the circuit according to S1.2 and S1.3, and connect them to the corresponding ports.

[0051] S3.3: The computer identifies the circuit element to be optimized and divides the circuit part corresponding to the element to be optimized into the part to be optimized, while the rest is the fixed part.

[0052] S3.4: Using an analog integrated circuit topology generation algorithm, a new generated circuit with the corresponding number of ports is generated based on the number of ports of the circuit element to be optimized, and represented in the form of an adjacency matrix.

[0053] S3.5: The computer replaces the components of the newly generated circuit with those of the circuit to be optimized, and performs automated simulation verification to verify the feasibility and performance of the newly generated circuit. If the circuit does not meet the requirements, a new round of topology generation is performed; otherwise, the corresponding circuit is saved.

[0054] S4: Extended coding to support parameter optimization for analog integrated circuits.

[0055] S4.1: When performing parameter optimization, parameters can be divided into optimizable parameters, variable parameters, and fixed parameters. The definitions of these three types of parameters are as follows:

[0056] Optimizable parameters: In parameter optimization, the parameters of some circuit components need to be optimized. During the optimization process, the value of the parameters will change with the output of the optimization algorithm.

[0057] Variable parameters: In parameter optimization, some circuit components have certain functional relationships between their parameters. Therefore, parameters can be set as variables. Based on the optimizable parameters, special symbols are added to declare the parameter as a variable parameter. During the optimization process, the variable parameters will be calculated according to mathematical relationships. When the value of a variable changes, the value of the variable with the same variable name will also change.

[0058] Fixed parameters: In parameter optimization, we do not want to optimize the parameters of some circuit components. Therefore, we use a character type to set the value of the parameter. Based on the optimizable parameters, we add special symbols to declare the parameter as a fixed parameter. The value of the parameter will not change during the optimization process.

[0059] S4.2: When setting component parameters in S1.4, set the parameter type for each component according to the physical meaning of the circuit to be optimized.

[0060] S4.3: The computer reads the circuit code, identifies the parameter type, and optimizes the parameters according to the rules of each parameter type. If the performance does not meet the requirements during the optimization process, the next round of optimization is performed; otherwise, the corresponding circuit is saved.

[0061] While comprehensively describing analog integrated circuits, this invention proposes an adjacency matrix to represent the circuit topology and serve as the input and output of a topology generation algorithm. It is applicable to analog integrated circuit topology generation and parameter optimization, and can fully represent the information required for circuit topology generation and parameter optimization. This invention has the advantages of strong integration integrity, support for mutual conversion with netlists, and adaptability to circuit topology generation and parameter optimization. A circuit is essentially an undirected graph, with each circuit element as a vertex and electrical connections as edges. Different element types have different numbers and physical meanings of vertices and parameters. This invention uses graph theory to encode the circuit's topology and parameter information, representing the information of a single element as... Figure 1 The circuit structure is linearly combined to describe the complete circuit; the circuit encoding is converted into an adjacency matrix to describe the circuit topology and can be used as input to the topology generation algorithm; after determining the number of ports of the circuit to be optimized, the type of circuit to be optimized can be defined, and the topology can be divided into circuits to be optimized and fixed circuits, which is suitable for local topology generation of analog integrated circuits, and the adjacency matrix of the circuit is used as input and output to characterize the circuit topology; after determining the circuit parameter relationships, the parameters are divided into optimizable parameters, variable parameters, and fixed parameters, which is suitable for parameter optimization of analog integrated circuits.

Claims

1. An encoded representation method suitable for analog integrated circuit topology generation and parameter optimization, comprising, characterized by: Includes the following steps: S1: Encoding the analog integrated circuit, specifically including: S1.1: Define the number, number of pins, and number of parameters for each component type, and specify the physical meaning of the corresponding indexed pins and parameters, as well as the definition range of the parameters; S1.2: Initialize and add circuit components, and allocate storage space for the corresponding components; S1.3: The physical meaning of the pins corresponding to the component type, setting the value of the pin space corresponding to the component. If several pins have the same value, it means that the pins are connected to each other. S1.4: The physical meaning of the parameters corresponding to the component type, setting the value of the parameter space corresponding to the component. If the parameter range exceeds the limit range, it is set to the highest or lowest value of the parameter range. S1.5: Convert the final code into a netlist for circuit simulation; S2: Convert the circuit encoding into an adjacency matrix to represent the circuit connection relationships, specifically including: S2.1: Starting from the first pin of the first component, traverse all components in the circuit and record the component number and pin number connected to each pin of each component; S2.2: Construct an adjacency matrix by assigning component numbers and pin numbers according to the relationship between components and pins; S3: Extended coding to support analog integrated circuit topology generation, specifically including: S3.1: Determine the number of ports in the circuit section to be optimized. According to step 1.1, define the type of circuit to be optimized, where the initial value of the number of parameters in the circuit section to be optimized is 0. S3.2: Add the circuit components to be optimized to the circuit according to S1.2 and S1.3, and connect them to the corresponding ports. The pins of the circuit to be optimized have no physical meaning. S3.3: The computer identifies the circuit element to be optimized and divides the circuit part corresponding to the element to be optimized into the part to be optimized, while the remaining part is the fixed part; S3.4: Using an analog integrated circuit topology generation algorithm, a new generated circuit with the corresponding number of ports is generated based on the number of ports of the circuit element to be optimized, and represented in the form of an adjacency matrix; S3.5: The computer replaces the components of the newly generated circuit with those of the circuit to be optimized, and performs automated simulation verification to verify the feasibility and performance of the newly generated circuit. If the circuit does not meet the requirements, a new round of topology generation is performed; otherwise, the corresponding circuit is saved. S4: Extended coding to support analog integrated circuit parameter optimization, specifically including: S4.1: When performing parameter optimization, parameters can be divided into optimizable parameters, variable parameters, and fixed parameters. The definitions of these three types of parameters are as follows: Optimizable parameters: In parameter optimization, the parameters of some circuit components need to be optimized. During the optimization process, the value of the parameters will change with the output of the optimization algorithm. Variable parameters: In parameter optimization, there are certain functional relationships between the parameters of some circuit components. Therefore, the parameters can be set as variables. Based on the optimizable parameters, special symbols are added to declare the parameter as a variable parameter. During the optimization process, the variable parameters will be calculated according to mathematical relationships. When the value of a variable changes, the value of the variable with the same variable name will also change. Fixed parameters: In parameter optimization, we do not want to optimize the parameters of some circuit components. Therefore, we use a character type to set the value of the parameter. Based on the optimizable parameters, we add special symbols to declare the parameter as a fixed parameter. The value of the parameter will not change during the optimization process. S4.2: When setting component parameters in S1.4, set the parameter type of each component according to the physical meaning of the circuit to be optimized. S4.3: The computer reads the circuit code, identifies the parameter type, and optimizes the parameters according to the rules of each parameter type. If the performance does not meet the requirements during the optimization process, the next round of optimization is performed; otherwise, the corresponding circuit is saved.

Citation Information

Patent Citations

  • CN102751997A