Vertical-Structure LED Chip and Its Preparation Method, Light-Emitting Device, and Display Device

Abstract

The present invention discloses a vertical structure LED chip, a preparation method thereof, a light-emitting device and a display device. Since a current blocking layer with multiple discontinuous round holes is formed in the preparation of the vertical structure LED chip, and uniformly distributed and dense small holes are arranged in the current blocking layer in the step of preparing the chip to cover the entire bottom of the chip. When the chip works, the current will be forced to diffuse to the entire surface of the chip and then pass through the small holes, improving the overall current distribution of the chip and increasing the brightness. Under the same light-emitting area, the light-emitting device using this vertical structure LED chip has a higher luminous flux.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor devices, and particularly to a vertical structure LED chip, a preparation method thereof, a light emitting device, and a display device. Background Art

[0002] Traditional LED chips are mainly prepared on a sapphire substrate by means of metal organic chemical vapor deposition (MOCVD). However, due to the low conductivity of sapphire, which is basically an insulator, mesa etching (MESA) must be carried out to form a mesa structure on the surface of the epitaxial layer, but the mesa structure has the following disadvantages.

[0003] In principle, the current of a horizontal structure LED chip can only expand laterally, and current crowding effect is extremely likely to occur at the mesa. The current crowding effect will lead to serious uneven current distribution. The uneven distribution will not only cause uneven light emission and a decrease in light output power, thereby leading to a reduction in the electro-optical conversion efficiency, but also cause an excessive current density in a local area, resulting in excessive Joule heat, which will accelerate device aging and cause a decrease in the LED lifespan and other problems. For low-power LEDs, the current thermal effect can be alleviated by various heat dissipation means, but for high-power LED chips driven by a large current, the current crowding effect of the horizontal structure will be more serious, resulting in a low electro-optical conversion efficiency of the horizontal structure LED chip. Summary of the Invention

[0004] Based on this, in order to further improve the current distribution, reduce the current crowding effect, and increase the luminous flux of the LED chip, it is necessary to provide a vertical structure LED chip, a preparation method thereof, a light emitting device, and a display device.

[0005] The present invention provides a preparation method of a vertical structure LED chip, including the following steps:

[0006] S10: sequentially form a stacked first gallium nitride material layer, a multi-quantum well material layer, and a second gallium nitride material layer on a substrate to be bonded, and etch from the second gallium nitride material layer to the first gallium nitride material layer according to a preset insulating column position;

[0007] S20: sequentially form a metal reflective material layer and a current blocking material layer on the second gallium nitride material layer, etch the metal reflective material layer and the current blocking material layer at the preset insulating column position, and discontinuously etch a plurality of circular holes on the current blocking material layer until the metal reflective material layer is exposed to prepare a metal reflective layer and a current blocking layer;

[0008] S30: Form a metal protection material layer on the current blocking layer, etch the metal protection material layer at the position of the preset insulating posts to form a metal protection layer that surrounds the metal reflection layer and the current blocking layer;

[0009] S40: Fill insulating post materials at the positions of the preset insulating posts to prepare insulating posts, and form an insulating material layer on the metal protection layer and the insulating posts;

[0010] S50: Etch from the insulating material layer to the first gallium nitride material layer according to the preset first electrode post position, fill first electrode post materials at the preset first electrode post position to prepare the first electrode post and the insulating layer, and form a first electrode material layer on the insulating layer and the first electrode post to prepare the first electrode layer;

[0011] S60: Remove the substrate to be bonded;

[0012] S70: Remove the gallium nitride material on the first gallium nitride material layer outside the preset first gallium nitride layer position, remove the multiple quantum well material on the multiple quantum well material layer outside the preset multiple quantum well layer position, and remove the gallium nitride material on the second gallium nitride material layer outside the preset second gallium nitride layer position to prepare the first gallium nitride layer, the multiple quantum well layer, and the second gallium nitride layer, wherein the widths of the first gallium nitride layer, the multiple quantum well layer, and the second gallium nitride layer are the same, and are greater than the width of the metal reflection layer and less than the width of the metal protection layer;

[0013] S80: Form a second electrode on the side of the metal protection layer away from the insulating layer.

[0014] In one embodiment, before forming the first gallium nitride material layer on the substrate to be bonded in step S10, it further includes:

[0015] Form a buffer layer on the substrate to be bonded;

[0016] The first gallium nitride material layer is formed on the buffer layer.

[0017] In one embodiment, after step S50 and before step S60, it further includes:

[0018] Form a blocking layer and a bonding layer on the first electrode layer in sequence, provide a substrate with an adhesive layer, and bond the bonding layer and the adhesive layer.

[0019] In one embodiment, forming a second electrode on the side of the metal protection layer away from the insulating layer includes the following steps:

[0020] Form a passivation layer on the first gallium nitride layer and the metal protection layer;

[0021] Etch a preset second electrode position on the passivation layer, fill the second electrode material into the preset second electrode position to form the second electrode, and the second electrode is in contact with the metal protection layer.

[0022] In one embodiment, after step S60 and before step S70, it further includes a step of roughening the surface of the first gallium nitride material layer.

[0023] In one embodiment, a plurality of circular holes with a radius of 3 μm to 10 μm are etched discontinuously on the current blocking material layer.

[0024] In one embodiment, among the plurality of circular holes etched discontinuously on the current blocking material layer, the distance between the centers of two adjacent circular holes is 15 μm to 50 μm.

[0025] Furthermore, the present invention also provides a vertical structure LED chip prepared by the above preparation method.

[0026] The present invention further provides a light emitting device including the vertical structure LED chip as described above.

[0027] The present invention provides a display device, including: a circuit board and the light emitting device as described above, and the light emitting device is electrically connected to the circuit board through the first electrode and the second electrode of the vertical structure LED chip.

[0028] By the method of manufacturing a chip, especially by providing uniformly distributed and dense small holes in the formation of the current blocking layer, when the LED chip works, the current first enters the metal protection layer through the second electrode. Since a current blocking layer is added between the metal protection layer and the metal reflection layer, the current will be forced to diffuse over the entire surface of the metal protection layer and then pass through the openings of the current blocking layer to the metal reflection layer, making the current distribution of the whole chip uniform and each area in a better state, thereby improving the light emission uniformity of the chip and increasing the brightness; such that under the same light emitting area, the light emitting device using this vertical structure LED chip has a higher luminous flux. Description of the Drawings

[0029] Figure 1 It is a cross-sectional view of the vertical structure LED chip provided by the present invention;

[0030] Figure 2 It is a top view of the current blocking layer of the vertical structure LED chip provided by the present invention;

[0031] Figure 3 It is the display device provided by the present invention;

[0032] Figure 4The LED chip structure provided in Comparative Example 1;

[0033] The reference numerals in the accompanying drawings are explained as follows:

[0034] Vertical structure LED chip: 10, first gallium nitride layer: 101, multi-quantum well layer: 102, second gallium nitride layer: 103, metal reflective layer: 104, current blocking layer: 105, metal protective layer: 106, insulating structure: 107, insulating post: 107a, insulating layer: 107b, first electrode: 108, first electrode post: 108a, first electrode layer: 108b, second electrode: 109, substrate: 110, bonding layer: 111, bonding layer: 112, barrier layer: 113, passivation layer: 114, display device: 20, light-emitting device: 201, circuit board: 301. Detailed implementation manners

[0035] This application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive. Of course, they are only examples and are not intended to limit this application. In addition, this application may repeat reference numerals and / or letters in different examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or arrangements discussed.

[0036] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of such features. In the description of this application, "a plurality" means at least two, such as two, three, etc., unless otherwise specifically and clearly defined. In the description of this application, "several" means at least one, such as one, two, etc., unless otherwise specifically and clearly defined.

[0037] The terms "preferably", "more preferably", etc. in this application refer to the embodiments of this application that can provide certain beneficial effects in certain cases. However, in the same case or other cases, other embodiments may also be preferred. In addition, the description of one or more preferred embodiments does not imply that other embodiments are not available, nor is it intended to exclude other embodiments from the scope of this application.

[0038] When a numerical range is disclosed herein, the above range is considered continuous and includes the minimum and maximum values of the range, as well as every value therebetween. Further, when the range refers to integers, every integer between the minimum and maximum values of the range is included. In addition, when multiple ranges are provided to describe features or characteristics, the ranges may be combined. In other words, unless otherwise specified, all ranges disclosed herein should be understood to include any and all sub-ranges subsumed therein.

[0039] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the technical field to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0040] This application provides a method for fabricating a vertical structure LED chip, including the following steps S10 to step S70.

[0041] Step S10: Form a stacked first gallium nitride material layer, multiple quantum well material layer, and second gallium nitride material layer on the substrate to be bonded in sequence, and etch from the second gallium nitride material layer to the first gallium nitride material layer according to the preset insulating column positions.

[0042] In a specific example, in step S10, before forming the first gallium nitride material layer on the substrate to be bonded, it further includes:

[0043] Form a buffer layer on the substrate to be bonded;

[0044] The first gallium nitride material layer is formed on the buffer layer.

[0045] Specifically, form a buffer layer, a first gallium nitride material layer, a multiple quantum well material layer, and a second gallium nitride material layer on the substrate to be bonded in sequence.

[0046] It can be understood that the buffer layer, the first gallium nitride material layer, the multiple quantum well material layer, and the second gallium nitride material layer form an epitaxial layer, and the thickness of the epitaxial layer is 2 μm to 7 μm.

[0047] Further, the method for forming the above buffer layer, first gallium nitride material layer, multiple quantum well material layer, and second gallium nitride material layer may be but is not limited to at least one of metalorganic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), and physical vapor deposition (PVD).

[0048] The material of the above buffer layer can be, but is not limited to, at least one of AlN, AlGaN, and InGaN. The thickness of the buffer layer is 1 μm to 3 μm. The material of the multi-quantum well material layer can be, but is not limited to, InGaN / GaN. The thickness of the multi-quantum well material layer is 0.01 μm to 0.5 μm. The thickness of the first gallium nitride material layer is 1 μm to 3 μm. The thickness of the second gallium nitride material layer is 0.01 μm to 0.5 μm.

[0049] Understandably, a preset insulating pillar position is etched on the epitaxial layer. Specifically, fiducial points (Mark points) and insulating pillar patterns are fabricated on the epitaxial layer by means of photolithography, and inductively coupled plasma etching is performed on the epitaxial layer until the etching depth reaches the first gallium nitride material layer, where the Mark points are mainly used for alignment in subsequent processes.

[0050] Step S20: A metal reflective material layer and a current blocking material layer are sequentially formed on the second gallium nitride material layer. The metal reflective material layer and the current blocking material layer at the preset insulating pillar position are etched. Multiple circular holes are discontinuously etched through the current blocking material layer until the metal reflective material layer is exposed, to prepare a metal reflective layer and a current blocking layer.

[0051] Furthermore, the metal reflective material layer is formed by physical vapor deposition, which can be, but is not limited to, one or more of evaporation coating, sputtering coating, ion coating, ion beam assisted vapor deposition, and electron beam physical vapor deposition. Further, there is an annealing treatment step after the formation of the metal reflective material layer, and the annealing temperature is 200°C to 550°C, so that the metal reflective material layer forms a good ohmic contact with the epitaxial layer.

[0052] After forming the metal reflective material layer, a Mark point pattern for the next photolithography alignment is fabricated by photolithography, and then the Mark point pattern is prepared by wet etching; then a current blocking material layer is formed on the metal reflective material layer, and a pattern of the current blocking layer is fabricated by photolithography, and inductively coupled plasma etching or corrosion is performed on the pattern, and the current blocking material layer at the corresponding pattern is etched until the metal reflective material layer is exposed to form multiple circular holes. Understandably, the current blocking layer includes multiple discontinuous hollow circular holes.

[0053] In a specific example, multiple circular holes with a radius of 3 μm to 10 μm are discontinuously etched on the current blocking material layer. Preferably, the radius of the circular holes is 3 μm to 8 μm.

[0054] In a specific example, among the multiple circular holes discontinuously etched on the current blocking material layer, the distance between the centers of two adjacent circular holes is 15 μm to 50 μm. Preferably, the distance between the centers of two adjacent circular holes is 15 μm to 32 μm.

[0055] Further, the materials of the current blocking material layer are each independently selected from one or more of silicon nitride, silicon dioxide, and titanium pentoxide.

[0056] In a specific example, the thickness of the current blocking material layer is 0.2 μm to 0.5 μm, and the thickness of the metal reflective material layer is 0.1 μm to 1.2 μm.

[0057] Further, the material of the metal reflective material layer can be, but is not limited to, at least one selected from silver (Ag) and nickel (Ni). Specifically, the metal reflective material layer includes a composite structure of a silver layer and a nickel layer, where the thickness of the silver layer is 0.1 μm to 1 μm, and the thickness of the nickel layer is 0.001 μm to 0.05 μm. Preferably, the metal reflective material layer includes a Ni layer with a thickness of 0.001 μm to 0.003 μm and an Ag layer with a thickness of 0.1 μm to 0.2 μm.

[0058] Step S30: Form a metal protection material layer on the current blocking layer, etch the metal protection material layer at the preset insulating post position to form a metal protection layer that surrounds the metal reflective layer and the current blocking layer.

[0059] It can be understood that the method of forming the metal protection material layer is a physical vapor deposition method, which can be, but is not limited to, one or more of evaporation coating, sputtering coating, ion coating, ion beam assisted vapor deposition, and electron beam physical vapor deposition.

[0060] Specifically, a photolithography process is used to make the pattern of the metal protection layer. The metal protection layer protects the metal reflective layer from being damaged in subsequent processes. The metal protection material layer at the pattern is removed by a lift-off operation to form the metal protection layer. Further, the thickness of the metal protection layer is 1 μm to 4 μm. The material of the metal protection layer can be, but is not limited to, one or several selected from titanium (Ti), chromium (Cr), gold (Au), and platinum (Pt). The metal protection layer includes a Ti layer with a thickness of 0.3 μm to 0.6 μm, a Cr layer with a thickness of 0.01 μm to 0.1 μm, an Au layer with a thickness of 0.2 μm to 0.8 μm, and a Pt layer with a thickness of 0.2 μm to 0.6 μm.

[0061] Step S40: Fill the insulating post material at the preset insulating post position to prepare the insulating post, and form an insulating material layer on the metal protection layer and the insulating post.

[0062] Step S50: Etch from the insulating material layer to the first gallium nitride material layer according to the preset first electrode post position, fill the first electrode post material at the preset first electrode post position to prepare the first electrode post and the insulating layer, and form a first electrode material layer on the insulating layer and the first electrode post to prepare the first electrode layer.

[0063] In a specific example, the thickness of the insulating layer is 0.1 μm to 2 μm, the width of the insulating pillar is 40 μm to 60 μm, and the height of the insulating pillar is 0.1 μm to 2 μm.

[0064] Further, the materials of the insulating layer and the insulating pillar are each independently selected from at least one of silicon nitride, silicon dioxide, and titanium pentoxide.

[0065] Furthermore, the surface of the insulating layer away from the substrate is 1 μm to 4 μm away from the surface of the metal reflective layer away from the substrate.

[0066] Step S60: Remove the substrate to be bonded.

[0067] Further, remove the substrate to be bonded and the buffer layer. Specifically, the steps of removing the substrate to be bonded and the buffer layer include: grinding and thinning one side of the substrate to be bonded and the buffer layer, then performing chemical etching, and finally using inductively coupled plasma etching to remove the substrate to be bonded and the buffer layer.

[0068] In a specific example, after step S50 and before step S60, it further includes:

[0069] Form a barrier layer and a bonding layer on the first electrode layer in sequence, provide a substrate with an adhesive layer, and bond the bonding layer and the adhesive layer.

[0070] In a specific example, the formation methods of the first electrode pillar, the first electrode layer, the adhesive layer, the barrier layer, and the bonding layer are each independently selected from one or more of evaporation coating, sputtering coating, ion coating, ion beam assisted vapor deposition, and electron beam physical vapor deposition.

[0071] It can be understood that the substrate 110 is a silicon substrate or a silicon carbide substrate, and the thickness of the substrate 110 is 100 μm to 300 μm.

[0072] By aligning and bonding the bonding layer and the adhesive layer, it is easier to realize the flipping of the p - side and n - side of the LED chip, thus becoming the basis for subsequent fabrication of vertical chips. Moreover, large - area metal bonding can form a good heat - conduction effect.

[0073] Further, the thickness of the adhesive layer is 1 μm to 5 μm, the thickness of the bonding layer is 1 μm to 5 μm, and the thickness of the barrier layer is 1 μm to 3 μm.

[0074] Furthermore, the material of the adhesive layer can be, but is not limited to, one or several of chromium (Cr), nickel (Ni), tin (Sn), platinum (Pt), and gold (Au).

[0075] It can be understood that the material of the bonding layer can be, but is not limited to, one or several of chromium (Cr), nickel (Ni), tin (Sn), platinum (Pt), and gold (Au).

[0076] In a specific example, the material of the blocking layer can be, but is not limited to, one or more selected from chromium (Cr), titanium (Ti), platinum (Pt), and gold (Au).

[0077] Step S70: Remove the gallium nitride material on the first gallium nitride material layer outside the preset position of the first gallium nitride layer, remove the multiple quantum well material on the multiple quantum well material layer outside the preset position of the multiple quantum well layer, and remove the gallium nitride material on the second gallium nitride material layer outside the preset position of the second gallium nitride layer, to prepare the first gallium nitride layer, the multiple quantum well layer, and the second gallium nitride layer, wherein the widths of the first gallium nitride layer, the multiple quantum well layer, and the second gallium nitride layer are the same, and are greater than the width of the metal reflective layer and less than the width of the metal protective layer.

[0078] The material of the first gallium nitride layer is gallium nitride of the first conduction type, and the material of the second gallium nitride layer is gallium nitride of the second conduction type. Further, the first conduction type and the second conduction type are opposite. If the first conduction type is N-type, then the second conduction type is P-type; or if the first conduction type is P-type, then the second conduction type is N-type.

[0079] Further, the first gallium nitride layer is an N-GaN layer, and the second gallium nitride layer is a P-GaN layer.

[0080] It can be understood that the above is to fabricate an LED pattern on the surface of the wafer through a photolithography process. A photoresist is coated on the epitaxial layer at the light-emitting surface pattern of the LED chip for protection, and then the epitaxial layer is etched with a phosphoric acid solution at 120°C. The epitaxial layer in the patterned area protected by the photoresist will not be etched, while the epitaxial layer in the patterned area without photoresist protection will be completely etched away. The remaining patterned area is the final light-emitting surface pattern.

[0081] In a specific example, after step S60 and before step S70, there is also a step of roughening the surface of the first gallium nitride material layer.

[0082] Specifically, the surface of the first gallium nitride material layer processed in step S60 is roughened using a hot alkaline solution or a molten alkali; preferably, the above roughening treatment uses an aqueous solution of KOH, and the mass percentage concentration of KOH in the solution is 0.05% - 10%, and the temperature is 20°C - 90°C.

[0083] Step S80: Form a second electrode on the side of the metal protective layer away from the insulating layer.

[0084] In a specific example, forming a second electrode on the side of the metal protective layer away from the insulating layer includes the following steps:

[0085] Form a passivation layer on the first gallium nitride layer and the metal protective layer;

[0086] Etch a preset second electrode position on the passivation layer, fill the second electrode material into the preset second electrode position to form a second electrode, and the second electrode is in contact with the metal protection layer.

[0087] Further, the thickness of the passivation layer is 0.4 μm to 2 μm. Understandably, the material of the passivation layer is selected from one or more of, but not limited to, silicon dioxide SiO2, silicon nitride Si3N4, titanium dioxide TiO2, and titanium trioxide Ti3O5.

[0088] Further, the width of the first electrode post is 30 μm to 50 μm, the height of the first electrode post is 1 μm to 5 μm, the thickness of the first electrode layer is 1 μm to 5 μm, and the thickness of the second electrode is 1 μm to 5 μm.

[0089] Understandably, the material of the first electrode post and the material of the first electrode layer are metals with a first conduction type, and the material of the second electrode is a metal with a second conduction type. Further, the first conduction type and the second conduction type are opposite. If the first conduction type is N-type, the second conduction type is P-type, or if the first conduction type is P-type, the second conduction type is N-type.

[0090] Specifically, the first electrode is an N electrode, the second electrode is a P electrode, and the metals in the material of the first electrode post, the material of the first electrode layer, and the material of the second electrode are each independently selected from one or more of, but not limited to, chromium Cr, titanium Ti, aluminum Al, platinum Pt, and gold Au.

[0091] Further, as Figure 1 shown, the present application provides a vertical structure LED chip 10, which is prepared by the above-mentioned preparation method. The vertical structure LED chip 10 includes a first gallium nitride layer 101, a multi-quantum well layer 102, a second gallium nitride layer 103, a metal reflection layer 104, a current blocking layer 105, a metal protection layer 106, an insulating structure 107, and a first electrode 108. The first electrode 108 includes a first electrode post 108a and a first electrode layer 108b. The insulating structure 107 includes an insulating post 107a and an insulating layer 107b;

[0092] Wherein, one side of the first electrode layer 108b is in contact with one side of the first electrode column 108a and one side of the insulating layer 107b. The other side of the insulating layer 107b is in contact with one side of the insulating column 107a and one side of the metal protection layer 106. The insulating column 107a and the insulating layer 107b surround the first electrode column 108a. The metal protection layer 106 surrounds the current blocking layer 105 and the metal reflection layer 104 disposed on the current blocking layer 105. And the other side of the metal protection layer 106 is flush with the side of the metal reflection layer 104 away from the first electrode layer 108. The second gallium nitride layer 103, the multi-quantum well layer 102, and the first gallium nitride layer 101 are sequentially stacked on the side of the metal reflection layer 104 away from the first electrode layer 108b. The side of the second gallium nitride layer 103 away from the first gallium nitride layer 101 is in contact with the other side of the metal protection layer 106. The other side of the first electrode column 108a and the other side of the insulating column 107a are in the first gallium nitride layer 101.

[0093] Understandably, the above-mentioned vertical structure LED chip 10 further includes a substrate 110. The substrate 110 is disposed on the side of the first electrode 108 away from the second electrode 109, and the substrate 110 is in contact with the first electrode 108.

[0094] The above-mentioned vertical structure LED chip 10 further includes a second electrode 109. The side of the second gallium nitride layer 103 close to the substrate 110 is flush with the side of the second electrode 109 close to the substrate 110 and is in contact with the other side of the metal protection layer 106.

[0095] In a specific example, the vertical structure LED chip 10 further includes a barrier layer 113, a bonding layer 112, and an adhesive layer 111 between the substrate 110 and the first electrode 108. One side of the adhesive layer 111 is in contact with one side of the substrate, and the other side of the adhesive layer is in contact with one side of the bonding layer 112. The other side of the bonding layer 112 is in contact with one side of the barrier layer 113. The other side of the barrier layer 113 is in contact with one side of the first electrode layer 108b.

[0096] Furthermore, the vertical structure LED chip 10 further includes a passivation layer 114 disposed on the second gallium nitride layer 103. The passivation layer 114 surrounds the second gallium nitride layer 103, the multi-quantum well layer 102, and the first gallium nitride layer 101. The first gallium nitride layer 101 is in contact with the other side of the metal protection layer 106.

[0097] As Figure 2 shown, it is a top view of the current blocking layer 105 of the vertical structure LED chip provided by the present invention, in which the current blocking layer 105, the first electrode 108a, and the second electrode 109 can all be seen.

[0098] The present invention also provides a light-emitting device 201, which includes the vertical structure LED chip 10 as described above.

[0099] Furthermore, as Figure 3 shown, the present invention provides a display device 20, including: a circuit board 301 and the light-emitting device 201 as described above. The light-emitting device 201 is electrically connected to the circuit board 301 through the first electrode 108 and the second electrode 109 of the vertical structure LED chip 10. Specifically, the light-emitting device 201 is welded to the circuit board 301 through the first electrode 108 and the second electrode 109 of the vertical structure LED chip 10.

[0100] By means of the method for preparing the chip, especially by providing uniformly distributed and dense small holes in the formation of the current blocking layer 105, when the LED chip works, the current first enters the metal protection layer through the second electrode 109. Since the current blocking layer 105 is added between the metal protection layer 106 and the metal reflection layer 104, the current will be forced to diffuse over the entire surface of the metal protection layer 106 and then pass through the openings of the current blocking layer 105 to the metal reflection layer 104. Without the current blocking layer 105, most of the current will concentrate in the area closer to the second electrode 109 and pass through to the metal reflection layer 104, and the light emission distribution will show that the brightness of the area near the second electrode 109 is high and the brightness of the area far from the second electrode 109 is low. This makes the current distribution of the whole chip uniform and each area is in a better state, thereby improving the light emission uniformity of the chip and increasing the brightness; under the same light-emitting area, the light-emitting device 201 using this vertical structure LED chip 10 has a higher luminous flux.

[0101] The following provides specific embodiments to further illustrate in detail the vertical structure LED chip 10, its preparation method, the light-emitting device 201, and the display device 20 provided by the present application. The raw materials involved in the following specific embodiments, unless otherwise specified, can all be obtained commercially.

[0102] Example 1

[0103] The substrate is a Si substrate with a thickness of 300 μm. The bonding layer 111 on the substrate is a Cr / Pt / Ni / Sn / Au layer with a thickness of 1.5 μm. The bonding layer 112 on the bonding layer 111 is a Ni / Sn / Au layer with a total thickness of 1.4 μm. The barrier layer 113 on the bonding layer 112 is a Cr / Pt / Ti / Pt / Au / Ti / Pt layer with a thickness of 1.5 μm. The first electrode 108, i.e., the N electrode, on the barrier layer 113 includes a first electrode column 108a and a first electrode layer 108b. The first electrode layer 108b is an Al / Cr / Ti layer with a thickness of 2 μm, and the first electrode column 108a is an Al / Cr / Ti column with a height of 2 μm. The insulating structure 107 on the first electrode layer 108b includes an insulating column 107a and an insulating layer 107b. The insulating layer 107b is a SiO2 layer with a thickness of 1 μm, and the insulating column 107a is a SiO2 column with a height of 1 μm. The metal protection layer 106 on the insulating layer 107b is a Ti / Pt / Au / Cr / Pt / Ti layer with a thickness of 1.5 μm. The metal protection layer 106 surrounds 200 circular holes with a diameter of 15 μm, a current blocking layer 105 with a maximum thickness of 0.2 μm, an Ag layer with a thickness of 0.15 μm, and a Ni layer with a thickness of 0.001 μm as the metal reflection layer 104. On the metal reflection layer 104, there is a P-GaN layer with a thickness of 0.07 μm as the second gallium nitride layer 103, an InGaN / GaN multi-quantum well layer 102 with a thickness of 0.05 μm, and an N-GaN layer with a thickness of 3 μm as the first gallium nitride layer 101. The passivation layer 114 on the first gallium nitride layer 101 and the metal protection layer 106 is a SiO2 layer with a thickness of 0.2 μm. The second electrode 109, i.e., the P electrode, on the metal protection layer 106 is made of a Cr / Al / Ti / Pt / Au material with a thickness of 3.2 μm.

[0104] The preparation method of the above vertical structure LED chip 10 includes the following steps:

[0105] 1) Use MOCVD epitaxial technology to grow a buffer layer, a first gallium nitride layer 101 (n-GaN layer), an InGaN / GaN multi-quantum well layer 102, and a second gallium nitride layer 103 (p-GaN layer) on the substrate to be bonded, forming an LED epitaxial wafer with an epitaxial layer.

[0106] Then, the obtained LED epitaxial wafer is successively placed in organic cleaning tanks containing acetone and isopropyl acetone for 5 minutes each, then placed in a deionized water cleaning tank for 10 minutes, then placed in an acid cleaning tank, ultrasonically cleaned in SPM (a mixed solution of H2SO4, H2O2, and H2O) for 10 minutes, and then placed in a deionized water cleaning tank for 10 minutes. Finally, the LED epitaxial wafer is placed in a spin dryer to spin dry, and hot N2 is added to blow dry.

[0107] 2) After step 1), use photolithography to fabricate the Mark points and the insulating post patterns, and perform inductively coupled plasma etching on the epitaxial wafer with an etching depth of 1000 nm - 1500 nm. After the etching is completed, use an organic stripping solution to clean off the photoresist.

[0108] 3) After step 2), use electron beam evaporation or sputtering to prepare the metal reflective layer 104. After the evaporation is completed, perform an annealing operation at an annealing temperature of 350 °C. During the process, nitrogen and oxygen need to be introduced (the gas flow rate can be adjusted according to the actual situation).

[0109] Then use photolithography to fabricate the pattern of the metal reflective layer 104. Coat the photoresist onto the preset metal reflective layer 104 pattern to protect the pattern, and then use a mixed solution of ammonia water + hydrogen peroxide + water to chemically etch the metal reflective layer 104. Finally, use an organic stripping solution to clean off the photoresist.

[0110] 4) After step 3), use chemical vapor deposition to fabricate the current blocking layer 105, and use photolithography to fabricate the pattern of the current blocking layer 105. Coat the photoresist onto the preset current blocking layer 105 pattern to protect the pattern and perform inductively coupled plasma etching. Finally, use an organic stripping solution to clean off the photoresist.

[0111] 5) After step 4), use photolithography to fabricate the pattern of the metal protective layer 106. Coat the photoresist onto the preset metal protective layer 106 pattern to protect the pattern, and then use electron beam evaporation or sputtering to prepare the metal protective layer 106. Remove the excess metal and photoresist through a lift-off operation.

[0112] 6) After step 5), use chemical vapor deposition to fabricate the insulating post 107a and the insulating layer 107b, and use photolithography to fabricate the pattern of the insulating layer 107b. Coat the photoresist onto the preset insulating layer 107b pattern to protect the pattern, and etch the pattern with BOE. Finally, use an organic stripping solution to clean off the photoresist.

[0113] 7) On the LED epitaxial wafer obtained in step 6), use electron beam evaporation or sputtering to fabricate the first electrode post 108a (N electrode post), the first electrode layer 108b (N electrode layer), the blocking layer 113, and the bonding layer 112.

[0114] 8) Use electron beam evaporation or sputtering to fabricate the bonding layer 111 on the substrate layer.

[0115] 9) Align and bond the bonding layer 112 obtained after step 7) and the bonding layer 111 obtained after step 8) using a Bonding machine.

[0116] 10) After step 9), perform grinding and thinning to remove most of the thickness of the bonding substrate layer, then perform chemical etching, and finally use inductively coupled plasma etching to remove the remaining bonding substrate layer and buffer layer;

[0117] 11) Use an aqueous solution of KOH to roughen the surface of the first gallium nitride material layer obtained in step 10); wherein, the percentage concentration of the KOH aqueous solution is 0.05%, and the temperature is 70 °C;

[0118] 12) After the treatment in step 11), use photolithography to fabricate an LED pattern. The light-emitting surface pattern epitaxial layer will be protected by photoresist. Then, use a phosphoric acid solution at 120 °C to etch the wafer. The epitaxial layer in the patterned area protected by photoresist will not be etched, while the epitaxial layer in the patterned area without photoresist protection will be completely etched away. The remaining patterned area is the final light-emitting surface pattern to obtain an LED light-emitting surface chip;

[0119] 13) Deposit a passivation layer 114 on the surface of the LED chip obtained in step 12) using chemical vapor deposition, use photolithography to fabricate a second electrode 109 (P electrode) pattern, and perform BOE wet etching on the passivation layer 114 at the second electrode (P electrode) pattern to expose the metal protection metal layer in the electrode pattern area;

[0120] 14) Fabricate a second electrode 109 P electrode on the LED chip obtained in step 13) using electron beam evaporation or sputtering, and use the method of soaking in acetone and peeling off the blue film to remove the metal in the area other than the second electrode 109 (P electrode) to obtain a vertical structure LED chip 10.

[0121] Example 2

[0122] The difference from Example 1 is that the number of round holes in the current blocking layer is reduced from 200 to 150, and the preparation method is exactly the same as that in Example 1, only the photomask corresponding to the opening of the current blocking layer needs to be replaced.

[0123] Comparative Example 1

[0124] 1) Remove the current blocking layer under the metal reflective layer of the chip in the example, and directly contact the lower part of the metal reflective layer with the upper part of the metal protection layer (the LED chip structure of the comparative example is as Figure 4 shown).

[0125] 2) From bottom to top, it includes in sequence: a substrate layer, a bonding layer, a bonding layer, a blocking layer, an N electrode layer, an insulating layer, a metal protection layer, a metal reflective layer, a p-GaN layer, an InGaN / GaN multi-quantum well layer, an n-GaN layer, a passivation layer, and a P electrode

[0126] 3) The preparation method is as follows:

[0127] 1. Perform the same operations as in steps 1), 2), and 3) of Example 1 to fabricate an n-GaN layer, an InGaN / GaN multiple quantum well layer, a p-GaN layer, a MARK point, an N electrode hole, and a metal reflection layer;

[0128] 2. Perform the same operations as in steps 5), 6), 7), 8), 9), 10), 11), 12), 13), and 14) of Example 1 to fabricate a metal protection layer, an insulating layer, an N electrode layer, a barrier layer, a bonding layer, an adhesive layer, a light-emitting surface chip, a passivation layer, and a P electrode;

[0129] Experimental verification

[0130] Test and measure the luminous power and luminous area of the LED chips in the examples and comparative examples, and calculate the luminous efficiency. The specific experimental data are shown in the following table:

[0131] Table 1 Optical data of the LED chips in the examples and comparative examples

[0132]

[0133] As can be seen from Table 1, the luminous power, luminous area, and luminous efficiency of the vertical structure LED chips in the examples are all greater than those in the comparative examples, indicating that under the same luminous area, the LED lamps using this vertical structure LED chip have higher luminous flux, better current distribution, can effectively improve phenomena such as the dark area at the far end of the LED chip electrode, are more conducive to the optical path design in the downstream of the industrial chain, and have greater competitiveness in application fields with special requirements for the luminous spot.

[0134] The technical features of the above examples can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above examples are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered to be within the scope described in this specification.

[0135] The above-described examples only represent several implementation manners of the present application, which are convenient for understanding the technical solutions of the present application specifically and in detail, but should not be construed as a limitation on the scope of patent protection of the application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. It should be understood that the technical solutions obtained by those skilled in the art through logical analysis, reasoning, or limited experiments based on the technical solutions provided in the present application are all within the protection scope of the appended claims of the present application. Therefore, the protection scope of the patent of the present application should be subject to the content of the appended claims, and the specification and drawings can be used to explain the content of the claims.

Claims

1. A method for preparing a vertical structure LED chip, characterized in that, It includes the following steps: S10: Sequentially form a first gallium nitride material layer, a multi-quantum well material layer, and a second gallium nitride material layer which are stacked on the substrate to be bonded, and etch from the second gallium nitride material layer to the first gallium nitride material layer according to the preset insulating post positions; S20: Sequentially form a metal reflective material layer and a current blocking material layer on the second gallium nitride material layer, etch the metal reflective material layer and the current blocking material layer at the preset insulating post positions, and discontinuously etch a plurality of round holes on the current blocking material layer until the metal reflective material layer is exposed to prepare a metal reflective layer and a current blocking layer; S30: Form a metal protective material layer on the current blocking layer, etch the metal protective material layer at the preset insulating post positions to form a metal protective layer surrounding the metal reflective layer and the current blocking layer; S40: Fill insulating post materials at the preset insulating post positions to prepare insulating posts, and form an insulating material layer on the metal protective layer and the insulating posts; S50: Etch from the insulating material layer to the first gallium nitride material layer according to the preset first electrode post positions, fill first electrode post materials at the preset first electrode post positions to prepare a first electrode post and an insulating layer, and form a first electrode material layer on the insulating layer and the first electrode post to prepare a first electrode layer; S60: Remove the substrate to be bonded; S70: Remove the gallium nitride material on the first gallium nitride material layer except at the preset first gallium nitride layer positions, remove the multi-quantum well material on the multi-quantum well material layer except at the preset multi-quantum well layer positions, and remove the gallium nitride material on the second gallium nitride material layer except at the preset second gallium nitride layer positions to prepare a first gallium nitride layer, a multi-quantum well layer, and a second gallium nitride layer, wherein the widths of the first gallium nitride layer, the multi-quantum well layer, and the second gallium nitride layer are the same, and are greater than the width of the metal reflective layer and less than the width of the metal protective layer; S80: Form a second electrode on the side of the metal protective layer away from the insulating layer.

2. The manufacturing method of the vertical structure LED chip according to claim 1, characterized in that In step S10, before forming the first gallium nitride material layer on the substrate to be bonded, it further includes: Form a buffer layer on the substrate to be bonded; The first gallium nitride material layer is formed on the buffer layer.

3. The manufacturing method of the vertical structure LED chip as described in claim 1, characterized in that, After step S50 and before step S60, it further includes: Sequentially form a barrier layer and a bonding layer on the first electrode layer, provide a substrate with a bonding layer, and bond the bonding layer and the bonding layer.

4. The manufacturing method of the vertical structure LED chip as described in claim 1, characterized in that, Forming a second electrode on the side of the metal protective layer away from the insulating layer includes the following steps: Form a passivation layer on the first gallium nitride layer and the metal protective layer; Etch the preset second electrode positions on the passivation layer, and fill second electrode materials into the preset second electrode positions to form the second electrode, and the second electrode is in contact with the metal protective layer.

5. The manufacturing method of the vertical structure LED chip according to any one of claims 1 to 4, characterized in that, After step S60 and before step S70, it further includes a step of roughening the surface of the first gallium nitride material layer.

6. The manufacturing method of the vertical structure LED chip according to claim 1, characterized in that Discontinuously etch a plurality of round holes with a radius of 3 μm to 10 μm on the current blocking material layer.

7. The method for preparing a vertical structure LED chip according to claim 1 or 6, characterized in that, Among the multiple round holes etched discontinuously on the current blocking material layer, the distance between the centers of two adjacent round holes is 15 μm to 50 μm.

8. A vertical structure LED chip, characterized in that, Prepared by the preparation method according to any one of claims 1 to 7.

9. A light-emitting device, characterized in that, Comprising the vertical structure LED chip as claimed in claim 8.

10. A display device, characterized in that, Including: A circuit board and the light emitting device as claimed in claim 9, wherein the light emitting device is electrically connected to the circuit board through the first electrode and the second electrode of the vertical structure LED chip.

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