Method and system for constructing a notepad cache architecture based on a spatially reconfigurable array

Abstract

This invention provides a method and system for constructing a note-based cache architecture based on a spatially reconfigurable array, comprising: employing column address remapping for tasks with arbitrary granularity; partitioning and storing multiple arrays with different memory access steps, and using stream and array binding for concurrent access of multiple arrays; using static configuration to reduce configuration frequency, and using configuration parameters for address translation. This invention achieves zero waste of on-chip memory and conflict-free interaction between the computing array, DDR, and on-chip memory through a lightweight, scalable, and parameterized column address remapping mechanism. Based on the characteristics of parallel memory access of multiple arrays with varying step sizes, this invention organizes the memory access process of multiple arrays in a stream manner, and achieves concurrent, conflict-free access of multiple arrays through on-chip partitioning and the conversion between logical and physical address spaces.

Description

Technical Field

[0001] This invention relates to the field of on-chip caching technology for reconfigurable arrays, specifically to a method and system for constructing a note-based caching architecture based on spatially reconfigurable arrays, and more particularly to a note-based caching architecture for computationally intensive applications based on spatially reconfigurable arrays. Background Technology

[0002] Coarse-grained reconfigurable arrays (CGRAs) are a new type of processor that adapts to different computing tasks and leverages the high efficiency of data flow by reconfiguring the data flow through configuration. They are characterized by versatility and high computing power. CGRAs can maintain the same order of magnitude of computing power as application-specific integrated circuits (ASICs) or, like field-programmable gate arrays (FPGAs), adapt to different computing tasks through reconfiguration, combining high computing power and versatility. CGRAs are configured before executing computing tasks, setting the computational pattern and layout of the data flow into the array. After static configuration, the computing array performs computation and memory access according to the configured process.

[0003] Coarse-grained reconfigurable arrays (CGRAs) refer to arrays where the basic unit of data processing has a wide range of granularity, commonly 32 bits, corresponding to the INT32 and FP32 data types in algorithms. Due to their high computing power and versatility, CGRAs can handle both computationally intensive and memory-intensive application algorithms. Because of the high bandwidth requirements resulting from high computing power, a high-performance, high-throughput on-chip cache system is essential.

[0004] In the field of general-purpose processors, on-chip caches are widely used due to their ease of use and software transparency. Caches use global addresses and indirect addressing, requiring address translation. Furthermore, to determine if data is in the cache, a tag comparison process is needed. If the comparison fails, a cache miss occurs, and the data is retrieved from main memory, often taking dozens of cycles. In set-associative caches, after tag comparison, data from multiple sets is retrieved and compared, with a selector choosing the correct result. To achieve high bandwidth, caches often employ a multi-bank design, dividing the cache into multiple banks, each capable of independently responding to access requests. However, if data at different addresses in the same bank is requested simultaneously, a bank conflict occurs, requiring multiple cycles to process all requests for that bank. Due to potential bank conflicts and cache misses, it is difficult for the processor to return the data it wants to access within a specific timeframe. Coarse-grained reconfigurable architecture is a design with highly coupled computation and memory access. The computation unit can only start the operation after the memory access unit has provided the data. If a bank conflict or cache miss occurs during operation, the computation array can only pause and wait for the memory access unit, which will cause a significant performance loss.

[0005] Due to the highly coupled compute-memory access characteristics of reconfigurable arrays and the demand for high data throughput, a programmable, programmer-managed on-chip cache system was proposed. Scratchpads are used in GPUs, some real-time systems, and accelerators designed by NVIDIA. These scratchpads allow for explicit specification of data location via software. Explicit data movement ensures that data remains on-chip, preventing data loss and eliminating the need for tag matching, thus reducing circuitry and power consumption. This saves approximately 34% of area, allowing for the design of larger SRAM. However, scratchpads use an independent address space, and there is no hardware to handle address mapping between the scratchpad and main memory; explicit data movement is necessary, leading to unnecessary power consumption.

[0006] Of course, programmable temporary registers can also reduce bank conflicts during data access to some extent. Taking shared memory on a GPU as an example, shared memory can be regarded as a multi-bank SRAM, with data being moved from main memory to shared memory in parallel through multiple streams. When the processor core encounters a bank conflict while accessing data, memory padding can be used to modify the original data layout by adding some empty data positions to the original data. This causes the originally overlapping access requests to be transferred to different banks, thus avoiding bank conflicts. The advantage of this is that it provides an easy-to-program way to describe the data movement process by allocating a larger array space for explicit data movement. However, using empty padding data to move the original data leads to a waste of SRAM space. Moreover, the method of resolving bank conflicts using memory padding is not flexible, because memory padding only considers bank conflicts initiated by the processor and does not consider the process of writing from main memory to shared memory, where bank conflicts may also occur.

[0007] Data hit rate, bank conflict rate in multi-bank design, address translation method, SRAM space utilization, and cache control logic size are all major factors affecting the performance of on-chip cache systems. Among them, data hit rate and bank conflict rate determine the performance of reconfigurable arrays to a greater extent.

[0008] Heterogeneous processors like reconfigurable processors face challenges such as high data throughput and strong coupling between computation and memory access. Traditional caches struggle to provide efficient data throughput, and bank conflicts and missing data cause memory access latency, making it difficult to deliver data to the array in a timely manner. Furthermore, cache tag matching and multiplexing waste significant power and area. Existing note-based caching solutions eliminate missing data through prefetching and reduce bank conflicts through memory padding. However, this approach only addresses conflicts in on-chip memory access by the compute array, neglecting conflicts in DRAM read / write operations. Secondly, it is limited by idempotent hardware resources, leading to access conflicts or even greater resource waste when on-chip space allocation involves non-idempotent task partitioning. Finally, it cannot handle access conflicts caused by varying stride sizes in multi-array accesses. Summary of the Invention

[0009] To address the shortcomings of existing technologies, the purpose of this invention is to provide a method and system for constructing a note-based caching architecture based on a spatially reconfigurable array.

[0010] The present invention provides a method for constructing a note-style cache architecture based on a spatially reconfigurable array, comprising: employing column address remapping for tasks with arbitrary granularity; partitioning and storing multiple arrays with different memory access steps, and using stream and array binding for concurrent access of multiple arrays; using static configuration to reduce configuration frequency, and using configuration parameters for address translation.

[0011] Preferably, the column address remapping method involves dividing the data into blocks, with data within each block sharing an offset parameter, and the addresses accessed between blocks being staggered by offsets.

[0012] Preferably, by analyzing and summarizing the strafing characteristics of the application, corresponding block partitioning strategies and address offset strategies are designed for non-power-2 strafing, variable power-2 strafing, and other strafing.

[0013] Preferably, the array is partitioned for storage, and concurrent access to multiple arrays is achieved through stream and array binding, including:

[0014] The regular arrays with different memory access characteristics are stored in SPM in partitions. Partitioning is achieved by mapping from logical space to physical space. The memory access from the processor / DRAM end to a partition on the chip is defined as a stream. Memory access is organized in a stream manner by on-chip partitioning. Only one array is accessed within a partition to ensure that the access between arrays does not overlap.

[0015] Preferably, a static configuration method is used, which employs configuration parameters to achieve address translation, including: writing a static configuration at the start of the computing task to reduce the configuration frequency, rearranging the data through prefetching, and using the same configuration for processor-side memory access during the computing task to achieve configuration sharing.

[0016] The present invention provides a note-based caching architecture construction system based on a spatially reconfigurable array, comprising: employing column address remapping for tasks with arbitrary granularity; partitioning and storing multiple arrays with different memory access steps, and using stream and array binding for concurrent access of multiple arrays; using static configuration to reduce configuration frequency, and using configuration parameters for address translation.

[0017] Preferably, the column address remapping method involves dividing the data into blocks, with data within each block sharing an offset parameter, and the addresses accessed between blocks being staggered by offsets.

[0018] Preferably, by analyzing and summarizing the strafing characteristics of the application, corresponding block partitioning strategies and address offset strategies are designed for non-power-2 strafing, variable power-2 strafing, and other strafing.

[0019] Preferably, the array is partitioned for storage, and concurrent access to multiple arrays is achieved through stream and array binding, including:

[0020] The regular arrays with different memory access characteristics are stored in SPM in partitions. Partitioning is achieved by mapping from logical space to physical space. The memory access from the processor / DRAM end to a partition on the chip is defined as a stream. Memory access is organized in a stream manner by on-chip partitioning. Only one array is accessed within a partition to ensure that the access between arrays does not overlap.

[0021] According to the present invention, a reconfigurable processor includes a note-style cache architecture, wherein the note-style cache architecture is designed using the above-described method for constructing a note-style cache architecture based on a spatially reconfigurable array.

[0022] Compared with the prior art, the present invention has the following beneficial effects:

[0023] 1. This invention achieves the effect of no waste of on-chip memory and no conflict in the interaction between the computing array and DDR and the on-chip memory through a lightweight, scalable, and parameterized column address remapping mechanism.

[0024] 2. Based on the characteristics of multiple arrays accessing memory in parallel and with varying step sizes, this invention organizes the memory access process of multiple arrays in a stream manner, and achieves the effect of concurrent and conflict-free access of multiple arrays through on-chip partitioning and conversion between logical and physical address spaces. Attached Figure Description

[0025] Other features, objects, and advantages of the present invention will become more apparent from the following detailed description of non-limiting embodiments with reference to the accompanying drawings:

[0026] Figure 1 This is a schematic diagram of a typical heterogeneous reconfigurable array;

[0027] Figure 2 This is a schematic diagram illustrating the partitioned storage of data in SPM in this invention;

[0028] Figure 3 This is a diagram of the on-chip configurable note-style cache structure of the present invention;

[0029] Figure 4 This is a schematic diagram of the address translation logic of the present invention;

[0030] Figure 5 The number of execution cycles for different applications of this invention under Cache and configurable note-style caching;

[0031] Figure 6 This is a schematic diagram illustrating how the present invention resolves bank conflicts in processor access and DRAM access through address remapping. Detailed Implementation

[0032] The present invention will now be described in detail with reference to specific embodiments. These embodiments will help those skilled in the art to further understand the present invention, but do not limit the invention in any way. It should be noted that those skilled in the art can make several changes and improvements without departing from the concept of the present invention. These all fall within the protection scope of the present invention.

[0033] Example 1:

[0034] This invention provides a method for constructing a note-style cache architecture based on spatially reconfigurable arrays, specifically for typical coarse-grained reconfigurable arrays. Figure 1 This diagram illustrates a single array, where PE represents the compute unit and LSE represents the address generation unit. Before executing a computation task, the array uses a configure controller to write the functional configurations and interconnection configurations of all compute units and address generation units in a scan chain. This process is equivalent to hardening the algorithm onto the circuitry; after configuration, a fixed data path is formed. When a computation task begins, some compute units control the address generation unit to generate address access requests. These requests are sent to the on-chip cache, and the obtained data is returned to the address generation unit, which then passes the data to the remaining compute units. Data accessed by the memory access unit is directly passed to the compute array, creating a strong coupling between the two.

[0035] This invention is based on Figure 1 The coarse-grained reconfigurable array shown is the basic design, on which different types of applications can be mapped. The on-chip storage system designed in this invention can solve the problem of bank collisions that cannot be completely eliminated in traditional note-taking memories, and also solve problems such as data loss in cache. Data rearrangement is achieved by configuring this on-chip storage system, using different configurations for different types of applications.

[0036] This invention provides a method for constructing a Scratchpad Memory (SPM) architecture. SPM organizes the entire memory access process in a stream manner, and after statically configuring the parameters of the entire stream, no modification is required at runtime.

[0037] Because the coarse-grained reconfigurable processor (SPM) is a spatial architecture, once configured, all memory accesses required for the task will begin. This means it will simultaneously access four arrays: arrayA, arrayB, arrayC, and arrayD. To prevent overlap between arrays, they need to be partitioned for storage. A diagram illustrating data storage in the SPM is shown below. Figure 2 As shown, the SPM space is partitioned, with each partition occupying a space of P banks in width and Q rows in height. Because the minimum width of the partitions is limited to ensure full utilization of DRAM memory access bandwidth during DRAM read / write operations on each SPM partition, there is a constraint on the required minimum partition width.

[0038] SPM structural diagram as follows: Figure 2 As shown in the diagram, the original LSEs are organized as streams. A partition accessing the SPM from the processor / DRAM side is defined as a stream, and the stream contains several LSEs. This schematic SPM structure diagram only has four streams and corresponding configurable parameters, namely Config0 to 3. Each LSE issues an address request for the logical space. Each LSE is connected to an address translation logic. The address translation logic selects a set of corresponding configurations to read based on its stream, and uses the configured parameters to translate from logical address to SPM physical address. Finally, through an interconnect network (Cross bar), the requests for the corresponding banks are sequentially sent to different banks. The address translation logic reads the configuration at the start of a task and reads the new task after the task is completed, resulting in fewer register read / write operations and correspondingly lower energy consumption.

[0039] The address translation logic is responsible for converting conflicting address requests into conflict-free address requests. Before the computation task begins, the address translation logic reads in the corresponding configuration parameters, as shown in Table 1. The gray areas represent pre-configured parameters, which are related to the application's memory access characteristics. The structure of the address translation logic is as follows: Figure 4 As shown, the address translation logic reads the three-dimensional logical addresses in0 to in2. In each partition of the SPM, several rows of data are organized into data blocks. The address translation logic obtains the location of the corresponding data block from the row address, and adds the offset parameter of the data block to the original column address of the data block to obtain the logical column address of the SPM. The logical row address of the SPM is obtained by multiplying the data block number by the number of rows occupied by the data block and adding the first few bits of the offset within the block. Finally, the logical row and column addresses are added to the physical starting row and column address of the SPM partition to obtain the final physical row and column address.

[0040] Table 1 Summary of parameters in statically explicit configurable note-style cache

[0041]

[0042] The SPM accepts addresses up to three-dimensional logical addresses. Originally, the LSE was responsible for converting three-dimensional addresses into one-dimensional addresses. Moreover, since the LSE can only implement one MAC, a PE is needed to assist in the calculation during the conversion process. The SPM converts three-dimensional addresses into two-dimensional physical addresses through address translation logic, freeing up the functions of the LSE and some of the PE, thereby increasing the computing power of the PE on the array.

[0043] Meanwhile, during prefetching and write-back, SPM can reuse the configuration and logic from the computation process after providing the DRAM base address and the amount of data accessed. This means that the processor and DRAM can share the same configuration parameters and data path when accessing the same array, significantly reducing the number of configuration parameters. Utilizing the burst characteristics of DRAM, data is prefetched into SPM and address rearranged. Finally, the rearranged results are sequentially written back to DRAM via write-back. Because of this design, there are no bank conflicts when DRAM accesses SPM, thus fully utilizing the DRAM's memory bandwidth and reducing memory wall limitations.

[0044] In summary, the technical features of the newly proposed on-chip configurable note-style cache are mainly reflected in the following two points:

[0045] 1. For task partitioning of arbitrary granularity, lightweight column address offset translation is used to replace memory padding. Without wasting on-chip memory space, there are no read / write conflicts when the computing array and DDR interact with on-chip data. The average response time of read / write requests is short, and efficient pipelining is achieved.

[0046] 2. Partition multiple structured arrays with different access steps, bind the stream and the array, and support different address translation rules through the configuration parameters on the stream to achieve the effect of no conflict when multiple arrays are accessed concurrently;

[0047] 3. By using static configuration, low-frequency configuration is achieved, reducing configuration energy consumption. By using in-stream multiplexing parameters, processor memory access and DRAM memory access multiplexing parameters, address translation is achieved using low-overhead, lightweight configuration parameters, and on-chip configurable note-style cache is built.

[0048] The technical advantages of this invention will be verified through comparative experiments below.

[0049] This invention primarily proposes an explicit, statically configurable, note-based on-chip memory architecture for coarse-grained reconfigurable arrays. Comparison 1: Applications such as convolution, general matrix multiplication, and fast Fourier transform are mapped onto coarse-grained reconfigurable array processors using the proposed 16-bank explicit statically configurable note-based on-chip memory architecture and a 16-bank cache, obtaining the number of execution cycles for algorithms on different on-chip memory access architectures. Comparison 2: The proposed statically configurable note-based on-chip memory architecture, cache, and shared memory using memory padding are compared to demonstrate the technical effects of this invention.

[0050] The test cases in this paper include several typical convolutional layers in YOLOv3-tiny, and the parameters of the convolutional layers are shown in Table 2. Dense general matrix multiplication calculates the multiplication of two matrices with a width and height of 512, processing one block of the matrix in a single task, executed in parallel through multiple arrays. Fast Fourier Transform is tested with a 256-channel, 1D, 1024-point configuration.

[0051] Table 2 Typical Convolutional Layer Sizes

[0052]

[0053] Since conventional caches lack a prefetching mechanism, data loss occurs on the first access, which has a severe impact on performance. Therefore, the cache compared in this paper incorporates prefetching and write-back mechanisms, mainly to compare the performance improvement brought by the SPM proposed in this invention in eliminating bank conflict rate under a multi-bank design.

[0054] The technical effect of the present invention is demonstrated by the execution time: using the above configuration method, this paper uses a periodically accurate simulator with an error rate of less than 5% to simulate the execution time of different applications using cache and using configurable note-based memory. Figure 5 The paper presents a comparison of execution time for different applications using the caching method and the configurable note-based caching method proposed in this invention. According to statistics, there is an average performance improvement of about 20% in convolution, about 15% for general matrix multiplication, and 2.35 times for Fast Fourier Transform. This shows that the configurable note-based caching method proposed in this invention has a significant effect on eliminating bank conflicts, and the performance improvement is greater for applications with severe memory access conflicts.

[0055] The technical features of this invention are highlighted by comparing it with other architectures: Cache interacts with DRAM using cache lines, so there are no bank conflicts under any circumstances. However, bank conflicts often occur under various strafing access scenarios, resulting in poor performance. Shared Memory resolves bank conflicts through memory padding, but this only addresses single strafing accesses. When the strafing is variable, there will be processor-to-on-chip cache conflicts. Furthermore, in strafing scenarios other than powers of 2, padding causes consecutive data to be split across different lines, leading to bank conflicts in DRAM access. Additionally, memory padding results in some wasted on-chip space, leading to low space utilization. The patent proposed in this paper achieves zero memory access conflicts under various strafing scenarios by using data block segmentation and inter-block offsets (details are shown in Section 6), while also not wasting on-chip space, as shown in Table 3.

[0056] Table 3 Comparison between Cache, Shared Memory, and the patent in this paper.

[0057]

[0058] Example 2

[0059] The core technologies of the configurable note-taking memory proposed in this invention mainly include: organizing address requests in a streaming manner, implementing static address remapping in an explicitly configurable way, and eliminating bank conflicts by dividing data into blocks and offsetting data blocks. Based on the memory access characteristics of different applications, corresponding data block division and data block offset schemes are proposed to solve the problem of bank conflicts.

[0060] The following three examples illustrate the universality of this invention.

[0061] like Figure 6 As shown, when using a system to compute convolution, assuming the width and height of the input feature image are both 6, and the image is stored in main memory in row-major order, the heterogeneous computing system's data flow needs to access the first four rows of the input feature image simultaneously, meaning the data access span is 6. For example... Figure 6As shown in (a), the image on the left illustrates the data layout in the cache and the data layout desired by the processor. With a traditional cache, data is moved to the cache, and its layout is the same as in main memory. However, the processor wants to access the first four rows of data, and it prefers the data to be organized in column-major order. It can be seen that the data layout desired by the processor conflicts with the data layout provided by the cache. Taking accessing data 3, 9, 15, 21 (the gray data in the image) as an example, that is, accessing the data in the third column of the first four rows, a bank conflict occurs between data 3 and data 15, and between data 9 and data 21 in the cache's data layout.

[0062] The right side of the diagram shows the data layout method proposed in this invention. With this step-by-step access method, it can be observed that when accessing data in the cache, data conflicts occur in pairs. The data is organized into a data block using three rows. The 0th data block remains unchanged, while the 1st data block is shifted one row to the right. Data exceeding the right boundary is padded to the original left boundary. Through this movement, requests for data 3, 9, 15, and 21 are offset to different banks, meaning there are no bank conflicts for this type of request. Simultaneously, it can be seen that when data is sequentially moved from main memory to SPM, taking consecutive data 4, 5, 6, and 7 as an example, they are distributed across four different banks. This means there are no bank conflicts during the process of reading data from main memory and writing it to SPM.

[0063] Based on this data layout, data is sequentially moved from main memory to SPM. No bank conflicts occur during the process of the processor accessing data in SPM with a span of 6. The multi-bank design has the highest memory access efficiency, and the latency of all data requests is very short. This ensures the execution of computation in a heterogeneous computing processor with strong coupling between computation and memory access.

[0064] When using a processor to compute the FFT, assuming the FFT contains only 32 data points, it iterates through these 32 points using a 5-layer butterfly algorithm. The FFT algorithm accesses two data points at a time, updating both. Assuming one unrolling operation is performed, allowing it to access four data points at a time, then the span of the first butterfly operation is 8, and the span of the second butterfly operation is 4. Figure 6 As shown in b), taking the access of data 2, 10, 18, 26 in the first butterfly calculation as an example, and the access of data 0, 4, 8, 12 in the second butterfly calculation as an example, when using a traditional cache, when accessing data 2, 10, 18, 26, all four data items are located at different addresses within the same bank, resulting in a bank conflict. Similarly, when accessing data 0, 4, 8, 12, a bank conflict also occurs.

[0065] Figure 6 (b) shows the data layout proposed in this invention. For the step-by-step access method with a stride of 8, we treat four rows of data as one data block, i.e., the first four rows are considered data block 0, and the last four rows are considered data block 1. Shifting data block 1 one grid to the right solves the problem. For the step-by-step access method with a stride of 4, we treat one row of data as one data block. We do not operate on data block 0, shift data block 1 one grid to the right, data block 2 two grids to the right, and data block 3 three grids to the right. Combining these two data shifting methods, with a smaller data block granularity as the benchmark, the corresponding number of grids moved is shown in the list. It can be seen that when accessing data 2, 10, 18, and 26, they are distributed in banks 2, 0, 3, and 1 respectively, with no bank conflicts. When accessing data 0, 4, 8, and 12, they are distributed in banks 0, 1, 2, and 3 respectively, with no bank conflicts. This data layout supports variable strides, and through off-address write-back (the processor accesses data with a stride of 8,4 and writes back with a stride of 4,2), bank conflicts are avoided in all butterfly computations. Furthermore, as shown in the diagram, data moved sequentially from main memory also falls on different banks, eliminating bank conflicts.

[0066] When computing stencil-jacobi with a processor, data access is not a simple step-by-step process. Suppose the template computes an 8×4 matrix whose elements are a sequence increasing from 0, and it accesses the data of the four points above, below, left, and right of a given element in the matrix at a time. For example... Figure 6 As shown in c), taking the data 1, 4, 6, and 9 surrounding data point 5 as an example, when using the data layout of the cache, a bank conflict occurs when accessing data 1 and 9, and the processor wants to access these four data in a way that does not involve bank conflicts.

[0067] Figure 6 (c) shows the data layout proposed in this invention, with two rows per data block. Data block 0 is not shifted, while data block 1 is shifted one grid to the right, and this cycle repeats for subsequent data blocks. This shifting method can be seen to stagger access to data 1 and data 9 by avoiding banks, and also stagger access to data 4 and 6 by avoiding banks. This achieves bank-free access to data 1, 4, 6, and 9. Furthermore, for data sequentially written from DRAM to SPM, taking 16, 17, 18, and 19 in the diagram as examples, the writing process also avoids bank conflicts.

[0068] Based on the aforementioned explicit address relocation methods, SPM supports arbitrary step access, typically using convolution and FFT, as well as special access methods like Stencil. A simple observation of address requests reveals a consistent pattern in data block partitioning and offset. Explicit address remapping based on this observed pattern ensures no bank conflicts during data migration to SPM and processor access to SPM. This explicit address remapping method offers excellent flexibility and scalability, supporting various memory access modes. Simultaneously, this scheme maximizes SPM's memory access efficiency. For heterogeneous processors with highly coupled computation and memory access, it reduces memory access latency and ensures latency consistency, significantly improving the computational performance of coarse-grained reconfigurable arrays. In summary, the explicit statically configurable note-based cache proposed in this invention maximizes cache memory access efficiency, reduces the response time for each memory access request, and improves the computational performance of coarse-grained reconfigurable arrays.

[0069] This invention provides a note-based caching architecture construction system based on spatially reconfigurable arrays, including: using column address remapping for tasks with arbitrary granularity; partitioning and storing multiple arrays with different memory access steps, and using stream and array binding for concurrent access of multiple arrays; using static configuration to reduce configuration frequency, and using configuration parameters for address translation.

[0070] The column address remapping method divides the data into blocks, with data within each block sharing an offset parameter, and addresses accessed between blocks being staggered through offsets. By analyzing and summarizing the strafing characteristics of the application, corresponding block division and address offset strategies are designed for non-power-2 strafing, variable power-2 strafing, and other strafing accesses.

[0071] Array partitioning and multi-array concurrent access via stream and array binding include: partitioning arrays with different memory access characteristics in SPM, implementing partitioning through mapping from logical space to physical space, defining memory access from the processor / DRAM side to an on-chip partition as a stream, organizing memory access through on-chip partitioning and stream-based methods, accessing only one array within a partition, and ensuring that access between arrays does not overlap.

[0072] The present invention also provides a reconfigurable processor, the reconfigurable processor comprising a note cache architecture, the note cache architecture being designed using the aforementioned note cache architecture construction method based on a spatially reconfigurable array.

[0073] Specific embodiments of the present invention have been described above. It should be understood that the present invention is not limited to the specific embodiments described above, and those skilled in the art can make various changes or modifications within the scope of the claims, which do not affect the essence of the present invention. Unless otherwise specified, the embodiments and features described in these embodiments can be arbitrarily combined with each other.

Claims

1. A method for constructing a note-based cache architecture based on a spatially reconfigurable array, characterized in that, include: For tasks with arbitrary granularity, column address remapping is employed; Multiple arrays with different memory access steps are partitioned and stored, and concurrent access to multiple arrays is achieved by binding streams and arrays; static configuration is used to reduce configuration frequency, and address translation is performed using configuration parameters; The column address remapping method uses data to be divided into blocks, with data within a block sharing an offset parameter, and the addresses accessed between blocks being staggered by offsets; Array partitioning and concurrent access to multiple arrays via stream and array binding include: The regular arrays with different memory access characteristics are stored in SPM in partitions. Partitioning is achieved by mapping from logical space to physical space. The memory access from the processor / DRAM end to a partition on the chip is defined as a stream. Memory access is organized in a stream manner by on-chip partitioning. Only one array is accessed within a partition to ensure that the access between arrays does not overlap.

2. The method for constructing a note-taking cache architecture based on a spatially reconfigurable array according to claim 1, characterized in that: By analyzing and summarizing the strafing characteristics of applications, corresponding block partitioning strategies and address offset strategies are designed for non-power-2 strafing, variable power-2 strafing, and other strafing.

3. The method for constructing a note-taking cache architecture based on a spatially reconfigurable array according to claim 1, characterized in that: Using static configuration, address translation is achieved through configuration parameters. This includes: writing static configuration at the start of the computation task to reduce configuration frequency; rearranging data through prefetching; and using the same configuration for processor-side memory access during the computation task to achieve configuration sharing.

4. A note-taking caching architecture construction system based on spatially reconfigurable arrays, characterized in that: include: For tasks with arbitrary granularity, column address remapping is employed; Multiple arrays with different memory access steps are partitioned and stored, and concurrent access to multiple arrays is achieved by binding streams and arrays; static configuration is used to reduce configuration frequency, and address translation is performed using configuration parameters; The column address remapping method uses data to be divided into blocks, with data within a block sharing an offset parameter, and the addresses accessed between blocks being staggered by offsets; Array partitioning and concurrent access to multiple arrays via stream and array binding include: The regular arrays with different memory access characteristics are stored in SPM in partitions. Partitioning is achieved by mapping from logical space to physical space. The memory access from the processor / DRAM end to a partition on the chip is defined as a stream. Memory access is organized in a stream manner by on-chip partitioning. Only one array is accessed within a partition to ensure that the access between arrays does not overlap.

5. The note-based caching architecture construction system based on spatially reconfigurable arrays according to claim 4, characterized in that: By analyzing and summarizing the strafing characteristics of applications, corresponding block partitioning strategies and address offset strategies are designed for non-power-2 strafing, variable power-2 strafing, and other strafing.

6. A reconfigurable processor, characterized in that: The reconfigurable processor includes a note-based cache architecture, which is designed using the note-based cache architecture construction method based on a spatially reconfigurable array as described in any one of claims 1-3.

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