Method for implementing a tapped shift register based on a dual-port RAM and related device
By designing a dual-port RAM read/write port, a single-line input and multi-line output tapped shift register was achieved, solving the problems of low development efficiency and poor portability in FPGAs, and improving the reliability and controllability of the tapped shift register.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHANDONG YUNHAI GUOCHUANG CLOUD COMPUTING EQUIP IND INNOVATION CENT CO LTD
- Filing Date
- 2022-09-09
- Publication Date
- 2026-07-07
AI Technical Summary
The development efficiency of tapped shift registers in existing FPGAs is low, and their portability and reliability are poor, making it difficult to achieve the function of single-line input and multi-line output.
A tapped shift register is implemented using dual-port RAM. Multiple lines of data are read through the read port, the oldest line is discarded, and the remaining data is combined as the input to the write port to achieve single-line input and multi-line output.
This improved the development efficiency and reliability of tapped shift registers, enabling independent and controllable secondary design and porting.
Smart Images
Figure CN115640048B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of hardware development technology, and in particular to a method for implementing a tapped shift register based on dual-port RAM, and a data processing method, apparatus, electronic device, and computer-readable storage medium based on dual-port RAM. Background Technology
[0002] Currently, when processing image, video, or other similar image / video array data using FPGAs (Field Programmable Gate Arrays), it may be necessary to perform calculations or processing on data within the same column. For example, in the field of image and video processing, image algorithms are frequently used, and these algorithms often require processing data from the same column across several rows. However, image and video data streams are typically input line by line. Therefore, a module is needed to convert the original single-line input into multi-line input, i.e., to achieve single-line input and multi-line output functionality. In related technologies, tapped shift registers, in addition to possessing the first-in, first-out (FIFO) characteristic of ordinary shift registers, can also output intermediate data of the shift chain to the port in advance while performing normal shifting. With its single-ended input and multi-ended output characteristics, it can be used to implement this function.
[0003] However, for tapped shift registers, some FPGA series have dedicated macro function modules that can be called. But using these built-in function modules is often like a black box, with strong encapsulation, uncontrollable design code, and cannot be ported to other FPGA series. Other FPGA series do not have relevant modules available, requiring manual implementation of the function. Directly using hardware description languages for design results in relatively low coding efficiency, poor synthesis controllability, and often low performance.
[0004] Therefore, how to effectively improve the development efficiency of tapped shift registers while ensuring their portability and high reliability is a problem that urgently needs to be solved by those skilled in the art. Summary of the Invention
[0005] The purpose of this application is to provide a method for implementing a tapped shift register based on dual-port RAM. This method can effectively improve the development efficiency of tapped shift registers, while also ensuring the portability and high reliability of tapped shift registers. Another purpose of this application is to provide a data processing method, apparatus, electronic device, and computer-readable storage medium based on dual-port RAM, all of which have the above-mentioned beneficial effects.
[0006] In a first aspect, this application provides a method for implementing a tapped shift register based on a dual-port RAM. The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line is used to support a multi-line cache mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The method includes:
[0007] The row data of the row to which the current row data belongs in the data to be processed is taken as the read data of the read port;
[0008] The row with the smallest row number in the read data is discarded, and the other rows in the read data are combined with the current row data to form the write data of the write port;
[0009] The read data is used as the output data of the tap shift register, and the current row data is used as the input data of the tap shift register.
[0010] Optionally, the method for implementing a tapped shift register based on dual-port RAM further includes:
[0011] The read / write mode of the dual-port RAM is set to read-then-write mode.
[0012] Optionally, the column number of each target data in the written data is consistent with the column number of each target data in the read data, and the target data is the in-row data in the corresponding row data that passes through the write port or the read port.
[0013] Optionally, the dual-port RAM is located in the FPGA.
[0014] Secondly, this application also discloses a data processing method based on dual-port RAM, wherein the dual-port RAM includes a write port, a read port, and a preset number of cache lines, each cache line being used to support a multi-line cache mode, and the cache size of each cache line being consistent with the data size of each line of data in the data to be processed, the method comprising:
[0015] Before writing the current row data in the data to be processed through the write port, the row data of the row to which the current row data belongs is read through the read port for the previous preset number of rows; wherein, the read data of the read port is configured as the output data of the tap shift register;
[0016] The row with the smallest row number in the read data is discarded, and the current row data and the other rows in the read data are written through the write port; wherein, the current row data is configured as the input data of the tap shift register.
[0017] Optionally, the data processing method based on dual-port RAM further includes:
[0018] When target data is written to the current row of data through the write port, the current storage address of the target data in the dual-port RAM is determined;
[0019] When the current storage address is the highest storage address, the first storage address in the dual-port RAM is used as the storage address of the new target data.
[0020] Optionally, the data processing method based on dual-port RAM further includes:
[0021] When a valid signal for the target data is received, an enable signal is sent to the write port and the read port, so that the write port performs a data write operation according to the enable signal, and the read port performs a data read operation according to the enable signal.
[0022] Thirdly, this application also discloses a data processing device based on dual-port RAM, wherein the dual-port RAM includes a write port, a read port, and a preset number of cache lines, each cache line being used to support a multi-line cache mode, and the cache size of each cache line being consistent with the data size of each line of data in the data to be processed, the device comprising:
[0023] The output module is used to read the row data of the row to which the current row data belongs through the read port before writing the current row data in the data to be processed through the write port; wherein, the read data of the read port is configured as the output data of the tap shift register;
[0024] The input module is used to discard the row data with the smallest row number in the read data, and write the current row data and other rows data in the read data through the write port; wherein, the current row data is configured as the input data of the tap shift register.
[0025] Fourthly, this application also discloses an electronic device, comprising:
[0026] Memory, used to store computer programs;
[0027] A processor, configured to implement any of the data processing methods based on dual-port RAM as described above when executing the computer program.
[0028] Fifthly, this application also discloses a computer-readable storage medium storing a computer program, which, when executed by a processor, implements the steps of any of the data processing methods based on dual-port RAM as described above.
[0029] By applying the technical solution provided in this application, multi-line buffering is performed using a dual-port RAM (Random Access Memory). All data read from the dual-port RAM read port is used as the output data of the entire tap shift register. Simultaneously, the oldest row of read data is discarded, and the remaining rows are combined with the current row of data to be input into the dual-port RAM from the data to be processed, and used as the write data for the dual-port RAM write port. The current row of data is the input data of the tap shift register, and the row data of the row to which the current row of data belongs is the output data of the tap shift register. Thus, the single-line input and multi-line output function of the tap shift register is realized based on the dual-port RAM. This implementation method has high development efficiency and reliability, and the entire implementation process is autonomous and controllable, facilitating secondary design and portability. Attached Figure Description
[0030] To more clearly illustrate the technical solutions in the prior art and the embodiments of this application, the accompanying drawings used in the description of the prior art and the embodiments of this application will be briefly introduced below. Of course, the accompanying drawings described below with respect to the embodiments of this application are only a part of the embodiments in this application. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort, and such other drawings also fall within the protection scope of this application.
[0031] Figure 1 A flowchart illustrating a method for implementing a tapped shift register based on dual-port RAM, provided in this application;
[0032] Figure 2 A flowchart illustrating a data processing method based on dual-port RAM provided in this application;
[0033] Figure 3 A schematic diagram of the structure of a tapped shift register provided in this application;
[0034] Figure 4 A schematic diagram of a data processing device based on dual-port RAM provided in this application;
[0035] Figure 5 This is a schematic diagram of the structure of an electronic device provided in this application. Detailed Implementation
[0036] The core of this application is to provide a method for implementing a tapped shift register based on dual-port RAM. This method can effectively improve the development efficiency of tapped shift registers, while also ensuring the portability and high reliability of tapped shift registers. Another core aspect of this application is to provide a data processing method, apparatus, electronic device, and computer-readable storage medium based on dual-port RAM, all of which have the aforementioned beneficial effects.
[0037] To provide a clearer and more complete description of the technical solutions in the embodiments of this application, the technical solutions in the embodiments of this application will be described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this application without creative effort are within the scope of protection of this application.
[0038] This application provides a method for implementing a tapped shift register based on a dual-port RAM.
[0039] Please refer to Figure 1 , Figure 1 The present application provides a flowchart of a method for implementing a tapped shift register based on a dual-port RAM. The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line is used to support a multi-line cache mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The method for implementing a tapped shift register based on a dual-port RAM may include the following steps S101 to S103.
[0040] S101: Take the row data of the row to which the current row data belongs in the data to be processed as the read data of the read port;
[0041] First, a dual-port RAM is a random access memory with two ports: one for writing data and the other for reading data. These two ports can operate independently, performing read and write operations on the memory separately. Furthermore, the dual-port RAM includes a preset number of cache lines to support multi-line caching. One cache line can correspond to one line of data (input or output), and the size of each cache line is equal to the size of each line of data in the data to be processed. In other words, each cache line can store exactly one line of data to be processed, which is the data that needs to be processed using tapped shift registers and typically includes multiple lines of data. It is understood that the specific value of the preset number does not affect the implementation of this technical solution and can be determined by the actual performance of the dual-port RAM; this application does not limit it in this regard.
[0042] In one possible implementation, the dual-port RAM is located within the FPGA. Generally, the dual-port RAM can be located within the FPGA to support the FPGA in processing data in the same column across multiple rows of arrays.
[0043] Furthermore, this step aims to configure the data read from the read port. It should be noted that the tapped shift register based on the dual-port RAM is designed to perform computational processing on the data to be processed. Therefore, the data written through the write port must include each row of data from the data to be processed. Based on this, when a row of data (i.e., the current row) is about to be written through the write port, the row number of the current row can be determined first. Then, the row data of the row number preceding the current row number is used as the data read from the read port. Since the dual-port RAM includes a preset number of buffer rows, each buffer row is used to store one row of data.
[0044] For example, suppose a dual-port RAM has 3 cache lines. The current line of data belongs to the 5th line, which is the fifth line of data to be processed. Then, the data read through the read port is the first three lines of data of the fifth line, which are the second, third and fourth lines of data to be processed. Each line of data is transmitted through one cache line. Obviously, the number of lines of data in the read data corresponds to the number of cache lines in the dual-port RAM.
[0045] In one possible implementation, the method for implementing a tapped shift register based on dual-port RAM may further include setting the read / write mode of the dual-port RAM to a read-then-write mode.
[0046] This application aims to implement the read / write mode setting of a dual-port RAM, specifically a read-then-write mode, which also enables the output-then-input function of the tapped shift register. It is understood that when reading and writing operations are performed simultaneously on the same address of the dual-port RAM, parameters can be set to read-then-write, write-then-read, or other modes. Since reading and writing are always performed simultaneously on the same address, it can be set to read-then-write mode. Therefore, when a row of data is about to be written from the write port, the read port can first read a preset number of rows of data cached in the dual-port RAM before that row.
[0047] In one possible implementation, the column number of each target data in the written data is the same as the column number of each target data in the read data, and the target data is the in-row data in the corresponding row data passed through the write port or read port.
[0048] It's understandable that for a given set of data to be processed, each row contains multiple rows of data, and each row of data corresponds to a column in the data being processed. Therefore, when row data is written through the write port or read through the read port, it is written and read in units of row data. Based on this, the write and read ports can be configured as follows: the column number of each target data in the written data should be consistent with the column number of each target data in the read data. That is, when the write port writes row data to a certain column number, the read port will correspondingly read the same number of row data. For example, if the write port is about to write data to the fifth row, fourth column, then the read port will read the second row, fourth column, third row, fourth column, and fourth row, fourth column.
[0049] S102: Discard the row data with the smallest row number in the read data, and combine the other rows of data in the read data with the current row data to form the write data of the write port;
[0050] This step aims to configure the data to be written to the write port. As mentioned above, the data read from the read port is the row data of the row number preceding the current row in the data to be processed. At this time, the row data with the smallest row number in the read data is discarded. It can be understood that the row data with the smallest row number in the read data is also the oldest row data. Further, the other rows in the read data are combined with the aforementioned current row data to obtain the data to be written to the write port. It should be noted that the current row data is written as the first row data in the write data.
[0051] Based on the above example, the data read from the read port includes the second, third, and fourth rows of data in the data to be processed. At this time, the row with the smallest row number is the second row. Therefore, the second row can be deleted, and the third and fourth rows can be combined with the current row, i.e., the fifth row, to form the write data. The fifth row is used as the first row of the write data, and the third and fourth rows are used as the third and second rows of the write data, respectively. Similarly, the row number in the write data corresponds to the number of cache rows in the dual-port RAM.
[0052] S103: Use the read data as the output data of the tap shift register, and use the current row data as the input data of the tap shift register.
[0053] This step aims to configure a tapped shift register based on a dual-port RAM. The main point is to use all the data read from the read port of the dual-port RAM as the output data of the tapped shift register, and use the current row of data to be written to the write port of the dual-port RAM as the input data of the tapped shift register. Thus, the single-row input and multi-row output functions of the tapped shift register are realized based on the dual-port RAM, that is, the tapped shift register is implemented based on the dual-port RAM.
[0054] As can be seen, the method for implementing a tapped shift register based on dual-port RAM provided in this application uses dual-port RAM for multi-line buffering. All data read from the dual-port RAM read port is used as the output data of the entire tapped shift register. At the same time, the oldest row of data is discarded, and the remaining rows of data are combined with the current row of data to be input into the dual-port RAM from the data to be processed, and used as the write data of the dual-port RAM write port. The current row of data is the input data of the tapped shift register, and the row of data of the row to which the current row of data belongs is the output data of the tapped shift register. Thus, the function of single-line input and multi-line output of the tapped shift register is realized based on dual-port RAM. This implementation method has high development efficiency and reliability, and the entire implementation process is autonomous and controllable, which is convenient for secondary design and porting.
[0055] This application provides a data processing method based on dual-port RAM.
[0056] Please refer to Figure 2 , Figure 2 The present application provides a flowchart of a data processing method based on dual-port RAM. The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line is used to support a multi-line cache mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The data processing method based on dual-port RAM may include the following S201 and S202.
[0057] S201: Before writing the current row data in the data to be processed through the write port, read the row data of the row to which the current row data belongs through the read port for the previous preset number of rows; wherein, the read data of the read port is configured as the output data of the tap shift register;
[0058] First, a dual-port RAM is a random access memory with two ports: one for writing data and the other for reading data. These two ports can operate independently, performing read and write operations on the memory separately. Furthermore, the dual-port RAM includes a preset number of cache lines to support multi-line caching. One cache line can correspond to one line of data (input or output), and the size of each cache line is equal to the size of each line of data in the data to be processed. In other words, each cache line can store exactly one line of data to be processed, which is the data that needs to be processed using tapped shift registers and typically includes multiple lines of data. It is understood that the specific value of the preset number does not affect the implementation of this technical solution and can be determined by the actual performance of the dual-port RAM; this application does not limit it in this regard.
[0059] Furthermore, this step aims to implement the data output function during data processing. It should be noted that the tapped shift register implemented based on the dual-port RAM is intended to perform computational processing on the data to be processed. Therefore, the data written through the write port must include each row of data in the data to be processed. Based on this, when a row of data in the data to be processed (i.e., the current row of data mentioned above) is about to be written through the write port, the row number to which the current row belongs can be determined first. Then, the row data of the row number preceding the current row number is used as the data to be read through the read port. In other words, the row data of the row to which the current row belongs is read through the read port. Furthermore, since the dual-port RAM includes a preset number of buffer rows, each buffer row is used to store one row of data.
[0060] For example, suppose a dual-port RAM has 3 cache lines. The current line of data belongs to the 5th line, which is the fifth line of data to be processed. Then, the data read through the read port is the first three lines of data of the fifth line, which are the second, third and fourth lines of data to be processed. Each line of data is transmitted through one cache line. Obviously, the number of lines of data in the read data corresponds to the number of cache lines in the dual-port RAM.
[0061] Finally, to implement a tapped shift register based on dual-port RAM, the read data from the read port can be configured as the output data of the tapped shift register. In other words, the output data of the tapped shift register during data processing is the row data of the row to which the current row belongs in the data to be processed, which is the row data of the row preceding the preset number of rows.
[0062] S202: Discard the row data with the smallest row number in the read data, and write the current row data and the other rows data in the read data through the write port; wherein, the current row data is configured as the input data of the tap shift register.
[0063] This step aims to implement the data input function in the data processing process. As mentioned above, the data read from the read port is the row data of the row number preceding the current row in the data to be processed. At this time, the row data with the smallest row number value in the read data is discarded. It can be understood that the row data with the smallest row number value in the read data is also the oldest row data. Furthermore, the other rows in the read data are combined with the aforementioned current row data to obtain the write data for the write port. It should be noted that the current row data is written as the first row data in the write data, and thus, the write data can be written through the write port.
[0064] Based on the above example, the data read from the read port includes the second, third, and fourth rows of data in the data to be processed. At this time, the row with the smallest row number is the second row. Therefore, the second row can be deleted, and the third and fourth rows can be combined with the current row, i.e., the fifth row, to form the write data. The fifth row is used as the first row of the write data, and the third and fourth rows are used as the third and second rows of the write data, respectively. Then, the data is written through the write port. Similarly, the row number in the write data corresponds to the number of cache rows in the dual-port RAM.
[0065] Finally, to implement a tapped shift register based on dual-port RAM, the current row data can be configured as the input data of the tapped shift register. In other words, the input data of the tapped shift register during data processing is the row data that will be written to the first row buffer of the dual-port RAM from the data to be processed.
[0066] As can be seen, the data processing method based on dual-port RAM provided in this application uses dual-port RAM for multi-line buffering, and uses all the data read from the dual-port RAM read port as the output data of the entire tap shift register. At the same time, the oldest row of data is discarded from the read multi-line data, and the remaining other rows of data are combined with the current row of data in the data to be processed that will be input into the dual-port RAM as the write data of the dual-port RAM write port. The current row of data is the input data of the tap shift register, and the row data of the row to which the current row of data belongs is the output data of the tap shift register. Thus, the function of single-line input and multi-line output of the tap shift register is realized based on dual-port RAM. This implementation method has high development efficiency and reliability, and the entire implementation process is autonomous and controllable, which is convenient for secondary design and porting.
[0067] In one possible implementation, the data processing method based on dual-port RAM may further include the following steps: when writing target data in the current row of data through the write port, determining the current storage address of the target data in the dual-port RAM; when the current storage address is the highest storage address, using the first storage address in the dual-port RAM as the storage address of the new target data.
[0068] This application aims to implement the management function of read and write addresses in a dual-port RAM, thereby realizing the management function of storage addresses in the port shift register. In this application embodiment, the read and write addresses of the dual-port RAM are managed by counting the valid input data (i.e., the target data in the current row data, i.e., the data being written through the write port in the current row data). When the highest address is reached, the count value returns to the lowest address, i.e., the count is continuously cyclically counted within the address range of the dual-port RAM. The count value serves as both the read and write address of the dual-port RAM. Therefore, when data is written to the dual-port RAM, the write address starts from 0 and increments sequentially, returning to address 0 after reaching the highest address, and the writing cycle continues. Similarly, the read address starts from 0 and increments sequentially, returning to address 0 after reaching the highest address, and the reading cycle continues, thus achieving the function of buffering data by row cycle. Based on this, whenever target data is written to the current row of data through the write port, its current storage address in the dual-port RAM can be counted. Once the current storage address reaches the highest storage address, subsequent new target data can be stored in the first storage address of the dual-port RAM. Of course, the same applies to data output.
[0069] In one possible implementation, the data processing method based on dual-port RAM may further include: when a valid signal about target data is received, sending an enable signal to the write port and the read port, so that the write port performs a data write operation according to the enable signal, and the read port performs a data read operation according to the enable signal.
[0070] This application aims to implement the read-write synchronization function of a dual-port RAM, thereby achieving the output-output synchronization function of a tapped shift register. Specifically, the valid signal for writing data can be used simultaneously as the write data enable signal and the read data enable signal for the dual-port RAM. Therefore, when data within a row is written from the write port of the dual-port RAM, a corresponding data within the same row is simultaneously read from the read port. Based on this, when a valid signal for target data is received, the enable signals for both the write and read ports are triggered, causing the write port to perform a data write operation and the read port to perform a data read operation. Clearly, by simultaneously reading and writing to the dual-port RAM, the function of having data input at one end of the shift register while simultaneously having data output at the other end is achieved.
[0071] This application provides yet another method for implementing a tapped shift register based on a dual-port RAM.
[0072] Please refer to Figure 3 , Figure 3 The diagram below illustrates the structure of a tapped shift register provided in this application. As a tapped shift register implemented using a dual-port RAM, the dual-port RAM can be configured as follows:
[0073] (1) Define a dual-port RAM, with one port as the write port and one port as the read port. The capacity of the dual-port RAM is defined as: the original data bit width w multiplied by the number of taps n (i.e., the preset number mentioned above), and then multiplied by the number of data intervals between adjacent taps (i.e., the number of data items in each row of the data to be processed) m. The data bit width of both the write port and the read port is: the original data bit width multiplied by the number of taps (i.e., w*n). Therefore, the depth of the dual-port RAM is the number of data intervals m between adjacent taps. Taking an original data of 8 bits, a number of taps of 3, and an interval of 256 data items between adjacent taps (i.e., 256 data items per row, outputting 3 rows of the same column of data each time) as an example, the capacity of the dual-port RAM is defined as 8*3*256, the data bit width of both the write port and the read port is 8*3, and the depth of the dual-port RAM is 256.
[0074] (2) The read and write addresses of the dual-port RAM are managed by counting the valid input data. When the highest address is reached, the count value returns to the lowest address. That is, the count is continuously looped around the address range of the dual-port RAM. The count value serves as both the read and write address of the dual-port RAM. Therefore, when data is written to the dual-port RAM, the write address starts from 0 and increments sequentially. After reaching the highest address, it returns to address 0 and the writing cycle continues. Similarly, the read address starts from 0 and increments sequentially. After reaching the highest address, it returns to address 0 and the reading cycle continues. This achieves the function of buffering data by row periodically.
[0075] (3) To achieve read-write synchronization for the dual-port RAM, the write data valid signal is used as both the write data enable signal and the read data enable signal for the dual-port RAM. Therefore, when data in a row is written from the write port of the dual-port RAM, a corresponding data in a row is simultaneously read from the read port of the dual-port RAM. By simultaneously reading and writing to the dual-port RAM, the function of having data input at one end of the shift register and data output at the other end is realized.
[0076] (4) Set the dual-port RAM to read-before-write mode. When reading and writing operations are performed on the same address of the dual-port RAM at the same time, it can be set to read-before-write mode, write-before-read mode, or other modes through parameter settings. However, in this design, since reading and writing are always performed on the same address at the same time, it can be set to read-before-write mode. Therefore, when a row and column of data is about to be written from the write port, the read port first reads out the same column of data from the n rows of data before that row cached in the dual-port RAM. The read data is then used as the output data of the entire tap shift register.
[0077] (5) For the column data read from the read port, discard the oldest row of data, combine the new row of data, and rewrite it as the write data for the write port. Assuming the original data bit width is w and the number of taps is n, when the data to be written is the data in the x-th row and y-th column, the data read from the current dual-port RAM read port is the data in the y-th column from the xn-th row to the x-1-th row. The read data is used as the output data of the entire tap shift register. At the same time, the data in the x-(n-1)-th row to the x-1-th row of this column (a total of n-1 rows of data) is used as the data in the n-th row to the 2nd row of the write port. The original input data to be written (the current row of data) is used as the first row of data of the write port and written in the write port. Therefore, the whole process realizes the function of outputting the first n rows of data when a certain row of data is input, and then writing it together with the data in the previous n-1 rows of data into the dual-port RAM.
[0078] As can be seen from the above process, the entire module is a single-line input and multi-line output, while the internal dual-port RAM is a multi-line input and multi-line output. Thus, by cleverly utilizing the design of the dual-port RAM output returning to the input, the function of the tapped shift register is realized.
[0079] As can be seen, the method for implementing a tapped shift register based on dual-port RAM provided in this application uses dual-port RAM for multi-line buffering. All data read from the dual-port RAM read port is used as the output data of the entire tapped shift register. At the same time, the oldest row of data is discarded, and the remaining rows of data are combined with the current row of data to be input into the dual-port RAM from the data to be processed, and used as the write data of the dual-port RAM write port. The current row of data is the input data of the tapped shift register, and the row of data of the row to which the current row of data belongs is the output data of the tapped shift register. Thus, the function of single-line input and multi-line output of the tapped shift register is realized based on dual-port RAM. This implementation method has high development efficiency and reliability, and the entire implementation process is autonomous and controllable, which is convenient for secondary design and porting.
[0080] This application provides a data processing device based on dual-port RAM.
[0081] Please refer to Figure 4 , Figure 4 The present application provides a schematic diagram of a data processing device based on dual-port RAM. The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line supports a multi-line cache mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The data processing device based on dual-port RAM may include:
[0082] Output module 1 is used to read the row data of the row to which the current row belongs through the read port before writing the current row data in the data to be processed through the write port; wherein, the read data of the read port is configured as the output data of the tap shift register;
[0083] Input module 2 is used to discard the row data with the smallest row number in the read data, and write the current row data and other rows data in the read data through the write port; wherein, the current row data is configured as the input data of the tap shift register.
[0084] As can be seen, the data processing device based on dual-port RAM provided in this application embodiment performs multi-line buffering through dual-port RAM, uses all read data from the dual-port RAM read port as the output data of the entire tap shift register, discards the oldest row of read data, and combines the remaining rows of data with the current row of data to be input into the dual-port RAM from the data to be processed, as the write data of the dual-port RAM write port. The current row of data is the input data of the tap shift register, and the row data of the row to which the current row of data belongs is the output data of the tap shift register. Thus, the function of single-line input and multi-line output of the tap shift register is realized based on dual-port RAM. This implementation method has high development efficiency and reliability, and the entire implementation process is autonomous and controllable, which is convenient for secondary design and porting.
[0085] In one embodiment of this application, the data processing device based on dual-port RAM may further include a storage update module, which is used to determine the current storage address of the target data in the dual-port RAM when target data is written to the current row of data through the write port; when the current storage address is the highest storage address, the first storage address in the dual-port RAM is used as the storage address of the new target data.
[0086] In one embodiment of this application, the data processing device based on dual-port RAM may further include an enable trigger module, which sends an enable signal to the write port and the read port when a valid signal about target data is received, so that the write port performs a data write operation according to the enable signal and the read port performs a data read operation according to the enable signal.
[0087] For a description of the apparatus provided in the embodiments of this application, please refer to the above method embodiments; further details will not be repeated here.
[0088] This application provides an electronic device.
[0089] Please refer to Figure 5 , Figure 5 This application provides a schematic diagram of the structure of an electronic device, which may include:
[0090] Memory, used to store computer programs;
[0091] A processor, used to execute computer programs, can implement the steps of any of the data processing methods based on dual-port RAM described above.
[0092] like Figure 5 The diagram shows the structural composition of an electronic device, which may include a processor 10, a memory 11, a communication interface 12, and a communication bus 13. The processor 10, memory 11, and communication interface 12 all communicate with each other through the communication bus 13.
[0093] In this embodiment, the processor 10 may be a central processing unit (CPU), an application-specific integrated circuit, a digital signal processor, a field-programmable gate array, or other programmable logic devices.
[0094] The processor 10 can call programs stored in the memory 11. Specifically, the processor 10 can execute operations in the embodiments of the data processing method based on dual-port RAM.
[0095] The memory 11 is used to store one or more programs. The programs may include program code, which includes computer operation instructions. In this embodiment, the memory 11 stores at least a program for implementing the following functions:
[0096] Before writing the current row of data into the data to be processed through the write port, the row data of the row to which the current row belongs is read through the read port for the preset number of rows; wherein, the data read out of the read port is configured as the output data of the tap shift register;
[0097] The row with the smallest row number in the read data is discarded, and the current row data and the other rows in the read data are written through the write port; the current row data is configured as the input data of the tap shift register.
[0098] In one possible implementation, the memory 11 may include a program storage area and a data storage area, wherein the program storage area may store the operating system and applications required for at least one function; and the data storage area may store data created during use.
[0099] In addition, memory 11 may include high-speed random access memory, and may also include non-volatile memory, such as at least one disk storage device or other volatile solid-state storage device.
[0100] Communication interface 12 can be an interface for the communication module, used to connect with other devices or systems.
[0101] Of course, it should be noted that, Figure 5 The structure shown does not constitute a limitation on the electronic device in the embodiments of this application. In practical applications, the electronic device may include more than Figure 5 More or fewer components as shown, or combinations of certain components.
[0102] This application provides a computer-readable storage medium.
[0103] The computer-readable storage medium provided in this application embodiment stores a computer program, which, when executed by a processor, can implement the steps of any of the above-described data processing methods based on dual-port RAM.
[0104] The computer-readable storage medium may include various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.
[0105] For a description of the computer-readable storage medium provided in the embodiments of this application, please refer to the above method embodiments; further details will not be repeated here.
[0106] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatus disclosed in the embodiments, since it corresponds to the method disclosed in the embodiments, the description is relatively simple; relevant parts can be referred to in the method section.
[0107] Those skilled in the art will further recognize that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the components and steps of the various examples have been generally described in terms of functionality in the foregoing description. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0108] The steps of the methods or algorithms described in conjunction with the embodiments disclosed herein can be implemented directly by hardware, a software module executed by a processor, or a combination of both. The software module can be located in random access memory (RAM), main memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disk, removable disk, CD-ROM, or any other form of storage medium known in the art.
[0109] The technical solutions provided in this application have been described in detail above. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the embodiments above are only for the purpose of helping to understand the methods and core ideas of this application. It should be noted that those skilled in the art can make several improvements and modifications to this application without departing from the principles of this application, and these improvements and modifications also fall within the protection scope of this application.
Claims
1. A method for implementing a tapped shift register based on dual-port RAM, characterized in that, The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line supports a multi-line caching mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The method includes: The row data of the row to which the current row data belongs in the data to be processed is taken as the read data of the read port; The row with the smallest row number in the read data is discarded, and the other rows in the read data are combined with the current row data to form the write data of the write port; The read data is used as the output data of the tap shift register, and the current row data is used as the input data of the tap shift register.
2. The method according to claim 1, characterized in that, Also includes: The read / write mode of the dual-port RAM is set to read-then-write mode.
3. The method according to claim 2, characterized in that, The column number of each target data in the written data is consistent with the column number of each target data in the read data, and the target data is the in-row data in the corresponding row data that passes through the write port or the read port.
4. The method according to claim 1, characterized in that, The dual-port RAM is located in the FPGA.
5. A data processing method based on dual-port RAM, characterized in that, The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line supports a multi-line caching mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The method includes: Before writing the current row data in the data to be processed through the write port, the row data of the row to which the current row data belongs is read through the read port for the previous preset number of rows; wherein, the read data of the read port is configured as the output data of the tap shift register; The row with the smallest row number in the read data is discarded, and the current row data and the other rows in the read data are written through the write port; wherein, the current row data is configured as the input data of the tap shift register.
6. The method according to claim 5, characterized in that, Also includes: When target data is written to the current row of data through the write port, the current storage address of the target data in the dual-port RAM is determined; When the current storage address is the highest storage address, the first storage address in the dual-port RAM is used as the storage address of the new target data.
7. The method according to claim 6, characterized in that, Also includes: When a valid signal for the target data is received, an enable signal is sent to the write port and the read port, so that the write port performs a data write operation according to the enable signal, and the read port performs a data read operation according to the enable signal.
8. A data processing device based on dual-port RAM, characterized in that, The dual-port RAM includes a write port, a read port, and a preset number of cache lines. Each cache line supports a multi-line caching mode, and the cache size of each cache line is consistent with the data size of each line of data in the data to be processed. The device includes: The output module is used to read the row data of the row to which the current row data belongs through the read port before writing the current row data in the data to be processed through the write port; wherein, the read data of the read port is configured as the output data of the tap shift register; The input module is used to discard the row data with the smallest row number in the read data, and write the current row data and other rows data in the read data through the write port; wherein, the current row data is configured as the input data of the tap shift register.
9. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the data processing method based on dual-port RAM as described in any one of claims 5 to 7 when executing the computer program.
10. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the data processing method based on dual-port RAM as described in any one of claims 5 to 7.