Pixel driving circuit and display panel

Abstract

The present invention provides a pixel driving circuit and a display panel. The pixel driving circuit includes an amplitude regulation module and a pulse width modulation module. By electrically connecting both the amplitude regulation module and the pulse width modulation module to a first node, the pulse width and amplitude of the effective pulse of the driving current signal for driving the light-emitting device to emit light are respectively adjusted by using the pulse width modulation module and the amplitude regulation module in cooperation with a first data signal and a second data signal, so that the amplitude of the effective pulse of the driving current signal is different in corresponding different gray scale states, and the pulse width of the effective pulse of the driving current signal is different in corresponding different gray scale states, so that the light-emitting brightness and light-emitting duration of the light-emitting device are different in corresponding different gray scale states, to improve the light-emitting efficiency and light-emitting uniformity of the light-emitting device, and the display gray scale difference can be realized on the display screen.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and particularly relates to a pixel driving circuit and a display panel. Background Art

[0002] In a display panel, light-emitting diodes can be used as sub-pixels to achieve the display of images. However, when implementing low gray-scale display, there are problems of low luminous efficiency and poor brightness uniformity. Summary of the Invention

[0003] Embodiments of the present invention provide a pixel driving circuit and a display panel to improve the problems of low luminous efficiency and poor brightness uniformity existing in low gray-scale display.

[0004] Embodiments of the present invention provide a pixel driving circuit, including an amplitude regulation module and a pulse-width modulation module. The pulse-width modulation module is electrically connected to a first data line, a first node, and a modulation signal source, and is used to control the pulse width of an effective pulse of a driving current signal for driving a light-emitting device to emit light. The amplitude regulation module is electrically connected to a second data line and the first node, and is used to control the amplitude of the effective pulse of the driving current signal. Wherein, the effective pulse of the driving current signal has different pulse widths corresponding to different gray-scale states, and the effective pulse of the driving current signal has different amplitudes corresponding to different gray-scale states.

[0005] The present invention further provides a display panel, including any one of the above pixel driving circuits.

[0006] The present invention provides a pixel driving circuit and a display panel. The pixel driving circuit includes an amplitude regulation module and a pulse-width modulation module. By electrically connecting both the amplitude regulation module and the pulse-width modulation module to a first node, the pulse width and amplitude of an effective pulse of a driving current signal for driving a light-emitting device to emit light are respectively adjusted by cooperating with a first data signal and a second data signal by the pulse-width modulation module and the amplitude regulation module, so that the effective pulse of the driving current signal has different amplitudes corresponding to different gray-scale states, and the effective pulse of the driving current signal has different pulse widths corresponding to different gray-scale states, so that the light-emitting brightness and light-emitting duration of the light-emitting device are different corresponding to different gray-scale states, to improve the luminous efficiency and luminous uniformity of the light-emitting device, and to enable the display panel to achieve a display gray-scale difference. The display panel includes the pixel driving circuit. Description of the Drawings

[0007] To more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present invention. For those skilled in the art, without creative efforts, other accompanying drawings can be obtained based on these drawings.

[0008] Figure 1A is a graph showing the change of the luminous efficiency of a light-emitting device with current;

[0009] Figure 1B is a schematic structural diagram of a pixel driving circuit in the prior art;

[0010] Figures 2A - 2F is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention;

[0011] Figure 3 is a driving timing diagram provided by an embodiment of the present invention;

[0012] Figure 4 is a schematic structural diagram of a display panel provided by an embodiment of the present invention;

[0013] Figures 5A - 5D is a schematic structural diagram of a pixel driving circuit provided by an embodiment of the present invention. Specific Embodiments

[0014] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present invention. In addition, it should be understood that the specific embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention. In the present invention, unless otherwise stated, the orientation terms such as "upper" and "lower" usually refer to the upper and lower in the actual use or working state of the device, specifically the drawing direction in the accompanying drawings; and "inner" and "outer" refer to the outline of the device.

[0015] Specifically, as Figure 1A is a graph showing the change of the luminous efficiency of a light-emitting device with current. As Figure 1A can be seen, at low driving currents, the luminous efficiency of the light-emitting device will rapidly decrease. Therefore, to achieve the required luminous efficiency, the driving current needs to be increased, which will increase the power consumption; and the brightness uniformity at low driving currents will also deteriorate more, resulting in a problem of poor display screen uniformity.

[0016] Figure 1BIt is a schematic diagram of the pixel driving circuit structure of the prior art. The pixel driving circuit includes a driving transistor Tdr, a data writing transistor Tda, and a capacitor C. By controlling the voltage value of the data signal Data transmitted through the data line DaL, the voltage difference between the gate and the source of the driving transistor Tdr can be changed, thereby controlling the magnitude of the driving current, and thus changing the light emission brightness of the light emitting device D to achieve the gray scale difference of the display. However, when using Figure 1B the pixel driving circuit shown to drive the light emitting device D to emit light, the driving current corresponding to the low gray scale state is still a relatively low current, so the problems of low luminous efficiency and poor brightness uniformity cannot be avoided.

[0017] Figures 2A - 2F It is a schematic diagram of the pixel driving circuit provided by an embodiment of the present invention. The present invention provides a pixel driving circuit, including a pulse width modulation module 100 and an amplitude regulation module 200.

[0018] The pulse width modulation module 100 is electrically connected to the first data line DL1, the first node Q1, and the modulation signal source Sweep, so as to control the pulse width of the effective pulse of the driving current signal Id for driving the light emitting device D to emit light according to the voltage difference between the modulation signal Sw generated by the modulation signal source Sweep and the first data signal Data1 transmitted through the first data line DL1. The amplitude regulation module 200 is electrically connected to the second data line DL2 and the first node Q1, so as to control the amplitude of the effective pulse of the driving current signal Id according to the second data signal Data2 transmitted through the second data line DL2.

[0019] By using the amplitude regulation module 200 to make the amplitudes of the effective pulses of the driving current signal Id different in corresponding different gray scale states, and using the pulse width modulation module 100 to make the pulse widths of the effective pulses of the driving current signal Id different in corresponding different gray scale states, so that the light emission brightness and light emission duration of the light emitting device D are different in corresponding different gray scale states, so as to improve the light emission efficiency and light emission uniformity of the light emitting device D.

[0020] Optionally, the amplitude regulation module 200 and the pulse width modulation module 100 are connected in series between the first power supply terminal Vdd and the light emitting device D. For example, the pulse width modulation module 100 is electrically connected between the first power supply terminal Vdd and the first node Q1, the amplitude regulation module 200 is electrically connected between the first node Q1 and the anode of the light emitting device D, and the cathode of the light emitting device D is electrically connected to the second power supply terminal Vss, as Figure 2A shown; or the amplitude regulation module 200 is electrically connected between the first power supply terminal Vdd and the first node Q1, the pulse width modulation module 100 is electrically connected between the first node Q1 and the anode of the light emitting device D, and the cathode of the light emitting device D is electrically connected to the second power supply terminal Vss, as Figure 2B shown.

[0021] Optionally, please continue to refer to Figures 2A - 2F , the pulse width modulation module 100 includes a data conversion unit 101. The data conversion unit 101 is electrically connected to the second node Q2 and the third node Q3, and is configured to generate a current drive control signal according to the voltage difference between the modulation signal Sw and the first data signal Data1, and transmit the current drive control signal to the third node Q3.

[0022] Optionally, the data conversion unit 101 includes a current mirror unit 1011. The current mirror unit 1011 is electrically connected to the second node Q2, the fourth node Q4, the fifth node Q5, and the modulation signal source Sweep, and is configured to output a current pulse width modulation signal according to the voltage difference between the modulation signal Sw generated by the modulation signal source Sweep and the first data signal Data1 received by the second node Q2, and output the current pulse width modulation signal to the fifth node Q5.

[0023] Optionally, the current mirror unit 1011 includes: a first transistor T1, a second transistor T2, a third transistor T3, and a fourth transistor T4.

[0024] The gate of the first transistor T1 is electrically connected to the modulation signal source Sweep, and the source and drain of the first transistor T1 are electrically connected between the fourth node Q4 and the fifth node Q5. The gate of the second transistor T2 is electrically connected to the second node Q2, and one of the source and drain of the second transistor T2 is electrically connected to the fourth node Q4. The gate of the third transistor T3 is electrically connected to the other of the source and drain of the second transistor T2, and the source and drain of the third transistor T3 are electrically connected between the other of the source and drain of the second transistor T2 and the third power supply terminal Switch_L. The gate of the fourth transistor T4 is electrically connected to the other of the source and drain of the second transistor T2, and the source and drain of the fourth transistor T4 are electrically connected between the fifth node Q5 and the third power supply terminal Switch_L.

[0025] Optionally, the fourth node Q4 can be connected to a constant power supply. Optionally, the data conversion unit 101 further includes a current source unit 1012, and the current source unit 1012 is electrically connected to the fourth node Q4.

[0026] Optionally, the current source unit includes a fifth transistor T5. The gate of the fifth transistor T5 is electrically connected to the fourth power supply terminal Vs, and the source and drain of the fifth transistor T5 are electrically connected between the fifth power supply terminal Switch_H and the fourth node Q4. The fifth transistor T5 is configured to transmit the fifth power supply signal transmitted by the fifth power supply terminal Switch_H to the fourth node Q4.

[0027] Optionally, the fifth transistor T5 is a P-type transistor or an N-type transistor. The fifth transistor T5 is a silicon transistor or an oxide transistor. Further, the fifth transistor T5 is a P-type transistor. Since the voltage difference between the gate and the source of the fifth transistor T5 is the difference between the fourth power signal transmitted by the fourth power terminal Vs and the fifth power signal transmitted by the fifth power terminal Switch_H, the current flowing through the fifth node Q5 is relatively stable, which is beneficial to the operation of the pixel driving circuit.

[0028] Optionally, the data conversion unit 101 further includes a signal correction unit 1013. The signal correction unit 1013 is electrically connected to the fifth node Q5 and the third node Q3, and is configured to generate a current drive control signal according to the current pulse width modulation signal and transmit the current drive control signal to the third node Q3.

[0029] Optionally, the signal correction unit 1013 includes a sixth transistor T6 and a seventh transistor T7. The gate of the sixth transistor T6 is electrically connected to the fifth node Q5. The source and drain of the sixth transistor T6 are electrically connected between the third power terminal Switch_L and the third node Q3, and are configured to transmit the third power signal transmitted by the third power terminal Switch_L to the third node Q3 according to the current pulse width modulation signal. The gate of the seventh transistor T7 is electrically connected to the fifth node Q5. The source and drain of the seventh transistor T7 are electrically connected between the sixth power terminal Inv_H and the third node Q3, and are configured to transmit the sixth power signal transmitted by the sixth power terminal Inv_H to the third node Q3 according to the current pulse width modulation signal. Under the action of the current pulse width modulation signal, the sixth transistor T6 and the seventh transistor T7 cooperate with the third power signal and the sixth power signal to generate a current drive control signal.

[0030] Optionally, please continue to refer to Figures 2A - 2F , the pulse width modulation module 100 further includes a first data writing unit 102. The first data writing unit 102 is electrically connected to the first data line DL1 and the second node Q2, and is configured to transmit the first data signal Data1 to the second node Q2.

[0031] Optionally, the first data writing unit 102 includes an eighth transistor T8. The gate of the eighth transistor T8 is electrically connected to the first control line PWL1. The source and drain of the eighth transistor T8 are electrically connected between the second node Q2 and the first data line DL1. The eighth transistor T8 is configured to transmit the first data signal Data1 transmitted by the first data line DL1 to the second node Q2 according to the first control signal PWM(n) transmitted by the first control line PWL1.

[0032] Optionally, the first data writing unit further includes a first capacitor C1. The first capacitor C1 is connected in series between the second node Q2 and the second power supply terminal Vss for maintaining the potential of the second node Q2.

[0033] Optionally, the pulse width modulation module 100 further includes a first current driving unit 103. The first current driving unit 103 is electrically connected to the third node Q3, the first node Q1, and the light emitting device D, as Figure 2B shown; or the first current driving unit 103 is electrically connected to the third node Q3, the first node Q1, and the first power supply terminal Vdd, as Figure 2A shown.

[0034] Optionally, the first current driving unit 103 includes a ninth transistor T9. The gate of the ninth transistor T9 is electrically connected to the third node Q3. The source and drain of the ninth transistor T9 are electrically connected between the first node Q1 and the light emitting device D, as Figure 2C and Figure 2E shown; or the source and drain of the ninth transistor T9 are electrically connected between the first node Q1 and the first power supply terminal Vdd, as Figure 2D and Figure 2F shown.

[0035] Optionally, please continue to refer to Figures 2A - 2F , the amplitude regulation module 200 includes a second data writing unit 201, a second current driving unit 202, a threshold voltage compensation unit 203, a storage unit 204, a first reset unit 205, and a switch unit.

[0036] The second data writing unit 201 is electrically connected to the second data line DL2 and the sixth node Q6 for transmitting the second data signal Data2 transmitted by the second data line DL2 to the sixth node Q6. Optionally, the second data writing unit 201 includes a tenth transistor T10. The gate of the tenth transistor T10 is electrically connected to the second control line PAL1. The source and drain of the tenth transistor T10 are electrically connected between the second data line DL2 and the sixth node Q6. The tenth transistor T10 is configured to transmit the second data signal Data2 transmitted by the second data line DL2 to the sixth node Q6 according to the second control signal PAM(n) transmitted by the second control line PAL1.

[0037] The second current driving unit 202 is electrically connected to the sixth node Q6, the seventh node Q7, and the eighth node Q8 for controlling the amplitude of the driving current signal Id according to the second data signal Data2. Optionally, the second current driving unit 202 includes an eleventh transistor T11. The gate of the eleventh transistor T11 is electrically connected to the eighth node Q8. The source and drain of the eleventh transistor T11 are electrically connected between the sixth node Q6 and the seventh node Q7.

[0038] The threshold voltage compensation unit 203 is electrically connected to the seventh node Q7 and the eighth node Q8, for transmitting a second data signal Data2 with the function of compensating the threshold voltage to the eighth node Q8. Optionally, the threshold voltage compensation unit 203 includes a twelfth transistor T12. The gate of the twelfth transistor T12 is electrically connected to the second control line PAL1, and the source and drain of the twelfth transistor T12 are electrically connected between the seventh node Q7 and the eighth node Q8.

[0039] The storage unit 204 is electrically connected between the first power supply terminal Vdd and the eighth node Q8, as Figure 2B shown; or the storage unit 204 is electrically connected between the first node Q1 and the eighth node Q8, as Figure 2A shown, for maintaining the potential of the eighth node Q8.

[0040] Optionally, the storage unit 204 includes a second capacitor C2. The second capacitor C2 is connected in series between the first power supply terminal Vdd and the eighth node Q8, as Figure 2C and Figure 2E shown; or the second capacitor C2 is connected in series between the first node Q1 and the eighth node Q8, as Figure 2D and Figure 2F shown.

[0041] The switch unit includes a first switch unit 2061 and a second switch unit 2062. The first switch unit 2061 is electrically connected between the first power supply terminal Vdd and the sixth node Q6, and the second switch unit 2062 is electrically connected between the seventh node Q7 and the first node Q1, as Figure 2B shown; or the first switch unit 2061 is electrically connected between the first node Q1 and the sixth node Q6, and the second switch unit 2062 is electrically connected between the seventh node Q7 and the light-emitting device D, as Figure 2A shown.

[0042] Optionally, the first switch unit 2061 includes a thirteenth transistor T13. The gate of the thirteenth transistor T13 is electrically connected to the light-emitting control line EML, and the source and drain of the thirteenth transistor T13 are electrically connected between the first power supply terminal Vdd and the sixth node Q6, as Figure 2C and Figure 2E shown; or the source and drain of the thirteenth transistor T13 are electrically connected between the first node Q1 and the sixth node Q6, as Figure 2D and Figure 2FAs shown. Among them, compared with the design in which the source and drain of the thirteenth transistor T13 are electrically connected between the first node Q1 and the sixth node Q6, electrically connecting the source and drain of the thirteenth transistor T13 between the first power supply terminal Vdd and the sixth node Q6 can make the voltage difference between the gate and source of the eleventh transistor T11 more stable, which is beneficial to realizing the uniform design of the electrical properties.

[0043] The second switching unit 2062 includes a fourteenth transistor T14. The gate of the fourteenth transistor T14 is electrically connected to the emission control line EML. The source and drain of the fourteenth transistor T14 are electrically connected between the seventh node Q7 and the first node Q1, as Figure 2C and Figure 2E shown; or the source and drain of the fourteenth transistor T14 are electrically connected between the seventh node Q7 and the anode of the light-emitting device D, as Figure 2D and Figure 2F shown. The thirteenth transistor T13, the fourteenth transistor T14, and the ninth transistor T9 respectively generate a drive current signal Id in the path from the first power supply terminal Vdd to the second power supply terminal Vss under the action of the emission control signal Em(n) and the current drive control signal.

[0044] The first reset unit 205 is electrically connected between the first reset line VL and the eighth node Q8 to reset the eighth node Q8 according to the first reset signal VI transmitted by the first reset line VL. Optionally, the first reset unit 205 includes a fifteenth transistor T15. The gate of the fifteenth transistor T15 is electrically connected to the third control line PAL2. The source and drain of the fifteenth transistor T15 are electrically connected between the first reset line VL and the eighth node Q8. The fifteenth transistor T15 is used to transmit the first reset signal VI transmitted by the first reset line VL to the eighth node Q8.

[0045] Optionally, the pixel driving circuit further includes a second reset unit 300. The second reset unit 300 is electrically connected to the anode of the light-emitting device D to reset the anode potential of the light-emitting device D.

[0046] Optionally, as Figures 2E - 2F shown, the second reset unit 300 includes a sixteenth transistor T16. The gate of the sixteenth transistor T16 is electrically connected to the first control line PWL1. The source and drain of the sixteenth transistor T16 are electrically connected between the first node Q1 and the second power supply terminal Vss.

[0047] Optionally, the first power supply terminal Vdd, the second power supply terminal Vss, the third power supply terminal Switch_L, the fourth power supply terminal Vs, the fifth power supply terminal Switch_H, and the sixth power supply terminal Inv_H are all DC power supply terminals, and the first reset signal VI is a DC signal. Among them, the voltage value of the first power signal transmitted by the first power supply terminal Vdd is greater than the voltage value of the second power signal transmitted by the second power supply terminal Vss, the voltage value of the fifth power signal transmitted by the fifth power supply terminal Switch_H is greater than the voltage value of the third power signal transmitted by the third power supply terminal Switch_L, and the voltage value of the sixth power signal transmitted by the sixth power supply terminal Inv_H is greater than the voltage value of the third power signal transmitted by the third power supply terminal Switch_L, so that the pixel driving circuit can work properly.

[0048] Optionally, the modulation signal Sw is a triangular wave signal. Accordingly, as the modulation signal Sw varies, there will be cases where the first data signal Data1 is greater than the modulation signal Sw, or the first data signal Data1 is equal to the modulation signal Sw, or the first data signal Data1 is less than the modulation signal Sw. The branch currents flowing through the first transistor T1 and the fourth transistor T4 and the branch currents flowing through the second transistor T2 and the third transistor T3 are determined by the modulation signal Sw and the potential of the second node Q2, respectively. Thus, if both the first transistor T1 and the second transistor T2 are P-type transistors, when the potential of the second node Q2 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistances of the branches where the first transistor T1 and the fourth transistor T4 are located and the branches where the second transistor T2 and the third transistor T3 are located and the third power signal transmitted by the third power supply terminal Switch_L are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 increases, the voltage drop across the source and drain of the fourth transistor T4 increases, thereby increasing the potential of the fifth node Q5, and the sixth transistor T6 turns on as the potential of the fifth node Q5 increases, and the third power signal transmitted by the third power supply terminal Switch_L is transmitted to the third node Q3. Conversely, when the potential of the second node Q2 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistances of the branches where the first transistor T1 and the fourth transistor T4 are located and the branches where the second transistor T2 and the third transistor T3 are located and the third power signal transmitted by the third power supply terminal Switch_L are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 decreases, the voltage across the source and drain of the fourth transistor T4 decreases, thereby decreasing the potential of the fifth node Q5, and the seventh transistor T7 turns on as the potential of the fifth node Q5 decreases, and the sixth power signal transmitted by the sixth power supply terminal Inv_H is transmitted to the third node Q3. Correspondingly, within the first time period, the amplitude value of the modulation signal Sw is less than the amplitude value of the first data signal Data1, then the pulse width of the effective pulse of the drive current signal Id is equal to the first time period.

[0049] It can be understood that when both the first transistor T1 and the second transistor T2 are N-type transistors, when the potential of the second node Q2 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3, so that the potential of the fifth node Q5 rises, and the sixth transistor T6 turns on as the potential of the fifth node Q5 rises, and the third power signal transmitted by the third power supply terminal Switch_L is transmitted to the third node Q3. When the potential of the second node Q2 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3, so that the potential of the fifth node Q5 drops, and the seventh transistor T7 turns on as the potential of the fifth node Q5 drops, and the sixth power signal transmitted by the sixth power supply terminal Inv_H is transmitted to the third node Q3. Correspondingly, in the second time period, the amplitude value of the modulation signal Sw is greater than the amplitude value of the first data signal Data1, and the pulse width of the effective pulse of the drive current signal Id is equal to the second time period.

[0050] Optionally, in the high gray scale state, the drive current signal Id has a plurality of first effective pulses; in the low gray scale state, the drive current signal Id has a plurality of second effective pulses. Among them, the pulse width of the first effective pulse is greater than the pulse width of the second effective pulse, and the amplitude of the first effective pulse is less than the amplitude of the second effective pulse, so that the light emitting duration of the light emitting device D corresponding to the high gray scale state is longer than the light emitting duration of the light emitting device D corresponding to the low gray scale state, and the light emitting brightness of the light emitting device D corresponding to the high gray scale state is less than the light emitting brightness of the light emitting device D corresponding to the low gray scale state, thereby improving the problems of low light emitting efficiency and poor brightness uniformity during low gray scale display.

[0051] Optionally, the first transistor T1 to the sixteenth transistor T16 are P-type transistors or N-type transistors. The first transistor T1 to the sixteenth transistor T16 are silicon transistors or oxide transistors.

[0052] Figure 3 is the drive timing diagram provided by the embodiment of the present invention. Taking the first transistor T1, the second transistor T2, the seventh transistor T7 to the fifteenth transistor T15 as P-type transistors, and the third transistor T3 to the sixth transistor T6 as N-type transistors as an example, for Figure 2C The working principle of the pixel drive circuit shown is described. Among them, V1 to V6 respectively represent the amplitude values of the first power signal to the sixth power signal, V7 represents the amplitude value of the first reset signal VI; V8 represents the high potential, V9 represents the low potential; TB and TD both represent the pulse width; Vsh represents the maximum value of the modulation signal Sw, and Vsl represents the minimum value of the modulation signal Sw.

[0053] When, within the first frame Frame1, the third control signal PAM(n - 1) transmitted by the third control line PAL2 is at a low potential, and the second control signal PAM(n) transmitted by the second control line PAL1, the first control signal PWM(n) transmitted by the first control line PWL1, and the light emission control signal Em(n) transmitted by the light emission control line EML are all at high potentials, the fifteenth transistor T15 is turned on, and the first reset signal VI transmitted by the first reset line VL is transmitted to the eighth node Q8 to reset the eighth node Q8 using the first reset signal VI.

[0054] When the second control signal PAM(n) is at a low potential, and the third control signal PAM(n - 1), the first control signal PWM(n), and the light emission control signal Em(n) are all at high potentials, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the second data signal Data2 (the second data signal Data2 corresponds to having a first voltage value VA) transmitted by the second data line DL2 is transmitted to the eighth node Q8 through the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12.

[0055] When the first control signal PWM(n) is at a low potential, and the third control signal PAM(n - 1), the second control signal PAM(n), and the light emission control signal Em(n) are all at high potentials, the eighth transistor T8 is turned on, and the first data signal Data1 (the first data signal Data1 corresponds to having a second voltage value VB) transmitted by the first data line DL1 is transmitted to the second node Q2.

[0056] When the light-emitting control signal Em(n) is at a low potential and the third control signal PAM(n - 1), the second control signal PAM(n), and the first control signal PWM(n) are all at high potentials, if the potential of the second node Q2 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistances of the branches where the first transistor T1 and the fourth transistor T4 are located and the branches where the second transistor T2 and the third transistor T3 are located, as well as the third power signal transmitted by the third power supply terminal Switch_L, are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 increases, the voltage drop across the source and drain of the fourth transistor T4 increases, thereby increasing the potential of the fifth node Q5. The sixth transistor T6 turns on as the potential of the fifth node Q5 increases, and the third power signal transmitted by the third power supply terminal Switch_L is transmitted to the third node Q3, and the ninth transistor T9 turns on, so that the drive current signal Id has an effective pulse, and within the time period corresponding to the pulse width TB of the effective pulse of the drive current signal Id, the light-emitting device D enters the light-emitting state. When the potential of the second node Q2 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3. Since the resistances of the branches where the first transistor T1 and the fourth transistor T4 are located and the branches where the second transistor T2 and the third transistor T3 are located, as well as the third power signal transmitted by the third power supply terminal Switch_L, are fixed, when the branch current flowing through the first transistor T1 and the fourth transistor T4 decreases, the voltage across the source and drain of the fourth transistor T4 decreases, thereby decreasing the potential of the fifth node Q5. The seventh transistor T7 turns on as the potential of the fifth node Q5 decreases, and the sixth power signal transmitted by the sixth power supply terminal Inv_H is transmitted to the third node Q3, and the ninth transistor T9 turns off, so that the drive current signal Id has an invalid pulse, and within the time period corresponding to the invalid pulse of the drive current signal Id, the light-emitting device D enters the non-light-emitting state. Until the light-emitting control signal Em(n) changes from a low potential to a high potential, the light-emitting state of the light-emitting device D enters a cyclic state according to the difference between the modulation signal Sw and the potential of the second node Q2.

[0057] In the second frame Frame2, when the third control signal PAM(n - 1) is at a low potential and the second control signal PAM(n), the first control signal PWM(n), and the light-emitting control signal Em(n) are all at high potentials, the fifteenth transistor T15 turns on, and the first reset signal transmitted by the first reset line is transmitted to the eighth node Q8 to reset the eighth node Q8 using the first reset signal.

[0058] When the second control signal PAM(n) is at a low potential, and the third control signal PAM(n - 1), the first control signal PWM(n), and the light emission control signal Em(n) are all at high potentials, the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12 are turned on, and the second data signal Data2 transmitted by the second data line DL2 (the second data signal Data2 corresponds to a third voltage value VC different from the first voltage value VA) is transmitted to the eighth node Q8 through the tenth transistor T10, the eleventh transistor T11, and the twelfth transistor T12.

[0059] When the first control signal PWM(n) is at a low potential, and the third control signal PAM(n - 1), the second control signal PAM(n), and the light emission control signal Em(n) are all at high potentials, the eighth transistor T8 is turned on, and the first data signal Data1 transmitted by the first data line DL1 (the first data signal Data1 corresponds to a fourth voltage value VD different from the second voltage value VB) is transmitted to the second node Q2.

[0060] When the light emission control signal Em(n) is at a low potential, and the third control signal PAM(n - 1), the second control signal PAM(n), and the first control signal PWM(n) are all at high potentials, if the potential of the second node Q2 is greater than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is greater than the branch current flowing through the second transistor T2 and the third transistor T3, causing the potential of the fifth node Q5 to rise. The sixth transistor T6 is turned on as the potential of the fifth node Q5 rises, and the third power signal transmitted by the third power supply terminal Switch_L is transmitted to the third node Q3. The ninth transistor T9 is turned on, so that the drive current signal Id has an effective pulse, and within the time period corresponding to the pulse width TD of the effective pulse of the drive current signal Id, the light emitting device D enters the light emitting state. When the potential of the second node Q2 is less than the modulation signal Sw, the branch current flowing through the first transistor T1 and the fourth transistor T4 is less than the branch current flowing through the second transistor T2 and the third transistor T3, causing the potential of the fifth node Q5 to drop. The seventh transistor T7 is turned on as the potential of the fifth node Q5 drops, and the sixth power signal transmitted by the sixth power supply terminal Inv_H is transmitted to the third node Q3. The ninth transistor T9 is turned off, so that the drive current signal Id has an invalid pulse, and within the time period corresponding to the invalid pulse of the drive current signal Id, the light emitting device D enters the non - light emitting state. Until the light emission control signal Em(n) changes from a low potential to a high potential, the light emitting state of the light emitting device D enters a cyclic state according to the difference between the modulation signal Sw and the potential of the second node Q2.

[0061] By controlling the voltage values of the first data signal Data1 transmitted on the first data line DL1 and the voltage values of the second data signal Data2 transmitted on the second data line DL2 within different frames, the effective pulses of the drive current signal Id can have different pulse widths and amplitudes within different frames, such that the light-emitting device D has different light-emitting durations and light-emitting brightnesses corresponding to different gray-scale states, thereby enabling the display gray-scale difference to be realized.

[0062] Optionally, the gray-scale state corresponding to the first frame Frame1 is a high gray-scale state, and the gray-scale state corresponding to the second frame Frame2 is a low gray-scale state. The drive current signal Id has a plurality of first effective pulses within the first frame Frame1 and a plurality of second effective pulses within the second frame Frame2. The pulse width of the first effective pulse is TB, the pulse width of the second effective pulse is TD, the amplitude of the first effective pulse is I_A, and the amplitude of the second effective pulse is I_C. Then TB > TD and I_A < I_C, so that the light-emitting duration of the light-emitting device D corresponding to the high gray-scale state is longer than that of the light-emitting device D corresponding to the low gray-scale state, and the light-emitting brightness of the light-emitting device D corresponding to the high gray-scale state is less than that of the light-emitting device D corresponding to the low gray-scale state. Since the light-emitting brightness of the light-emitting device D is proportional to the product of time and the drive current Id, making the light-emitting duration of the light-emitting device D corresponding to the high gray-scale state longer than that of the light-emitting device D corresponding to the low gray-scale state, and the light-emitting brightness of the light-emitting device D corresponding to the high gray-scale state less than that of the light-emitting device D corresponding to the low gray-scale state can adjust the brightness difference between the high gray-scale and the low gray-scale, thereby improving the problems of low light-emitting efficiency and poor brightness uniformity existing during low gray-scale display.

[0063] In addition, since the light-emitting device D enters a cyclic state of the light-emitting state and the non-light-emitting state with the difference between the modulation signal Sw and the potential of the first node Q1 during the effective stage of the light-emitting control signal Em(n), the problem of brightness decay existing when the light-emitting device D continuously emits light for a long time can be improved, and the flicker problem can also be improved. Among them, the effective stage of the light-emitting control signal Em(n) refers to the stage that can turn on the thirteenth transistor T13 and the fourteenth transistor T14.

[0064] It can be understood that when corresponding to different grayscale states, the effective pulse action time of the driving current signal Id can be adjusted by adjusting the duty cycle of the first control signal PWM(n). For example, when corresponding to a high grayscale state, the duty cycle of the first control signal PWM(n) is set higher to increase the effective pulse action time of the driving current signal Id; when corresponding to a low grayscale state, the duty cycle of the first control signal PWM(n) is set lower to reduce the effective pulse action time of the driving current signal Id. It can be understood that the frequency and amplitude of the modulation signal Sw can be set according to actual requirements.

[0065] The sixteenth transistor T16 conducts during the stage when the first control line PWL1 controls the eighth transistor T8 to conduct, so as to transmit the second power signal transmitted from the second power supply terminal Vss to the anode of the light-emitting device D, so as to reset the anode potential of the light-emitting device D.

[0066] Figures 2D - 2F The working principle of the shown pixel driving circuit is the same as that of Figure 2C the shown pixel driving circuit, and will not be elaborated here.

[0067] The present invention also provides a display panel, including any one of the above pixel driving circuits.

[0068] Figure 4 It is a schematic structural diagram of the display panel provided by the embodiment of the present invention. The present invention also provides a display panel, including a plurality of pixel driving circuits and a plurality of light-emitting devices D, and the plurality of pixel driving circuits and the plurality of light-emitting devices D are electrically connected.

[0069] Optionally, the anode of the light-emitting device D is electrically connected to the first power supply terminal Vdd, and the pixel driving circuit is electrically connected between the cathode of the corresponding light-emitting device D and the second power supply terminal Vss; or, the cathode of the light-emitting device D is electrically connected to the second power supply terminal Vss, and the pixel driving circuit is electrically connected between the anode of the corresponding light-emitting device D and the first power supply terminal Vdd. Optionally, the light-emitting device D includes an organic light-emitting diode, a submillimeter light-emitting diode, and a micro light-emitting diode.

[0070] Figures 5A - 5D It is a schematic structural diagram of the pixel driving circuit provided by the embodiment of the present invention. At least one pixel driving circuit includes: a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a first capacitor C1, and a second capacitor C2.

[0071] The first capacitor C1 is connected in series between the second node Q2 and the second power supply terminal Vss. The gate of the first transistor T1 is electrically connected to the modulation signal source Sweep, and the source and drain of the first transistor T1 are electrically connected between the fourth node Q4 and the fifth node Q5; the gate of the second transistor T2 is electrically connected to the second node Q2, and one of the source and drain of the second transistor T2 is electrically connected to the fourth node Q4; the gate of the third transistor T3 is electrically connected to the other of the source and drain of the second transistor T2, and the source and drain of the third transistor T3 are electrically connected between the other of the source and drain of the second transistor T2 and the third power supply terminal Switch_L; the gate of the fourth transistor T4 is electrically connected to the other of the source and drain of the second transistor T2, and the source and drain of the fourth transistor T4 are electrically connected between the fifth node Q5 and the third power supply terminal Switch_L; the gate of the fifth transistor T5 is electrically connected to the fourth power supply terminal Vs, and the source and drain of the fifth transistor T5 are electrically connected between the fifth power supply terminal Switch_H and the fourth node Q4; the gate of the sixth transistor T6 is electrically connected to the fifth node Q5, and the source and drain of the sixth transistor T6 are electrically connected between the third power supply terminal Switch_L and the third node Q3; the gate of the seventh transistor T7 is electrically connected to the fifth node Q5, and the source and drain of the seventh transistor T7 are electrically connected between the sixth power supply terminal Inv_H and the third node Q3; the gate of the eighth transistor T8 is electrically connected to the first control line PWL1, and the source and drain of the eighth transistor T8 are electrically connected between the second node Q2 and the first data line DL1.

[0072] Optionally, the gate of the ninth transistor T9 is electrically connected to the third node Q3, and the source and drain of the ninth transistor T9 are electrically connected between the first node Q1 and the corresponding light-emitting device D, as Figure 5A and Figure 5C shown; or the source and drain of the ninth transistor T9 are electrically connected between the first node Q1 and the first power supply terminal Vdd, as Figure 5B and Figure 5D shown.

[0073] The gate of the tenth transistor T10 is electrically connected to the second control line PAL1. The source and drain of the tenth transistor T10 are electrically connected between the second data line DL2 and the sixth node Q6. The gate of the eleventh transistor T11 is electrically connected to the eighth node Q8. The source and drain of the eleventh transistor T11 are electrically connected between the sixth node Q6 and the seventh node Q7. The gate of the twelfth transistor T12 is electrically connected to the second control line PAL1. The source and drain of the twelfth transistor T12 are electrically connected between the seventh node Q7 and the eighth node Q8. The gate of the fifteenth transistor T15 is electrically connected to the third control line PAL2. The source and drain of the fifteenth transistor T15 are electrically connected between the first reset line VL and the eighth node Q8.

[0074] Optionally, the gates of the thirteenth transistor T13 and the fourteenth transistor T14 are both electrically connected to the light-emitting control line EML. The source and drain of the thirteenth transistor T13 are electrically connected between the first power supply terminal Vdd and the sixth node Q6. The source and drain of the fourteenth transistor T14 are electrically connected between the seventh node Q7 and the first node Q1. The second capacitor C2 is connected in series between the first power supply terminal Vdd and the eighth node Q8, as Figure 5A and Figure 5C shown; or the source and drain of the thirteenth transistor T13 are electrically connected between the first node Q1 and the sixth node Q6. The source and drain of the fourteenth transistor T14 are electrically connected between the seventh node Q7 and the corresponding light-emitting device D. The second capacitor C2 is connected in series between the first node Q1 and the eighth node Q8, as Figure 5B and Figure 5D shown.

[0075] Optionally, at least one pixel driving circuit further includes a sixteenth transistor T16. The gate of the sixteenth transistor T16 is electrically connected to the first control line PWL1. The source and drain of the sixteenth transistor T16 are electrically connected between the first node Q1 and the second power supply terminal Vss, as Figures 5C - 5D shown.

[0076] Optionally, the plurality of light-emitting devices D include a first light-emitting device, a second light-emitting device, and a third light-emitting device having different light-emitting colors. The plurality of pixel driving circuits include a first pixel driving circuit for driving the first light-emitting device to emit light, a second pixel driving circuit for driving the second light-emitting device to emit light, and a third pixel driving circuit for driving the third light-emitting device to emit light. By respectively making the first data signal and the second data signal transmitted by the first data line DL1 and the second data line DL2 electrically connected to the first pixel driving circuit, the second pixel driving circuit, and the third pixel driving circuit have different voltage values, the light-emitting durations and light-emitting brightnesses of the first light-emitting device, the second light-emitting device, and the third light-emitting device corresponding to the same gray-scale state can be made different, so that the display gray-scale difference can be realized, and the problems of low light-emitting efficiency and poor brightness uniformity existing in low-gray-scale display can be improved.

[0077] The present invention further provides a display device, and the display device includes any one of the above-mentioned driving circuits or any one of the above-mentioned display panels. It can be understood that the display device includes a movable display device (such as a laptop computer, a mobile phone, etc.), a fixed terminal (such as a desktop computer, a television, etc.), a measuring device (such as a sports bracelet, a thermometer, etc.), and the like.

[0078] In this article, specific examples are used to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention; at the same time, for those skilled in the art, according to the idea of the present invention, there will be changes in the specific implementation manner and application scope. In summary, the content of this specification should not be construed as a limitation to the present invention.

Claims

1. A pixel driving circuit, characterized in that, comprising: a pulse width modulation module electrically connected to a first data line, a first node and a modulation signal source, for controlling the pulse width of an effective pulse of a driving current signal for driving a light emitting device to emit light; and an amplitude regulation module electrically connected to a second data line and the first node, for controlling the amplitude of the effective pulse of the driving current signal; wherein, the effective pulse of the driving current signal has different pulse widths corresponding to different gray scale states, and the effective pulse of the driving current signal has different amplitudes corresponding to different gray scale states; wherein, the pulse width modulation module comprises: a first data writing unit electrically connected to the first data line and a second node, for transmitting a first data signal transmitted by the first data line to the second node; a data conversion unit electrically connected to the second node and a third node, for generating a current driving control signal and transmitting the current driving control signal to the third node; and a first current driving unit electrically connected to the third node, the first node and the light emitting device, for controlling the pulse width of the effective pulse of the driving current signal.

2. The pixel driving circuit according to claim 1, characterized in that, the modulation signal generated by the modulation signal source is a triangular wave signal.

3. The pixel driving circuit according to claim 2, characterized in that, within a first time period, the voltage value of the modulation signal is less than the voltage value of the first data signal transmitted by the first data line; wherein, the pulse width is equal to the first time period.

4. The pixel driving circuit according to claim 1, characterized in that, in a high gray scale state, the driving current signal has a plurality of first effective pulses; in a low gray scale state, the driving current signal has a plurality of second effective pulses; wherein, the pulse width of the first effective pulse is greater than the pulse width of the second effective pulse, and the amplitude of the first effective pulse is less than the amplitude of the second effective pulse.

5. The pixel driving circuit according to claim 1, characterized in that, the amplitude regulation module is electrically connected between a first power supply terminal and the first node, the pulse width modulation module is electrically connected between the first node and the anode of the light emitting device, and the cathode of the light emitting device is electrically connected to a second power supply terminal.

6. The pixel driving circuit according to claim 5, characterized in that, the data conversion unit comprises: a first transistor, the gate of the first transistor is electrically connected to the modulation signal source, and the source and drain of the first transistor are electrically connected between a fourth node and a fifth node; a second transistor, the gate of the second transistor is electrically connected to the second node, and one of the source and drain of the second transistor is electrically connected to the fourth node; A third transistor, wherein a gate of the third transistor is electrically connected to the other one of the source and the drain of the second transistor, and a source and a drain of the third transistor are electrically connected between the other one of the source and the drain of the second transistor and a third power supply terminal; A fourth transistor, wherein a gate of the fourth transistor is electrically connected to the other one of the source and the drain of the second transistor, and a source and a drain of the fourth transistor are electrically connected between a fifth node and the third power supply terminal; A fifth transistor, wherein a gate of the fifth transistor is electrically connected to a fourth power supply terminal, and a source and a drain of the fifth transistor are electrically connected between a fifth power supply terminal and the fourth node; A sixth transistor, wherein a gate of the sixth transistor is electrically connected to the fifth node, and a source and a drain of the sixth transistor are electrically connected between the third power supply terminal and the third node; and A seventh transistor, wherein a gate of the seventh transistor is electrically connected to the fifth node, and a source and a drain of the seventh transistor are electrically connected between a sixth power supply terminal and the third node; wherein a voltage value of a first power signal transmitted by the first power supply terminal is greater than a voltage value of a second power signal transmitted by the second power supply terminal, a voltage value of a third power signal transmitted by the third power supply terminal is less than a voltage value of a fifth power signal transmitted by the fifth power supply terminal, and a voltage value of a sixth power signal transmitted by the sixth power supply terminal is greater than a voltage value of the third power signal transmitted by the third power supply terminal.

7. The pixel driving circuit according to claim 6, wherein, the fifth transistor is a P-type transistor.

8. The pixel driving circuit according to claim 5, wherein, the first data writing unit includes an eighth transistor and a first capacitor; a gate of the eighth transistor is electrically connected to a first control line, and a source and a drain of the eighth transistor are electrically connected between the second node and the first data line; the first capacitor is connected in series between the second node and the second power supply terminal; the first current driving unit includes a ninth transistor, a gate of the ninth transistor is electrically connected to the third node, and a source and a drain of the ninth transistor are electrically connected between the first node and the light emitting device.

9. The pixel driving circuit according to claim 1, wherein, the amplitude regulating module includes: a second data writing unit, electrically connected to the second data line and a sixth node, for transmitting a second data signal transmitted by the second data line to the sixth node; a second current driving unit, electrically connected to the sixth node, a seventh node and an eighth node, for controlling an amplitude of the effective pulse of the driving current signal; a threshold voltage compensation unit, electrically connected to the seventh node and the eighth node; a storage unit, electrically connected between the first power supply terminal and the eighth node; a first switching unit, electrically connected between the first power supply terminal and the sixth node; a second switching unit, electrically connected between the seventh node and the first node; and The first reset unit is electrically connected between the first reset line and the eighth node.

10. The pixel driving circuit according to claim 9, wherein, the second data writing unit includes a tenth transistor, the gate of the tenth transistor is electrically connected to the second control line, and the source and drain of the tenth transistor are electrically connected between the second data line and the sixth node; the second current driving unit includes an eleventh transistor, the gate of the eleventh transistor is electrically connected to the eighth node, and the source and drain of the eleventh transistor are electrically connected between the sixth node and the seventh node; the storage unit includes a second capacitor, and the second capacitor is connected in series between the first power supply terminal and the eighth node; the threshold voltage compensation unit includes a twelfth transistor, the gate of the twelfth transistor is electrically connected to the second control line, and the source and drain of the twelfth transistor are electrically connected between the seventh node and the eighth node; the first switching unit includes a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the light emission control line, and the source and drain of the thirteenth transistor are electrically connected between the first power supply terminal and the sixth node; the second switching unit includes a fourteenth transistor, the gate of the fourteenth transistor is electrically connected to the light emission control line, and the source and drain of the fourteenth transistor are electrically connected between the seventh node and the first node; the first reset unit includes a fifteenth transistor, the gate of the fifteenth transistor is electrically connected to the third control line, and the source and drain of the fifteenth transistor are electrically connected between the first reset line and the eighth node.

11. The pixel driving circuit according to claim 1, wherein, further comprising: a second reset unit, including a sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the first control line, and the source and drain of the sixteenth transistor are electrically connected between the first node and the second power supply terminal.

12. The pixel driving circuit according to claim 1, wherein, the pulse width modulation module is electrically connected between the first power supply terminal and the first node, the amplitude regulation module is electrically connected between the first node and the anode of the light emitting device, and the cathode of the light emitting device is electrically connected to the second power supply terminal.

13. A display panel, wherein, comprising a plurality of pixel driving circuits and a plurality of light emitting devices, the plurality of pixel driving circuits and the plurality of light emitting devices are electrically connected, and at least one of the pixel driving circuits includes: a first transistor, the gate of the first transistor is electrically connected to a modulation signal source, and the source and drain of the first transistor are electrically connected between a fourth node and a fifth node; a second transistor, the gate of the second transistor is electrically connected to the second node, and one of the source and drain of the second transistor is electrically connected to the fourth node; A third transistor, wherein a gate of the third transistor is electrically connected to the other one of the source and the drain of the second transistor, and a source and a drain of the third transistor are electrically connected between the other one of the source and the drain of the second transistor and a third power supply terminal; A fourth transistor, wherein a gate of the fourth transistor is electrically connected to the other one of the source and the drain of the second transistor, and a source and a drain of the fourth transistor are electrically connected between a fifth node and the third power supply terminal; A fifth transistor, wherein a gate of the fifth transistor is electrically connected to a fourth power supply terminal, and a source and a drain of the fifth transistor are electrically connected between a fifth power supply terminal and the fourth node; A sixth transistor, wherein a gate of the sixth transistor is electrically connected to the fifth node, and a source and a drain of the sixth transistor are electrically connected between the third power supply terminal and a third node; A seventh transistor, wherein a gate of the seventh transistor is electrically connected to the fifth node, and a source and a drain of the seventh transistor are electrically connected between a sixth power supply terminal and the third node; An eighth transistor, wherein a gate of the eighth transistor is electrically connected to a first control line, and a source and a drain of the eighth transistor are electrically connected between the second node and a first data line; A ninth transistor, wherein a gate of the ninth transistor is electrically connected to the third node, and a source and a drain of the ninth transistor are electrically connected between the first node and the corresponding light-emitting device; A tenth transistor, wherein a gate of the tenth transistor is electrically connected to a second control line, and a source and a drain of the tenth transistor are electrically connected between a second data line and a sixth node; An eleventh transistor, wherein a gate of the eleventh transistor is electrically connected to an eighth node, and a source and a drain of the eleventh transistor are electrically connected between the sixth node and a seventh node; A twelfth transistor, wherein a gate of the twelfth transistor is electrically connected to the second control line, and a source and a drain of the twelfth transistor are electrically connected between the seventh node and the eighth node; A thirteenth transistor, wherein a gate of the thirteenth transistor is electrically connected to a light-emitting control line, and a source and a drain of the thirteenth transistor are electrically connected between a first power supply terminal and the sixth node; A fourteenth transistor, wherein a gate of the fourteenth transistor is electrically connected to the light-emitting control line, and a source and a drain of the fourteenth transistor are electrically connected between the seventh node and the first node; A fifteenth transistor, wherein a gate of the fifteenth transistor is electrically connected to a third control line, and a source and a drain of the fifteenth transistor are electrically connected between a first reset line and the eighth node; A first capacitor, connected in series between the second node and a second power supply terminal; and A second capacitor, connected in series between the first power supply terminal and the eighth node.

14. The display panel according to claim 13, wherein, at least one of the pixel driving circuits further includes: The sixteenth transistor, the gate of the sixteenth transistor is electrically connected to the first control line, and the source and drain of the sixteenth transistor are electrically connected between the first node and the second power supply terminal.

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