Display panel, preparation method thereof and electronic device
By introducing a stacked structure of metal oxide layers into the OLED panel, the problem of polymer aggregation during ILD etching is solved, thereby improving the yield of the display panel and the optical inspection effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HEFEI XINSHENG OPTOELECTRONICS TECH CO LTD
- Filing Date
- 2022-10-21
- Publication Date
- 2026-05-29
AI Technical Summary
During the ILD etching process of OLED panels, polymers accumulate on the walls of the ILD vias, leading to reduced display panel yield and poor optical inspection.
A metal oxide layer is deposited between the gate layer and the second insulating layer to form a stacked structure, which avoids the induced aggregation of precipitates by the metal material and reduces the formation of polymers.
It improves the optical inspection results and yield of display panels, reduces the impact of defects, and enhances the quality of display panels.
Smart Images
Figure CN115643775B_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and in particular to a display panel and its manufacturing method, and an electronic device. Background Technology
[0002] In existing organic light-emitting diode (OLED) panel structure designs, especially for large-size, high-resolution display panels, the interlayer insulating layer (ILD) is prone to the following defects during dry etching to form ILD vias: ... Figure 1 As shown, the PR adhesive used to fix the ILD mask generates byproducts during ion bombardment, which adhere to the walls of the etched ILD vias. Especially under the induction of the gate metal at the bottom of the ILD, a large amount of precipitates accumulate at the bottom of the ILD vias near the gate metal, forming deposits such as... Figure 1 The polymers corresponding to the irregular black areas in the middle can severely affect the optical inspection results of the display panel, leading to defective map bursts. This makes it impossible to effectively detect and repair defects, thus reducing the yield of the display panel. Summary of the Invention
[0003] The purpose of this disclosure is to provide a display panel and its manufacturing method, as well as an electronic device, to solve the problem of burst points caused by polymers during the ILD etching process in the prior art, which affect the yield of the display panel.
[0004] The embodiments of this disclosure adopt the following technical solution: a display panel, comprising: a substrate; a buffer layer disposed on one side surface of the substrate; a first insulating layer disposed on the side surface of the buffer layer away from the substrate, the first insulating layer having a first pattern; a gate layer disposed on the side surface of the first insulating layer away from the buffer layer, the orthographic projection of the gate layer on the substrate completely coinciding with the orthographic projection of the first insulating layer on the substrate; a metal oxide layer disposed on the side surface of the gate layer away from the insulating layer, the orthographic projection of the metal oxide layer on the substrate completely coinciding with the orthographic projection of the gate layer on the substrate; a second insulating layer disposed on the side surface of the metal oxide layer away from the gate layer, the second insulating layer including at least a first through-hole penetrating the second insulating layer, the orthographic projection of the first through-hole on the substrate being located within the orthographic projection of the metal oxide layer on the substrate; a metal layer disposed on the side surface of the second insulating layer away from the metal oxide layer, the metal layer having a second pattern, the orthographic projection of the second pattern on the substrate completely covering the orthographic projection of the first through-hole on the substrate, such that the metal layer is connected to the metal oxide layer through the first through-hole.
[0005] In some embodiments, the metal oxide layer is made based on indium tin oxide or zinc oxide material doped with aluminum.
[0006] In some embodiments, the thickness of the metal oxide layer is between 300 and 700 angstroms.
[0007] In some embodiments, the thickness of the metal oxide layer is 450 angstroms.
[0008] In some embodiments, the invention further includes a protective layer disposed on the surface of the metal layer on the side away from the second insulating layer.
[0009] Embodiments of this disclosure also provide a method for fabricating a display panel, comprising: providing a substrate; fabricating a buffer layer on one side surface of the substrate; fabricating a first insulating layer on the side surface of the buffer layer away from the substrate; sequentially fabricating a gate layer and a metal oxide layer on the side surface of the first insulating layer away from the buffer layer; etching the metal oxide layer and the gate layer using a first mask to give the metal oxide layer and the gate layer a first pattern; etching the first insulating layer to give the first insulating layer the first pattern, and making the orthographic projection of the gate layer on the substrate completely coincide with the orthographic projection of the first insulating layer on the substrate; fabricating a second insulating layer on the side surface of the metal oxide layer away from the gate layer, and forming a first through-hole penetrating the second insulating layer, the orthographic projection of the first through-hole on the substrate being located within the orthographic projection of the metal oxide layer on the substrate; fabricating a metal layer on the surface of the second insulating layer away from the metal oxide layer, connecting the metal layer to the metal oxide layer based on the first through-hole, and etching the metal layer to give the metal layer a second pattern.
[0010] In some embodiments, etching the metal oxide layer and the gate layer using a first mask to give the metal oxide layer and the gate layer a first pattern includes: attaching the first mask to the surface of the metal oxide layer away from the gate layer, the first mask having a window that matches the shape of the first pattern; sequentially etching the material in the metal oxide layer and the gate layer at positions corresponding to the window to give the metal oxide layer and the gate layer the first pattern; and peeling off the first mask from the surface of the metal oxide layer.
[0011] In some embodiments, the thickness of the metal oxide layer is between 300 and 700 angstroms.
[0012] In some embodiments, after preparing a metal layer on the surface of the second insulating layer away from the metal oxide layer, connecting the metal layer to the metal oxide layer through the first via, and etching the metal layer to give the metal layer a second pattern, the method further includes: preparing a protective layer on the surface of the metal layer away from the second insulating layer.
[0013] Embodiments of this disclosure also provide an electronic device, which includes at least the display panel described above.
[0014] The beneficial effects of the embodiments disclosed herein are as follows: depositing a metal oxide layer between the gate layer and the second insulating layer to form a stacked structure avoids the induced aggregation of precipitates by metal materials, reduces the formation of polymers, thereby improving the optical inspection results of the display panel, which is beneficial for subsequent defect detection, and thus improves the yield and quality of the display panel. Attached Figure Description
[0015] To more clearly illustrate the technical solutions in the embodiments of this disclosure or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0016] Figure 1 This is a schematic diagram of the hierarchical structure of a display panel in the prior art;
[0017] Figure 2 This is a schematic diagram of the hierarchical structure of the display panel in the first embodiment of this disclosure;
[0018] Figure 3 This is a schematic diagram of another hierarchical structure of the display panel in the first embodiment of this disclosure;
[0019] Figure 4 This is a flowchart of a method for preparing a display panel according to the second embodiment of this disclosure. Detailed Implementation
[0020] Various embodiments and features of this disclosure are described herein with reference to the accompanying drawings.
[0021] It should be understood that various modifications can be made to the embodiments described herein. Therefore, the above description should not be considered as limiting, but merely as an example of embodiments. Other modifications within the scope and spirit of this disclosure will be apparent to those skilled in the art.
[0022] The accompanying drawings, which are included in and form part of this specification, illustrate embodiments of the present disclosure and, together with the general description of the disclosure given above and the detailed description of the embodiments given below, serve to explain the principles of the disclosure.
[0023] These and other features of this disclosure will become apparent from the following description of preferred forms of embodiments given as non-limiting examples, with reference to the accompanying drawings.
[0024] It should also be understood that although this disclosure has been described with reference to some specific examples, many other equivalent forms of this disclosure can be definitively implemented by those skilled in the art, which have the features of the claims and are therefore within the scope of protection defined herein.
[0025] The above and other aspects, features and advantages of this disclosure will become more apparent when taken in conjunction with the accompanying drawings and in view of the following detailed description.
[0026] Specific embodiments of this disclosure are described thereafter with reference to the accompanying drawings; however, it should be understood that the claimed embodiments are merely examples of this disclosure, which may be implemented in various ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that could obscure this disclosure. Therefore, the specific structural and functional details claimed herein are not intended to be limiting, but merely to serve as the basis and representative basis for the claims to teach those skilled in the art to use this disclosure in a variety of substantially any suitable detailed structures.
[0027] This specification may use the phrases “in one embodiment,” “in another embodiment,” “in yet another embodiment,” or “in still another embodiment,” all of which may refer to one or more of the same or different embodiments according to this disclosure.
[0028] In existing OLED panel structure designs, especially for large-size, high-resolution display panels, the interlayer insulating layer (ILD) is prone to the following defects during dry etching to form ILD vias: such as... Figure 1 As shown, the PR adhesive used to fix the ILD mask generates byproducts during ion bombardment, which adhere to the walls of the etched ILD vias. Especially under the induction of the gate metal at the bottom of the ILD, a large amount of precipitates accumulate at the bottom of the ILD vias near the gate metal, forming deposits such as... Figure 1The polymers corresponding to the irregular black areas in the display panel can severely affect the optical inspection results, leading to defective map pop-ups. This makes it impossible to effectively detect and repair defects, resulting in a decrease in the yield of the display panel. Furthermore, ion bombardment can cause unevenness on the gate metal surface, which can easily affect the contact between the gate and the metal layer SD, thus impacting the signal transmission performance of the corresponding circuits.
[0029] To address the aforementioned issues, the first embodiment of this disclosure provides a display panel that improves upon existing panel layer structures by utilizing the deposition of a metal oxide layer to avoid the induced aggregation of precipitates by metal materials and reduce polymer formation.
[0030] Specifically, Figure 2 A schematic diagram of the hierarchical structure of the display panel in this embodiment is shown. For example... Figure 2 As shown, the display panel mainly includes a substrate 10, a buffer layer 20, a first insulating layer 30, a gate layer 40, a metal oxide layer 50, a second insulating layer 60, and a metal layer 70. The design of the substrate 10, buffer layer 20, first insulating layer 30, gate layer 40, second insulating layer 60, and metal layer 70 are all designs of corresponding layers in conventional display panels, mainly used for the design of data signal lines in the display area of the display panel. The corresponding structure of the thin-film transistor (TFT) used to drive the pixels to light up in the display panel is not within the scope of improvement in this embodiment. As long as the corresponding layers and patterns are prepared according to the pixel position settings during the overall layer preparation, this embodiment will not provide a detailed description.
[0031] In this embodiment, the substrate 10 can be made of a material with supporting properties, typically using white glass as the substrate; on one side surface of the substrate 10 (i.e. Figure 2 A buffer layer 20 is provided on the upper surface of the substrate 10. The buffer layer 20 is mainly provided to facilitate the fabrication of subsequent layers. On the surface of the buffer layer 20 away from the substrate 10 (i.e., Figure 2 The upper surface of the buffer layer 20 is provided with a first insulating layer 30, namely the GI layer used as the gate insulating layer. The first insulating layer 30 has a first pattern, the specific shape of which is determined according to the functional requirements of the display panel and the wiring distribution.
[0032] Furthermore, on the surface of the first insulating layer 30 away from the buffer layer 20 (i.e. Figure 2A gate layer 40 is disposed on the upper surface of the first insulating layer 30. This gate layer 40 also has a first pattern, and its orthographic projection on the substrate 10 completely coincides with the orthographic projection of the first insulating layer 30 on the substrate 10. It is mainly made of metal materials with good conductivity, such as copper (Cu) or aluminum (Al), and is primarily used to reduce the resistance of the data signal lines (i.e., metal layer 70) to achieve good signal transmission. It should be noted that in this embodiment, the gate layer 40 can be disposed on the same layer as the gate structure of the TFT. The fabrication processes and materials are completely identical; it is only necessary to ensure that they are mutually insulated when disposed on the same layer to avoid mutual interference between signals.
[0033] On the surface of the gate layer 40 away from the first insulating layer 30 (i.e. Figure 2 A metal oxide layer 50 is disposed on the upper surface of the gate layer 40. This metal oxide layer 50 and the gate layer 40 are stacked, meaning the orthogonal projection of the metal oxide layer 50 onto the substrate 10 completely coincides with the orthogonal projection of the gate layer 40 onto the substrate 10. In this embodiment, the metal oxide layer 50 mainly refers to a layer made of indium tin oxide (ITO) or aluminum-doped zinc oxide (AZO), which has good conductivity. Since the metal oxide layer 50 is disposed between the gate layer 40 and the metal layer 70, to ensure that the resistance of the corresponding lines is not too high, the metal oxide layer 50 needs to have good conductivity and a certain thickness. In actual implementation, the thickness of the metal oxide layer 50 in this embodiment can be set between 300 and 700 angstroms as needed. Considering the resistance and the overall thickness balance of the display panel, its thickness can preferably be set to 450 angstroms.
[0034] It should be noted that the first insulating layer 30, gate layer 40 and metal oxide layer 50 are all deposited on the entire surface and then etched using a first mask to form the first pattern. The specific preparation process and methods will be described in detail in the second embodiment of this disclosure.
[0035] A second insulating layer 60, i.e., an interlayer insulating layer (ILD), is provided on the surface of the metal oxide layer 50 away from the gate layer 40. The second insulating layer 60 includes at least a first via 61 penetrating the second insulating layer 60. The location of the first via 61 is within the region corresponding to the metal oxide layer 50, i.e., the orthographic projection of the first via 61 on the substrate 10 is located within the orthographic projection of the metal oxide layer 50 on the substrate 10. The main purpose of the via 61 is to enable communication between the subsequent metal layer 70 and the underlying conductive layer, thereby reducing the resistance of the data signal line. The specific number and shape of the via 61 can be determined according to actual needs.
[0036] During the creation of the first via 61, the second insulating layer 60 at the corresponding position needs to be etched using a second mask. The second mask is mainly fixed to the surface of the second insulating layer 60 by PR adhesive. During dry etching, ions bombard the second insulating layer 60 material and the PR adhesive at the same time. Since the metal oxide layer 50 is used to shield the metal of the gate layer 40 in this embodiment, the metal material is prevented from accumulating on the precipitates generated by the PR adhesive during the bombardment process. Therefore, the precipitates will not remain at the bottom of the first via 61 to form polymers. The precipitates formed at the upper edge of the first via 61 (i.e., the edge near the PR adhesive) will be cleaned away by the cleaning solution during the peeling operation of the second mask. This solves the problem of polymer formation during ILD etching, avoids the impact of explosion points on the optical detection effect of the display panel, and achieves the effect of improving the yield and quality of the display panel.
[0037] A metal layer 70, or SD layer, is provided on the surface of the second insulating layer 60 away from the metal oxide layer 50. The metal layer 70 has a second pattern based on the functional requirements of the display panel and the wiring distribution. The orthogonal projection of the second pattern on the substrate 10 completely covers the orthogonal projection of the first through hole 61 on the substrate 10, so that the metal layer 70 can be connected to the metal oxide layer 50 through the first through hole 61 during the manufacturing process, thereby reducing the overall resistance of the signal line.
[0038] In addition, such as Figure 2 As shown, a protective layer 80 can also be provided on the surface of the metal layer 70 away from the second insulating layer 60. This layer is mainly used for insulation and protection of the underlying circuitry, and can also serve as a flattening layer to facilitate the installation of other layers or structures on the display panel. Its thickness is typically between 3000 and 5000 angstroms. Figure 2 Based on the display panel layer structure shown, other layer structures such as active layer, color filter array, pixel array, and encapsulation cover plate may also be included. These are not shown in this embodiment, but can be fabricated in the corresponding positions according to requirements during actual fabrication.
[0039] Figure 3 This is a schematic diagram of another hierarchical structure of the display panel in this embodiment, compared to... Figure 2 The hierarchical structure shown, Figure 3 In the layered structure shown, a shielding layer 90 is also provided on the upper surface of the substrate 10, which is mainly used to shield the electronic components below the substrate 10 from external light. The shape of the metal layer 70 at the corresponding position may also change, and can be adjusted according to the requirements.
[0040] The second embodiment of this disclosure provides a method for manufacturing a display panel, which is mainly used to perform the hierarchical structure of the display panel mentioned in the first embodiment of this disclosure. In the actual manufacturing process of the display panel, the manufacturing steps of this embodiment can be integrated and adjusted by combining the manufacturing processes of other hierarchical structures. Figure 4 This is a flowchart of the method for manufacturing the display panel in this embodiment, which mainly includes steps S10 to S70:
[0041] S10, a substrate is provided, and a buffer layer is prepared on one side surface of the substrate;
[0042] S20, a first insulating layer is prepared on the surface of the buffer layer away from the substrate;
[0043] S30, a gate layer and a metal oxide layer are sequentially prepared on the surface of the first insulating layer away from the buffer layer; in actual implementation, the thickness of the metal oxide layer can be set between 300 and 700 angstroms as needed. Considering the resistance and the overall thickness balance of the display panel, its thickness can preferably be set to 450 angstroms.
[0044] S40, the metal oxide layer and the gate layer are etched using the first mask to give the metal oxide layer and the gate layer a first pattern;
[0045] S50, the first insulating layer is etched to give the first insulating layer a first pattern, and the orthogonal projection of the gate layer on the substrate is made to completely coincide with the orthogonal projection of the first insulating layer on the substrate.
[0046] S60, a second insulating layer is prepared on the surface of the metal oxide layer away from the gate layer, and a first through-hole is formed in the second insulating layer, wherein the orthogonal projection of the first through-hole on the substrate is located within the orthogonal projection of the metal oxide layer on the substrate.
[0047] S70, a metal layer is prepared on the surface of the second insulating layer away from the metal oxide layer, so that the metal layer is connected to the metal oxide layer based on the first through hole, and the metal layer is etched to give the metal layer a second pattern.
[0048] When performing step S30, the following steps are specifically executed:
[0049] S31, a first mask is attached to the surface of the metal oxide layer away from the gate layer. The first mask has a window that matches the shape of the first pattern. The specific shape of the first pattern can be set with reference to the display panel function and wiring distribution. The mask corresponding to the first pattern in the first mask is retained, and the remaining positions form windows for subsequent etching steps.
[0050] S32, the materials corresponding to the window positions in the metal oxide layer and the gate layer are etched sequentially to give the metal oxide layer and the gate layer a first pattern; the metal oxide layer and the gate layer are etched using a first mask with a window, the material corresponding to the window position is etched away, while the position covered by the mask is retained, thus forming the first pattern; in the specific etching process, different etching methods are selected according to the different materials of the metal oxide layer and the gate layer. Since the two are stacked, only the same first mask is used for etching;
[0051] S33, the first mask on the surface of the metal oxide layer is peeled off.
[0052] When preparing the first via, a second mask can be used to etch the second insulating layer, i.e., etch away the material at the location where the first via needs to be formed, thus creating a via penetrating the second insulating layer. Specifically, during the creation of the first via, the second mask is used to etch the second insulating layer at the corresponding location. The second mask is mainly fixed to the surface of the second insulating layer by PR adhesive. During dry etching, ions bombard the second insulating layer material and the PR adhesive simultaneously. Since the metal oxide layer in this embodiment shields the metal of the gate layer, it prevents the metal material from accumulating on the precipitates generated by the PR adhesive during bombardment. Therefore, the precipitates will not remain at the bottom of the first via to form polymers. The precipitates formed at the upper edge of the first via (i.e., the edge near the PR adhesive) will be cleaned away by the cleaning solution during the peeling operation of the second mask, thereby solving the problem of polymer formation during ILD etching, avoiding the impact of explosion points on the optical detection effect of the display panel, and achieving the effect of improving the yield and quality of the display panel.
[0053] After the metal layer is prepared, a protective layer can be further prepared on its surface to insulate and protect the underlying circuitry. This protective layer can also serve as a planarization layer to facilitate the installation of other layers or structures in the display panel. Its thickness is typically between 3000 and 5000 angstroms. Additionally, the display panel may include other layered structures such as an active layer, color filter array, pixel array, and encapsulation cover. This embodiment does not describe the preparation process for these layers; in actual preparation, conventional methods can be followed.
[0054] The third embodiment of this disclosure provides an electronic device that includes at least the display panel provided in the first embodiment of this disclosure, thereby improving the overall yield and quality of the electronic device. The electronic device in this embodiment mainly refers to a large-size, high-resolution display device, such as a 95-inch 8K resolution television. The electronic device may also include modules or components for implementing other functions, which can be added according to the corresponding functions.
[0055] The foregoing has provided a detailed description of several embodiments of this disclosure. However, this disclosure is not limited to these specific embodiments. Those skilled in the art can make various variations and modifications based on the concept of this disclosure, and all such variations and modifications should fall within the scope of protection claimed by this disclosure.
Claims
1. A display panel, characterized in that, include: substrate; A buffer layer is disposed on one side surface of the substrate; A first insulating layer is disposed on the surface of the buffer layer away from the substrate, the first insulating layer having a first pattern; A gate layer disposed on the surface of the first insulating layer away from the buffer layer, wherein the orthographic projection of the gate layer on the substrate completely coincides with the orthographic projection of the first insulating layer on the substrate; A metal oxide layer disposed on the surface of the gate layer away from the insulating layer, wherein the orthographic projection of the metal oxide layer on the substrate completely coincides with the orthographic projection of the gate layer on the substrate; A second insulating layer is disposed on the surface of the metal oxide layer away from the gate layer. The second insulating layer includes at least a first through-hole penetrating the second insulating layer. The orthographic projection of the first through-hole on the substrate is located within the orthographic projection of the metal oxide layer on the substrate. A metal layer is disposed on the surface of the second insulating layer away from the metal oxide layer. The metal layer has a second pattern, and the orthogonal projection of the second pattern on the substrate completely covers the orthogonal projection of the first through hole on the substrate, so that the metal layer is connected to the metal oxide layer through the first through hole.
2. The display panel according to claim 1, characterized in that, The metal oxide layer is made based on indium tin oxide or zinc oxide material doped with aluminum.
3. The display panel according to claim 1, characterized in that, The thickness of the metal oxide layer is between 300 and 700 angstroms.
4. The display panel according to claim 3, characterized in that, The thickness of the metal oxide layer is 450 angstroms.
5. The display panel according to any one of claims 1 to 4, characterized in that, Also includes: A protective layer is disposed on the surface of the metal layer away from the second insulating layer.
6. A method for manufacturing a display panel, characterized in that, include: A substrate is provided, and a buffer layer is formed on one surface of the substrate; A first insulating layer is prepared on the surface of the buffer layer away from the substrate; A gate layer and a metal oxide layer are sequentially formed on the surface of the first insulating layer away from the buffer layer; The metal oxide layer and the gate layer are etched using a first mask to give the metal oxide layer and the gate layer a first pattern; The first insulating layer is etched to give it the first pattern, and the orthographic projection of the gate layer on the substrate is made to completely coincide with the orthographic projection of the first insulating layer on the substrate. A second insulating layer is formed on the surface of the metal oxide layer away from the gate layer, and a first through-hole is formed in the second insulating layer, wherein the orthographic projection of the first through-hole on the substrate is located within the orthographic projection of the metal oxide layer on the substrate; A metal layer is prepared on the surface of the second insulating layer away from the metal oxide layer, such that the metal layer is connected to the metal oxide layer through the first via, and the metal layer is etched to give the metal layer a second pattern.
7. The preparation method according to claim 6, characterized in that, The step of etching the metal oxide layer and the gate layer using a first mask to give the metal oxide layer and the gate layer a first pattern includes: The first mask is attached to the surface of the metal oxide layer away from the gate layer, and the first mask has a window that matches the shape of the first pattern. The materials in the metal oxide layer and the gate layer corresponding to the window are etched sequentially to give the metal oxide layer and the gate layer a first pattern; The first mask on the surface of the metal oxide layer is peeled off.
8. The preparation method according to claim 6, characterized in that, The thickness of the metal oxide layer is between 300 and 700 angstroms.
9. The preparation method according to any one of claims 6 to 8, characterized in that, After fabricating a metal layer on the surface of the second insulating layer away from the metal oxide layer, connecting the metal layer to the metal oxide layer via the first via, and etching the metal layer to give it a second pattern, the method further includes: A protective layer is prepared on the surface of the metal layer on the side away from the second insulating layer.
10. An electronic device comprising at least a display panel as claimed in any one of claims 1 to 5.