Method and apparatus for measuring delay skew of digital channels, electronic device

Abstract

The application relates to a delay deviation measurement method and device of a digital channel, and an electronic device. The method comprises the following steps: synchronously transmitting a preset periodic waveform signal from the head ends of a first digital channel and a second digital channel to be measured; obtaining N clock signals, wherein the phase of a later clock signal in the N clock signals is delayed from a former clock signal by a first preset clock period; sampling the tail end of the first digital channel to obtain at least P first sampling signals; sampling the tail end of the second digital channel to obtain at least Q second sampling signals; and determining the phase deviation value of the signals output from the tail ends of the two digital channels based on the at least P first sampling signals and the at least Q second sampling signals. Through the application, the problems of high measurement cost, complex measurement process and low fault tolerance in the related art for measuring the delay deviation between multiple channels are solved, and the measurement cost and the measurement complexity are reduced when the delay deviation between multiple channels is measured.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of calibration verification, and particularly relates to a method and device for measuring delay deviation of a digital channel, and an electronic device. BACKGROUND

[0002] As a special device for detecting the function and performance of a chip, ATE (Automatic Test Equipment) has a high precision standard in performance detection. In particular, there is a Timing calibration technology for digital resources in the ATE device, and the calibration precision directly affects the overall test precision and test capability of the device. The calibration precision is generally the time deviation value between multiple channels.

[0003] Currently, the method for measuring the deviation value between multiple channels is to measure by using a high-cost measuring device such as a high-speed oscilloscope. The measured signal and the reference signal are input to a special device at one time by using a mechanical arm, and then the measurement result is read. Or, the measured signal is introduced into a high-precision time measurement chip at one time by using a multi-way relay switch, and then the result is read. It can be seen that the method for measuring the deviation value between multiple channels in the related art has the problems of high measurement cost, complex measurement process, and low fault tolerance, and is not suitable for measurement. Therefore, there is no effective solution to the problem of high measurement cost, complex measurement process, and low fault tolerance in the related art for measuring the delay deviation between multiple channels. SUMMARY

[0004] In this embodiment, a method and device for measuring delay deviation of a digital channel, and an electronic device are provided to solve the problem of high measurement cost, complex measurement process, and low fault tolerance in the related art for measuring the delay deviation between multiple channels.

[0005] In a first aspect, a method for measuring delay skew of digital channels is provided in the embodiments. The method includes: transmitting a preset periodic waveform signal synchronously from a head end of a first digital channel and a second digital channel to be measured; obtaining N clock signals, a phase of a later clock signal in the N clock signals being delayed from a phase of an earlier clock signal by a first preset clock period; sampling at least P first sampling signals at an end of the first digital channel based on rising edges of at least the first P clock signals in the N clock signals, a Pth first sampling signal in the at least P first sampling signals being an all-zero signal; sampling at least Q second sampling signals at an end of the second digital channel based on rising edges of at least the first Q clock signals in the N clock signals, a Qth second sampling signal in the at least Q second sampling signals being an all-zero signal; and determining a phase skew value of signals output at the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P, and Q are positive integers greater than or equal to 3.

[0006] In one of the embodiments, a pulse width of the preset periodic waveform signal is greater than half a clock period, and a period of the periodic waveform is not less than three clock periods.

[0007] In another embodiment, the determining of the phase skew value of the signals output at the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals includes:

[0008] determining a phase relationship of the signals output at the ends of the first digital channel and the second digital channel based on a Rth first sampling signal in the at least P first sampling signals and a Rth second sampling signal in the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the Rth first sampling signal and the Rth second sampling signal are both non-all-zero signals; determining a number of the first preset clock periods of the phase skew of the signals output at the ends of the first digital channel and the second digital channel based on a number of the non-all-zero signals in the at least P first sampling signals and a number of the non-all-zero signals in the at least Q second sampling signals; and determining the phase skew value of the signals output at the ends of the first digital channel and the second digital channel based on the phase relationship of the signals output at the ends of the first digital channel and the second digital channel and the number of the first preset clock periods.

[0009] In one of the embodiments, the determining the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel based on the Rth first sampling signal among the at least P first sampling signals and the Rth second sampling signal among the at least Q second sampling signals comprises: in the case that the binary value obtained by shifting the binary value of the Rth first sampling signal to the right by one bit is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal outputted at the end of the first digital channel is one clock cycle earlier than the phase of the signal outputted at the end of the second digital channel; in the case that the binary value obtained by shifting the binary value of the Rth first sampling signal to the left by one bit is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal outputted at the end of the first digital channel is one clock cycle later than the phase of the signal outputted at the end of the second digital channel; in the case that the binary value of the Rth first sampling signal is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal outputted at the end of the first digital channel is in the same clock cycle as the phase of the signal outputted at the end of the second digital channel.

[0010] In another embodiment, the binary value of the Rth first sampling signal is determined by the sampling values corresponding to all the sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to all the sampling points in the Rth second sampling signal.

[0011] In one of the embodiments, the binary value of the Rth first sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the Rth second sampling signal; wherein the positions of the continuous partial sampling points in the Rth first sampling signal and the positions of the continuous partial sampling points in the Rth second sampling signal correspond to each other, and the binary value of the Rth first sampling signal and the binary value of the Rth second sampling signal are not equal to zero.

[0012] In another embodiment, the determining the phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel based on the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel and the number of the first preset clock cycles comprises: the phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel and the clock cycle, plus the product of the number of the first preset clock cycles and the first preset clock cycle.

[0013] In one of the embodiments, if the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel is that the phase of the signal outputted at the end of the first digital channel is earlier than the phase of the signal outputted at the end of the second digital channel by one clock cycle, the representative value of the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel is 1; if the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel is that the phase of the signal outputted at the end of the first digital channel is later than the phase of the signal outputted at the end of the second digital channel by one clock cycle, the representative value of the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel is -1; if the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel is that the phase of the signal outputted at the end of the first digital channel is in the same clock cycle as the phase of the signal outputted at the end of the second digital channel, the representative value of the phase relationship between the signals outputted at the ends of the first digital channel and the second digital channel is 0.

[0014] In a second aspect, a device for measuring delay deviation of digital channels is provided in the embodiments, and the device comprises:

[0015] The signal sending module is configured to send a preset periodic waveform signal synchronously from the first digital channel and the second digital channel to be measured; the clock cycle obtaining module is configured to obtain N clock signals, a phase of a later clock signal in the N clock signals being delayed from a phase of an earlier clock signal by a first preset clock cycle; the first sampling signal sampling module is configured to sample at least P first sampling signals at an end of the first digital channel based on rising edges of at least P clock signals in the N clock signals, a Pth first sampling signal in the at least P first sampling signals being a full-zero signal; the second sampling signal sampling module is configured to sample at least Q second sampling signals at an end of the second digital channel based on rising edges of at least Q clock signals in the N clock signals, a Qth second sampling signal in the at least Q second sampling signals being a full-zero signal; and the deviation value calculating module is configured to determine a phase deviation value of signals outputted at the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are positive integers greater than or equal to 3.

[0016] In a third aspect, an electronic device is provided in the embodiments, which comprises a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the method for measuring delay deviation of digital channels according to the first aspect when running the computer program.

[0017] Compared with the related art, the delay deviation measurement method of the digital channel provided in the embodiment is characterized in that: a preset periodic waveform signal is synchronously transmitted from the head ends of a first digital channel and a second digital channel to be measured; N clock signals are acquired, a phase of a later clock signal in the N clock signals is delayed by a first preset clock period compared with a phase of an earlier clock signal; at least P first sampling signals are respectively sampled at a tail end of the first digital channel based on at least the first P clock signals in the N clock signals, the at least P first sampling signals include at least one all-zero signal and at least one non-all-zero signal; at least Q second sampling signals are respectively sampled at a tail end of the second digital channel based on at least the first Q clock signals in the N clock signals, the at least Q second sampling signals include at least one all-zero signal and at least one non-all-zero signal; and a phase deviation value of signals output at the tail ends of the first digital channel and the second digital channel is determined based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are positive integers, and P and Q are not greater than N, thereby solving the problem of high measurement cost or complex measurement process and low fault tolerance rate in the related art for measuring delay deviation among multiple channels, and achieving the purpose of reducing measurement cost and measurement complexity when measuring delay deviation among multiple channels.

[0018] The details of one or more embodiments of the application are set forth in the accompanying drawings and the description below. Other features, objects, and advantages of the application will be apparent from the description of the application and from the drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0019] The accompanying drawings, which are included to provide a further understanding of the application and are incorporated in and constitute a part of this application, illustrate embodiments of the application and serve to explain the application. In the drawings:

[0020] Figure 1 is a flow chart of the delay deviation measurement method of the digital channel according to an embodiment of the application.

[0021] Figure 2 is a sampling signal schematic diagram of the delay deviation measurement method of the digital channel according to an embodiment of the application.

[0022] Figure 3 is a phase relationship representation diagram of the delay deviation measurement method of the digital channel according to an embodiment of the application.

[0023] Figure 4 is a general measurement flow structure schematic diagram of the delay deviation measurement device of the digital channel according to an embodiment of the application.

[0024] Figure 5 is a functional module schematic diagram of each part of the delay deviation measurement device of the digital channel according to an embodiment of the application.

[0025] Figure 6 is a structure block diagram of a delay deviation measurement device of a digital channel of an embodiment of the present application. DETAILED DESCRIPTION

[0026] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and explained below in conjunction with the accompanying drawings and embodiments.

[0027] Unless otherwise defined, technical terms or scientific terms used in the present application shall have the general meaning understood by a person with ordinary skill in the art to which the present application belongs. In the present application, "one", "a", "an", "the", "these" and similar words do not represent a quantitative limitation, and they can be singular or plural. In the present application, the terms "include", "contain", "have" and any variants thereof are intended to cover non-exclusive inclusion; for example, a process, method and system, product or device containing a series of steps or modules (units) are not limited to the listed steps or modules (units), but can include steps or modules (units) not listed, or can include other steps or modules (units) inherent to the process, method, product or device. In the present application, the terms "connected", "connected", "coupled" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. In the present application, "multiple" means two or more. The association between the associated objects is described by "and / or", which means that there can be three relationships, for example, "A and / or B" can mean that A exists alone, A and B exist together, and B exists alone. In general, the character " / " represents an "or" relationship between the associated objects. In the present application, the terms "first", "second", "third" and the like are only used to distinguish similar objects, and do not represent a specific order for the objects.

[0028] In the present embodiment, a digital channel delay deviation measurement method is provided, Figure 1 is a flow chart of a digital channel delay deviation measurement method of an embodiment of the present application, as Figure 1 shown, the flow includes the following steps:

[0029] Step S201, a preset periodic waveform signal is synchronously transmitted from the head ends of the first digital channel and the second digital channel to be measured.

[0030] The purpose of the embodiment is to measure the delay deviation between the two digital channels, based on which, it can be understood that if there is a delay deviation between the two digital channels, then when the two digital channels transmit the same signal, the time when the signal transmitted at the head of the channel is received at the tail of the channel is different. Therefore, the embodiment first synchronously transmits a preset periodic waveform signal at the head of the first digital channel and the second digital channel. The waveform of the preset periodic waveform signal in the embodiment is periodically changed. In addition, in addition to being periodically changed, the period length and the wavelength of the periodic waveform signal can also be set according to specific embodiments, as long as the signal transmitted to the first digital channel and the second digital channel is a periodic signal.

[0031] In step S202, N clock signals are obtained, and a phase of a later clock signal in the N clock signals is delayed from a phase of an earlier clock signal by a first preset clock period.

[0032] It can be understood that in the last step, the preset periodic waveform signal is transmitted to the head of the first digital channel and the second digital channel, then the preset periodic signal is output at the end of the digital channel, and then the deviation value is obtained based on the signal received from the end. However, when the signal is received, the unit of the deviation value is small, and the deviation of the two cannot be directly obtained. Based on this, the embodiment samples the periodic waveform signal by the clock signal, and the signal difference obtained by sampling by the clock signal is easier to calculate. In the embodiment, N clock signals are first obtained, and every two adjacent clock signals in the N clock signals have a delay relationship. In the embodiment, the delay value can be arbitrarily set. The first preset clock period can be 1 / N clock period, or an arbitrarily set delay period length. As long as the period length of the first preset clock period is less than 1 standard clock period, the delay clock signal can more accurately sample the periodic signal to obtain the delay between the channels without extremely small clock signals. Therefore, in the embodiment, N clock signals are obtained, and the delay between every two adjacent signals in the N clock signals is the first preset clock period. In addition, the delay between the first clock signal and the last clock signal is not more than 1 clock period.

[0033] In step S203, based on rising edges of at least P clock signals in the N clock signals, at least P first sampling signals are respectively sampled at the end of the first digital channel, and the Pth first sampling signal in the at least P first sampling signals is a full-zero signal.

[0034] In the embodiment, the N clock signals obtained in the above embodiment are used to sample the preset periodic waveform signal received by the first digital channel end from the first digital channel head end. In the embodiment, the preset periodic waveform signal is sampled by the rising edge of the clock signal. It can be understood that when sampling the first digital channel end, each sampling will obtain a first sampling signal. N clock signals can sample N first sampling signals. When there are at least one all-zero signal and at least one non-all-zero signal in the first sampling signal, the phase deviation value can be calculated. Therefore, after sampling the first digital channel end by the first P clock signals, at least P first sampling signals are obtained, and at least the Pth signal is an all-zero signal, so that the sampling can be completed. It can be understood that the first sampling signal includes a plurality of sampling data, and the sampling data includes zero value sampling data and non-zero value sampling data. When the clock signal is at the rising edge, if the periodic waveform signal is high, the sampling data is non-zero value; if the periodic waveform signal is not high, the sampling data is zero value. If all the sampling data in the sampling signal are zero value, the sampling signal is all-zero signal; if there is non-zero value in the sampling data in the sampling signal, the sampling signal is non-all-zero signal.

[0035] In step S204, at least Q rising edges of the N clock signals are used to sample the second digital channel end to obtain at least Q second sampling signals, and the at least Q second sampling signals include at least one all-zero signal and at least one non-all-zero signal. The Qth second sampling signal in the at least Q second sampling signals is an all-zero signal.

[0036] In step S203, the second digital channel end is sampled by at least Q clock signals in the N clock signals. The Q second sampling signals obtained by the at least Q clock signals include at least one all-zero signal and at least one non-all-zero signal, so that the delay deviation of the second sampling signal can be measured.

[0037] In step S205, the phase deviation value of the signals output by the first digital channel end and the second digital channel end is determined based on the at least P first sampling signals and the at least Q second sampling signals. N, P and Q are all positive integers greater than or equal to 3.

[0038] In the embodiment, the at least P first sampling signals and the at least Q second sampling signals are used to compare the sampling signals between the two channels. Further, the phase relationship between the two channels is determined based on the comparison result. The number of non-all-zero signals and all-zero signals in the two signals is used to calculate the phase deviation value, so as to obtain the phase deviation value between the two channels.

[0039] Through the above steps, a preset periodic waveform signal is first sent to the beginning of the first digital channel and the second digital channel. Then, multiple adjacent clock signals with the same delay are acquired. The ends of the first digital channel and the second digital channel are sampled to obtain the first sampled signal and the second sampled signal. Then, the phase deviation value of the first digital channel and the second digital channel is calculated based on the first sampled signal and the second sampled signal. This solves the problems of high measurement cost or complex measurement process and low fault tolerance in the related technology for measuring the delay deviation between multiple channels. It realizes the reduction of measurement cost and measurement complexity when measuring the delay deviation between multiple channels.

[0040] In one embodiment, the pulse width of the preset periodic waveform signal is greater than half a clock cycle, and the period of the periodic waveform is not less than three clock cycles.

[0041] like Figure 2 As shown, in this embodiment, to ensure normal signal sampling, the pulse width of the periodic waveform needs to be set to be greater than half a clock cycle. Based on this, the sampling process avoids acquiring the same high level of the waveform signal over multiple clock cycles, ensuring that the preset periodic waveform signal is sampled by the clock signal at the end of the digital channel. Furthermore, in this embodiment, determining the phase relationship between the two channels using the first and second sampling signals requires that the sampling signal includes at least three sets of sampling data. The number of sampling data sets is determined by the ratio of the periodic waveform's period to the clock cycle. To ensure at least three sets of sampling data are obtained, the periodic waveform's period needs to be at least three clock cycles to guarantee the phase relationship determination and normal signal sampling. Therefore, the accuracy of signal sampling and the accuracy of phase relationship determination can be improved.

[0042] In another embodiment, the determining the phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals comprises: determining the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel based on an Rth first sampling signal in the at least P first sampling signals and an Rth second sampling signal in the at least Q second sampling signals, where R is a positive integer not greater than P and Q, and the Rth first sampling signal and the Rth second sampling signal are both non-all-zero signals; determining the number of first preset clock periods of the phase deviation of the signals outputted at the ends of the first digital channel and the second digital channel based on the number of non-all-zero signals in the at least P first sampling signals and the number of non-all-zero signals in the at least Q second sampling signals; and determining the phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel based on the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel and the number of first preset clock periods.

[0043] It can be understood that, in the embodiment, the phase deviation value is obtained based on the at least P first sampling signals and the at least Q second sampling signals. First, the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is determined based on the first sampling signal and the second sampling signal obtained based on the same clock signal, i.e., the Rth first sampling signal in the at least P first sampling signals and the Rth second sampling signal in the at least Q second sampling signals. In the embodiment, the phase relationship is determined based on the values of the two sampling signals and a preset phase relationship table. The phase relationship table is obtained based on known phase relationships and known corresponding signals, and has reference significance. Then, after the phase relationship is determined, the time length of the phase deviation is determined based on the number of non-all-zero signals in the at least P first sampling signals, i.e., the number of non-all-zero signals before the first all-zero signal in the first sampling signal, and the number of non-all-zero signals in the at least Q second sampling signals. The phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel is obtained by calculation based on the phase relationship, the time length, and the signal period unit in the current signal. The phase deviation value obtained based on the method improves the efficiency of obtaining the phase deviation value and reduces the calculation cost.

[0044] In one embodiment, determining the phase relationship between the signals output from the end of the first digital channel and the second digital channel based on the Rth first sampled signal among the at least P first sampled signals and the Rth second sampled signal among the at least Q second sampled signals includes: if the binary value obtained by shifting the binary value of the Rth first sampled signal one bit to the right is the same as the binary value of the Rth second sampled signal, then the phase of the signal output from the end of the first digital channel is determined to be one clock cycle earlier than the phase of the signal output from the end of the second digital channel; if the binary value obtained by shifting the binary value of the Rth first sampled signal one bit to the left is the same as the binary value of the Rth second sampled signal, then the phase of the signal output from the end of the first digital channel is determined to be one clock cycle later than the phase of the signal output from the end of the second digital channel; if the binary value of the Rth first sampled signal is the same as the binary value of the Rth second sampled signal, then the phase of the signal output from the end of the first digital channel and the phase of the signal output from the end of the second digital channel are within the same clock cycle.

[0045] In this embodiment, as Figure 3 As shown, the phase relationship table is determined by shifting the binary values ​​of the sampled signals. Shifting the binary value of the Rth first sampled signal one bit to the right delays it by one clock cycle. In this case, the first sampled signal is the same as the second sampled signal, meaning the phase of the signal output from the first digital terminal is one clock cycle ahead of the phase of the signal output from the second digital channel. Similarly, shifting the binary value of the first sampled signal one bit to the left advances it by one clock cycle. Based on this, if the shifted first sampled signal is the same as the corresponding second sampled signal, the phase of the signal output from the first digital terminal is one clock cycle behind the phase of the signal output from the second digital channel. If no shift is needed and they are the same, then the phases of the signals output from the first and second digital channels are considered to be the same, i.e., within the same cycle. This method improves the efficiency of determining the phase relationship between channels using sampled signals.

[0046] In another embodiment, the binary value of the Rth first sampled signal is determined by the sampled values ​​corresponding to all sampled points in the Rth first sampled signal, and the binary value of the Rth second sampled signal is determined by the sampled values ​​corresponding to all sampled points in the Rth second sampled signal.

[0047] It can be understood that the binary value of the first sampling signal is determined by the sampling values corresponding to all sampling points. That is, when the preset periodic waveform signal received by the first digital channel end through the clock signal is sampled, a series of sampling values are obtained, wherein each sampling value is obtained by the corresponding sampling point; in this embodiment, when each rising edge of the clock signal, the state of the corresponding periodic waveform signal is determined, if it is high, the sampling value is non-zero, if it is low, the sampling value is zero, based on this, a number of binary values in the first sampling signal are obtained, based on the binary values, the sampling result of the periodic waveform signal based on the clock signal can be effectively expressed. The sampling result is more obvious, and the phase judgment and deviation calculation are more easy, which improves the efficiency of calculating the phase deviation.

[0048] In one embodiment, the binary value of the Rth first sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the Rth second sampling signal; wherein the positions of the continuous partial sampling points in the Rth first sampling signal and the continuous partial sampling points in the Rth second sampling signal correspond to each other, and the binary value of the Rth first sampling signal and the binary value of the Rth second sampling signal are not equal to zero.

[0049] In this embodiment, the binary value of the first sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the first sampling signal; it can be understood that each sampling in this embodiment is sampling the periodic waveform signal through the clock signal, therefore, the continuous sampling points correspond to the fixed sampling points of each period of the clock signal, and the sampling values are obtained by sampling the periodic waveform signal through the fixed sampling points. For example, at each rising edge of the clock signal, the periodic waveform signal is sampled, if the sampling result is high, the sampling value is 1, if the sampling result is low, the sampling value is 0, therefore, the sampling of the first digital channel end and the sampling of the second digital channel end are the same sampling mode. In addition, since the phase relationship cannot be determined by two all-zero sampling signals, the Rth first sampling signal and the second sampling signal for determining the phase relationship need to be non-all-zero sampling signals, based on this, it can be ensured that the phase relationship can be determined.

[0050] In another embodiment, the phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel is determined based on the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel and the number of the first preset clock periods, which comprises that the phase deviation value of the signals outputted at the ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel and the clock period, plus the product of the number of the first preset clock periods and the first preset clock period.

[0051] In the embodiment, the phase deviation value is calculated based on the overall clock phase difference, i.e. based on the phase relationship and the size of the clock period, and then the specific deviation value is calculated by the product of the number of the first preset clock periods and the first preset clock period. It can be understood that the number of the first preset clock periods can be replaced by a negative number, i.e. when the number of the non-all-zero signals in the first sampling signal is less than the number of the non-all-zero signals in the second sampling signal, the number of the first preset clock periods is negative. Then the specific value of the phase deviation value is determined by the number of the first preset clock periods. It can be understood that the more the number of the first preset clock periods, the greater the deviation value, and the greater the first preset clock period, the greater the deviation value. Based on this, the size of the phase deviation value can be more accurately calculated, and the calculation error can be reduced.

[0052] In one of the embodiments, if the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is that the phase of the signal outputted at the end of the first digital channel is one clock period earlier than the phase of the signal outputted at the end of the second digital channel, then the representative value of the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is 1; if the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is that the phase of the signal outputted at the end of the first digital channel is one clock period later than the phase of the signal outputted at the end of the second digital channel, then the representative value of the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is -1; if the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is that the phase of the signal outputted at the end of the first digital channel is in the same clock period as the phase of the signal outputted at the end of the second digital channel, then the representative value of the phase relationship of the signals outputted at the ends of the first digital channel and the second digital channel is 0.

[0053] It is easy to understand that if the phase of the signal outputted at the end of the first digital channel is one clock cycle earlier than the phase of the signal outputted at the end of the second digital channel, the deviation value of the first digital channel and the second digital channel should be calculated on the basis of 1 clock cycle, and based on this, the phase representative value is 1; similarly, if the phase of the signal outputted at the end of the first digital channel is one clock cycle later than the phase of the signal outputted at the end of the second digital channel, the deviation value of the first digital channel and the second digital channel should be calculated on the basis of -1 clock cycle; if the phase of the signal outputted at the end of the first digital channel is in the same clock cycle as the phase of the signal outputted at the end of the second digital channel, the deviation value is 0 clock cycle, and on this basis, the specific deviation value is calculated through the number of the first preset clock cycles and the first preset clock cycle, to ensure the accurate calculation of the final deviation value.

[0054] In the embodiment, the delay deviation measurement process of a specific digital channel is as shown in Figure 4 The measurement device CHK_TCT mainly measures the delay deviation of the signals received by the POGO connector through the simultaneous transmission of the drivers in the Pin electronc among multiple channels (TC[255:0]) in the embodiment, and calculates the deviation values between the remaining channels and T0 by parallel measurement of the signals received by the POGO connector through CHK_TCT, taking T0 as the reference.

[0055] In one specific embodiment, as shown in Figure 5The delay deviation measurement method of the digital channel is designed to automatically measure the mutual time difference of 256 signals output by a digital single board in an ATE device to a connector. The basic components are as follows. The external interface can be an SPI interface responsible for communication with the host or other communication interfaces responsible for communication with the host. The TC[255:0] interface is connected to the measured signal. The remaining interfaces are all internal interfaces. The main components are described as follows: 1. The measurement unit is the core device of the FPGA, which is responsible for sampling and algorithm processing of the measured signal and communication with the host; 2. The clock PLL chip outputs a sampling clock with adjustable frequency, and the default is 200MHz, with extremely low clock jitter performance; 3. The DelayLine chip is used to delay the clock phase output by the PLL chip, and then provide it to the FPGA as a sampling clock. The chip delay step is 10ps, that is, the measurement resolution, and the maximum delay step is 1023 steps; 4. The Flash chip stores the FPGA loading file; 5. The Flash chip stores the time-related calculation results; 6. The crystal oscillator is used as the FPGA system clock to realize the management channels of SPI and I2C; 7. The DAC chip outputs an adjustable voltage signal as the decision level of the I / O pin of the FPGA. The measurement method is implemented in the FPGA inside the Measure Unit, and the internal implementation logic is shown in the following figure. The measured signal is first introduced into the chip through the I / O pin and then enters the IODELAY module. The main function of the module is to adjust the wiring delay of the chip pin to the flip-flop FF and the delay difference between the Sample Clock and different flip-flops to avoid introducing additional delay errors. The signal output by the flip-flop sampling is calculated and processed by the algorithm logic unit to obtain the final deviation value. The basic principle of the measurement algorithm is to compare the delay difference between channels by measuring the position deviation between the edges of the signal and the rising edge of the clock. The measured signal is first introduced into the chip through the I / O pin and then enters the IODELAY module. The main function of the module is to adjust the wiring delay of the chip pin to the flip-flop FF and the delay difference between the Sample Clock and different flip-flops to avoid introducing additional delay errors. The signal output by the flip-flop sampling is calculated and processed by the algorithm logic unit to obtain the final deviation value. The basic principle of the measurement algorithm is to compare the delay difference between channels by measuring the position deviation between the edges of the signal and the rising edge of the clock. Figure 2For example: ① use the Pattern Generator to send a specific code type of periodic waveform, the specific requirements are that the pulse width needs to be greater than half a clock cycle and less than one clock cycle, and the signal period needs to be at least 3 clock cycles, which can be determined according to the maximum deviation of the measured signal; ② 0, 1, 2, 3, and 4 are different phase sampling clocks in the Measure Unit FPGA, and the DelayLine chip is used to realize clock phase adjustment. In the following figure, 0 is the initial sampling clock, the DelayLine chip is set to 0ps delay time, 1 is the sampling clock after the DelayLine chip is set to 10ps delay time, 2, 3, and 4 are sequentially increased by 10ps delay; ③ use 0, 1, 2, 3, and 4 clock sampling in turn, until all channels appear data from non-0 to all 0 stop, get several sampling signals; ④ calculate according to the sampling result, first judge the phase relationship between channels through the first three codes of the same sampling data, then add the difference of the sampling times to get the time difference between channels, and the phase relationship table is as shown in Figure 3 ; ⑤ take TC0 as the reference, the sampling code of TC255 is 001 at the 0th sampling, TC0 is 100, which indicates that TC255 is one clock cycle earlier than TC0, and the sampling times are one more than TC0, so the final deviation value is: T255 = T0 - 5ns (clock cycle) + 1*10ps.

[0056] It should be noted that the steps shown in the above flow or the flowchart of the accompanying drawings can be executed in a computer system such as a set of computer executable instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from here.

[0057] In this embodiment, a digital channel delay deviation measurement device is also provided, which is used to realize the above-mentioned embodiments and preferred embodiments, and the description of which has been described above. The terms "module", "unit", "sub-unit" and the like used below can be a combination of software and / or hardware that realizes a predetermined function. Although the device described in the following embodiments is preferably realized in software, hardware, or a combination of software and hardware is also possible and is conceived.

[0058] Figure 6 is a structure block diagram of the digital channel delay deviation measurement device of an embodiment of the present application, as shown in Figure 3 , the device comprises: a to-be-measured signal sending module 10, a clock period acquisition module 20, a first sampling signal sampling module 30, a second sampling signal sampling module 40, and a deviation value calculation module 50.

[0059] The signal to be measured sending module 10 is configured to send a preset periodic waveform signal from the first digital channel and the second digital channel to be measured.

[0060] The clock period obtaining module 20 is configured to obtain N clock signals, wherein a phase of a later clock signal is delayed from a phase of an earlier clock signal by a first preset clock period.

[0061] The clock period obtaining module 20 is further configured to set a pulse width of the preset periodic waveform signal to be greater than half a clock period, and set a period of the periodic waveform to be not less than three clock periods.

[0062] The first sampling signal sampling module 30 is configured to sample at least P first sampling signals at an end of the first digital channel based on rising edges of at least the first P clock signals of the N clock signals, wherein a Pth first sampling signal of the at least P first sampling signals is a full zero signal.

[0063] The second sampling signal sampling module 40 is configured to sample at least Q second sampling signals at an end of the second digital channel based on rising edges of at least the first Q clock signals of the N clock signals, wherein a Qth second sampling signal of the at least Q second sampling signals is a full zero signal.

[0064] The deviation value calculating module 50 is configured to determine a phase deviation value of signals output at the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are positive integers greater than or equal to 3.

[0065] The deviation value calculating module 50 is further configured to determine a phase relationship of the signals output at the ends of the first digital channel and the second digital channel based on a Rth first sampling signal of the at least P first sampling signals and a Rth second sampling signal of the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the Rth first sampling signal and the Rth second sampling signal are both non-full zero signals; determine a number of the first preset clock periods of the phase deviation of the signals output at the ends of the first digital channel and the second digital channel based on a number of non-full zero signals of the at least P first sampling signals and a number of non-full zero signals of the at least Q second sampling signals; and determine the phase deviation value of the signals output at the ends of the first digital channel and the second digital channel based on the phase relationship of the signals output at the ends of the first digital channel and the second digital channel and the number of the first preset clock periods.

[0066] The bias value calculation module 50 further comprises: in the case that the binary value obtained by shifting the binary value of the Rth first sampling signal to the right by one bit is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal output at the end of the first digital channel is one clock cycle earlier than the phase of the signal output at the end of the second digital channel; in the case that the binary value obtained by shifting the binary value of the Rth first sampling signal to the left by one bit is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal output at the end of the first digital channel is one clock cycle later than the phase of the signal output at the end of the second digital channel; and in the case that the binary value of the Rth first sampling signal is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal output at the end of the first digital channel is in the same clock cycle as the phase of the signal output at the end of the second digital channel.

[0067] The bias value calculation module 50 further comprises: the binary value of the Rth first sampling signal is determined by the sampling values corresponding to all sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to all sampling points in the Rth second sampling signal.

[0068] The bias value calculation module 50 further comprises: the binary value of the Rth first sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to the continuous partial sampling points in the Rth second sampling signal; wherein the positions of the continuous partial sampling points in the Rth first sampling signal and the continuous partial sampling points in the Rth second sampling signal correspond to each other, and the binary value of the Rth first sampling signal and the binary value of the Rth second sampling signal are not equal to zero.

[0069] The bias value calculation module 50 further comprises: the phase bias value of the signals output at the ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relationship of the signals output at the ends of the first digital channel and the second digital channel and the clock cycle, plus the product of the number of the first preset clock cycles and the first preset clock cycle.

[0070] The bias value calculation module 50 further comprises: if the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel is one clock cycle earlier than the phase of the signal output at the end of the second digital channel, then the phase relationship between the signals output at the ends of the first digital channel and the second digital channel represents a value of 1; if the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel is one clock cycle later than the phase of the signal output at the end of the second digital channel, then the phase relationship between the signals output at the ends of the first digital channel and the second digital channel represents a value of -1; if the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel is within the same clock cycle as the phase of the signal output at the end of the second digital channel, then the phase relationship between the signals output at the ends of the first digital channel and the second digital channel represents a value of 0.

[0071] It should be noted that each of the above modules can be a functional module or a program module, and can be implemented by software or hardware. For the modules implemented by hardware, each of the above modules can be located in the same processor; or each of the above modules can also be located in different processors in any combination.

[0072] The embodiment also provides an electronic device including a memory and a processor, the memory storing a computer program, and the processor being configured to execute the computer program to perform the steps in any of the above method embodiments.

[0073] Optionally, the electronic device can further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0074] Optionally, in the embodiment, the processor can be configured to execute the following steps by the computer program:

[0075] S1, synchronously transmitting a preset periodic waveform signal from the first digital channel and the second digital channel to be measured.

[0076] S2, obtaining N clock signals, wherein a phase of a later clock signal in the N clock signals is delayed by a first preset clock cycle compared with a phase of an earlier clock signal.

[0077] S3, based on rising edges of at least P clock signals in the N clock signals, sampling at least P first sampling signals at an end of the first digital channel, respectively, and a Pth first sampling signal in the at least P first sampling signals is a full-zero signal.

[0078] S4, sampling at least Q second sampling signals at the end of the second digital channel based on rising edges of at least the first Q clock signals in the N clock signals, wherein the Qth second sampling signal in the at least Q second sampling signals is an all-zero signal.

[0079] S5, determining a phase deviation value of signals outputted at the end of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are positive integers greater than or equal to 3.

[0080] It should be noted that the specific examples in the embodiment can refer to the examples described in the above embodiments and optional implementation manners, and will not be described herein again.

[0081] In addition, in combination with the digital channel delay deviation measurement method provided in the above embodiments, a storage medium can also be provided in the embodiment to implement. The storage medium has a computer program stored thereon; the computer program is executed by a processor to implement any one of the digital channel delay deviation measurement methods in the above embodiments.

[0082] It should be understood that the specific embodiments described herein are only used to explain this application, but not to limit it. According to the embodiments provided in the present application, all other embodiments obtained by those of ordinary skill in the art without creative labor are within the scope of protection of the present application.

[0083] Obviously, the drawings are only some examples or embodiments of the present application, and those of ordinary skill in the art can also apply the present application to other similar situations without creative labor. In addition, it can be understood that although the work done in the development process may be complex and long, some design, manufacture or production changes made by those of ordinary skill in the art according to the technical content disclosed in the present application are only routine technical means and should not be regarded as insufficient disclosure of the present application.

[0084] The word "embodiment" in the present application means that the specific features, structures or characteristics described in combination with the embodiments can be included in at least one embodiment of the present application. The appearance of this phrase in various places in the specification does not necessarily mean the same embodiment, nor does it mean independence or alternative to each other. Those of ordinary skill in the art can clearly or implicitly understand that the embodiments described in the present application can be combined with other embodiments without conflict.

[0085] The above embodiments only express several implementation ways of the present application, and the description is specific and detailed, but it should not be understood as a limitation to the patent protection scope. It should be pointed out that, for ordinary skilled in the art, several modifications and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

Claims

1. A method of measuring delay skew of a digital channel, characterized by, The method comprises the following steps: sending a preset periodic waveform signal from the head ends of the first and second digital channels to be tested synchronously; obtaining N clock signals, wherein the phase of a later clock signal is delayed by a first preset clock period compared with that of a former clock signal; sampling at least P first sampling signals at the tail ends of the first digital channel based on the rising edges of at least the first P clock signals, wherein the Pth first sampling signal is a full zero signal; sampling at least Q second sampling signals at the tail ends of the second digital channel based on the rising edges of at least the first Q clock signals, wherein the Qth second sampling signal is a full zero signal; determining the phase deviation value of the signals output at the tail ends of the first and second digital channels based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are positive integers greater than or equal to 3.

2. The method of measuring delay skew of digital channels according to claim 1, wherein, The pulse width of the preset periodic waveform signal is greater than half a clock period, and the period of the periodic waveform is not less than three clock periods.

3. The method of measuring delay skew of digital channels of claim 2, wherein, The determination of the phase deviation value of the signals output at the tail ends of the first and second digital channels based on the at least P first sampling signals and the at least Q second sampling signals comprises: determining the phase relationship of the signals output at the tail ends of the first and second digital channels based on the Rth first sampling signal among the at least P first sampling signals and the Rth second sampling signal among the at least Q second sampling signals, wherein R is a positive integer not greater than P and Q, and the Rth first sampling signal and the Rth second sampling signal are both non-full zero signals; determining the number of first preset clock periods of the phase deviation of the signals output at the tail ends of the first and second digital channels based on the number of non-full zero signals among the at least P first sampling signals and the number of non-full zero signals among the at least Q second sampling signals; determining the phase deviation value of the signals output at the tail ends of the first and second digital channels based on the phase relationship of the signals output at the tail ends of the first and second digital channels and the number of first preset clock periods.

4. The method of measuring delay skew of digital channels of claim 3, wherein, The determination of the phase relationship of the signals output at the tail ends of the first and second digital channels based on the Rth first sampling signal among the at least P first sampling signals and the Rth second sampling signal among the at least Q second sampling signals comprises: in the case that the binary value obtained by shifting the binary value of the Rth first sampling signal to the right by one bit is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal output at the tail end of the first digital channel is one clock period earlier than that of the signal output at the tail end of the second digital channel. in a case where a binary value of the Rth first sampling signal is the same as a binary value of the Rth second sampling signal, determining that the phase of the signal output at the end of the first digital channel is one clock cycle later than the phase of the signal output at the end of the second digital channel; in a case where the binary value of the Rth first sampling signal is the same as the binary value of the Rth second sampling signal, determining that the phase of the signal output at the end of the first digital channel is in the same clock cycle as the phase of the signal output at the end of the second digital channel.

5. The method of measuring delay skew of digital channels of claim 4, wherein, The binary value of the Rth first sampling signal is determined by the sampling values corresponding to all sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to all sampling points in the Rth second sampling signal.

6. The method of claim 5, wherein the binary value of the Rth first sampling signal is determined by the sampling values corresponding to partial sampling points in the Rth first sampling signal, and the binary value of the Rth second sampling signal is determined by the sampling values corresponding to partial sampling points in the Rth second sampling signal; wherein the positions of the partial sampling points in the Rth first sampling signal and the positions of the partial sampling points in the Rth second sampling signal correspond to each other, and the binary value of the Rth first sampling signal and the binary value of the Rth second sampling signal are not equal to zero.

7. The method of measuring delay skew of digital channels of claim 6, wherein, Based on the phase relationship between the signals output at the ends of the first digital channel and the second digital channel, and the number of the first preset clock cycles, determining the phase deviation value of the signals output at the ends of the first digital channel and the second digital channel includes: The phase deviation value of the signals output at the ends of the first digital channel and the second digital channel is equal to the product of the representative value of the phase relationship between the signals output at the ends of the first digital channel and the second digital channel and the clock cycle, plus the product of the number of the first preset clock cycles and the first preset clock cycle.

8. The method of claim 7, wherein if the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel is one clock cycle earlier than the phase of the signal output at the end of the second digital channel, the representative value of the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is 1; if the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel is one clock cycle later than the phase of the signal output at the end of the second digital channel, the representative value of the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is -1; If the phase relationship between the signals at the ends of the first digital channel and the second digital channel is that the phase of the signal output at the end of the first digital channel and the phase of the signal output at the end of the second digital channel are in the same clock cycle, then the phase relationship between the signals output at the ends of the first digital channel and the second digital channel is represented by a value of 0.

9. A device for measuring delay skew of digital channels, characterized by The method comprises the steps of: a signal sending module for sending a preset periodic waveform signal from the head ends of the first digital channel and the second digital channel to be tested synchronously; a clock cycle obtaining module for obtaining N clock signals, wherein the phase of a later clock signal in the N clock signals is delayed by a first preset clock cycle compared with the phase of an earlier clock signal; a first sampling signal sampling module for sampling at least P first sampling signals at the end of the first digital channel based on the rising edges of at least the first P clock signals in the N clock signals, wherein the Pth first sampling signal in the at least P first sampling signals is a full-zero signal; a second sampling signal sampling module for sampling at least Q second sampling signals at the end of the second digital channel based on the rising edges of at least the first Q clock signals in the N clock signals, wherein the Qth second sampling signal in the at least Q second sampling signals is a full-zero signal; a deviation value calculating module for determining the phase deviation value of the signals output at the ends of the first digital channel and the second digital channel based on the at least P first sampling signals and the at least Q second sampling signals, wherein N, P and Q are all positive integers greater than or equal to 3. 10.An electronic device comprising a memory and a processor, the electronic device characterized by, The memory stores a computer program, and the processor is configured to run the computer program to execute the delay deviation measurement method in any one of claims 1 to 8. The memory stores a computer program, and the processor is configured to run the computer program to execute the delay deviation measurement method in any one of claims 1 to 8.

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