A fast equivalent sampling method and system for a time-domain ground penetrating radar receiver
By generating a sampling method that controls the radar receiver with two clocks, the problems of low sampling efficiency and poor flexibility of time-domain ground-penetrating radar receivers are solved, achieving efficient sampling and rapid movement, and reducing cost and complexity.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- XI AN JIAOTONG UNIV
- Filing Date
- 2022-10-27
- Publication Date
- 2026-06-23
AI Technical Summary
Existing time-domain ground-penetrating radar receivers suffer from low sampling efficiency, poor flexibility in time window changes, limited movement speed, and significant echo distortion, all of which affect detection performance.
Two time-dependent clocks, a high-frequency clock and a low-frequency clock, are generated. The low-frequency clock triggers a narrow pulse signal source, and the high-frequency clock delays the analog-to-digital converter for sampling. Multi-point acquisition is achieved by combining an FPGA chip and a programmable delay chip.
It improves the scanning speed and real-time performance of radar echo data, enhances the moving speed of radar equipment and the flexibility of the echo observation window, and reduces device cost and circuit complexity.
Smart Images
Figure CN115657016B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of radar technology, specifically to a fast equivalent sampling method and system for a time-domain ground-penetrating radar receiver. Background Technology
[0002] Ground-penetrating radar (GPR) technology is a detection technique that uses high-frequency electromagnetic waves to obtain information about the distribution patterns of underground media. Common time-domain GPR can image and locate underground targets by utilizing the reflection and scattering of broadband electromagnetic pulses at discontinuities in the underground medium, enabling high-resolution detection of targets from a few centimeters to tens of meters underground. This technology plays an extremely important and widespread role in military reconnaissance, mineral geological exploration, engineering quality inspection, archaeology, and search and rescue. Currently, common time-domain GPR mainly consists of four parts: a receiver, a narrow pulse signal source, a transceiver antenna, and a host computer.
[0003] Because narrow pulse signals are ultra-wideband signals, it is difficult for general ADC chips to meet both analog bandwidth requirements and high sampling rate requirements. Therefore, in practical engineering, equivalent sampling is usually used to receive radar echoes. This involves sampling the periodically triggered narrow pulse signal once per cycle and then piecing together all the sampled points into a complete narrow pulse waveform. This sampling method can significantly reduce the sampling rate requirements of the receiver on the ADC chip and achieve a very high equivalent sampling rate, reducing design difficulty and cost. However, under this sampling method, the time to receive one narrow pulse waveform increases significantly with the increase of the echo signal observation window, reducing the receiver's sampling efficiency and flexibility, limiting the movement speed of the ground penetrating radar during operation, and even causing significant distortion in the received echo, affecting the detection performance of the ground penetrating radar system. Summary of the Invention
[0004] To address the problems existing in the prior art, the present invention aims to provide a fast equivalent sampling method for time-domain ground-penetrating radar receivers, which solves the problems of low sampling efficiency, poor flexibility of time window changes, limited moving speed, and large echo distortion in time-domain ground-penetrating radar receivers, thereby improving the detection performance of existing time-domain ground-penetrating radars.
[0005] This invention is achieved through the following technical solution:
[0006] A fast equivalent sampling method for a time-domain ground-penetrating radar receiver includes the following steps:
[0007] Generate two clocks with a time relationship, a high-frequency clock and a low-frequency clock, and the two clocks always have a certain frequency difference;
[0008] A narrow pulse signal source is triggered by a low-frequency clock to generate and transmit the narrow pulse;
[0009] After converting the high-frequency clock into a gated clock, the clock signal of the gated clock is delayed, and the delayed clock signal is used to control the analog-to-digital converter to perform narrow pulse echo sampling.
[0010] Preferably, the high-frequency clock is converted into a gated clock through combinational logic processing.
[0011] Preferably, the high-frequency clock has a frequency of 100MHz, and the low-frequency clock has a frequency of less than 1MHz.
[0012] Preferably, the delay of the gated clock increases linearly with the low-frequency clock period T.
[0013] Preferably, the analog-to-digital converter has a maximum sampling rate of over 100 MSPS and an analog input bandwidth greater than or equal to the pulse signal bandwidth.
[0014] Preferably, the first group of clock signals of the gated clock has a delay of 0, the second group of clock signals has a delay of t, the third group of clock signals has a delay of 2t, and the T1 / t group of clock signals has a delay of (T1-t), where T1 is the high-frequency clock period;
[0015] Each clock signal triggers an analog-to-digital converter to collect N points, which are then received and processed by an FPGA chip to complete one radar echo waveform sampling.
[0016] A system for a fast equivalent sampling method for a time-domain ground-penetrating radar receiver includes an FPGA chip, a programmable delay chip, a narrow pulse signal source, and an ADC chip;
[0017] The output of the FPGA chip is connected to a programmable delay chip and a narrow pulse signal source, respectively. The narrow pulse signal source is connected to the radar transmitting antenna. The output of the programmable delay chip is connected to the ADC chip. The input of the ADC chip is connected to the radar receiving antenna. The output of the ADC chip is connected to the FPGA chip.
[0018] The FPGA chip is used to output two high-frequency clocks and a gated clock that have a time relationship;
[0019] The narrow pulse signal source is used to generate a narrow pulse signal based on the received low-frequency clock and transmit it through the radar transmitting antenna;
[0020] The programmable delay chip is used to delay the clock signal of the gated clock.
[0021] The ADC chip is used to acquire the echo waveform of a narrow pulse based on the received clock signal and send it to the FPGA chip.
[0022] Preferably, the narrow pulse signal period of the narrow pulse signal source is equal to the low-frequency clock period, and the low-frequency clock period is greater than the radar echo observation window length.
[0023] Compared with the prior art, the present invention has the following beneficial technical effects:
[0024] This invention provides a fast equivalent sampling method for a time-domain ground-penetrating radar receiver. It generates two clocks with significantly different frequencies and a strict time relationship: one high-frequency clock and the other low-frequency clock. The low-frequency clock output is used to trigger a narrow-pulse signal source to generate pulses. The high-frequency clock is processed by combinational logic to become a gated clock, and the gated clock signal is delayed. This delayed clock signal is then used to control an analog-to-digital converter to sample the narrow-pulse echo, completing the sampling process of the antenna-received echo. This method, through the coordination of the low-frequency and high-frequency clocks, achieves an ultra-high equivalent sampling rate of up to 100 GSPS to collect multiple points within each cycle of the radar echo signal. This significantly reduces the acquisition time of the complete radar echo, improves the scanning speed and real-time performance of the echo data, and increases the upper limit of the radar equipment's movement speed. Simultaneously, it eliminates the limitation of the radar echo observation window length imposed by programmable delay chips, greatly improving the flexibility and scalability of the radar echo observation window, and reducing the device cost, circuit complexity, and power consumption associated with programmable delay chips.
[0025] Furthermore, the length of the radar echo signal observation window is no longer determined by the maximum delay value of the programmable delay chip, but only by the number of acquisition points within a single radar echo cycle. This can greatly improve the flexibility and scalability of the radar echo observation window, while reducing the device cost of the programmable delay chip, as well as reducing circuit complexity and power consumption. Attached Figure Description
[0026] Figure 1 This is a schematic diagram illustrating the principle of fast equivalent sampling in this invention.
[0027] Figure 2 This is a block diagram of the fast equivalent sampling circuit of the present invention.
[0028] In the diagram: 1. Low-frequency clock; 2. Radar echo observation waveform; 3. Gated clock; 4. ADC chip; 5. FPGA chip; 6. Programmable delay chip; 7. Narrow pulse signal source; T is the low-frequency clock cycle; T1 is the high-frequency clock cycle; N is the number of high-frequency clock cycles; t is the gated clock step delay; T2 is the length of the radar echo observation window. Detailed Implementation
[0029] The present invention will now be described in further detail with reference to the accompanying drawings. These descriptions are intended to explain the invention and not to limit it.
[0030] See Figure 1 A fast equivalent sampling method for a time-domain ground-penetrating radar receiver includes the following steps:
[0031] Step 1: Generate two clocks with a time relationship, a high-frequency clock and a low-frequency clock, and the two clocks always have a certain frequency difference.
[0032] Specifically, the PLL circuit of the FPGA chip is used to generate two clocks with significantly different frequencies and strict time relationships: one is a high-frequency clock and the other is a low-frequency clock. The high-frequency clock has a frequency of 100MHz, while the low-frequency clock frequency is related to the trigger frequency of the narrow pulse signal and the length of the radar echo observation window, and is usually within 1MHz. After the high-frequency clock becomes a gated clock, it is still a periodic signal with the same period as the low-frequency clock. Each period contains the same number of 100MHz clock cycles, the specific number of which depends on the length of the radar echo observation window.
[0033] Step 2: Use a low-frequency clock output to trigger an external narrow pulse signal source to generate pulses; the high-frequency clock is processed by combinational logic into a gated clock and output to a programmable delay chip.
[0034] The programmable delay chip has a delay accuracy of no less than 10ps and a maximum delay of no less than 10ns. The programmable delay chip is controlled by the FPGA chip and the total delay value increases linearly with the low-frequency clock cycle.
[0035] Step 3: The gated clock is output to the clock input of the ADC chip after passing through the programmable delay chip, completing the sampling of the antenna received echo, and the sampled data is sent to the FPGA chip.
[0036] The ADC chip has a maximum sampling rate of over 100 MSPS and an analog input bandwidth that is greater than or equal to the bandwidth of the pulse signal generated by the narrow pulse signal source.
[0037] See Figure 2 A fast equivalent sampling system for a time-domain ground-penetrating radar receiver includes an FPGA chip 5, a programmable delay chip 6, a narrow pulse signal source 7, and an ADC chip 4.
[0038] The output of the FPGA chip 5 is connected to the programmable delay chip 6 and the narrow pulse signal source 7, respectively. The narrow pulse signal source 7 is connected to the radar transmitting antenna. The output of the programmable delay chip 6 is connected to the ADC chip 4. The input of the ADC chip 4 is connected to the radar receiving antenna. The output of the ADC chip 4 is connected to the FPGA chip 5. The FPGA chip 5 is used to output two high-frequency clocks 1 and 3 with a time relationship.
[0039] Narrow pulse signal source 7 is used to generate periodic narrow pulse signals based on the received low-frequency clock and transmit them through the radar transmitting antenna;
[0040] The programmable delay chip 6 is used to receive the gated clock 3 and provide a step delay for each group of clock signals of the gated clock 3 that increases linearly with the low-frequency clock period T;
[0041] ADC chip 4 is used to acquire radar echo waveforms based on the received clock signal and send them to FPGA chip 5.
[0042] The fast equivalent sampling system of this time-domain ground-penetrating radar receiver utilizes the PLL circuitry and combinational logic within the FPGA chip 5 to generate a low-frequency clock 1 and a gated clock 3. The low-frequency clock 1 is primarily related to the highest trigger frequency of the narrow pulse signal source 7 and the maximum observation window length of the radar echo signal, typically within 1MHz. The gated clock 3 is obtained by processing the high-frequency clock within the FPGA chip 5 through combinational logic. Since the frequency of the high-frequency clock is fixed at 100MHz, the corresponding high-frequency clock period T1 should satisfy T1 = 10ns. When the low-frequency clock 1 and the gated clock 3 are output from the FPGA chip 5, the phase relationship between the two clocks must be strictly fixed, and the jitter must be controlled within the ps range.
[0043] Low-frequency clock 1 is used to trigger narrow pulse signal source 6 to generate periodic narrow pulse signals: After being generated by the PLL circuit inside FPGA chip 5, low-frequency clock 1 is directly output to the clock input port of external narrow pulse signal source 7 through IO pin, triggering narrow pulse signal source 7 to generate periodic narrow pulse signals, the period of which is equal to the low-frequency clock period T; in order to avoid overlap between radar echo observation windows, the low-frequency clock period T should be greater than the radar echo observation window length T2, that is, T>T2.
[0044] The gated clock 3 is used to divide the radar echo waveform 2 into N segments with a high-frequency clock period T1, and performs simultaneous sampling of multiple segments under the action of the programmable delay chip 6: After the high-frequency clock is generated by the PLL circuit inside the FPGA chip 5, it is converted into the gated clock 3 using combinational logic, and then output to the external programmable delay chip 6 through the IO pin; when the gated clock 3 is output to the programmable delay chip 6, the programmable delay chip 6 provides the gated clock 3 with a step delay that increases linearly with the low-frequency clock period T: the first group of clock signals is delayed by 0, the second group of clock signals is delayed by t, the third group of clock signals is delayed by 2t, and so on, until the T1 / t group of clock signals is delayed by (T1-t). Each group of clock signals 3 triggers the ADC chip 4 to collect N points, so each radar echo waveform consists of NT1 / t points, which are received and processed by the FPGA chip 5. After completing one radar echo waveform sampling, the delay of the programmable delay chip 6 is reset to zero, and the next linearly increasing cycle begins.
[0045] This invention provides a fast equivalent sampling system for a time-domain ground-penetrating radar receiver. It utilizes the PLL circuit built into an FPGA chip to generate two clocks with significantly different frequencies and a strict time relationship: one high-frequency clock and the other low-frequency clock. The low-frequency clock output from the PLL circuit is then used to trigger a narrow-pulse signal source to generate pulses. The high-frequency clock generated by the PLL circuit is processed by combinational logic into a gated clock, which is then output to a programmable delay chip. Finally, the gated clock, after passing through the programmable delay chip, is output to the sampling trigger clock input of an ADC chip, completing the sampling process of the antenna-received echo. This method, through the coordination of the low-frequency and high-frequency clocks, achieves an ultra-high equivalent sampling rate of up to 100 GSPS to collect multiple points within each cycle of the radar echo signal. This significantly reduces the acquisition time of the complete radar echo, improves the scanning speed and real-time performance of the echo data, and increases the upper limit of the radar equipment's movement speed. Simultaneously, it eliminates the limitation of the radar echo observation window length imposed by the programmable delay chip, greatly improving the flexibility and scalability of the radar echo observation window while reducing the device cost, circuit complexity, and power consumption associated with the programmable delay chip.
[0046] The above content is only for illustrating the technical concept of the present invention and should not be construed as limiting the scope of protection of the present invention. Any modifications made to the technical solution based on the technical concept proposed in this invention shall fall within the scope of protection of the claims of this invention.
Claims
1. A fast equivalent sampling method for a time-domain ground-penetrating radar receiver, characterized in that, Includes the following steps: Two clocks with a time relationship, a high-frequency clock and a low-frequency clock, are generated, and the two clocks always have a certain frequency difference; the frequency of the high-frequency clock is 100MHz, and the frequency of the low-frequency clock is less than 1MHz; and the high-frequency clock and the low-frequency clock are periodic signals, and the number of 100MHz clock cycles contained in each cycle is determined according to the length of the radar echo observation window. A narrow pulse signal source is triggered by a low-frequency clock to generate and transmit the narrow pulse; After converting the high-frequency clock into a gated clock, the clock signal of the gated clock is delayed, and the delayed clock signal is used to control the analog-to-digital converter to perform narrow pulse echo sampling.
2. The fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to claim 1, characterized in that, The high-frequency clock is converted into a gated clock through combinational logic processing.
3. The fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to claim 1, characterized in that, The high-frequency clock has a frequency of 100MHz, and the low-frequency clock has a frequency of less than 1MHz.
4. The fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to claim 1, characterized in that, The delay of the gated clock increases linearly with the low-frequency clock period T.
5. The fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to claim 1, characterized in that, The analog-to-digital converter has a maximum sampling rate of over 100 MSPS and an analog input bandwidth greater than or equal to the pulse signal bandwidth.
6. The fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to claim 1, characterized in that, The first group of clock signals of the gated clock has a delay of 0, the second group of clock signals has a delay of t, the third group of clock signals has a delay of 2t, and the T1 / t group of clock signals has a delay of (T1-t), where T1 is the high-frequency clock period. Each clock signal triggers an analog-to-digital converter to collect N points, which are then received and processed by the FPGA chip (5) to complete one radar echo waveform sampling.
7. A system for implementing the fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to any one of claims 1-6, characterized in that, It includes an FPGA chip (5), a programmable delay chip (6), a narrow pulse signal source (7), and an ADC chip (4). The output of the FPGA chip (5) is connected to the programmable delay chip (6) and the narrow pulse signal source (7), respectively. The narrow pulse signal source (7) is connected to the radar transmitting antenna. The output of the programmable delay chip (6) is connected to the ADC chip (4). The input of the ADC chip (4) is connected to the radar receiving antenna. The output of the ADC chip (4) is connected to the FPGA chip (5). The FPGA chip (5) is used to output two low-frequency clocks (1) and gated clocks (3) that have a time relationship. The narrow pulse signal source (7) is used to generate a narrow pulse signal based on the received low-frequency clock and transmit it through the radar transmitting antenna; The programmable delay chip (6) is used to delay the clock signal of the gated clock; The ADC chip (4) is used to acquire the echo waveform of the narrow pulse according to the received clock signal and send it to the FPGA chip (5).
8. The system of a fast equivalent sampling method for a time-domain ground-penetrating radar receiver according to claim 7, characterized in that, The narrow pulse signal period of the narrow pulse signal source (7) is equal to the low-frequency clock period, and the low-frequency clock period is greater than the radar echo observation window length.