A DLDO circuit using a bidirectional successive approximation comparison SAR binary circuit

Abstract

The present invention relates to the field of integrated circuit technology, and discloses a DLDO circuit using a bidirectional successive approximation comparison type SAR binary circuit, the circuit comprising a binary coarse adjustment circuit with a bidirectional successive approximation comparison type (SAR) as the core, a fine adjustment circuit, a window comparator, a single limit comparator and a load circuit. Among them, the binary circuit part also includes a large-size binary PMOS array, and the fine adjustment circuit includes a fine adjustment logic and a small-size PMOS array. Among them, the single limit comparator compares the output voltage VOUT with the reference voltage VREF to obtain a direction FD signal, which is used to control the adjustment direction of the bidirectional binary coarse adjustment circuit and the fine adjustment circuit, so that the input voltage VOUT approaches the reference voltage VREF. The present invention has the advantages of fast transient response speed, small up and down voltage, simple circuit structure, full integration, etc. The circuit realizes the ability to quickly stabilize the output voltage near the reference value, reduces the up and down voltage, and ensures the load capacity of the output voltage VOUT.

Description

Technical Field

[0001] The invention relates to the technical field of integrated circuits, in particular to a DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit. Background Art

[0002] LDO is the abbreviation of Low dropout regulator, which is a low voltage difference linear regulator. Low voltage difference linear regulator is a circuit that satisfies the low voltage difference conversion between input and output. The voltage difference refers to the minimum difference between input voltage and output voltage required to maintain the output voltage within 100mV of its rated value. Digital LDO is digital LDO. Digital LDO has smaller power transistors, fewer stability issues and better process scalability than analog LDO, so it is used in mobile power systems.

[0003] However, compared with analog LDO, traditional digital LDO has the disadvantages of slower transient response and large overshoot and overshoot voltages because it uses a large number of shift registers and initializes the adjustment control word. Therefore, it is necessary to improve the transient response speed of the circuit and reduce the overshoot and overshoot voltage of the circuit while ensuring the stability of the circuit output, and make improvements in turn. Summary of the invention

[0004] 1. Technical issues to be resolved

[0005] In view of the shortcomings of the prior art, the present invention provides a DLDO circuit using a bidirectional successive approximation comparison type SAR binary circuit, which has the advantages of fast transient response speed, small overshoot and undershoot voltages, simple circuit structure, and full integration. It solves the problem of improving the transient response speed of the circuit and reducing the overshoot and undershoot voltages of the circuit while ensuring the stability of the circuit output.

[0006] (II) Technical solution

[0007] In order to achieve the above-mentioned fast transient response speed, small overshoot and undershoot voltage, simple circuit structure, and full integration, the present invention provides the following technical solutions: a DLDO circuit using a bidirectional successive approximation comparison type SAR binary circuit, including: a bidirectional binary coarse adjustment circuit, a fine adjustment circuit, a window comparator, a single limit comparator, and a load circuit. Among them, the bidirectional binary coarse adjustment circuit includes a bidirectional successive approximation comparison type (SAR) and a large-size binary PMOS array, and the fine adjustment circuit includes a fine adjustment logic and a small-size PMOS array.

[0008] The input end of the window comparator is connected to the circuit output voltage VOUT, and the output end thereof is connected to the input end of the bidirectional successive approximation comparator type SAR and the fine adjustment logic. The input end of the single limit comparator is connected to the circuit output voltage VOUT, and the output end thereof is connected to the input end of the bidirectional successive approximation comparator type SAR and the fine adjustment logic. The output end of the bidirectional successive approximation comparator type SAR is connected to the input end of the large-size binary PMOS array, and the output end of the fine adjustment logic is connected to the input end of the small-size PMOS array. The output end of the large-size binary PMOS array and the output end of the small-size PMOS array are connected as the output voltage VOUT of the circuit.

[0009] The single limit comparator compares the output voltage VOUT with the reference voltage VREF to obtain a direction FD signal, which is used to control the adjustment direction of the bidirectional binary coarse adjustment circuit and the fine adjustment circuit. When VOUT>VREF, FD=0 is obtained, which is used to control the bidirectional successive approximation comparison type SAR and the fine adjustment logic module to adjust in the direction of turning off the PMOS tube, ensuring that the output voltage VOUT approaches the reference voltage VREF, and vice versa. The correct adjustment direction of the output voltage is ensured.

[0010] The window comparator compares the output voltage VOUT with the window upper and lower limit voltages VREFH and VREFL to obtain a window signal EN, which is used to control whether the bidirectional binary coarse adjustment circuit and the fine adjustment circuit are enabled or not. When the output voltage VOUT is outside the window, the control of the bidirectional binary coarse adjustment circuit is enabled and the control of the fine adjustment circuit is disabled; when the output voltage VOUT is within the window, the control of the fine adjustment circuit is enabled and the control of the bidirectional binary coarse adjustment circuit is disabled. Ensure that the circuit can adaptively select the appropriate step size.

[0011] The bidirectional binary coarse adjustment circuit uses a large-size binary PMOS array to achieve a gradual reduction in the coarse adjustment step, effectively reduce the overshoot and overshoot voltages and accelerate the transient response, while avoiding further overshoot of the output voltage.

[0012] Preferably, the bidirectional successive approximation comparison SAR circuit adopts a circular shift register technology to determine the current coarse adjustment position, and uses a NOT gate, an OR gate and an AND gate to calculate the S signal and the R signal required for the current adjustment position and the previous adjustment position according to the output signal of the single limit comparator, and inputs the S signal and the R signal into the edge SR trigger module to calculate the control word Cn of the current coarse adjustment position. Each round of adjustment only initializes the adjustment position but not the control word, which effectively reduces the up and down voltages. The bidirectional technology is used to calculate the coarse adjustment control word of the current adjustment position and the previous adjustment position, and the control word has the bidirectional correction capability, which effectively avoids misadjustment and thus avoids further overshoot.

[0013] Preferably, the edge SR trigger module combines the level-triggered D trigger and the level-triggered SR trigger to realize edge triggering, effectively avoiding multiple flips and unexpected flips of the trigger, and improving the anti-interference ability of the SR trigger. At the same time, compared with the blocking edge SR trigger, its circuit is simple and easy to implement.

[0014] Preferably, a large size binary PMOS array such as Figure 4 As shown, its size is reduced in binary form. Combined with the bidirectional successive approximation comparison SAR, a binary circuit is implemented, which improves the transient response speed of the circuit. Its adjustment step size is reduced in sequence, which effectively avoids further overshoot of the output voltage.

[0015] (III) Beneficial effects

[0016] Compared with the prior art, the present invention provides a DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit, which has the following beneficial effects:

[0017] 1. The present invention adopts bidirectional successive approximation comparison SAR technology, which enables the coarse adjustment circuit to have bidirectional correction capability of the control word, thus avoiding further overshoot of the output voltage. Each round of adjustment only initializes the adjustment bit but not the control word, effectively reducing the overshoot and overshoot voltages.

[0018] 2. The present invention adopts the combination technology of level-triggered D trigger and level-triggered SR trigger to realize edge-triggered SR trigger, which effectively avoids multiple flips and unexpected flips of the trigger and improves the anti-interference ability of the SR trigger.

[0019] 3. The present invention adopts a binary large-size PMOS array, combined with the bidirectional successive approximation comparison type SAR, to realize a binary circuit, thereby improving the transient response speed of the circuit. The adjustment step size is reduced successively, effectively avoiding further overshoot of the output voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 Overall structure diagram of DLDO circuit;

[0021] Figure 2 Bidirectional successive approximation comparison SAR structure diagram;

[0022] Figure 3 Edge-triggered SR flip-flop structure diagram;

[0023] Figure 4 Schematic diagram of a large-scale binary PMOS array. DETAILED DESCRIPTION

[0024] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0025] See also Figure 1-4 , the present invention provides a technical solution: a DLDO circuit using a bidirectional successive approximation comparison type SAR binary circuit, including a bidirectional binary coarse adjustment circuit with a bidirectional successive approximation comparison type SAR as the core, a fine adjustment circuit, a window comparator, a single limit comparator and a load circuit;

[0026] The bidirectional binary coarse adjustment circuit part also includes a large-size binary PMOS array;

[0027] The input end of the window comparator is connected to the circuit output voltage VOUT, and the output end thereof is connected to the input end of the bidirectional successive approximation comparator type SAR and the fine adjustment logic;

[0028] The input end of the single limit comparator is connected to the circuit output voltage VOUT, and the output end thereof is connected to the input end of the bidirectional successive approximation comparator type SAR and the fine adjustment logic;

[0029] The output end of the bidirectional successive approximation comparison type SAR is connected to the input end of the large-size binary PMOS array, and the output end of the fine-tuning logic is connected to the input end of the small-size PMOS array;

[0030] The output end of the large-size binary PMOS array and the output end of the small-size PMOS array are connected to serve as the output voltage VOUT of the circuit.

[0031] The single limit comparator compares the output voltage VOUT with the reference voltage VREF to obtain the direction FD signal, which is used to control the adjustment direction of the bidirectional binary method coarse adjustment circuit and the fine adjustment circuit. When VOUT>VREF, FD=0 is obtained, which is used to control the bidirectional successive approximation comparison type SAR and the fine adjustment logic module to adjust in the direction of turning off the PMOS tube, so that the output voltage VOUT approaches the reference voltage VREF, and vice versa. The correct adjustment direction of the output voltage is ensured.

[0032] The window comparator compares the output voltage VOUT with the window upper and lower limit voltages VREFH and VREFL to obtain the window signal EN, which is used to control whether the bidirectional binary coarse adjustment circuit and the fine adjustment circuit are enabled or not. When the output voltage VOUT is outside the window, the control of the bidirectional binary coarse adjustment circuit is enabled and the control of the fine adjustment circuit is disabled; when the output voltage VOUT is within the window, the control of the fine adjustment circuit is enabled and the control of the bidirectional binary coarse adjustment circuit is disabled. Ensure that the circuit can adaptively select the appropriate step size.

[0033] The bidirectional binary coarse adjustment circuit uses a large-size binary PMOS array to achieve a gradual reduction in the coarse adjustment step size, effectively reducing the overshoot and overshoot voltages and accelerating the transient response, while avoiding further overshoot of the output voltage.

[0034] Bidirectional successive approximation comparison SAR circuit Figure 2 As shown, the circular shift register technology is used to determine the current coarse adjustment bit, and the S signal and R signal required for the current adjustment bit and the previous adjustment bit are calculated based on the output signal of the single limit comparator by using the NOT gate, OR gate and AND gate. The S signal and R signal are input into the edge SR trigger module to calculate the control word Cn of the current coarse adjustment bit. Each round of adjustment only initializes the adjustment bit but not the control word, which effectively reduces the up and down voltages. The bidirectional technology is used to calculate the coarse adjustment control word of the current adjustment bit and the previous adjustment bit, which has the bidirectional correction capability of the control word, effectively avoiding misadjustment and thus avoiding further overshoot.

[0035] Edge SR trigger module such as Figure 3 As shown, it combines the level-triggered D flip-flop and the level-triggered SR flip-flop to realize edge triggering, effectively avoiding multiple flips and unexpected flips of the trigger, and improving the anti-interference ability of the SR flip-flop. At the same time, compared with the blocking edge SR flip-flop, its circuit is simple and easy to implement.

[0036] Large size binary PMOS arrays such as Figure 4 As shown in the figure, its size is reduced in binary form. The combined bidirectional successive approximation comparison SAR realizes the binary circuit and improves the transient response speed of the circuit. Its adjustment step size is reduced in sequence, which effectively avoids further overshoot of the output voltage.

[0037] The main working process of the circuit is as follows:

[0038] 1. The voltage signal output by the PMOS array is input to the single limit comparator and the window comparator. The single limit comparator detects and judges the signal to control the adjustment direction of the circuit; the window comparator detects and judges the signal to control the circuit to enable coarse adjustment or fine adjustment.

[0039] 2. When the coarse adjustment mode is enabled, the coarse adjustment bit is initialized first, and then the S signal generation module and the R signal generation module accurately calculate the S signal and R signal of the current adjustment bit and the previous adjustment bit. Then they are locked into the edge SR trigger to achieve accurate calculation of the coarse adjustment control word. When the fine adjustment mode is enabled, the fine adjustment control word is calculated by the fine adjustment logic.

[0040] 3. The control word is output to the PMOS array to control the on or off of the PMOS array to adapt to changes in load current, stabilize the output voltage, and achieve adjustment.

[0041] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the appended claims and their equivalents.

Claims

1. A DLDO circuit using a bidirectional successive approximation comparison SAR dichotomy circuit, characterized in that: It includes a bidirectional binary method coarse adjustment circuit, a fine adjustment circuit, a window comparator, a single limit comparator and a load circuit with a bidirectional successive approximation comparison SAR as the core; The bidirectional binary coarse adjustment circuit part also includes a large-size binary PMOS array; The input end of the window comparator is connected to the circuit output voltage VOUT, and the output end thereof is connected to the input end of the bidirectional successive approximation comparator type SAR and the fine adjustment logic; The input end of the single limit comparator is connected to the circuit output voltage VOUT, and the output end thereof is connected to the input end of the bidirectional successive approximation comparator type SAR and the fine adjustment logic; The output end of the bidirectional successive approximation comparison type SAR is connected to the input end of the large-size binary PMOS array, and the output end of the fine-tuning logic is connected to the input end of the small-size PMOS array; The output end of the large-size binary PMOS array and the output end of the small-size PMOS array are connected to serve as the output voltage VOUT of the circuit; The bidirectional successive approximation comparison SAR adopts a circular shift register technology to determine the current coarse adjustment position, uses a NOT gate, an OR gate and an AND gate and calculates the S signal and R signal required for the current adjustment position and the previous adjustment position according to the output signal of the single limit comparator, inputs the S signal and the R signal into the edge SR trigger module, and calculates the control word Cn of the current coarse adjustment position.

2. The DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit according to claim 1, characterized in that: The single-limit comparator compares the output voltage VOUT with the reference voltage VREF to obtain a direction FD signal, which is used to control the adjustment direction of the bidirectional binary coarse adjustment circuit and the fine adjustment circuit. When VOUT>VREF, FD=0 is obtained, which is used to control the bidirectional successive approximation comparison type SAR and the fine adjustment logic module to adjust in the direction of turning off the PMOS tube, so that the output voltage VOUT approaches the reference voltage VREF.

3. The DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit according to claim 1, characterized in that: The window comparator compares the output voltage VOUT with the upper and lower limit voltages VREFH and VREFL of the window to obtain a window signal EN, which is used to control whether the bidirectional binary coarse adjustment circuit and the fine adjustment circuit are enabled or not. When the output voltage VOUT is outside the window, the control of the bidirectional binary coarse adjustment circuit is enabled and the control of the fine adjustment circuit is disabled; when the output voltage VOUT is within the window, the control of the fine adjustment circuit is enabled and the control of the bidirectional binary coarse adjustment circuit is disabled.

4. The DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit according to claim 1, characterized in that: The bidirectional binary coarse adjustment circuit uses a bidirectional SAR circuit and a large-size binary PMOS array to achieve a gradual reduction in the coarse adjustment step, effectively reduce the overshoot and overshoot voltages and accelerate the transient response, while avoiding further overshoot of the output voltage.

5. The DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit according to claim 1, characterized in that: The edge SR trigger module combines the level-triggered D trigger and the level-triggered SR trigger to realize edge triggering, effectively avoiding multiple flips and unexpected flips of the trigger, and improving the anti-interference ability of the SR trigger. At the same time, compared with the blocking edge SR trigger, its circuit is simple and easy to implement.

6. The DLDO circuit using a bidirectional successive approximation comparison type SAR dichotomy circuit according to claim 1, characterized in that: The size of the large-size binary PMOS array is reduced in binary form; combined with the bidirectional successive approximation comparison SAR, a binary division circuit is realized, and the transient response speed of the circuit is improved; its adjustment step size is reduced in sequence, effectively avoiding further overshoot of the output voltage.

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