Method for off-chip DDR bandwidth offloading in raid sequential write scenario, terminal and storage medium

Abstract

The present application relates to the technical field of computers, in particular to a method for off-chip DDR bandwidth offloading in a RAID sequential writing scenario, a terminal and a storage medium. The method comprises the following steps: moving new data D' from a host DDR to on-chip cache space U of a RAID management chip; calling a RAID computing engine to read D' from the on-chip cache U, and writing D' and new check data P' obtained by calculation back to V and X in the off-chip DDR respectively; and storing D' and P' data in V and X spaces of the off-chip DDR. The present application partially offloads the storage bandwidth demand of the off-chip DDR by introducing on-chip cache, thereby improving the bandwidth upper limit of the host computer in the sequential writing scenario.

Description

Technical Field

[0001] This invention relates to the field of computer technology, and in particular to a method, terminal, and storage medium for offloading off-chip DDR bandwidth in RAID sequential write scenarios. Background Technology

[0002] RAID technology combines multiple independent storage media (SSDs or HDDs) into a single unit, presenting it to the host computer as a single storage device with data redundancy protection, and responding to the host computer's management and read / write I / O requests. Taking RAID 0 as an example, it transforms a single I / O request from the host computer into concurrent operations on multiple independent storage media, thereby improving overall bandwidth and latency performance. A RAID group typically consists of n data disks and m parity disks. Based on different organization methods and algorithms, RAID can be classified into different RAID levels, commonly including RAID 0 (n=k, m=0), RAID 1 (n=1, m=1), RAID 10 (n=k, m=k), RAID 5 (n=k, m=1), and RAID 6 (n=k, m=2), etc.

[0003] During the process of the processing module responding to sequential write I / O requests for RAID5 and RAID6 from the host computer, the RAID processing module typically performs "full striping" aggregation of multiple sequential write I / Os. In the case of full striping, new parity data is calculated from the complete new data, and both are directly overwritten and written to disk. For example... Figure 8 The diagram illustrates the full-band write processing steps for RAID 5 (4+1), which mainly consist of three steps.

[0004] 1. Move the new data D' from the host DDR to the local off-chip DDR space;

[0005] 2. Call the RAID calculation engine to read D' from the local DDR and write the calculated new parity data P' back to the local DDR space;

[0006] 3. Copy the data from the middle to disk.

[0007] In existing RAID processing technologies, the total sequential write bandwidth of the hard drive and the bandwidth of local storage affect its processing performance. To address this technical issue, a method for offloading off-chip DDR bandwidth, a terminal, and storage media for RAID sequential write scenarios are proposed. Summary of the Invention

[0008] To address the technical problems existing in the prior art, this invention provides a method, terminal, and storage medium for off-chip DDR bandwidth offloading in RAID sequential write scenarios. During RAID processing, the on-chip cache partially offloads the storage bandwidth requirements of off-chip DDR, thereby improving the bandwidth of the host computer in sequential write scenarios.

[0009] To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

[0010] In a first aspect, in one embodiment of the present invention, an off-chip DDR bandwidth offloading method for RAID sequential write scenarios is provided, the method comprising the following steps:

[0011] The new data D' is moved from the host DDR to the on-chip cache space U of the RAID management chip;

[0012] The RAID calculation engine is invoked to read D' from the on-chip cache U, and D' and the newly calculated parity data P' are written back to V and X in the off-chip DDR respectively;

[0013] Write the D' and P' data in the V and X spaces of the off-chip DDR to disk.

[0014] As a further aspect of the present invention, the RAID full stripe write processing includes a "write through" mode and a "write back" mode.

[0015] As a further aspect of the present invention, when in "write-through" mode, before moving the new data D' from the host DDR to the on-chip cache space U of the RAID management chip, the following steps are included:

[0016] Full-band aggregation across I / O ports;

[0017] After successful aggregation, allocate a storage space U of new data size D' in the on-chip SRAM;

[0018] Allocate memory spaces V and X in the off-chip DDR.

[0019] As a further aspect of the present invention, when in "write-through" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes: releasing the on-chip cache space U.

[0020] As a further aspect of the present invention, when in "write-through" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk further includes: releasing the storage spaces V and X in the off-chip DDR; and then responding to the host.

[0021] As a further aspect of the present invention, when in "write-back" mode, the process of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip further includes, beforehand, full-strip aggregation across I / O ports;

[0022] After successful aggregation, allocate a new data storage space U of size D' in the on-chip SRAM.

[0023] As a further aspect of the present invention, when in "write-back" mode, the step of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip further includes responding to the host.

[0024] Check whether the cache data in DDR has been hit, and get the result list 'a';

[0025] Perform a completion operation on list a to obtain storage spaces V and X in the off-chip DDR;

[0026] The list 'a' includes three results: no hit, partial hit, and full hit.

[0027] As a further aspect of the present invention, when in "write-back" mode, the RAID calculation engine is invoked to read D' from the on-chip cache U, and D' and the calculated new parity data P' are written back to V and X in the off-chip DDR respectively. After that, the on-chip cache space U is released.

[0028] Secondly, in another embodiment provided by the present invention, a terminal is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of the off-chip DDR bandwidth offloading method in a RAID sequential write scenario.

[0029] Thirdly, in another embodiment of the present invention, a storage medium is provided that stores a computer program, which, when loaded and executed by a processor, implements the steps of the off-chip DDR bandwidth offloading method in the RAID sequential write scenario.

[0030] The technical solution provided by this invention has the following beneficial effects:

[0031] This invention provides a method, terminal, and storage medium for offloading off-chip DDR bandwidth in RAID sequential write scenarios. The method involves moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip; calling the RAID calculation engine to read D' from the on-chip cache U; and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR, respectively; and finally, writing the D' and P' data in the V and X spaces of the off-chip DDR to disk. This invention partially offloads the storage bandwidth requirements of the off-chip DDR by introducing an on-chip cache, thereby increasing the bandwidth limit of the host computer in sequential write scenarios.

[0032] These or other aspects of the invention will become more apparent from the following description of embodiments. It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only, and are not intended to limit the invention. Attached Figure Description

[0033] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0034] Figure 1 This is a flowchart of an off-chip DDR bandwidth offloading method in a RAID sequential write scenario according to an embodiment of the present invention;

[0035] Figure 2 This is a structural diagram of an application device for an off-chip DDR bandwidth offloading method in a RAID sequential write scenario according to an embodiment of the present invention.

[0036] Figure 3 This is a comparison diagram of the effects of the present invention and the prior art;

[0037] Figure 4 This is a scenario definition diagram of "Write Through (WT)" and "Write Back (WB)" in the off-chip DDR bandwidth offloading method under the RAID sequential write scenario of an embodiment of the present invention;

[0038] Figure 5 This invention relates to a method for off-chip DDR bandwidth offloading in a RAID sequential write scenario, specifically a full-strip write processing flow in "write-through" mode.

[0039] Figure 6 This invention relates to a method for off-chip DDR bandwidth offloading in a RAID sequential write scenario, specifically a full-strip write processing flow in "write-back" mode.

[0040] Figure 7 This is a schematic diagram of the structure of a terminal according to an embodiment of the present invention;

[0041] Figure 8 This is existing technology.

[0042] In the diagram: Processor-401, Communication Interface-402, Memory-403, Communication Bus-404. Detailed Implementation

[0043] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] The flowchart shown in the attached diagram is for illustrative purposes only and does not necessarily include all content and operations / steps, nor does it necessarily have to be performed in the order described. For example, some operations / steps can be broken down, combined, or partially merged, so the actual execution order may change depending on the actual situation.

[0045] It should be understood that the terminology used in this specification is for the purpose of describing particular embodiments only and is not intended to limit the invention. As used in this specification and the appended claims, the singular forms “a,” “an,” and “the” are intended to include the plural forms unless the context clearly indicates otherwise.

[0046] Specifically, the embodiments of the present invention will be further described below with reference to the accompanying drawings.

[0047] Please see Figure 1 , Figure 1 This is a flowchart of an off-chip DDR bandwidth offloading method in a RAID sequential write scenario provided by an embodiment of the present invention, as shown below. Figure 1 As shown, the off-chip DDR bandwidth offloading method in this RAID sequential write scenario includes steps S10 to S30. The method is applied to RAID full-strip write processing.

[0048] S10. Move the new data D' from the host DDR to the on-chip cache space U of the RAID management chip;

[0049] S20. Call the RAID calculation engine to read D' from the on-chip cache U, and write D' and the newly calculated parity data P' back to V and X in the off-chip DDR respectively;

[0050] S30: Write the D' and P' data in the V and X spaces of the external DDR to disk.

[0051] This invention reduces the storage requirements of off-chip DDR by introducing on-chip cache.

[0052] The amplification factor for RAID5 (n+1 disks RAID) and RAID6 (n+2 disks RAID) is calculated as follows:

[0053]

[0054]

[0055] The RAID full stripe write processing includes a "write through" mode and a "write back" mode.

[0056] In an embodiment of the present invention, when in "write-through" mode, before moving the new data D' from the host DDR to the on-chip cache space U of the RAID management chip, the following steps are included:

[0057] Full-band aggregation across I / O ports;

[0058] After successful aggregation, allocate a storage space U of new data size D' in the on-chip SRAM;

[0059] Allocate memory spaces V and X in the off-chip DDR.

[0060] In an embodiment of the present invention, when in "write-through" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes: releasing the on-chip cache space U.

[0061] In an embodiment of the present invention, when in "write-through" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk further includes: releasing the storage spaces V and X in the off-chip DDR; and then responding to the host.

[0062] In an embodiment of the present invention, when in "write-back" mode, the process of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip includes, beforehand, full stripe aggregation across I / O ports;

[0063] After successful aggregation, allocate a new data storage space U of size D' in the on-chip SRAM.

[0064] In an embodiment of the present invention, when in "write-back" mode, the step of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip is followed by responding to the host.

[0065] Check whether the cache data in DDR has been hit, and get the result list 'a';

[0066] Complete the list 'a' to obtain storage spaces V and X in the off-chip DDR.

[0067] The list 'a' includes three results: no hit, partial hit, and full hit.

[0068] In an embodiment of the present invention, when in "write-back" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes releasing the on-chip cache space U.

[0069] In an embodiment of the present invention, when in "write-back" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk, and then further includes updating the cache management mapping table, releasing the iCache page table, and releasing the storage spaces V and X in the off-chip DDR.

[0070] In the RAID process, this invention partially offloads the storage bandwidth requirements of off-chip DDR through on-chip cache, thereby improving the bandwidth of the host computer in sequential write scenarios.

[0071] It should be understood that although the above description follows a certain order, these steps are not necessarily executed in that order. Unless otherwise expressly stated herein, there is no strict order restriction on the execution of these steps, and they can be executed in other orders. Moreover, some steps in this embodiment may include multiple steps or multiple stages, which are not necessarily completed at the same time, but may be executed at different times. The execution order of these steps or stages is not necessarily sequential, but may be performed alternately or in turn with other steps or at least a portion of the steps or stages in other steps.

[0072] In one embodiment, see Figure 5 As shown, an embodiment of the present invention also provides a terminal, including a processor 401, a communication interface 402, a memory 403 and a communication bus 404, wherein the processor 401, the communication interface 402 and the memory 403 communicate with each other through the communication bus 404.

[0073] Memory 403 is used to store computer programs;

[0074] When processor 401 executes the computer program stored in memory 403, it executes the off-chip DDR bandwidth offloading method in the RAID sequential write scenario. When the processor executes instructions, it implements the steps in the above method embodiment:

[0075] S10. Move the new data D' from the host DDR to the on-chip cache space U of the RAID management chip;

[0076] S20. Call the RAID calculation engine to read D' from the on-chip cache U, and write D' and the newly calculated parity data P' back to V and X in the off-chip DDR respectively;

[0077] S30: Write the D' and P' data in the V and X spaces of the external DDR to disk.

[0078] This invention reduces the storage requirements of off-chip DDR by introducing on-chip cache.

[0079] The amplification factor for RAID5 (n+1 disks RAID) and RAID6 (n+2 disks RAID) is calculated as follows:

[0080]

[0081]

[0082] The RAID full stripe write processing includes a "write through" mode and a "write back" mode.

[0083] In an embodiment of the present invention, when in "write-through" mode, before moving the new data D' from the host DDR to the on-chip cache space U of the RAID management chip, the following steps are included:

[0084] Full-band aggregation across I / O ports;

[0085] After successful aggregation, allocate a storage space U of new data size D' in the on-chip SRAM;

[0086] Allocate memory spaces V and X in the off-chip DDR.

[0087] In an embodiment of the present invention, when in "write-through" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes: releasing the on-chip cache space U.

[0088] In an embodiment of the present invention, when in "write-through" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk further includes: releasing the storage spaces V and X in the off-chip DDR; and then responding to the host.

[0089] In an embodiment of the present invention, when in "write-back" mode, the process of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip includes, beforehand, full stripe aggregation across I / O ports;

[0090] After successful aggregation, allocate a new data storage space U of size D' in the on-chip SRAM.

[0091] In an embodiment of the present invention, when in "write-back" mode, the step of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip is followed by responding to the host.

[0092] Check whether the cache data in DDR has been hit, and get the result list 'a';

[0093] Complete the list 'a' to obtain storage spaces V and X in the off-chip DDR.

[0094] The list 'a' includes three results: no hit, partial hit, and full hit.

[0095] In an embodiment of the present invention, when in "write-back" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes releasing the on-chip cache space U.

[0096] In an embodiment of the present invention, when in "write-back" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk, and then further includes updating the cache management mapping table, releasing the iCache page table, and releasing the storage spaces V and X in the off-chip DDR.

[0097] The communication bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0098] The communication interface is used for communication between the aforementioned terminal and other devices.

[0099] The memory may include random access memory (RAM) or non-volatile memory, such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0100] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0101] The terminal includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs. The network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The terminal can operate independently to implement this invention, or it can connect to a network and interact with other terminals on the network to implement this invention. The network in which the terminal is located includes, but is not limited to, the Internet, wide area network (WAN), metropolitan area network (MAN), local area network (LAN), and VPN network.

[0102] The terminal includes user equipment and network equipment. The user equipment includes, but is not limited to, computers, smartphones, and PDAs. The network equipment includes, but is not limited to, a single network server, a server group consisting of multiple network servers, or a cloud based on cloud computing, which is a type of distributed computing consisting of a super virtual computer composed of a group of loosely coupled computers. The terminal can operate independently to implement this invention, or it can connect to a network and interact with other terminals on the network to implement this invention. The network in which the terminal is located includes, but is not limited to, the Internet, wide area network (WAN), metropolitan area network (MAN), local area network (LAN), and VPN network.

[0103] It should also be understood that the term "and / or" as used in this specification and the appended claims refers to any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0104] In one embodiment of the present invention, a storage medium is also provided, on which a computer program is stored, which, when executed by a processor, implements the steps in the above method embodiments:

[0105] S10. Move the new data D' from the host DDR to the on-chip cache space U of the RAID management chip;

[0106] S20. Call the RAID calculation engine to read D' from the on-chip cache U, and write D' and the newly calculated parity data P' back to V and X in the off-chip DDR respectively;

[0107] S30: Write the D' and P' data in the V and X spaces of the external DDR to disk.

[0108] This invention reduces the storage requirements of off-chip DDR by introducing on-chip cache.

[0109] The amplification factor for RAID5 (n+1 disks RAID) and RAID6 (n+2 disks RAID) is calculated as follows:

[0110]

[0111]

[0112] The RAID full stripe write processing includes a "write through" mode and a "write back" mode.

[0113] In an embodiment of the present invention, when in "write-through" mode, before moving the new data D' from the host DDR to the on-chip cache space U of the RAID management chip, the following steps are included:

[0114] Full-band aggregation across I / O ports;

[0115] After successful aggregation, allocate a storage space U of new data size D' in the on-chip SRAM;

[0116] Allocate memory spaces V and X in the off-chip DDR.

[0117] In an embodiment of the present invention, when in "write-through" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes: releasing the on-chip cache space U.

[0118] In an embodiment of the present invention, when in "write-through" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk further includes: releasing the storage spaces V and X in the off-chip DDR; and then responding to the host.

[0119] In an embodiment of the present invention, when in "write-back" mode, the process of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip includes, beforehand, full stripe aggregation across I / O ports;

[0120] After successful aggregation, allocate a new data storage space U of size D' in the on-chip SRAM.

[0121] In an embodiment of the present invention, when in "write-back" mode, the step of moving new data D' from the host DDR to the on-chip cache space U of the RAID management chip is followed by responding to the host.

[0122] Check whether the cache data in DDR has been hit, and get the result list 'a';

[0123] Complete the list 'a' to obtain storage spaces V and X in the off-chip DDR.

[0124] The list 'a' includes three results: no hit, partial hit, and full hit.

[0125] In an embodiment of the present invention, when in "write-back" mode, the step of calling the RAID calculation engine to read D' from the on-chip cache U, and writing D' and the calculated new parity data P' back to V and X in the off-chip DDR respectively, and then further includes releasing the on-chip cache space U.

[0126] In an embodiment of the present invention, when in "write-back" mode, the step of writing the D' and P' data in the V and X spaces of the off-chip DDR to disk, and then further includes updating the cache management mapping table, releasing the iCache page table, and releasing the storage spaces V and X in the off-chip DDR.

[0127] Those skilled in the art will understand that all or part of the processes in the methods of the above embodiments can be implemented by a computer program instructing related hardware. The computer program can be stored in a non-volatile computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. Furthermore, any references to memory, storage, databases, or other media used in the embodiments provided by this invention can include at least one of non-volatile and volatile memory.

[0128] It should be understood that, as used herein, the singular form "a" is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations of one or more of the associatedly listed items. The embodiment numbers disclosed above are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0129] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for offloading off-chip DDR bandwidth in a RAID sequential write scenario, the method being applied to RAID full-strip write processing, characterized in that, The method includes: The new data D' is moved from the host DDR to the on-chip cache space of the RAID management chip. middle; Call the RAID calculation engine from the on-chip cache Read D' from the memory and write D' and the newly calculated parity data P' back to the external DDR memory respectively. and middle; external DDR and The D' and P' data in the space are written to disk; The RAID full stripe write processing includes a "write-through" mode and a "write-back" mode; When in "write-through" mode, the new data D' is moved from the host DDR to the on-chip cache space of the RAID management chip. Previously, it also included: Full-band aggregation across I / O ports; After successful aggregation, allocate a storage space U of the new data D' in the on-chip SRAM; Allocate storage space V in off-chip DDR and ; When in "write-back" mode, the new data D' is moved from the host DDR to the on-chip cache space of the RAID management chip. Previously, this also included full-band aggregation across I / O ports; After successful aggregation, allocate a new data storage space U of size D' in the on-chip SRAM.

2. The off-chip DDR bandwidth offloading method in a RAID sequential write scenario as described in claim 1, characterized in that, When in "write-through" mode, the RAID calculation engine is invoked to retrieve data from the on-chip cache. Read D' from the memory and write D' and the newly calculated parity data P' back to the external DDR memory respectively. and The next step includes: releasing the on-chip cache space U.

3. The off-chip DDR bandwidth offloading method in a RAID sequential write scenario as described in claim 2, characterized in that, When in "write-through" mode, the external DDR memory... and The D' and P' data in the space are written to disk, followed by: releasing the external DDR storage space V and Then respond to the host.

4. The off-chip DDR bandwidth offloading method in a RAID sequential write scenario as described in claim 1, characterized in that, When in "write-back" mode, the new data D' is moved from the host DDR to the on-chip cache space of the RAID management chip. In the middle, it also includes the responding host; Check whether the cache data in DDR has been hit, and get the result list 'a'; Complete the list 'a' to obtain the storage space V in the off-chip DDR. ; The list 'a' includes three results: no hit, partial hit, and full hit.

5. The off-chip DDR bandwidth offloading method in a RAID sequential write scenario as described in claim 4, characterized in that, When in "write-back" mode, the RAID calculation engine is invoked to retrieve data from the on-chip cache. Read D' from the memory and write D' and the newly calculated parity data P' back to the external DDR memory respectively. and The next step includes releasing the on-chip cache space U.

6. A terminal, comprising a memory and a processor, wherein the memory stores a computer program, and the processor loads and executes the computer program to implement the steps of the off-chip DDR bandwidth offloading method in a RAID sequential write scenario as described in any one of claims 1-5.

7. A storage medium storing a computer program, wherein the computer program, when loaded and executed by a processor, implements the steps of the off-chip DDR bandwidth offloading method in a RAID sequential write scenario as described in any one of claims 1-5.

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