PCIe and RapidIO Composite Task Packet Transfer System and Method

Abstract

The present invention discloses a PCIe and RapidIO composite task packet transfer system and method, belonging to the field of computer communication technologies. The system includes a PCIe transceiver, an AXI4-Stream composite task data packet transfer path, an AXI4-Lite maintenance transaction transfer path, and a RapidIO transceiver; the PCIe transceiver includes a composite task data packet construction module, a PCIe root complex driver module, a PCIe physical link, and a PCIe endpoint circuit module. The present invention adopts a composite task data packet transfer method of single sending and multiple executions, and adopts appropriate data packet configuration and encoding / decoding methods, which can further improve the conversion performance of multiple data packets while ensuring the flexible configurability of the channel.

Description

Technical Field

[0001] The present invention relates to the field of computer communication technologies, and particularly to a PCIe and RapidIO composite task packet transfer system and method. Background Art

[0002] In the networking process of a communication system, a display and control terminal often uses a PCIe bus protocol interface for external data interaction, and internal modules usually use a serial RapidIO protocol for cluster interaction. The correct and stable transmission of control and data information between the PCIe interface and the serial RapidIO interface determines the stability of the system.

[0003] Currently, there are two types of conversion systems in the prior art: a conversion system based on a bridging chip and a hardware programmable bridging system based on an FPGA. Among them, the former has limited configurability; the latter has strong flexibility and a high degree of user configurability. For example, the patent "A PCIE and RapidIO Data Conversion Device" with the authorization announcement number CN214474972U realizes data transmission with an arbitration mechanism through DMA, improving the conversion performance of a single data packet.

[0004] In order to further improve the conversion performance of multiple data packets while ensuring flexible channel configurability, it is necessary to design a composite task data packet transfer method that sends once and executes multiple times. Summary of the Invention

[0005] In view of this, the present invention proposes a PCIe and RapidIO composite task packet transfer system and method, which can realize the transfer of composite task data packets between the PCIe side and the RapidIO side.

[0006] To achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A PCIe and RapidIO composite task packet transfer system includes a PCIe transceiver, an AXI4-Stream composite task data packet transfer path, an AXI4-Lite maintenance transaction transfer path, and a RapidIO transceiver; the PCIe transceiver includes a composite task data packet construction module, a PCIe root complex driver module, a PCIe physical link, and a PCIe endpoint circuit module;

[0008] The composite task data packet construction module encodes the task packet according to the number of tasks to be transmitted, the task type, and specific transaction data, generating a composite task packet;

[0009] The PCIe root complex driver module receives the data packet generated by the composite task data packet construction module and sends it to the PCIe physical link for differential transmission;

[0010] The PCIe endpoint circuit module receives data from the PCIe physical link and completes the data migration between the address space of the PCIe transceiver and the address space of the AXI4-Stream composite task data packet transfer path;

[0011] The AXI4-Lite maintenance transaction transfer path is implemented based on a dual-port cross-clock domain first-in-first-out queue to complete the transmission of maintenance transactions;

[0012] The AXI4-Stream composite task data packet transfer path receives the transaction packets sent by the PCIe transceiver. After data cross-clock domain synchronization processing, decoding, distribution, and transmission operations are performed, and finally the data is transmitted to the RapidIO transceiver;

[0013] The RapidIO transceiver is used to receive the transaction data of each format packet decoded and sent by the AXI4-Stream composite task data packet transfer path, as well as the maintenance transactions sent by the AXI4-Lite maintenance transaction transfer path.

[0014] Furthermore, the number and type of tasks are determined by the data frame header. The task type includes three categories. Among them, type I tasks are the transfer transactions of the optimized format data packets in the packet header encoding logic layer, type II tasks are port initialization transactions, and type III tasks are link self-loop test transactions;

[0015] The single task data packet input to the composite task data packet construction module is composed of a data frame header, a data payload length, device ID signal data, a HELLO format data packet, and a data payload; among them, the data frame header of the single task data packet is encoded using one-hot code. The composite task packet is composed of multiple single task data packets, and there is exactly one data frame header.

[0016] Furthermore, the AXI4-Stream composite task data packet transfer path includes a data cross-clock domain synchronization module, a first edge detection module, a task distribution module, a replay buffer module, a task arbitration module, a second edge detection module, a transaction data distribution module, and a data verification module; the RapidIO transceiver includes a RapidIO circuit interface module, a RapidIO physical link, and a peripheral RapidIO device;

[0017] The first edge detection module captures the rising edge by operating on the registered next-state handshake signal tvalid_qn and the current-state handshake signal tvalid_qn1, and grabs the frame header data carrying the task number and task type information as the selection signal of the task distribution module;

[0018] The task allocation module includes a selection signal input port controlled by a first edge detector, a task allocation enable port controlled by a replay buffer module, a transaction data input port connected to a data cross-clock domain synchronization module, and three output paths for transmitting tasks of different types; the task allocation module decodes the transaction type and the number of transactions by looking up a table for the data input through the selection signal input port, allocates and outputs the tasks, adds a frame tail check suffix, and sends them to the task arbitration module and the replay buffer module;

[0019] The task arbitration module has a priority configuration interface. The task arbitration module determines the transmission order when multiple task packets arrive simultaneously through priority arbitration; in the default configuration, the priority of type II tasks is higher than that of type III tasks, and the priority of type III tasks is higher than that of type I tasks;

[0020] The second edge detection module and the transaction data allocation module are used to capture and split the user-defined signals and data signals of type I and type III tasks output by the task arbitration module. Among them, the user-defined signals are directly output to the user-defined signal port of the RapidIO circuit interface module, and the data signals are connected to the data verification module;

[0021] The data verification module contains two data input ports, two frame tail output ports, and two types of transaction data output ports; the frame tail output ports are connected to the replay buffer module. The two types of transaction data output ports are the type I / III RapidIO basic data packet output port and the type II configuration data packet output port respectively. The type I / III RapidIO basic data packet output port is connected to the data signal port of the RapidIO circuit interface module;

[0022] The replay buffer module is implemented based on the high-speed and low-latency dedicated random access memory block in the FPGA. It buffers and temporarily stores the signals of each path output by the task allocation module, and compares the frame tail signal received from the data verification module with the temporarily stored transaction frame tail. If the comparison result is consistent, it releases the data of the corresponding task temporarily stored, feeds it back to the task allocation enable port of the task allocation module, and proceeds to the transmission of the next task; if the comparison result is inconsistent, it sends the task with transmission failure to the transaction data input port of the task allocation module for retransmission. If it still fails after the set number of replays, it feeds back the corresponding failed task to the PCIe transceiver;

[0023] The RapidIO circuit interface module completes the transmission of transactions according to the HELLO format packet header specific to type I / III tasks, and sends them to the RapidIO physical link through a high-speed transceiver, waiting for the peripheral RapidIO device to receive.

[0024] A PCIe and RapidIO composite task packet transfer method, implemented based on the PCIe and RapidIO composite task packet transfer system described in any of the above, wherein the PCIe transceiver encodes the task packet and sends it to the AXI4-Stream composite task data packet transfer path. The AXI4-Stream composite task data packet transfer path decodes the quantity and type of the task packet, and then performs distribution and transmission operations, and finally transmits the data to the RapidIO transceiver.

[0025] Further, it includes the following steps:

[0026] Step 1, the composite task data packet construction module in the PCIe transceiver encodes the task packet according to the number of tasks to be transmitted, task types, and transaction data. The encoded composite task data packet is sent to the PCIe endpoint circuit module through the PCIe root complex driver module and the PCIe link.

[0027] Step 2, the PCIe endpoint circuit module sends the composite task data packet to the AXI4-Stream composite task data packet transfer path through the internal host-to-card channel.

[0028] Step 3, the data packet is transferred to the RapidIO circuit interface module through the AXI4-Stream composite task data packet transfer path.

[0029] Step 4, the RapidIO circuit interface module receives the data packet from the AXI4-Stream composite task data packet transfer path, completes the HELLO format unpacking operation, and transmits it to the peripheral RapidIO device through the RapidIO physical link.

[0030] Further, the specific method of Step 1 is as follows:

[0031] (101) The composite task data packet construction module in the PCIe transceiver encodes the frame header according to the number of tasks to be sent and task types, and uses the first 8 Byte data signal for transmission. Among them, the number of tasks is counted in binary, a single type is encoded using one-hot code, and the composite task frame header is encoded using the OR operation of multiple single tasks.

[0032] After the header of (102) is encoded, if a type-I task is to be transmitted, the third data signal transmits the user-defined signal information, and then the transaction to be sent is encapsulated in the HELLO format, followed by the data; if a type-II task is to be transmitted, the transmission level enable signal is connected to the RapidIO transceiver, and the initialization process is controlled by the state machine inside the RapidIO transceiver to check the link status and switch the link operation mode; if a type-III task is to be transmitted, a direct loopback is performed on the physical layer transceiver link at the RapidIO transceiver, and the host terminal simulates a type-I task for transmission.

[0033] After the data encoding of each task in (103), the composite task data packet is sent to the PCIe endpoint circuit module through the PCIe root complex driver module and the PCIe physical link.

[0034] Further, the specific method of step 3 is as follows:

[0035] (301) The data packet is first synchronized through the data cross-clock domain synchronization module.

[0036] After the data is synchronized in (302), the first edge detection module grabs the first 8-Byte data frame header as the selection signal for the task allocation module; the task allocation module looks up the table based on the first 8-Byte data frame header to obtain the number of tasks and the task type, and splits different tasks and adds a frame tail check code in combination with the secondary 8-Byte data payload length field of the data input path.

[0037] In (303), the task allocation module sends the segmented data with the check code to the corresponding task paths I / II / III for transmission. At the same time, the data is also sent to the replay buffer module for temporary storage.

[0038] In (304), the data of each task path is connected to the task arbitration module, and the task arbitration module transmits the composite task data packet in the order of the fixed priority transaction; the data signals of the type-I and type-III task output channels of the task arbitration module are connected to a data distribution module, the data distribution module is connected to a second edge detection module composed of D flip-flops and logic gate structures, and the output signal of the second edge detection module is used as the selection signal for the data distribution module, so as to transmit the first data of the data signal as the ID number to the user-defined signal of the RapidIO circuit interface module, and the remaining data is transmitted to the data verification module; the type-II task data is directly transmitted to the data verification module.

[0039] The (305) data verification module captures and strips the frame tail verification packet of each task data packet, feeds the verification packet back to the replay buffer module, and transfers the I / III type task data without the frame tail to the data signal port of the RapidIO circuit interface module; for type II tasks, the transmission level enable signal is connected to the RapidIO transceiver, and the initialization process is controlled through the state machine inside the RapidIO transceiver to check the link status and switch the link operation mode.

[0040] (306)The replay buffer module temporarily stores the task data sent by the task allocation module in step (303). After receiving the verification packet fed back by the data verification module in step (305), it compares with the verification signal sent by the task allocation module that is temporarily stored. If the comparison result is consistent, it releases the temporarily stored data of the corresponding task and proceeds with the transmission of the next task; if the comparison result is inconsistent, it sends the task that fails to be transmitted to the task allocation module for retransmission, and repeats steps (302) to (306); if it still fails after the set number of replays, it feeds back the corresponding failed task to the PCIe transceiver.

[0041] The beneficial effects of the present invention are as follows:

[0042] 1. The present invention adopts a composite task data packet transfer method of single - time sending and multiple executions, and adopts appropriate data packet configuration and encoding / decoding methods, which can further improve the conversion performance of multiple data packets while ensuring the flexibility and configurability of the channel.

[0043] 2. Based on the two - way conversion of transactions such as SWRITE, NWRITE_R, NWRITE, NREAD, DOORBELL, MESSAGE, and MAINTENANCE, the present invention adds a frame header prefix to the data packet to mark multiple tasks, and adds processes such as decoding, replay buffering, and data allocation after data transfer across clock domains, which can realize the allocation and transmission of multiple tasks.

[0044] 3. The present invention can uniformly encode multiple types of tasks, can achieve the transfer of multiple tasks at one time, and on the basis of ensuring the two - way conversion of basic transactions such as SWRITE, NWRITE_R, NWRITE, NREAD, DOORBELL, MESSAGE, and MAINTENANCE, makes greater use of the PCIe bandwidth.

[0045] 4. The present invention has a replay buffer mechanism, which can automatically replay tasks that fail to be transmitted. After multiple replays fail, it will give up replaying, return the task data packet, and automatically transfer the next task to avoid problems such as system deadlock and transfer channel blockage. Description of the Drawings

[0046] Figure 1 It is the structure diagram of the composite task data packet transfer system.

[0047] Figure 2 It is the diagram of format change during data packet transfer and transmission.

[0048] In the figure: 1 - PCIe transceiver; 2 - AXI4-Stream composite task data packet transfer path; 3 - AXI4-Lite maintenance transaction transfer path; 4 - RapidIO transceiver; 5 - composite task data packet construction module; 6 - PCIe root complex driver module; 7 - PCIe physical link; 8 - PCIe endpoint circuit module; 9 - data cross-clock domain synchronization module; 10 - first edge detection module; 11 - task allocation module; 12 - replay buffer module; 13 - task arbitration module; 14 - second edge detection module; 15 - transaction data allocation module; 16 - data verification module; 17 - RapidIO circuit interface module; 18 - RapidIO physical link; 19 - peripheral RapidIO device. Detailed implementation manners

[0049] As Figure 1 shown, a PCIe and RapidIO composite task packet transfer system includes four parts: PCIe transceiver 1, AXI4-Stream composite task data packet transfer path 2, AXI4-Lite maintenance transaction transfer path 3, and RapidIO transceiver 4. The PCIe transceiver 1 includes a composite task data packet construction module 5, a PCIe root complex driver module 6, a PCIe physical link 7, and a PCIe endpoint circuit module 8; the AXI4-Stream composite task data packet transfer path 2 includes a data cross-clock domain synchronization module 9, a first edge detection module 10, a task allocation module 11, a replay buffer module 12, a task arbitration module 13, a second edge detection module 14, a transaction data allocation module 15, and a data verification module 16; the RapidIO transceiver 4 is composed of a RapidIO circuit interface module 17, a RapidIO physical link 18, and a peripheral RapidIO device 19.

[0050] The composite task data packet construction module 5 encodes the task packet according to the number of tasks to be transmitted, task types, and specific transaction data to generate a composite task packet; the number of tasks and task types are determined by an 8-Byte data frame header, and the task types include three categories. Among them, type I task is the data packet transfer transaction of the optimized format at the packet header encoding logic layer, type II task is the port initialization transaction, and type III task is the link self-loop test transaction.

[0051] As Figure 2As shown in -①, to unify the format of each task data packet, a single task data packet consists of an 8-Byte data frame header, an 8-Byte data payload length, an 8-Byte device ID signal data (reserved item for type-II tasks), an 8-Byte HELLO format data packet (reserved item for type-II tasks), and a data payload of up to 256 Bytes. Among them, the data frame header of a single task is encoded using one-hot code, and the frame header of a composite task is encoded through the encoding of a single task frame header or operation, so as to simplify the multi-task encoding logic, facilitate task allocation, and be conducive to the expansion of the number of tasks and task types. A composite task packet is composed of multiple single task data packets and contains only one data frame header.

[0052] The PCIe root complex driver module 6 receives the data packet generated by the composite task data packet construction module 5 and sends it to the PCIe physical link 7 for differential transmission. The PCIe endpoint circuit module 8 receives the data from the PCIe physical link 7 and completes the high-performance data migration between the address space of the PCIe transceiver 1 and the address space of the AXI4-Stream composite task data packet transfer path 2.

[0053] The AXI4-Lite maintenance transaction transfer path 3 is implemented based on a dual-port cross-clock domain first-in-first-out queue to complete the transmission of maintenance transactions. The AXI4-Stream composite task data packet transfer path 2 receives the transaction packet sent by the PCIe transceiver 1, performs operations such as decoding and distribution transmission after synchronous processing through the data cross-clock domain synchronization module 9, and finally transmits the data to the RapidIO transceiver 4.

[0054] The first edge detection module 10 captures the rising edge by operating on the registered next-state handshake signal tvalid_qn and the current-state handshake signal tvalid_qn1, and grabs the first 8 Bytes of data carrying the task quantity and task type information as the selection signal of the task allocation module 11.

[0055] The task allocation module 11 includes a selection signal input port controlled by the first edge detector 10, a task allocation enable port controlled by the replay buffer module, a transaction data input port connected to the data cross-clock domain synchronization module 9, and 3 transmission output paths for different types of tasks. This module decodes the transaction type and transaction quantity by looking up the table for the data input through the selection signal input port, allocates and outputs the tasks, adds a frame tail check suffix, and sends them to the task arbitration module 13 and the replay buffer module 12.

[0056] It is difficult to predict the combinational logic delay in the task allocation module 11, and the data on the task transmission output paths I / II / III may arrive at the transaction data allocation module 15 simultaneously. A task arbitration module 13 is added between the above two modules. This module integrates a fixed-priority arbitration algorithm with configurable priorities, which is used to determine the transmission order when multiple task packets arrive simultaneously. In the default configuration, the priority of class II tasks is higher than that of class III tasks, and the priority of class III tasks is higher than that of class I tasks. The priority configuration interface of the task arbitration module 13 is physically entity-constrained and can be configured as the types of tasks are added, deleted, or modified.

[0057] The second edge detection module 14 and the transaction data allocation module 15 are used to capture and split the user-defined signals tuser and data signals tdata of class I and class III tasks output by the task arbitration module. Among them, the user-defined signal tuser is directly output to the tuser signal input port of the RapidIO circuit interface module 17. The data signal is connected to the data verification module 16.

[0058] The data verification module 16 has two data input ports, two frame tail output ports, and two types of transaction data output ports. The frame tail output ports are connected to the replay buffer module 12. The two types of transaction data output ports are the class I / III RapidIO basic data packet output port and the class II configuration data packet output port respectively. The class I / III RapidIO basic data packet output port is connected to the tdata port of the RapidIO circuit interface module 17.

[0059] The replay buffer module 12 is implemented based on the high-speed and low-latency dedicated random access memory block (Block Random Access Memory, BRAM) in the FPGA. It buffers and temporarily stores the signals on each path output by the task allocation module 11 until it receives the frame tail signal sent by the data verification module 16 and compares it with the temporarily stored transaction frame tail. If the comparison result is consistent, the data of the corresponding task is released and fed back to the task allocation enable port of the task allocation module 11 for the transmission of the next task. If the comparison result is inconsistent, the task that fails to be transmitted is sent to the transaction data input port of the task allocation module 11 for retransmission. If it still fails after the set number of replays, the corresponding failed task is fed back to the PCIe transceiver 1, and the number of replays can be set.

[0060] The RapidIO transceiver 4 is used to receive the packet transaction data of each format sent after decoding by the AXI4-Stream composite task packet transfer path 2 and the maintenance transaction sent by the AXI4-Lite maintenance transaction transfer path 3. The RapidIO circuit interface module 17 completes the transmission of the transaction according to the HELLO format packet header specific to the I / III type tasks, and sends it to the RapidIO physical link 18 through the high-speed transceiver, waiting for the peripheral RapidIO device 19 to receive.

[0061] A PCIe and RapidIO composite task packet transfer method is used to add a composite task packet construction module 5 and a composite task packet transfer path 2 on the basis of realizing the basic I / O transaction transmission of PCIe and RapidIO, complete the encoding and decoding of the composite task packet, so as to realize the transmission of multiple tasks at one time in the actual application and make greater use of the PCIe transmission bandwidth. This method is implemented based on the above system. Among them, the PCIe transceiver 1 encodes the task packet and sends it to the AXI4-Stream composite task packet transfer path 2. The AXI4-Stream composite task packet transfer path 2 decodes the quantity and type of the task packet and sends it to the corresponding data channels I / II / III. Combining the task arbitration module 13 and the replay buffer module 12, it is finally transferred to the RapidIO transceiver 4. The specific steps of this method are as follows:

[0062] Step 1, the composite task packet construction module 5 encodes the task packet according to the number of tasks to be transmitted, the task type and the transaction data. The encoded composite task packet is sent to the PCIe endpoint circuit module through the PCIe root complex driver module and the PCIe link. The specific method of Step 1 is as follows:

[0063] (101) The composite task packet construction module 5 in the PCIe transceiver 1 encodes the frame header according to the number of tasks and the task type to be sent, and uses the first 8 Byte data signal tdata for transmission. Among them, the number of tasks is counted in binary, the single type is encoded by one-hot code, and the composite task frame header is encoded by the OR operation of multiple single tasks.

[0064] After the header encoding of (102), if a Class I task is to be transmitted, the third data signal tdata transmits the user-defined signal tuser information, and then the transaction to be sent is encapsulated in the HELLO format, with the data following immediately. If a Class II task is to be transmitted, the transmission level enable signal is connected to the RapidIO transceiver 4, and the initialization process is controlled by the state machine inside the RapidIO transceiver 4 to check the link status and switch the link operation mode. If a Class III task is to be transmitted, a direct loopback is performed on the physical layer transceiver link at the RapidIO transceiver 4, and the host terminal can simulate the transmission of a Class I task.

[0065] After the data encoding of each task in (103), the composite task data packet is sent to the PCIe endpoint circuit module 8 through the PCIe root complex driver module 6 and the PCIe physical link 7.

[0066] Step 2: The PCIe endpoint circuit module 8 sends the composite task data packet to the AXI4-Stream composite task data packet transfer path 2 through the internal host-to-card channel.

[0067] Step 3: The data packet is transferred to the RapidIO circuit interface module 17 through the AXI4-Stream composite task data packet transfer path 2.

[0068] (301) The data packet is first synchronized through the data cross-clock domain synchronization module 9.

[0069] After the data is synchronized, the first edge detection module 10 grabs the first 8-Byte data frame header as the selection signal for the task allocation module 11. The task allocation module 11 looks up the table for this 8-Byte data to obtain the number of tasks and the task type, and splits different tasks and adds the frame tail check code in combination with the secondary 8-Byte data payload length field of the data input path.

[0070] As shown in Figure 2 -② for the data packet format, the task allocation module 11 sends the split data with the check code to the corresponding task paths I / II / III for transmission. At the same time, the data is also sent to the replay buffer module 12 for temporary storage.

[0071] The data connections of each task path are connected to the task arbitration module 13. The task arbitration module 13 transmits the composite task data packets in sequence according to the fixed priority transaction order, ensuring the stability of the configuration, test, and data transaction transmissions. The data signal tdata of the Class I and Class III task output channels of the task arbitration module 13 is connected to a data distribution module 15. The data distribution module 15 is connected to a second edge detection module 14 composed of D flip-flops and logic gate structures. The output signal of the second edge detection module 14 serves as the selection signal for the data distribution module 15. This structure realizes the transfer of the first data of the data signal tdata as the ID number to the user-defined signal tuser of the RapidIO circuit interface module 17, and the remaining data is transferred to the data verification module 16; the Class II task data is directly transferred to the data verification module 16.

[0072] (305)As Figure 2 shown in the data packet format of -③, the data verification module 16 grabs and strips the frame tail verification packet of each task data packet, feeds the verification packet back to the replay buffer module 12, and transfers the Class I / III task data without the frame tail to the data signal port tdata of the RapidIO circuit interface module 17. The Class II tasks are transmitted as described in (102).

[0073] (306)The replay buffer module 12 temporarily stores the task data sent by the task distribution module 11 described in (303). After receiving the verification packet fed back by the data verification module 16 described in (305), it compares it with the verification signal sent by the task distribution module 11 that is temporarily stored. If the comparison result is consistent, it releases the temporarily stored data of the corresponding task and proceeds to the transmission of the next task. If the comparison result is inconsistent, it sends the task that fails to be transmitted to the task distribution module 11 for retransmission, repeating steps (302) to (306). If it still fails after the set number of replays, it feeds back the corresponding failed task to the PCIe transceiver 1, and the number of replays can be set.

[0074] Step 4: The RapidIO circuit interface module 17 receives the data packet from the AXI4-Stream composite task data packet transfer path 2, completes operations such as unpacking the HELLO format, and transmits it to the peripheral RapidIO device 19 through the RapidIO physical link 18.

[0075] Finally, it should be noted that the above-described embodiments are only specific embodiments of the present invention, which are used to illustrate the technical solutions of the present invention, rather than limiting them. The protection scope of the present invention is not limited thereto. The basic idea of the present invention is to add a composite task data packet construction module and a composite task data packet transfer module on the basis of a traditional PCIe to RapidIO data transmission system to complete the encoding and decoding of the composite task data packet, and realize the function of transmitting multiple RapidIO transactions / configurations in one task packet, so as to further utilize the hardware resources and transmission bandwidth.

Claims

1. A PCIe and RapidIO composite task packet transfer system, characterized in that, It includes a PCIe transceiver, an AXI4-Stream composite task data packet transfer path, an AXI4-Lite maintenance transaction transfer path, and a RapidIO transceiver; The PCIe transceiver includes a composite task data packet construction module, a PCIe root complex driver module, a PCIe physical link, and a PCIe endpoint circuit module; The composite task data packet construction module encodes the task packet according to the number of tasks to be transmitted, the task type, and the specific transaction data to generate a composite task packet; The PCIe root complex driver module receives the data packet generated by the composite task data packet construction module and sends it to the PCIe physical link for differential transmission; The PCIe endpoint circuit module receives the data from the PCIe physical link and completes the data migration between the address space of the PCIe transceiver and the address space of the AXI4-Stream composite task data packet transfer path; The AXI4-Lite maintenance transaction transfer path is implemented based on a dual-port cross-clock domain first-in-first-out queue to complete the transmission of maintenance transactions; The AXI4-Stream composite task data packet transfer path receives the transaction packet sent by the PCIe transceiver, performs decoding, distribution, and transmission operations after data cross-clock domain synchronization processing, and finally transmits the data to the RapidIO transceiver; The RapidIO transceiver is used to receive the transaction data of each format packet decoded and sent by the AXI4-Stream composite task data packet transfer path, and the maintenance transactions sent by the AXI4-Lite maintenance transaction transfer path.

2. The PCIe and RapidIO composite task packet transfer system according to claim 1, wherein The number of tasks and the task type are determined by the data frame header. The task type includes three categories. Among them, type I task is the data packet transfer transaction of the optimized format of the header encoding logic layer, type II task is the port initialization transaction, and type III task is the link self-loop test transaction; The single task data packet input to the composite task data packet construction module consists of a data frame header, a data payload length, device ID signal data, a HELLO format data packet, and a data payload; among them, the data frame header of the single task data packet is encoded using a one-hot code. The composite task packet is composed of multiple single task data packets, and there is exactly one data frame header.

3. The PCIe and RapidIO composite task packet transfer system according to claim 2, characterized in that, The AXI4-Stream composite task data packet transfer path includes a data cross-clock domain synchronization module, a first edge detection module, a task distribution module, a replay buffer module, a task arbitration module, a second edge detection module, a transaction data distribution module, and a data verification module; the RapidIO transceiver includes a RapidIO circuit interface module, a RapidIO physical link, and a peripheral RapidIO device; The first edge detection module captures the rising edge by operating on the registered next-state handshake signal tvalid_qn and the current-state handshake signal tvalid_qn1, and grabs the frame header data carrying the number of tasks and task type information as the selection signal of the task distribution module; The task allocation module includes a selection signal input port controlled by a first edge detector, a task allocation enable port controlled by a replay buffer module, a transaction data input port connected to a data cross-clock domain synchronization module, and three output paths for transmitting tasks of different types; The task allocation module decodes the transaction type and the number of transactions by looking up the data input through the selection signal input port, allocates and outputs the tasks, adds a frame tail check suffix, and sends them to the task arbitration module and the replay buffer module; The task arbitration module has a priority configuration interface. The task arbitration module determines the transmission order when multiple task packets arrive simultaneously through priority arbitration; in the default configuration, the priority of type II tasks is higher than that of type III tasks, and the priority of type III tasks is higher than that of type I tasks; The second edge detection module and the transaction data allocation module are used to capture and split the user-defined signals and data signals of type I and type III tasks output by the task arbitration module. The user-defined signals are directly output to the user-defined signal port of the RapidIO circuit interface module, and the data signals are connected to the data verification module; The data verification module has two data input ports, two frame tail output ports, and two types of transaction data output ports; the frame tail output ports are connected to the replay buffer module. The two types of transaction data output ports are the type I / III RapidIO basic data packet output port and the type II configuration data packet output port. The type I / III RapidIO basic data packet output port is connected to the data signal port of the RapidIO circuit interface module; The replay buffer module is implemented based on the high-speed and low-latency dedicated random access memory block in the FPGA. It buffers and temporarily stores the signals of each path output by the task allocation module, and compares the frame tail signal received from the data verification module with the temporarily stored transaction frame tail. If the comparison result is consistent, it releases the temporarily stored data of the corresponding task, feeds it back to the task allocation enable port of the task allocation module, and proceeds with the transmission of the next task; if the comparison result is inconsistent, it sends the task with transmission failure to the transaction data input port of the task allocation module for retransmission. If it still fails after the set number of replays, it feeds back the corresponding failed task to the PCIe transceiver; The RapidIO circuit interface module completes the transmission of transactions according to the HELLO format packet header specific to type I / III tasks, and sends them to the RapidIO physical link through a high-speed transceiver, waiting for the peripheral RapidIO device to receive.

4. A PCIe and RapidIO composite task packet transfer method, implemented based on the PCIe and RapidIO composite task packet transfer system according to any one of claims 1 to 3, wherein, The PCIe transceiver encodes the task packet and sends it to the AXI4-Stream composite task data packet transfer path. The AXI4-Stream composite task data packet transfer path decodes the number and type of the task packet, and then performs allocation and transmission operations, and finally transmits the data to the RapidIO transceiver.

5. A PCIe and RapidIO composite task packet transfer method according to claim 4, characterized in that It includes the following steps: Step 1, the composite task data packet construction module encodes the task packet according to the number of tasks to be transmitted, task types, and transaction data. The encoded composite task data packet is sent to the PCIe endpoint circuit module through the PCIe root complex driver module and the PCIe link; Step 2, the PCIe endpoint circuit module sends the composite task data packet to the AXI4-Stream composite task data packet transfer path through the internal host-to-card channel; Step 3, the data packet is transferred to the RapidIO circuit interface module through the AXI4-Stream composite task data packet transfer path; Step 4, the RapidIO circuit interface module receives the data packet from the AXI4-Stream composite task data packet transfer path, completes the unpacking operation of the HELLO format, and transmits it to the peripheral RapidIO device through the RapidIO physical link.

6. A PCIe and RapidIO composite task packet transfer method according to claim 5, wherein The specific method of Step 1 is as follows: (101) The composite task data packet construction module in the PCIe transceiver encodes the frame header according to the number of tasks and task types to be sent, and uses the first 8 Byte data signal for transmission. Among them, the number of tasks is counted in binary, a single type is encoded using the one-hot code, and the composite task frame header is encoded using the logical OR operation of multiple single tasks; (102) After the packet header encoding is completed, if transmitting type I tasks, the third data signal transmits the user-defined signal information, and then the HELLO format encapsulation is performed on the transaction to be sent, and the data follows immediately; if transmitting type II tasks, the transmission level enable signal is connected to the RapidIO transceiver, and the initialization process is controlled by the state machine inside the RapidIO transceiver to check the link status and switch the link operation mode; if transmitting type III tasks, a direct loopback is performed on the physical layer transceiver link at the RapidIO transceiver, and the host computer terminal simulates type I tasks for transmission; (103) After the encoding of each task data is completed, the composite task data packet is sent to the PCIe endpoint circuit module through the PCIe root complex driver module and the PCIe physical link.

7. A PCIe and RapidIO composite task packet transfer method according to claim 5, characterized in that The specific method of Step 3 is as follows: (301) The data packet is first synchronized through the data cross-clock domain synchronization module; (302) After data synchronization, the first edge detection module grabs the first 8 Byte data frame header as the selection signal for the task allocation module; the task allocation module looks up the table for the first 8 Byte data frame header to obtain the number of tasks and task types, and combines the secondary 8 Byte data payload length field of the data input path to split different tasks and add a frame tail check code; (303) The task allocation module sends the split data with the check code to the corresponding task paths I / II / III for transmission. At the same time, the data is also sent to the replay buffer module for temporary storage; (304) The data of each task path is connected to the task arbitration module, and the task arbitration module transmits the composite task data packet in the order of fixed priority transactions; Task The data signals of the Class I and Class III task output channels of the arbitration module are connected to a data distribution module. The data distribution module is connected to a second edge detection module composed of D flip-flops and logic gate structures. The output signal of the second edge detection module serves as the selection signal for the data distribution module, so as to transfer the first data of the data signal as the ID number to the user-defined signal of the RapidIO circuit interface module, and the remaining data is transferred to the data verification module; the Class II task data is directly transferred to the data verification module; (305) The data verification module grabs and strips the frame tail verification packet of each task data packet, feeds the verification packet back to the replay buffer module, and transfers the Class I / III task data without the frame tail to the data signal port of the RapidIO circuit interface module; for Class II tasks, the transmission level enable signal is connected to the RapidIO transceiver, and the initialization process is controlled by the state machine inside the RapidIO transceiver to check the link status and switch the link operation mode; (306) The replay buffer module temporarily stores the task data sent by the task distribution module in step (303). After receiving the verification packet fed back by the data verification module in step (305), it compares it with the verification signal sent by the temporarily stored task distribution module. If the comparison result is consistent, the temporarily stored data of the corresponding task is released to proceed with the transmission of the next task; if the comparison result is inconsistent, the task that fails to be transferred is sent to the task distribution module for retransmission, and steps (302) to (306) are repeated; if it still fails after the set number of replays, the corresponding failed task is fed back to the PCIe transceiver.

Images