Detection of time conditions related to a two-wire bus

Abstract

The present disclosure relates to detection of time conditions related to a two-wire bus. A value representing the duration of a low state of a synchronization signal on the bus is measured and then compared to a threshold value. The threshold value is stored in a memory and the measured value represents the longest duration of a low state of the synchronization signal in a first comparison.

Description

[0001] This application is a divisional application of patent application No. 201811142366.7, filed on September 28, 2018, entitled "Detection of timing conditions related to a two-wire bus". Technical Field

[0002] This disclosure generally relates to electronic circuits, and more specifically to circuits capable of being connected to an I2C two-wire bus. Background Technology

[0003] The I2C bus is a two-wire bus consisting of two conductors, one for serially transmitting data and the other for transmitting a synchronization signal. SMB, or System Management Bus (SMBus), is a specific I2C bus that further provides the detection of timing conditions related to the duration of the synchronization signal's low state. More specifically, the SMB standard provides the ability to detect whether the synchronization signal is held low for a given period of time. Summary of the Invention

[0004] The embodiments of this disclosure overcome all or part of the drawbacks of existing methods and / or circuits for detecting timing conditions related to the duration of a low state of a synchronization signal for an I2C bus, particularly an SMB.

[0005] Another embodiment more specifically relates to detecting timing conditions related to the duration of a low state of the synchronization signal of the I2C bus, particularly the SMB, during the transmission of bytes on the I2C bus.

[0006] Another embodiment eliminates manufacturing dispersion of the circuit, which verifies timing conditions related to the duration of the low state of the synchronization signal of the I2C bus, and more particularly the SMB.

[0007] Therefore, embodiments provide a method in which a value representing the duration of a low state of a bus synchronization signal is compared with a threshold stored in memory, the value representing the longest duration of the low state of the signal in a first comparison.

[0008] According to an embodiment, in the first comparison, the value represents the longest duration of the low state of the signal that has occurred prior to the first comparison.

[0009] According to an embodiment, the first comparison is performed after a threshold is read from the memory, and the read is performed synchronously with a synchronization signal.

[0010] According to the embodiment, the memory is a non-volatile memory.

[0011] According to an embodiment, the threshold stored in the memory is determined during the calibration phase.

[0012] According to the embodiment, the bus is an I2C bus, such as an SMB.

[0013] According to an example, the threshold represents the duration in the range of 25ms to 35ms.

[0014] According to an embodiment, after the bus has been set to operate, a threshold is read from the memory during the first transmission of bytes on the bus.

[0015] According to an embodiment, the first comparison should be performed before the time when the acknowledgment of the byte is transmitted on the bus.

[0016] According to an embodiment, the first comparison is performed between the transmission of the last bit of the byte and the aforementioned time.

[0017] Another embodiment also provides an apparatus capable of implementing the above-described method.

[0018] According to an embodiment, the device includes an oscillator and a counter configured to count the number of cycles of the oscillator during each low state of the signal, the value being determined based on the number of cycles counted for each low state.

[0019] According to an embodiment, after each low state of the signal prior to the first comparison, if the number of cycles is greater than the value, the value is updated using the number of cycles counted during the low state.

[0020] According to the embodiment, the memory, oscillator, and counter also implement an presence detection function.

[0021] According to an embodiment, the memory is an EEPROM type memory, and the oscillator and counter belong to the circuitry used for writing to the memory. Attached Figure Description

[0022] The foregoing and other features and advantages are discussed in detail in the following non-limiting description of specific embodiments, taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 It is a simplified representation in the form of a block of an electronic system that includes circuitry connected to the I2C bus;

[0024] Figure 2 It is shown in a very schematic way. Figure 1 Timing diagram of communication between two circuits in an electronic system according to the I2C protocol;

[0025] Figure 3 It shows the detection and Figure 1 A flowchart illustrating an embodiment of a method for determining the duration of a low-state condition related to the synchronization signal of a bus; and

[0026] Figure 4 It is shown Figure 3 Timing diagrams of more detailed embodiments of the method. Detailed Implementation

[0027] In the different accompanying drawings, the same elements are designated by the same reference numerals. For clarity, only those steps and elements useful for understanding the described embodiments are shown and described in detail. In particular, the operation of the SMB is not described in detail; the described embodiments are compatible with the general operation of an SMB. Furthermore, the operation of devices or circuits connected to the SMB is not described; the described embodiments are compatible with commonly used devices or circuits intended for connection to an SMB.

[0028] In the following description, SMB refers to the bus according to the "System Management Bus" or SMBus standard, which was published on December 20, 2014 and is available at http: / / smbus.org / specs / SMBus_3_0_20141220.pdf.

[0029] Figure 1 This is a simplified representation of an electronic system, in the form of a box, including circuits 1, 3, and 5 connected to the I2C bus 7. Bus 7 includes conductor 9 for transmitting the binary data signal SDA and conductor 11 for transmitting the binary synchronization signal SCL. Each circuit 1, 3, and 5 is connected to conductors 9 and 11. Each circuit 1, 3, and 5 is also connected to conductor 13, which is set to a reference potential, typically ground (GND). Circuits 1, 3, and 5, and other circuits connected to the I2C bus or belonging to the same electronic circuit, can be powered at the same or different voltages. For example, circuits 1, 3, and 5 are connected to conductor 15, which is set to a positive power supply potential Vdd relative to ground (GND). Conductors 9 and 11 are connected to conductor 15 via pull-up resistors Rp, respectively. Therefore, in the idle state, signals SDA and SCL are at potentials close to the potential Vdd, which represents one of the two binary states (high state) of signals SDA and SCL, the other binary state (low state) represented by the ground potential GND.

[0030] In the I2C protocol setup, for transmissions on bus 7, one circuit (e.g., circuit 1) is used as the master (MD) and applies the synchronization signal SCL. Other circuits connected to the bus (e.g., 3 and 5) then have a slave (SD) status to receive data transmitted by circuit 1. This data can be directed to multiple slave circuits or to a single circuit among them. Depending on the communication direction, the same circuit can initially have a master function and then a slave function.

[0031] Figure 2 It is shown in a very schematic way. Figure 1A timing diagram of communication between two circuits in an electronic system according to the I2C protocol. The timing diagram, not drawn to scale, shows an example of the shapes of signals SCL and SDA.

[0032] The I2C protocol defines the communication start condition START by switching the signal SDA low (at time t0) while the signal SCL is high. This switching is initiated by one circuit in a network that adopts the master state for communication. Different slave circuits monitor the corresponding states of signals SCL and SDA and detect the START condition, which indicates that communication will begin.

[0033] Then, the master circuit (here, circuit 1) transmits the first byte. To do this, after switching the signal SCL low at time t1 following time t0, the master circuit 1 applies the state of the signal SDA at time t2 following time t1, based on the state of the first bit B7 of the byte to be transmitted, and then releases the signal SCL high at time t3 following time t2. During the next rising edge of the signal SCL, at time t3, the state of the signal SDA is read by the slave circuits (here, circuits 3 and 5). At time t4 following time t3, when the signal SCL returns to low, the master circuit 1 continues operating using the next bit B6, B5...B0 until the entire byte has been transmitted. Most commonly, the first byte sent by the master circuit 1 includes seven address bits identifying the receiving circuit, followed by bits indicating the expected operation (read / write) of the master circuit. Different slave circuits detect the transmitted data and, in particular, determine whether the next byte (or subsequent bytes) is for them based on the first byte forming the receiving address.

[0034] At the end of the last bit B0 of the first byte (time t5), when the master circuit sets the signal SCL low, it releases the signal SDA high. The slave circuit (e.g., circuit 3), identified by the transmitted address, acknowledges (ACKs) the transmitted byte by switching the signal SDA low at time t6 after time t5. At time t7 after time t6, at the next rising edge of the signal SCL, the master circuit 1 detects this low state of the signal SDA. At time t8 after time t7, when the signal SCL switches back low, the master circuit 1 can transmit the next byte, and so on, until the communication ends.

[0035] Once the next byte (or subsequent bytes) has been transmitted, and an acknowledgment (ACK) has been received from slave circuit 3 after each byte transmission, master circuit 1 applies the stop condition STOP by releasing signal SDA to high (time t9) while signal SCL is high. Slave circuits 3 and 5, which monitor the differences in signals SCL and SDA, detect the STOP state indicating the end of communication. Then, circuits 1, 3, and 5 connected to the bus are placed into a state where they await new communication (in other words, await a new condition START). For example, each circuit 1, 3, and 5 includes an interface for reading / writing on bus 7, which is then set to this state of waiting for a new condition START.

[0036] If no acknowledgment is sent from the circuit after the main circuit transmits the byte ( Figure 2 (Not shown in the diagram), the SDA signal remains high after the transmission of the last bit of the byte. Main circuit 1 detects no ACK at the next rising edge of the SCL signal. It can then transmit a new condition START, also known as condition RESTART or condition STOP.

[0037] In addition to the operations described above, the SMB protocol also provides a mechanism to detect when the SCL signal remains blocked in a low state for a time longer than a given maximum time period DMAX, which is the same for all circuits connected to the bus. The time period DMAX is in the range of 25 to 35 ms, for example, 30 ms, and... Figure 2 The diagram is shown in the figure between time t10 and t11.

[0038] To verify that the duration of each low state of signal SCL remains below the selected time period DMAX, each circuit connected to the bus is configured to include a circuit capable of supplying a value representing the duration of each low state of signal SCL. This value is then compared to a threshold representing the time period DMAX. For example, the duration of a low state of signal SCL can be represented by the number of oscillator cycles counted during this low state, and this number of cycles is then compared to the number of oscillator cycles corresponding to the time period DMAX (i.e., the threshold representing the time period DMAX).

[0039] It can be configured such that, for a selected time period DMAX, the threshold representing DMAX is the same for multiple circuits. For example, each of these circuits could include a register whose contents are initialized to contain the threshold. The threshold would then be available once the circuit is powered on. However, due to manufacturing dispersion among identical circuits, the value representing the same duration of a low state of signal SCL might differ between circuits. This could cause one circuit to detect that the duration of this low state SCL exceeds the selected time period DMAX, while another circuit, even if identical, might not detect it.

[0040] Therefore, a calibrated threshold TIMEOUT is provided for each circuit to account for manufacturing variations between identical circuits. The calibrated threshold is then stored in the circuit's non-volatile memory. It can be configured so that the calibrated threshold stored in memory is read out once the circuit is powered on, but this would require a specific readout device and a synchronization signal specific to that readout device.

[0041] In the above embodiments, an initialization phase is provided during which a threshold representing the time period DMAX is read from non-volatile memory. This initialization phase is implemented in each circuit connected to the bus. The initialization phase begins simultaneously with the start of byte transmission on the bus and ends before an acknowledgment (ACK) for that byte should be generated. In other words, the initialization phase occurs during byte transmission. More specifically, the initialization phase is implemented after the circuit connected to the bus has been powered on, during the transmission of the first byte on the bus.

[0042] As an example, the start of the initialization phase corresponds to the detection of the condition START that indicates the start of communication, and the initialization phase is performed during the transmission of the first byte of this communication.

[0043] During the initialization phase, a threshold representing the time period DMAX is read from memory synchronously with the signal SCL, while simultaneously determining a value representing the longest duration of the low state of the signal SCL. At the end of the initialization phase, if the determined value is greater than the read threshold, at least one of the low states of the signal SCL has lasted longer than the time period DMAX. Each circuit is then placed in the same state as when the condition STOP is received, for example, by resetting its bus read / write interface, and the circuitry used to generate an ACK for the transmitted byte during the initialization phase will not generate an ACK for that byte. Therefore, when the first duration of the low state of the signal SCL is measured before the read of the threshold representing the time period DMAX, verification of the fact that the duration of the low state of the signal SCL has exceeded the threshold time period DMAX is performed. This simplifies the read of the threshold from memory, which can then be performed synchronously with the signal SCL in the same way as conventionally reading data from memory. In practice, if a new condition START is transmitted before an ACK for the byte should be generated, the transmission of the byte on the bus can be interrupted. In this case, if the initialization phase is in progress, it is interrupted and canceled, and a new initialization phase is implemented the next time a byte is transmitted on the bus.

[0044] The advantage here is that, during the transmission of the first byte after the circuit connected to the bus is powered on, if at least one low state of the signal SCL lasts longer than the time period DMAX during this transmission period, this has no impact before an acknowledgment (ACK) for the transmitted byte should be generated, especially for the main circuit. Another advantage is that the threshold representing the time period DMAX, read from memory synchronously with the signal SCL, ends before an acknowledgment (ACK) for this byte should be generated.

[0045] Many circuits designed for connection to SMBs already include non-volatile memory, such as EEPROM, and circuitry for reading from this memory, synchronized with the SCL signal. The advantage is that a threshold representing the time period DMAX can be stored in this existing memory and read by circuitry used to read from this memory, without the need for a specific readout circuitry. A concrete example of circuitry including non-volatile memory, such as EEPROM, and a device for reading from this memory is circuitry implementing an presence detection function, commonly abbreviated as "Serial Presence Detection" (SPD). This function is implemented, for example, by providing an EEPROM for DRAM (Dynamic Random Access Memory) circuitry, where information about DRAM operation is stored, such as information related to the access time of the DRAM.

[0046] Figure 3 It shows the detection and Figure 1 A flowchart of an embodiment of a method relating the duration of the low state of the bus synchronization signal to time conditions, the method being implemented, for example, by each of circuits 1, 3 and 5 connected to the bus.

[0047] The method begins with initialization phase 303. During initialization phase 303, in step 305 (READ TIMEOUT), a threshold TIMEOUT representing the time period DMAX is read from memory. Step 305 (READ TIMEOUT) is executed in parallel with steps 307, 309, 311, 313, 315, and 317, which determine the value representing the longest duration of being in the low state of signal SCL during initialization phase 303. As previously described, this initialization phase begins simultaneously with the start of byte transmission on the bus (e.g., the first byte transmitted after the circuitry to the bus is powered on).

[0048] In initialization phase 303, before the first low state of signal SCL after the start of initialization phase 303 (in... Figure 2 In step 307 (INIT VALUE, i.e., initialize VALUE) executed between time t0 and t1, the value VALUE is initialized, for example, to zero. Following step 307 is step 309 (SCL LOW?, i.e., SCL is low?), which detects whether the signal SCL is switched to a low state. When the signal SCL switches to a low state (output Y of box 309), the value DSCL representing the duration of this low state is determined in the next step 311 (DETERMINE DSCL, i.e., determine DSCL). Following step 311 is step 313 (DSCL>VALUE?), where the value DSCL is compared with the value VALUE. If the value DSCL is greater than the value VALUE (output Y of box 313), then in the next step 315 (VALUE=DSCL) before step 317 (END INITIALIZATION?, i.e., end initialization?), the value VALUE is updated with the value DSCL. Otherwise (output N of box 313), step 313 is immediately followed by step 317.

[0049] Step 317 includes verifying whether the initialization phase has ended. If the initialization phase 303 has not ended (output N of block 317), then steps 309, 311, 313, 317 and possibly 315 are executed again. Thus, during the initialization phase, for each cycle of signal SCL, the loop including steps 309, 311, 313, 315 and 317 is executed once. If the initialization phase 303 has ended (output Y of block 317), then in the next step 319 (VALUE < TIMEOUT?), the value VALUE is compared with the threshold TIMEOUT. According to an embodiment, the initialization phase 303 ends at the eighth rising edge of signal SCL after the start of the initialization phase 303. In an alternative embodiment, the initialization phase 303 ends at a given rising edge of signal SCL for which it is known that the reading of the threshold representing the time period DMAX has ended, and this given rising edge is before the eighth rising edge of signal SCL after the start of the initialization phase 303.

[0050] During the first comparison 319, the value VALUE represents the longest duration of the low state of signal SCL during the initialization phase 303. In the case where the initialization phase 303 ends at the eighth rising edge of signal SCL after the start of the initialization phase 303, this first comparison 319 is performed, for example, before the falling edge of signal SCL after this eighth rising edge, such that the result of this first comparison 319 is known before the time ( Figure 2 time t6 in) at which the acknowledgement ACK of the byte transmitted during the initialization phase should be generated. In the case where the initialization phase 303 ends at a given rising edge of signal SCL before the eighth rising edge of signal SCL after the start of this initialization phase, the first comparison 319 is performed, for example, between this given rising edge and the next falling edge of signal SCL.

[0051] If in step 319, the value VALUE is greater than the threshold TIMEOUT (output Y of block 319), then at least one low state of signal SCL during the initialization phase 303 has lasted longer than the time period DMAX. In the next step 321 (RESET, i.e., reset), then, the circuit implementing the method is placed in the same state as if it had received the condition STOP. Otherwise (output N of block 319), in Figure 3In the illustrated embodiment, the circuit verifies whether each subsequent low state of the signal SCL lasts longer than the time period DMAX. To achieve this, in step 309' (SCL LOW?, i.e., SCL is low?) immediately following step 319, the signal SCL is detected to switch to a low state, and when the signal SCL switches to a low state (output Y of block 309'), the value DSCL of this low state is determined in the next step 311' (DETERMINE DSCL, i.e., determine DSCL), step 311' being, for example, the same as step 311. Then, before executing step 319 again, the value VALUE is updated with the value DSCL in step 315' (VALUE = DSCL), where the value VALUE now represents the duration of the last low state of the signal SCL.

[0052] In an alternative embodiment, step 315' is replaced by a step of directly comparing the threshold TIMEOUT with the value DSCL determined in the previous step 311'. If the value DSCL is greater than the threshold TIMEOUT, the next step is step 321; otherwise, the next step is step 309'.

[0053] In another alternative embodiment, a step similar to or the same as step 313 is provided between steps 311' and 315', such that the value VALUE is updated with the last value DSCL only when the value DSCL represents the longest duration of the low state of the signal SLC that has occurred.

[0054] In another alternative embodiment, initialization phase 303 is performed for each byte transmitted on the bus. Preferably, each initialization phase then ends at the eighth rising edge after the start of this initialization phase. Furthermore, in this variation, initialization phase 303 is preferably configured to include two additional steps. The first of the two additional steps is performed, for example, between steps 317 and 319, and includes modifying the state of a flag to indicate that a threshold has been read. The second of the two additional steps is performed, for example, only in step 305 (… Figure 3The process executes before the right-hand branch (in the first initialization phase 303) and includes verifying the state of the flag, such that if the flag indicates that the threshold TIMEOUT has been read during the previous initialization phase 303, step 305 is not executed. Therefore, the threshold TIMEOUT will only be read once at the first initialization phase 303, which allows for limiting read access to the memory where the threshold TIMEOUT is stored, and thus reduces the power consumption of the circuitry implementing the initialization phase 303. Preferably, the first initialization phase begins with the detection condition START, during which the threshold TIMEOUT is read. Therefore, it is advantageous that reading the threshold TIMEOUT from memory is performed during the transmission of a byte formed by the address of the receiving circuit and bits indicating the desired operation (read / write), which makes it possible to avoid reading the threshold from memory while data is to be transmitted on the bus. As an example, the flag corresponds to a first binary state indicating that the threshold TIMEOUT has not yet been read and a second binary state indicating that the threshold TIMEOUT has been read.

[0055] although Figure 3 Not shown in the diagram, but if a new condition START is transmitted during initialization phase 303, as previously described, this initialization phase is interrupted and canceled, and a new initialization phase 303 is implemented during the next transmission of bytes.

[0056] In the following description, implementation Figure 3 The method considers a case where each circuit includes an oscillator and a counter synchronized with that oscillator, and the period of the signal provided by the oscillator is shorter than the period of the signal SCL of the bus to which the circuit is intended to connect. For each low state of the signal SCL, the value DSCL then corresponds to the number of oscillator cycles counted during that low state. By counting the number of oscillator cycles during the time period DMAX, the calibrated threshold TIMEOUT of the circuit is determined by means of the oscillator and the counter of the circuit. The calibrated threshold TIMEOUT is then equal to the number of cycles counted during the time period DMAX, that is, equal to the content of the counter at the end of the time period DMAX, and is recorded in the circuit memory. This calibration phase is performed for each circuit intended to connect to the same bus using the same time period DMAX.

[0057] Figure 4 This illustrates, for example, an implementation using an EEPROM-type memory. Figure 3 Timing diagrams of more detailed embodiments of the method. Figure 4 The methods include those that have already been combined Figure 3 The steps described are indicated by the same reference numerals in the accompanying drawings, and these steps will not be described again.

[0058] In this embodiment, after step 305 of reading the threshold TIMEOUT from the memory (here, an EEPROM-type non-volatile memory), step 501 of writing the threshold TIMEOUT to the first register RegA (RegA = TIMEOUT) follows. The duration of the low state of signal SCL is represented by the number of oscillator cycles, which is counted by a counter C associated with the oscillator (e.g., the oscillator and counter of the circuitry used for writing to the EEPROM). Figure 3 In contrast, step 311 is replaced by equivalent steps 503, 505, and 507. In step 503, immediately after detecting a low state of signal SCL (output Y of block 309), counter C is initialized to zero (C = 0), and then, in the next step 505 (INC C), counter C is incremented once in sync with the oscillator. After step 505, step 507 (SCL HIGH?, i.e., SCL is high?) ​​includes verifying whether signal SCL has switched to a high state. If not (output N of block 507), signal SCL remains low, and step 505, which increments the counter, is executed again. Otherwise (output Y of block 507), signal SCL is high, and then the content of counter C represents the duration of the last low state of signal SCL. Similarly, step 311' ( Figure 3 The steps 503', 505' and 507' are replaced with equivalent steps 503', 505' and 507', which are the same as steps 503', 505' and 507', respectively.

[0059] Furthermore, in this embodiment, regarding Figure 3 The described value VALUE corresponds to the content of the second register RegB. Therefore, step 307 ( Figure 3 Step 313 is replaced by the equivalent step 509 (RegB = 0) of initializing register RegB, and step 313 is replaced by the equivalent step 511 (C > RegB?) of comparing the content of counter C with the content of register RegB. In step 511, if the content of counter C is greater than the content of register RegB (output Y of box 511), then register RegB is updated with the content of counter C in the next step 513 (RegB = C). Similarly, step 315' ( Figure 3 The step 513 is replaced with an equivalent step 513' that is the same as step 513. In addition, step 319, which compares the value VALUE with the threshold TIMEOUT, is replaced with an equivalent step 515 (RegB>RegA?) that compares the contents of register RegB with the contents of register RegA.

[0060] At the beginning of initialization phase 303, for example, just before step 509, as in this case, step 517 (i = 0) initializes the loop variable i to zero. It can be understood that step 517 can be executed in parallel with step 509 or just after step 509. For each detection of the rising edge of signal SCL (output Y of block 507), the loop variable i is incremented in step 519 (i = i + 1), which is executed, for example, between steps 507 and 511.

[0061] In this embodiment, initialization phase 303 ends at the eighth rising edge of signal SCL after the initialization begins. Then, step 317 is replaced by an equivalent step 521 (i = 8?), which includes verifying whether variable i is equal to 8, that is, whether the eighth rising edge of signal SCL has just occurred, which marks the end of initialization phase 303.

[0062] Therefore, during the first comparison 515 after initialization phase 303, the value VALUE, which represents the longest duration of being in a low state and is stored in register RegB, is effectively compared with the threshold TIMEOUT, which is read from memory and stored in register RegA.

[0063] about Figure 3 The described alternative embodiments can be converted into information about Figure 4 The described embodiments.

[0064] Specific embodiments have been described. Various changes, modifications, and improvements will be readily apparent to those skilled in the art. In particular, Figure 1 An electronic system may include multiple circuits that are different from the circuit shown in the figure.

[0065] Able to achieve Figure 3 and Figure 4 The circuitry of the method is not limited to circuitry including EEPROM-type non-volatile memory and its readout circuitry. Other circuitry designed based on the above description to implement this method is within the capabilities of those skilled in the art.

[0066] adapt Figure 3 and 4The number of steps and / or steps of the method are also within the capabilities of those skilled in the art. For example, step 503 of initializing counter C can be performed before step 309, between step 501 and step 309, while initialization phase 303 has not yet ended (branch N of block 501). Furthermore, the previously described method and calibration phase can also be applied to cases where the duration of each low state of signal SCL is represented by using a down counter instead of a value determined by the counter, and more generally to cases where the duration can be represented by, for example, voltage level in addition to the number of oscillator cycles.

[0067] Such changes, modifications, and improvements are intended to be part of this disclosure and are intended to fall within the spirit and scope of the invention. Therefore, the foregoing description is exemplary only and not restrictive. The invention is limited only by the following claims and their equivalents.

Claims

1. A method comprising: A threshold is stored in the memory of a circuit configured to access the bus, the threshold being calibrated for the circuit to account for manufacturing variations between circuits; as well as The threshold stored in the memory is compared with a first value representing the duration of a low state of a synchronization signal transmitted to the circuit on the bus, wherein the first value represents the longest duration of the low state of the synchronization signal during the transmission of data bytes on the bus; and If the first value exceeds the threshold, then communication on the bus is reset.

2. The method according to claim 1, further comprising: Read the threshold from the memory; as well as In the comparison, the first value represents the longest duration that has occurred during the time period required to read the threshold from the memory.

3. The method of claim 2, wherein the reading is performed synchronously with the transmission of the synchronization signal.

4. The method according to claim 1, wherein the memory is a non-volatile memory.

5. The method according to claim 1, wherein the bus is an I2C bus.

6. The method of claim 5, wherein the threshold represents a duration in the range of 25 ms to 35 ms.

7. The method according to claim 5, further comprising: The threshold is read from the memory during the transmission of data bytes on the bus.

8. The method according to claim 7, further comprising: The comparison is performed before the confirmation of the data byte is transmitted on the bus.

9. The method according to claim 8, further comprising: The comparison is performed between the transmission of the last bit of the data byte and the confirmed transmission.

10. The method of claim 1, wherein the data byte is a start byte for initiating a transmission on the bus.

11. A device configured to connect to a bus and configured to implement the method of claim 1.

12. The device of claim 11, comprising an oscillator and a counter, the counter being configured to count the number of cycles of the oscillator during each low state of the synchronization signal, the first value being determined based on the number of cycles counted during each low state.

13. The device of claim 12, wherein after each low state of the synchronization signal prior to the comparison, if the number of cycles is greater than the first value, the first value is updated with the number of cycles counted during the low state.

14. The device of claim 12, wherein the memory, the oscillator, and the counter further implement an presence detection function.

15. The device of claim 12, wherein the memory is an EEPROM type memory, and the oscillator and the counter belong to circuitry for writing to the memory.

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