A polarization code decoding device for space

Abstract

The present invention discloses a polar code decoding device for space use, comprising: a data receiving and distribution module and M parallel decoding modules. The decoding modules operate in parallel to improve throughput, and each independent decoding module is composed of a decoding process control module, a judgment and sorting module, an LLR update module, and a coding update module. The present invention saves logic and storage resources by reusing the LLR calculation module in the LLR update module and reusing the storage space for LLR intermediate values ​​and coding intermediate values. It uses a parallel bubble algorithm and a binary insertion algorithm for frozen bits and information bits, respectively, to save sorting time. It uses a pipeline operation and judgment selection calculation method to shorten LLR processing delay. It uses a method of recording index values ​​and a reverse CRC algorithm, eliminating the need for path replication. It adopts a "triple modular redundancy + dynamic refresh" design to adapt to space environments. It has the characteristics of low resource usage, low processing delay, high operating frequency, and strong tolerance to space environments.

Description

Technical Field

[0001] The present invention belongs to the technical field of communication electronic equipment, and in particular relates to a polarization code decoding device for space. Background Art

[0002] With the rapid development of wireless communications today, the need to transmit as much useful information as possible within a given bandwidth has been a pressing challenge. Ever since Shannon proposed the concept of channel capacity and the definition of a good code, researchers have been searching for a coding method that can achieve this capacity. In 2007, Arikan proposed the concept of polar codes. Polar codes exploit the phenomenon of channel polarization. When the number of combined channels approaches infinity, some channels become very good, suitable for transmitting useful information, while others become very bad, suitable for transmitting fixed information known to both the sender and the receiver. This code is the only error-correcting code theoretically proven to achieve the Shannon limit in binary discrete memoryless channels. Along with polar codes, Arikan proposed the serial cancellation (SC) decoding algorithm. While this algorithm is relatively simple, its performance is poor under short and medium code conditions. Subsequently, researchers proposed a list-based SCL algorithm assisted by a CRC to improve polar code decoding performance. This algorithm retains L candidate paths with the highest likelihood ratios during the calculation process and selects the optimal path from these L paths through a CRC check. This algorithm requires multiple path likelihood ratio sorting and path replication. The more paths there are, the higher the space complexity, the more storage, computing, and logic resources are used, and the greater the delay.

[0003] The ultra-long distances of space wireless communications require transmitting as much information as possible with minimal transmit power. The high coding gain of polar codes can significantly reduce transmit power, making them promising for broad application in satellite and space communications. However, spacecraft resources are limited, requiring a comprehensive consideration of computational, storage, and logic resource consumption, as well as time delay, to achieve polar code decoding with minimal resource costs. Furthermore, the complex electromagnetic environment and radiation conditions in space place higher demands on the decoding architecture. Summary of the Invention

[0004] To solve the above problems, the present invention aims to provide a polar code decoding device for space use, which can achieve low-latency polar code decoding under low resource consumption conditions to adapt to the space environment.

[0005] To achieve the above objectives, the technical solution of the present invention is: a spatial polar code decoding device, the decoding device using a CRC-SCL decoding algorithm to implement decoding of a polar code with a code length of 2^n or a shortened code generated by puncturing the polar code, comprising: a data receiving and distribution module and M decoding modules, the data receiving and distribution module being configured to receive a demodulated output signal, calculate an LLR value, and record a matching relationship between the decoding module and the LLR data, the decoding module using the data for decoding, where M is an integer greater than or equal to 1; the data receiving and distribution module comprising an LLR initialization module, n primary LLR buffers, and an address and data selection unit connected in sequence; the LLR initialization unit being configured to receive the demodulated output data and calculate an initial LLR value, and the primary LLR buffer being configured to buffer the data frame by frame. The initial LLR value is recorded in the address and data selection unit, and the address and data selection unit is used to record and track the corresponding relationship between the decoding module and the primary LLR buffer, and select the corresponding primary LLR buffer output when the decoding module reads it; the decoding module includes a decoding process control module, a judgment and sorting module, an LLR update module and a coding update module, the decoding process control module is connected to the judgment and sorting module, the LLR update module and the coding update module, the LLR update module is connected to the coding update module, and the coding update module is connected to the judgment and sorting module; the decoding process control module recursively calls the LLR update module to implement serial elimination decoding, the judgment and sorting module judges and sorts the decoded values, and after all decoding is completed, selects the path with the smallest CRC correctness or error likelihood ratio for output.

[0006] In one embodiment of the present invention, the number n of the primary LLR buffers and the number M of the decoding modules are related as follows: n=M+1.

[0007] In one embodiment of the present invention, the decoding device is implemented by programming decoding logic inside an FPGA, and the FPGA includes a block RAM.

[0008] In one embodiment of the present invention, the decoding process control module includes n-1 recursively called and mutually independent sub-control modules, each of which corresponds to polar code decoding with a code length of 2^i, where i = n...2. Sub-control modules with the same code length are multiplexed.

[0009] In one embodiment of the present invention, the LLR update module includes an LLR address control module, a universal LLR storage module, and an LLR calculation module. The LLR address control module is electrically connected to the n-1 recursively called and mutually independent sub-control modules and the universal LLR storage module, respectively. The LLR calculation module is electrically connected to the universal LLR storage module, the address and data selection module, the coding update module, and the judgment and sorting module.

[0010] In one embodiment of the present invention, the judgment and sorting module includes a leaf node calculation module, a sorting module and a path storage and reverse CRC check module, and the leaf node calculation module is electrically connected to the decoding process control module, the sorting module and the path storage and reverse CRC check module.

[0011] In one embodiment of the present invention, the coding update module includes a coding intermediate value update control module and a coding intermediate value cache electrically connected to each other, and the coding intermediate value update control module is electrically connected to the decoding process control module and the leaf node calculation module.

[0012] In one embodiment of the present invention, in the LLR updating module, LLR intermediate values ​​are uniformly stored in a common LLR storage module, and LLR intermediate value storage spaces at the same level are reused.

[0013] In one embodiment of the present invention, in the coding update module, coding intermediate values ​​are calculated hierarchically to save coding calculation time, and coding intermediate values ​​are uniformly stored in a coding intermediate value cache to save storage resources.

[0014] In one embodiment of the present invention, in the judgment and sorting module, a parallel bubble algorithm and a binary insertion algorithm are used for sorting frozen bits and information bits respectively to shorten the sorting time; a pipeline operation and judgment selection calculation method are used to shorten the processing delay; and a method of recording index values ​​and a reverse CRC algorithm are used to save path copying time.

[0015] Due to the adoption of the above technical solution, the present invention has the following advantages and positive effects compared with the prior art:

[0016] 1. The decoding device of the present invention uses a CRC-SCL decoding algorithm to decode polar codes with a code length of 2^n or shortened codes generated by puncturing the polar codes. This decoding device is implemented by an FPGA containing a built-in block RAM and decoding logic running within the FPGA, resulting in a simple and reliable implementation.

[0017] 2. The decoding device of the present invention saves logic and storage resources by reusing the LLR calculation module and the storage space for LLR intermediate values ​​and coding intermediate values. This achieves low-latency polar code decoding with low resource consumption to adapt to the spatial environment.

[0018] 3. The present invention uses a parallel bubbling algorithm and a binary insertion algorithm to sort frozen bits and information bits, respectively. It employs a pipeline operation and judgment-selective calculation method to shorten sorting time and processing delay. It also uses a record index value and a reverse CRC check algorithm to save path duplication time. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The specific embodiments of the present invention are further described in detail below with reference to the accompanying drawings, wherein:

[0020] Figure 1 This is a structural diagram of the polar code decoding device for space use according to the present invention;

[0021] Figure 2 This is a structural diagram of the polar code decoding device for space use according to the present invention;

[0022] Figure 3 This is a decoding control flow chart of the present invention;

[0023] Figure 4 This is a block diagram of the reverse CRC implementation of the present invention. DETAILED DESCRIPTION

[0024] The present invention will be further described below in conjunction with the accompanying drawings and specific embodiments. The advantages and features of the present invention will become more apparent from the following description and claims. It should be noted that the drawings are greatly simplified and not to exact ratios, and are intended solely to facilitate and clearly illustrate the embodiments of the present invention.

[0025] It should be noted that all directional indications in the embodiments of the present invention (such as up, down, left, right, front, back, etc.) are only used to explain the relative position relationship, movement status, etc. between the various components under a certain specific posture (as shown in the accompanying drawings). If the specific posture changes, the directional indication will also change accordingly.

[0026] At the same time, expressions such as “first” and “second” are only used to distinguish multiple configurations, rather than to limit the order between configurations or other features.

[0027] In addition, the expression “including” an element is an “open” expression, which simply means that corresponding components exist and should not be interpreted as excluding additional components.

[0028] See Figure 1 The spatial polar code decoding device of the present invention consists of a data receiving and distribution module and M decoding modules. These M decoding modules are identical and operate in parallel and pipelined to improve decoding throughput. The number of decoding modules is determined by the average bit rate of the input data and the system operating clock and can be increased or decreased based on actual circumstances. The decoding device uses a CRC-SCL (Cyclic Redundancy Check-Successive Cancellation List) decoding algorithm to decode polar codes with a code length of 2^n.

[0029] Preferably, anti-single particle protection measures are taken to adapt to the complex space environment.

[0030] For more details, see Figure 2 The data receiving and distribution module consists of an LLR (Log-Likelihood-Ratio) initialization module, a primary LLR buffer, and an address and data selection module. The LLR initialization module receives the demodulated output signal, performs uniform integer quantization on the signal, generates an 8-bit LLR initial value, and then writes it into the primary LLR buffer. After each frame is received, a new buffer is replaced and written to the subsequent decoding module for decoding. The primary LLR buffer has one more LLR buffer than the decoding module, that is, M+1, and is used to temporarily store corresponding LLR data while the decoding module is operating. The address and data selection module is responsible for recording and tracking the correspondence between the decoding module and the primary LLR buffer. When the decoding module reads the LLR value at the puncture point, it outputs the default LLR value, that is, the maximum value.

[0031] Furthermore, each independent decoding module is composed of a decoding process control module, a decision and sorting module, an LLR update module and a coding update module.

[0032] The decoding process control module is used to control the process of the decoding process. Preferably, the decoding process control module is composed of n-1 independent sub-control modules, which are recursively called. Each sub-control module corresponds to polar code decoding with a code length of 2^i (i=n...2), and sub-control modules with the same code length are fully reused.

[0033] The judgment and sorting module consists of a leaf node calculation module, a sorting module, and a path storage and reverse CRC check module. When the decoding reaches a leaf node, the decoded value is judged, the path is expanded, and the error likelihood ratio of the selected path is calculated. The frozen bits and information bits are sorted using a parallel bubble algorithm and a binary insertion algorithm respectively to save sorting time and computational complexity. After sorting, the top M paths with the lowest error likelihood ratio are retained, and the path index value is recorded without copying the path. When the decoding reaches the final bit, the path index value is used to perform a reverse CRC check, and the path with the correct CRC or the lowest error likelihood ratio is selected for output. To adapt to the spatial environment, the frozen bit storage module is designed with a dynamic refresh function that can self-correct and recover single-bit errors.

[0034] The LLR update module consists of an LLR address control module, a general LLR storage module, and an LLR calculation module. The LLR update module is reused by decoding sub-control modules of all code lengths and uses a block RAM with a depth of 2^(n+1) to store all LLR intermediate values. LLR intermediate values ​​of the same code length use the same storage space to conserve resources. Pipelining and decision-making are used to complete LLR update operations for left and right nodes using different algorithms, thus conserving logic resources.

[0035] The encoding update module is reused by the decoding sub-control modules of all code lengths. It uses a cache with a depth of 2^n to store the intermediate encoding values. It uses the path index value input by the lower-level decoding to calculate and update the encoding value of each path. The encoding values ​​of the same bit in each layer are stored in the same location to save storage resources.

[0036] The specific process is as follows Figure 3 As shown, each sub-control module calls the LLR calculation module, the lower-level decoding module, and the code update module according to the process to implement the recursive decoding call process from code length 2^n to 2. For each call, the decoding process control module provides the called module with control information such as the read and write start address, step, path index, and left and right indicators. After the decoding of the current layer is completed, it provides path index information for the decoding of the upper layer.

[0037] For example, the lower-layer decoding module called by the decoding control module with a code length of 2 is the decision and sorting module. Its function is to expand the existing L error likelihood ratios to 2L according to the following formula based on the input L LLRs, then select the smallest L among them and retain them, and update the residual path sequence. The formula is:

[0038]

[0039]

[0040] According to the formula, the sorting can be simplified into two cases:

[0041] 1. For the frozen bit, since the preset value is known and the path is unique, only L pas (from L+1 to 2L) need to be sorted. This is achieved using an improved bubble sort method. The implementation method is as follows:

[0042] A):pa n+L and pa n+1+L , n=1,3,5...pairwise comparison, pa n+L >pa n+1+L They exchange with each other;

[0043] B):pa n+L and pa n+1+L , n=2,4,6...pairwise comparison, pan+L >pa n+1+L They exchange with each other;

[0044] C): Repeat A) and B) until the number of times is equal to L, and the sorting is completed.

[0045] Using this parallel comparison algorithm, sorting requires a total of L clock cycles, which is better than the conventional bubble sort method's L(L-1) / 2 clock cycles.

[0046] 2. Information bit, due to pa n n=1,2,3...L has been sorted, only pa n , n=L+1,L+2,...2L-1, a total of L-1 numbers are inserted into pa in order of size n-L In the subsequent sequence, until the insertion point number is greater than L, the first L numbers are the required sequence. The insertion algorithm uses the binary insertion method, and the maximum number of comparisons is This is better than the 2L(2L-1) / 2 comparisons of the conventional bubble sort method.

[0047] In the above sorting process, record each pa n The original sequence number of the pa, which indicates which residual path the pa is extended from, and the first L pa after the sequence number n The serial number is recorded as the path index and uploaded to the upper module, without the need to copy the first n-1 bits of the path, thus saving path copying time.

[0048] After all bits are judged, the stored path index is used to perform reverse CRC check on the remaining paths, and the paths are rearranged at the same time. After the check is completed, the path that succeeds the check is selected for output. If there is no successful path, the first path is selected for output. Figure 4 shown.

[0049] The sorting operation and reverse CRC calculation require frozen word location information, which is stored in a dual-port RAM with a bit width of 3 and a depth of 2^n. To adapt to single-particle environments, this RAM utilizes a "triple-module redundancy + dynamic refresh" design. One port is used for reading, outputting two out of three, while the other port reads data in the background and writes it back to the original address after a two-out-of-three determination.

[0050] The LLR update module is responsible for calculating the LLR values ​​required for lower-level decoding. By leveraging the recursive nature of calls between decoding modules at each layer, all LLR calculations reuse the same module. Intermediate LLR values ​​need to be retained until all calculations at this layer are completed, but can be discarded afterward. LLR intermediate values ​​with the same code length can reuse the same storage space. All LLR intermediate values ​​are stored in the same block RAM with a depth of 2^(n+1), further improving RAM utilization and saving address generation logic. The address allocation for this RAM is shown in Table 1 (code length 1024 bits).

[0051] Table 1:

[0052] Address Space Content(list*width) depth 0～511 512-code length LLR median value 512 512～767 256-code length LLR median value 256 768～895 128-code length LLR median value 128 895～959 64-code LLR median value 64 960～991 32-code LLR median value 32 992～1007 16-code length LLR median value 16 1008～1015 8-code LLR median value 8 1016～1019 4-code LLR median value 4 1020～1021 2-code length LLR median value 2

[0053] list: Maximum number of residual paths

[0054] width: single LLR value width

[0055] LLR calculation uses the minimum sum algorithm, and the calculation formula is:

[0056]

[0057] where f i (a) is the LLR calculation formula for the i-th path in the lower left corner;

[0058] gi(a) is the LLR calculation formula for the i-th path in the lower right corner;

[0059] n is the current code length;

[0060] is the decision value of the i-th path fed back by the lower left layer;

[0061] index(i) is the index value of the i-th path fed back by the lower left layer.

[0062] When calculating f(x), the lower left LLR of each surviving path is updated. When calculating g(x), the path index value uploaded by the lower module is selected. The LLR value of the corresponding path is calculated and updated.

[0063] In order to increase the operating frequency, the operation is further simplified step by step. The operation steps are as follows:

[0064] 1) Simultaneously calculate -L i (a), -L i (a+n / 2), L i (a)+L i (a+n / 2), L i (a+n / 2)-L i (a);

[0065] 2) Select f(x) and g(x) according to Table 2 and output the results;

[0066] 3) Select one of f(x) and g(x) to output according to the left and right instructions;

[0067] 4) Bit truncation and overflow operations.

[0068] By utilizing the dual-port operation characteristics of the block RAM and combining it with the pipeline operation of the above algorithm, an LLR update of n / 2 code length can be completed within n+6 clocks.

[0069] Table 2:

[0070]

[0071] MSB(x) is the most significant bit of x.

[0072] The coding update module uses the coding intermediate value of the lower layer and the path index to calculate the coding intermediate value of the current layer. The calculation formula is:

[0073] Among them, c i (l) is the lth bit of the i-th path; index(i) is the index value of the i-th path fed back by the lower right layer.

[0074] Taking advantage of the fact that the calculation of each layer is only related to the intermediate value of the lower layer code, and the intermediate value of the lower layer code is no longer used after the calculation is completed, a RAM with a depth of 2^n is used to store the intermediate value of the code. After the lower layer code value is read, the encoding result is written back to the original address, which not only avoids the repeated encoding calculation starting from the bottom layer in the traditional algorithm, but also saves storage space.

[0075] Using this solution, a polar code decoding device with a code length of 1024 was implemented on a Xilinx FPGA XC7K325. The number of decoding modules was 3 and the maximum number of residual sequences was 4. The resources used are shown in Table 3.

[0076] Table 3:

[0077]

[0078] While the embodiments of the present invention have been described in detail above with reference to the accompanying drawings, the present invention is not limited to the above embodiments. Those skilled in the art may make various modifications and variations to the receiving device of the present invention without departing from the spirit and scope of the present invention. Even if various modifications are made to the present invention, as long as such modifications fall within the scope of the claims of the present invention and their equivalents, they will still fall within the scope of protection of the present invention.

Claims

1. A spatial polar code decoding device, wherein the device uses a CRC-SCL decoding algorithm to decode a polar code with a code length of 2^n or a shortened code generated by puncturing the polar code, and wherein: include: a data receiving and distribution module and M decoding modules, wherein the data receiving and distribution module is used to receive the demodulated output signal, calculate the LLR value and record the matching relationship between the decoding module and the LLR data, and the decoding module uses the data for decoding, where M is an integer greater than or equal to 1; The data receiving and distributing module includes an LLR initialization module, n primary LLR buffers, and an address and data selection unit connected in sequence; the LLR initialization module is used to receive the demodulated output data and calculate the initial LLR value, the primary LLR buffer unit is used to buffer the initial LLR value frame by frame, and the address and data selection unit is used to record and track the corresponding relationship between the decoding module and the primary LLR buffer, and select the corresponding primary LLR buffer output when the decoding module reads; The decoding module includes a decoding process control module, a judgment and sorting module, an LLR update module, and a coding update module. The decoding process control module is connected to the judgment and sorting module, the LLR update module, and the coding update module. The LLR update module is connected to the coding update module, and the coding update module is connected to the judgment and sorting module. The decoding process control module recursively calls the LLR update module to implement serial elimination decoding. The judgment and sorting module judges and sorts the decoded values. After all decoding is completed, the path with the smallest CRC correctness or error likelihood ratio is selected for output. The decoding process control module includes n-1 recursively called and mutually independent sub-control modules, each sub-control module corresponding to polar code decoding of 2^i code length, where i=n...2, and sub-control modules with the same code length are multiplexed; The LLR update module includes an LLR address control module, a universal LLR storage module, and an LLR calculation module. The LLR address control module is electrically connected to n recursively called and mutually independent sub-control modules and the universal LLR storage module, respectively. The LLR calculation module is electrically connected to the universal LLR storage module, the address and data selection module, the coding update module, and the judgment and sorting module.

2. The spatial polar code decoding device according to claim 1, wherein: The number n of the primary LLR buffers is related to the number M of the decoding modules: n=M+1.

3. The spatial polar code decoding device according to claim 1, wherein: The decoding device is implemented by programming decoding logic inside FPGA, and the FPGA contains Block RAM.

4. The spatial polar code decoding device according to claim 1, wherein: The judgment and sorting module includes a leaf node calculation module, a sorting module and a path storage and reverse CRC check module. The leaf node calculation module is electrically connected to the decoding process control module, the sorting module and the path storage and reverse CRC check module.

5. The spatial polar code decoding device according to claim 4, wherein: The coding update module includes a coding intermediate value update control module and a coding intermediate value cache electrically connected to each other. The coding intermediate value update control module is electrically connected to the decoding process control module and the leaf node calculation module.

6. The spatial polar code decoding device according to claim 5, wherein: In the LLR updating module, LLR intermediate values ​​are uniformly stored in the general LLR storage module, and LLR intermediate value storage spaces at the same level are reused.

7. The spatial polar code decoding device according to claim 6, wherein: In the coding update module, coding intermediate values ​​are calculated hierarchically to save coding calculation time, and coding intermediate values ​​are uniformly stored in a coding intermediate value cache to save storage resources.

8. The spatial polar code decoding device according to claim 6, wherein: In the judgment and sorting module, a parallel bubble algorithm and a binary insertion algorithm are used to sort frozen bits and information bits respectively to shorten the sorting time; a pipeline operation and judgment selection calculation method are used to shorten the processing delay; and a method of recording index values ​​and a reverse CRC algorithm are used to save path copying time.

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