Array substrate and display device

Abstract

An array substrate and a display device, wherein the array substrate includes: a substrate (01), a plurality of sub-pixels (02), a plurality of data lines (03), a plurality of first power supply lines (04), and a plurality of data line leads (05). The array substrate further includes: a plurality of selection switches (06), which are located in the peripheral region (BB) and arranged at intervals, and the plurality of selection switches (06) are located on the side of the plurality of data line leads (05) away from the display region (AA); a plurality of data signal input lines (07), which are located in the peripheral region (BB) and on the side of the plurality of selection switches (06) away from the display region (AA), and at least one of each of the plurality of selection switches (06) is connected to one of the plurality of data signal input lines (07); a first power supply bus (08), which is located in the peripheral region (BB) and on the side of the plurality of selection switches (06) away from the display region (AA); a plurality of connection parts (09), which are connected to the first power supply bus (08) and the plurality of first power supply lines (04), and the plurality of connection parts (09) extend towards the display region (AA) along the region between the plurality of selection switches (06). Effective transmission of power signals can be achieved.

Description

Technical Field

[0001] The present disclosure relates to the field of displays, and particularly to an array substrate and a display device. Background Art

[0002] In recent years, with the progress of intelligent display technology, Organic Light Emitting Diode (OLED) has become one of the hotspots in the current display research field. More and more Active Matrix Organic Light Emitting Diode (AMOLED) display panels have entered the market. Compared with traditional Thin Film Transistor Liquid Crystal Display (TFT-LCD) panels, AMOLED displays have faster response speeds and higher contrast ratios. Summary of the Invention

[0003] The present disclosure provides an array substrate and a display device.

[0004] In a first aspect, the present disclosure provides an array substrate, comprising:

[0005] a substrate, the substrate comprising a display area and a peripheral area at least on one side of the display area;

[0006] a plurality of sub-pixels, located in the display area;

[0007] a plurality of data lines, located in the display area, configured to provide data signals to the plurality of sub-pixels;

[0008] a plurality of first power supply lines, located in the display area, configured to provide power supply signals to the plurality of sub-pixels;

[0009] a plurality of data line leads, located in the peripheral area and electrically connected to the plurality of data lines;

[0010] a plurality of selection switches, located in the peripheral area and arranged at intervals, the plurality of selection switches being on a side of the plurality of data line leads away from the display area, and at least each of some of the plurality of selection switches connecting at least two of the plurality of data line leads;

[0011] a plurality of data signal input lines, located in the peripheral area and on a side of the plurality of selection switches away from the display area, and at least each of some of the plurality of selection switches connecting one of the plurality of data signal input lines;

[0012] A first power supply bus, located in the peripheral area and on a side of the plurality of selection switches away from the display area;

[0013] A plurality of connection parts, electrically connected to the first power supply bus and the plurality of first power lines, and the plurality of connection parts extend towards the display area along an area between the plurality of selection switches.

[0014] Optionally, further comprising a second power supply bus located between the plurality of selection switches and the display area;

[0015] Wherein, the plurality of connection parts are respectively connected to the first power supply bus and the second power supply bus.

[0016] Optionally, the first power supply bus and the second power supply bus are on the same layer.

[0017] Optionally, the first power supply bus, the second power supply bus and the plurality of connection parts are on the same layer.

[0018] Optionally, the first power supply bus, the second power supply bus and the plurality of connection parts define a plurality of first openings arranged in an array, and a positive projection of the plurality of selection switches on the substrate is located in the plurality of first openings.

[0019] Optionally, further comprising a third power supply bus,

[0020] A positive projection of the third power supply bus on the substrate and a positive projection of the first power supply bus on the substrate at least partially overlap, and the third power supply bus is connected to the first power supply bus.

[0021] Optionally, further comprising a fourth power supply bus,

[0022] A positive projection of the fourth power supply bus on the substrate and a positive projection of the second power supply bus on the substrate at least partially overlap, and the fourth power supply bus is connected to the second power supply bus.

[0023] Optionally, the third power supply bus and the fourth power supply bus are on the same layer.

[0024] Optionally, at least one of the plurality of sub-pixels includes a driving thin film transistor and a connecting electrode;

[0025] The driving thin film transistor includes a driving active layer located on the substrate, a driving gate located on a side of the driving active layer away from the substrate, a driving source electrode and a driving drain electrode located on a side of the driving gate away from the substrate; the connecting electrode is located on a side of the driving source electrode and the driving drain electrode away from the substrate;

[0026] The first power supply bus, the second power supply bus, and the connection electrode are located on the same layer.

[0027] Optionally, at least one of the plurality of sub-pixels includes a driving thin film transistor and a connection electrode;

[0028] The driving thin film transistor includes a driving active layer located on the substrate, a driving gate located on a side of the driving active layer away from the substrate, a driving source electrode and a driving drain electrode located on a side of the driving gate away from the substrate; the connection electrode is located on a side of the driving source electrode and the driving drain electrode away from the substrate;

[0029] The third power supply bus, the fourth power supply bus, and the driving source electrode are located on the same layer, or the third power supply bus, the fourth power supply bus, and the driving drain electrode are located on the same layer.

[0030] Optionally, the selection switch includes:

[0031] A first active layer located on the substrate;

[0032] A first gate and a second gate located on a side of the first active layer away from the substrate, the first gate and the second gate are located on the same layer and do not overlap;

[0033] A first source electrode, a first drain electrode, and a second drain electrode located on a side of the first gate and the second gate away from the substrate, the first source electrode, the first drain electrode, and the second drain electrode are located on the same layer and do not overlap, and the first source electrode is located between the first drain electrode and the second drain electrode;

[0034] The first source electrode is connected to one of the plurality of data signal input lines, and the first drain electrode and the second drain electrode are connected to one of the plurality of data line leads.

[0035] Optionally, the positive projection of each of the first gate and the second gate on the substrate does not overlap with the positive projection of the first source electrode, the first drain electrode, and the second drain electrode on the substrate.

[0036] Optionally, a first control line and a second control line are further included;

[0037] The first control line is connected to the first gate, and the second control line is connected to the second gate;

[0038] The positive projection of the first control line and the second control line on the substrate overlaps with the positive projection of the plurality of first openings on the substrate.

[0039] Optionally, at least one of the plurality of connection portions includes a second opening, and the orthographic projection of the second opening on the substrate substrate overlaps with the orthographic projections of the first control line and the second control line on the substrate substrate.

[0040] Optionally, the plurality of data line leads and the first gate or the second gate are located on the same layer.

[0041] Optionally, the plurality of data signal input lines include a first data signal input line and a second data signal input line, the first data signal input line and the second data signal input line are alternately arranged, and the first data signal input line and the second data signal input line are located on different layers.

[0042] Optionally, at least one of the plurality of sub-pixels includes a driving thin film transistor, a connection electrode, and a storage capacitor;

[0043] The driving thin film transistor includes a driving active layer located on the substrate substrate, a driving gate located on a side of the driving active layer away from the substrate substrate, a gate insulating layer (GI2) located on a side of the driving gate away from the substrate substrate, an interlayer dielectric layer located on a side of the gate insulating layer (GI2) away from the substrate substrate, and a driving source electrode and a driving drain electrode located on a side of the interlayer dielectric layer away from the substrate substrate; the connection electrode is located on a side of the driving source electrode and the driving drain electrode away from the substrate substrate;

[0044] The storage capacitor includes a first capacitor electrode and a second capacitor electrode, the first capacitor electrode and the driving gate are located on the same layer, and the second capacitor electrode is located between the gate insulating layer (GI2) and the interlayer dielectric layer;

[0045] The first data signal input line and the driving gate are located on the same layer, and the second data signal input line and the second capacitor electrode are located on the same layer.

[0046] Optionally, the first active layer and the driving active layer are located on the same layer, the first gate and the driving gate are located on the same layer, and the first source electrode and the driving source electrode are located on the same layer.

[0047] Optionally, at least one of the plurality of sub-pixels further includes: a light emitting diode located on a side of the connection electrode away from the substrate substrate, and the driving drain electrode, the connection electrode, and the light emitting diode are sequentially connected.

[0048] In a second aspect, a display device is provided, including any one of the above display substrates. Description of the Drawings

[0049] Figure 1Schematic diagram of a structure of an array substrate provided by an embodiment of the present disclosure;

[0050] Figure 2 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section XX;

[0051] Figure 3 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section YY;

[0052] Figure 4 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section ZZ;

[0053] Figure 5 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section UU;

[0054] Figure 6 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section VV;

[0055] Figure 7-1 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section WW;

[0056] Figure 7-2 An embodiment of the present disclosure provides a Figure 1 Schematic diagram of cross-section TT;

[0057] Figure 8 Schematic diagram of a structure of a display device provided by an embodiment of the present disclosure. Detailed implementation manners

[0058] To make the principles, technical solutions, and advantages of the present disclosure clearer, the following will further describe the embodiments of the present disclosure in detail with reference to the accompanying drawings.

[0059] The array substrate in the related art includes a display area and a peripheral area. Among them, a power bus for providing a power signal (usually represented by VDD in the art) for the display area, and a selection switch for providing a data signal for the display area, such as a multiplexer (MUX), are arranged in the peripheral area. However, the power bus and the selection switch overlap, generating parasitic capacitance and affecting the normal operation of the power bus and the selection switch.

[0060] The embodiment of the present disclosure provides an array substrate, in which the power bus and the MUX do not overlap, so parasitic capacitance will not be generated. Exemplarily, Figure 1 Schematic diagram of a structure of an array substrate provided by an embodiment of the present disclosure, as Figure 1As shown, the array substrate includes:

[0061] A substrate substrate 01, which includes a display area AA and a peripheral area BB at least on one side of the display area AA. Figure 1 Here, the peripheral area BB is located on four sides of the display area AA as an example.

[0062] Multiple sub-pixels 02, located in the display area AA;

[0063] Multiple data lines 03, located in the display area AA, and configured to provide data signals to the multiple sub-pixels 02;

[0064] Multiple first power supply lines 04, located in the display area AA, and configured to provide power supply signals to the multiple sub-pixels 02;

[0065] Multiple data line leads 05, located in the peripheral area BB and connected to the multiple data lines 03;

[0066] Multiple selection switches 06, located in the peripheral area BB and arranged at intervals. The multiple selection switches 06 are located on the side of the multiple data line leads 05 away from the display area AA. Each of at least some of the multiple selection switches 06 is connected to at least two of the multiple data line leads 05. Figure 1 Here, each selection switch 06 is connected to two data line leads 05 as an example.

[0067] Multiple data signal input lines 07, located in the peripheral area BB and on the side of the multiple selection switches 06 away from the display area AA. Each of at least some of the multiple selection switches 06 is connected to one of the multiple data signal input lines 07. Figure 1 Here, each selection switch 06 is connected to one data signal input line 07 as an example.

[0068] A first power supply bus 08, located in the peripheral area BB and on the side of the multiple selection switches 06 away from the display area AA;

[0069] Multiple connection parts 09, connected to the first power supply bus 08 and the multiple first power supply lines 04, and the multiple connection parts 09 extend towards the display area AA along the area between the multiple selection switches 06.

[0070] In summary, in the array substrate provided by the embodiments of the present disclosure, the first power supply bus located in the peripheral area does not overlap with the selection switch. Therefore, the overlapping degree of the first power supply bus and the selection switch is reduced, and further the parasitic capacitance formed by the first power supply bus and the selection switch is reduced, so that both the first power supply bus and the selection switch can work normally.

[0071] It should be noted that, in the embodiments of the present disclosure, the first power bus 08 can be connected to the sub-pixels 02 in the display area AA through the above-mentioned plurality of connection portions 09 and a plurality of first power lines 04 to achieve the purpose of supplying power to the sub-pixels 02.

[0072] Optionally, please continue to refer to Figure 1 , the array substrate further includes a second power bus 010 located between the plurality of selection switches 06 and the display area AA. The plurality of connection portions 09 are respectively connected to the first power bus 08 and the second power bus 010, that is, each connection portion 09 is connected to the first power bus 08 and the second power bus 010. As can be seen from Figure 1 , the second power bus 010 does not overlap with the selection switch 06 either. Therefore, there is no parasitic capacitance between the second power bus 010 and the selection switch 06, and the second power bus 010 can also work properly.

[0073] Exemplarily, the first power bus 08 and the second power bus 010 are located on the same layer. It should be noted that the meaning of two structures being on the same layer is that the materials of these two structures are the same, and these two structures can be obtained by the same lithography process. When the first power bus 08 and the second power bus 010 are located on the same layer, the first power bus 08 and the second power bus 010 can be obtained simultaneously by one lithography process, so that the process complexity of manufacturing the array substrate can be reduced. Further, the first power bus 08, the second power bus 010 and the plurality of connection portions 09 are located on the same layer. At this time, the first power bus 08, the second power bus 010 and the plurality of connection portions 09 can be manufactured by the same lithography process, which can further reduce the process complexity of manufacturing the array substrate. Of course, the first power bus and the second power bus may not be located on the same layer, and the embodiments of the present disclosure do not limit this.

[0074] Please continue to refer to Figure 1 , the first power bus 08, the second power bus 010 and the plurality of connection portions 09 define a plurality of first openings 011 arranged in an array, and the orthographic projections of the plurality of selection switches 06 on the substrate 01 are located in the plurality of first openings 011. Exemplarily, the plurality of selection switches 06 correspond to the plurality of first openings 011 one by one, and the orthographic projection of each selection switch 06 on the substrate 01 can be located within the corresponding first opening 011. It can be seen that the first power bus 08, the second power bus 010 and the connection portion 09 configured to transmit power signals do not overlap with the selection switch 06, which can reduce parasitic capacitance. In this way, the power signal can be effectively transmitted to the sub-pixels 02 in the display area AA.

[0075] Optionally, Figure 2 This is a kind provided by the embodiments of the present disclosure Figure 1Schematic diagram of the middle cross-section XX. Please refer to Figure 1 and Figure 2 . The array substrate further includes a third power bus 012. The orthographic projection of the third power bus 012 on the substrate 01 and the orthographic projection of the first power bus 08 on the substrate 01 at least partially overlap, and the third power bus 012 is connected to the first power bus 08. Exemplarily, there are some insulating layers between the first power bus 08 and the third power bus 012, and the first power bus 08 and the third power bus 012 can be connected through vias VH1 in these insulating layers.

[0076] It should be noted that in the related art, the power bus configured to transmit power signals is usually a single-layer structure, and this single-layer structure will cause a relatively high resistance during the transmission of power signals, resulting in a relatively large voltage drop during the transmission of power signals. In the embodiment of the present disclosure, the first power bus 08 can also be connected to the third power bus 012, so that the structure configured to transmit power signals is a double-layer structure, reducing the resistance and voltage drop during the transmission of power signals.

[0077] Optionally, Figure 3 is a schematic diagram of the middle cross-section YY provided by the embodiment of the present disclosure. Please refer to Figure 1 and Figure 1 and Figure 3 . The array substrate further includes a fourth power bus 013. The orthographic projection of the fourth power bus 013 on the substrate 01 and the orthographic projection of the second power bus 010 on the substrate 01 at least partially overlap, and the fourth power bus 013 is connected to the second power bus 010. Exemplarily, there are some insulating layers between the second power bus 010 and the fourth power bus 013, and the second power bus 010 and the fourth power bus 013 can be connected through vias VH2 in these insulating layers.

[0078] When the array substrate further includes a fourth power bus 013, the second power bus 010 can also be connected to the fourth power bus 013, so that the structure configured to transmit power signals is a double-layer structure, reducing the resistance and voltage drop during the transmission of power signals.

[0079] Exemplarily, Figure 2 the third power bus 012 in Figure 3The fourth power supply bus 013 in [description] can be located on the same layer. In this way, when fabricating the array substrate, the third power supply bus 012 and the fourth power supply bus 013 can be fabricated simultaneously, thereby reducing the process complexity of fabricating the array substrate. Of course, the third power supply bus 012 and the fourth power supply bus 013 may not be located on the same layer, and the embodiments of the present disclosure do not limit this. Optionally, in the embodiments of the present invention, the connection part 09 is taken as a single-layer structure as an example. Of course, the connection part 09 can also be made into a double-layer structure. For example, it further includes a connection sub-part 09' (not shown and marked in the accompanying drawings of the specification). The connection sub-part 09' is located on the same layer as the third power supply bus 012 and is connected to the third power supply bus 012 and the fourth power supply bus 013. Optionally, the connection part 09 and the connection sub-part 09' can also be connected through vias.

[0080] Figure 4 A kind provided by the embodiments of the present disclosure Figure 1 Schematic diagram of the cross-section ZZ in [description], please refer to Figure 1 and Figure 4 Among them, at least one of the multiple sub-pixels 02 in the display area AA includes a driving thin film transistor 021 and a connection electrode 022. Among them, the driving thin film transistor 021 includes a driving active layer 0211 located on the substrate 01, a driving gate 0212 located on the side of the driving active layer 0211 away from the substrate 01, a driving source electrode 0213 and a driving drain electrode 0214 located on the side of the driving gate 0212 away from the substrate 01. The above-mentioned connection electrode 022 is located on the side of the driving source electrode 0213 and the driving drain electrode 0214 away from the substrate 01. Figure 4 The sub-pixel in [description] may further include a light-emitting diode 023 (including a first electrode 0231, a light-emitting layer 0232, and a second electrode 0233 arranged in sequence along the direction away from the substrate 01). The light-emitting diode 023 is located on the side of the connection electrode 022 away from the substrate 01, and the driving drain electrode 0214, the connection electrode 022, and the light-emitting diode 023 are connected in sequence.

[0081] Furthermore, Figure 4The sub-pixel 02 in can further include: a buffer layer 024, a first gate insulating layer 025, a second gate insulating layer 026, an interlayer dielectric layer 027, a passivation layer 028, a first planarization layer 029, a second planarization layer 030, a pixel defining layer 031, a support layer 032, and a packaging layer 033, which are arranged in sequence along a direction away from the substrate 01. The above-mentioned driving active layer 0211 is located between the buffer layer 024 and the first gate insulating layer 025; the driving gate 0212 is located between the first gate insulating layer 025 and the second gate insulating layer 026; the driving source electrode 0213 and the driving drain electrode 0214 are located between the interlayer dielectric layer 027 and the passivation layer 028; the connection electrode 022 is located between the first planarization layer 029 and the second planarization layer 030. The pixel defining layer 031 is configured to define a pixel region on the substrate 01, and the above-mentioned light-emitting diode 023 is located within this pixel region.

[0082] It should be noted that the buffer layer 024, the first gate insulating layer 025, the second gate insulating layer 026, the interlayer dielectric layer 027, the passivation layer 028, the first planarization layer 029, and the second planarization layer 030 in the display area AA can all extend to the peripheral area BB, and the relative positional relationship of these film layers in the peripheral area BB is the same as that in the display area AA, which will not be elaborated in this embodiment of the present disclosure.

[0083] In addition, Figure 4 The sub-pixel 02 in can further include: a storage capacitor 034, which includes a first capacitor electrode 0341 and a second capacitor electrode 0342. The first capacitor electrode 0341 is on the same layer as the driving gate 0212, and the second capacitor electrode 0342 is located between the second gate insulating layer 026 and the interlayer dielectric layer 027.

[0084] Optionally, some structures in the display area AA of the array substrate can be on the same layer as some structures in the peripheral area BB, and the following will explain these structures.

[0085] Exemplarily, the above-mentioned first power supply bus 08 and the second power supply bus 010 can be on the same layer as the connection electrode 022. In this way, when preparing the connection electrode 022 in the display area AA, the first power supply bus 08 and the second power supply bus 010 in the peripheral area BB can be prepared simultaneously, simplifying the process of manufacturing the array substrate. Of course, the first power supply bus 08 and the second power supply bus 010 may or may not be on the same layer as the connection electrode 022, and this embodiment of the present disclosure does not limit this.

[0086] When the connecting portion 09 and the first power supply bus 08 are on the same layer, if the first power supply bus 08 is also on the same layer as the connecting electrode 022, it indicates that the connecting portion 09 and the connecting electrode 022 are also on the same layer. The selection switch 06 is usually on a different layer from the connecting electrode 022. In this way, the connecting portion 09, the first power supply bus 08, and the second power supply bus 010 are all on different layers from the selection switch 06. Therefore, the parasitic capacitance between the connecting portion 09, the first power supply bus 08, and the second power supply bus 010 and the selection switch 06 can be further reduced.

[0087] Also, by way of example, the above-mentioned third power supply bus 012 and fourth power supply bus 013 are on the same layer as the driving source electrode 0213, or the above-mentioned third power supply bus 012 and fourth power supply bus 013 are on the same layer as the driving drain electrode 0214. In the embodiment of the present disclosure, the driving source electrode 0213 and the driving drain electrode 0214 are taken as an example of being on the same layer. Therefore, the third power supply bus 012, the fourth power supply bus 013, the driving source electrode 0213, and the driving drain electrode 0214 are all on the same layer. Of course, the third power supply bus 012 and fourth power supply bus 013 may not be on the same layer as the driving source electrode 0213, and the third power supply bus 012 and fourth power supply bus 013 may not be on the same layer as the driving drain electrode 0214. The embodiment of the present disclosure does not limit this.

[0088] Figure 5 A kind provided by the embodiment of the present disclosure Figure 1 Schematic diagram of the middle cross-section UU. Please refer to Figure 1 and Figure 5 , the above-mentioned selection switch 06 may include:

[0089] A first active layer 061 located on the substrate 01;

[0090] A first gate 062 and a second gate 063 located on the side of the first active layer 061 away from the substrate 01. The first gate 062 and the second gate 063 are on the same layer and do not overlap;

[0091] A first source electrode 064, a first drain electrode 065, and a second drain electrode 066 located on the side of the first gate 062 and the second gate 063 away from the substrate 01. The first source electrode 064, the first drain electrode 065, and the second drain electrode 066 are on the same layer and do not overlap. The first source electrode 064 is located between the first drain electrode 065 and the second drain electrode 066;

[0092] The first source electrode 064 is connected to one of the multiple data signal input lines 07, and the first drain electrode 065 and the second drain electrode 066 are connected to two of the multiple data line leads 05.

[0093] Optionally, the orthographic projection of each of the first gate 062 and the second gate 063 on the substrate 01 does not overlap with the orthographic projection of the first source 064, the first drain 065, and the second drain 066 on the substrate 01.

[0094] Optionally, some structures in the selection switch 06 may be on the same layer as some structures in the driving transistor. For example: the first active layer 061 and the driving active layer 0211 are on the same layer, the first gate 062 and the driving gate 0212 are on the same layer, and the first source 064 and the driving source 0213 are on the same layer. Of course, the first active layer 061 and the driving active layer 0211 may not be on the same layer, the first gate 062 and the driving gate 0212 may not be on the same layer, and the first source 064 and the driving source 0213 may not be on the same layer. The embodiments of the present disclosure do not limit this.

[0095] Please continue to refer to Figure 1 , the array substrate may further include a first control line 014 and a second control line 015; the first control line 014 is connected to the first gate 062, and the second control line 015 is connected to the second gate 063; the orthographic projections of the first control line 014 and the second control line 015 on the substrate 01 overlap with the orthographic projection of the plurality of first openings 011 on the substrate 01.

[0096] Optionally, Figure 6 This is a Figure 1 schematic diagram of the cross-section VV provided by the embodiment of the present disclosure, Figure 7-1 This is a Figure 1 schematic diagram of the cross-section WW provided by the embodiment of the present disclosure, Figure 7-2 This is a Figure 1 schematic diagram of the cross-section TT provided by the embodiment of the present disclosure. Please refer to Figure 1 , Figure 6 , Figure 7-1 and Figure 7-2 , at least one of the plurality of connection portions 09 includes a second opening 091, and the orthographic projection of the second opening 091 on the substrate 01 overlaps with the orthographic projections of the first control line 014 and the second control line 015 on the substrate 01. It should be noted that in the embodiment of the present disclosure, the second opening 091 is provided in the connection portion 09. Under the action of the second opening 091, the overlapping degree of the connection portion 09 with the first control line 014 and the second control line 015 can be reduced. Thereby, the parasitic capacitance formed by the connection portion 09 and these two control lines can be reduced, and the influence on the power signal transmitted on the connection portion 09 can be further reduced.

[0097] Optionally, multiple data line leads 05 are on the same layer as the first gate 062 or the second gate 063. By way of example, the first gate 062 and the second gate 063 may be on the same layer, in which case the multiple data line leads 05, the first gate 062, and the second gate 063 are all on the same layer. Of course, the multiple data line leads 05 may not be on the same layer as the first gate 062 or the second gate 063, and the embodiments of the present disclosure do not limit this.

[0098] Optionally, multiple data signal input lines 07 include a first data signal input line 071 and a second data signal input line 072. The first data signal input line 071 and the second data signal input line 072 are arranged alternately and are on different layers. By way of example, the above-mentioned first data signal input line 071 is on the same layer as the driving gate in the sub-pixel 02 (such as Figure 4 the driving gate 0212), and the second data signal input line 072 is on the same layer as the second capacitor electrode 0342 in the sub-pixel 02. Of course, the first data signal input line 071 may not be on the same layer as the driving gate in the sub-pixel 02, and the second data signal input line 072 may not be on the same layer as the second capacitor electrode 0342 in the sub-pixel 02, and the embodiments of the present disclosure do not limit this.

[0099] The working principle of the array substrate provided by the embodiments of the present disclosure will be described below.

[0100] When the array substrate needs to display an image, power signals are transmitted on the first power bus, the second power bus, the third power bus, the fourth power bus, and the connection part in the array substrate. The power signals are transmitted to each sub-pixel via multiple first power lines.

[0101] When the array substrate needs to display an image, the signal source end in the array substrate (such as Figure 1Multiple signal input pads C) among them can also respectively input data signals to multiple selection switches through multiple data signal input lines. When the signal source end inputs a data signal to a selection switch through each data signal input line, the data signal is input to the first source electrode of the selection switch. By cooperating with the first control line and the second control line, it can be realized that the data signal on the first source electrode is respectively transmitted to two data lines. Exemplarily, an enabling signal can be first input to the first control line to make the first source electrode and the first drain electrode conduct, and at this time, the data signal on the first source electrode is transmitted to a data line via the first drain electrode and a data line lead; then, an enabling signal is input to the second control line to make the first source electrode and the second drain electrode conduct, and at this time, the data signal on the first source electrode is transmitted to another data line via the second drain electrode and another data line lead. After data signals are input to each data line, the sub-pixels connected to each data line also receive the data signal.

[0102] After each sub-pixel receives the power signal and the data signal, it can emit light based on the power signal and the data signal, thereby achieving the purpose of the array substrate displaying an image. Since in the array substrate provided by the embodiments of the present disclosure, the degree of overlap between the structure configured to transmit the power signal and the selection switch is relatively low, therefore, the structure configured to transmit the power signal and the selection switch can both work properly. And, the structure configured to transmit the power signal in the array substrate is a multi-layer structure, so the impedance of the power signal transmission is small, and the power signal can be effectively transmitted to the sub-pixels. In addition, there are multiple structures on the same layer in the array substrate provided by the embodiments of the present disclosure, making the process flow for manufacturing the array substrate relatively simple.

[0103] Optionally, in the array substrate provided by the embodiments of the present disclosure, the material of the conductive structure can be a transparent material or a non-transparent material, such as metal elements such as indium tin oxide, copper, aluminum, silver, molybdenum, nickel, gold, etc., metal simple substances or alloys.

[0104] The present disclosure also provides a manufacturing method for any one of the above-mentioned array substrates, and the method includes:

[0105] Form multiple sub-pixels, multiple data lines, multiple first power supply lines, multiple data line leads, multiple selection switches, multiple data signal input lines, a first power supply bus, and multiple connection parts on a substrate.

[0106] Among them, the substrate includes a display area and a peripheral area at least on one side of the display area;

[0107] Multiple sub-pixels, located in the display area;

[0108] Multiple data lines, located in the display area, and configured to provide data signals to multiple sub-pixels;

[0109] A plurality of first power supply lines, located in the display area, are configured to supply power signals to a plurality of sub-pixels;

[0110] A plurality of data line leads, located in the peripheral area and connected to a plurality of data lines;

[0111] A plurality of selection switches, located in the peripheral area and arranged at intervals, the plurality of selection switches are located on the side of the plurality of data line leads away from the display area, and at least one of each of at least some of the plurality of selection switches is connected to at least two of the plurality of data line leads;

[0112] A plurality of data signal input lines, located in the peripheral area and on the side of the plurality of selection switches away from the display area, and at least one of each of at least some of the plurality of selection switches is connected to one of the plurality of data signal input lines;

[0113] A first power supply bus, located in the peripheral area and on the side of the plurality of selection switches away from the display area;

[0114] A plurality of connection parts, connected to the first power supply bus and the plurality of first power supply lines, and the plurality of connection parts extend towards the display area along the area between the plurality of selection switches.

[0115] Optionally, a second power supply bus, a third power supply bus, a fourth power supply bus, a first control line, and a second control line, one or more of which, can also be fabricated on the substrate. These structures can refer to the above-described array substrate embodiments, and the embodiments of the present disclosure will not be elaborated herein.

[0116] It should be understood that, with reference to any manufacturing method in the related art that has an array substrate similar to that provided by the embodiments of the present disclosure, the method of the embodiments of the present disclosure can be implemented by, for example, changing the pattern on the mask plate, and will not be elaborated herein one by one.

[0117] The embodiments of the present disclosure further provide a display device, which includes any one of the above-described array substrates. The display device in the embodiments of the present disclosure can be: a display panel (such as a liquid crystal display panel, an organic light-emitting diode display panel, etc.), a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, or any other product or component with a display function.

[0118] As an example, Figure 8 It is a schematic structural diagram of a display device provided by the embodiments of the present disclosure. The display device includes any one of the above-described display panels, and the display area AA of the display device includes sub-pixels 02 arranged in rows and columns. Figure 8 The detailed structure of the peripheral area BB is not shown.

[0119] In the present disclosure, "at least one" means one or more, and "a plurality of" means two or more. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one of a, b, or c can represent: a, b, c, a + b, a + c, b + c, and a + b + c, where a, b, and c can be single items or multiple items.

[0120] It should be noted that in the drawings, the sizes of some or all of the layers, or the sizes of some or all of the regions, may be exaggerated for clarity of illustration. Moreover, it can be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element, or there may be an intermediate layer. Additionally, it can be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element, or there may be more than one intermediate layer or element. Additionally, it can also be understood that when a layer or element is referred to as being "between" two layers or two elements, it can be the only layer between the two layers or two elements, or there may also be more than one intermediate layer or element. Similar reference numerals throughout indicate similar elements.

[0121] In the present disclosure, terms such as "first", "second", etc. are only configured for descriptive purposes and should not be construed as indicating or implying relative importance. The "connection" of two conductors refers to the direct or indirect connection of the two conductors, and the two conductors can transmit electrical signals.

[0122] It should be noted that the method embodiments provided in the embodiments of the present disclosure can be referred to in combination with the corresponding array substrate embodiments, and the embodiments of the present disclosure do not limit this. The order of the steps in the method embodiments provided in the embodiments of the present disclosure can be appropriately adjusted, and the steps can also be increased or decreased accordingly. Any method that can be easily thought of by any person skilled in the art within the technical scope disclosed by the present disclosure should be covered within the protection scope of the present disclosure, so details are not described herein again.

[0123] The above are only exemplary embodiments of the present disclosure and are not intended to limit the present disclosure. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present disclosure should be included within the protection scope of the present disclosure.

Claims

1. An array substrate, characterized in that, Comprising: A substrate, the substrate comprising a display area and a peripheral area at least on one side of the display area; A plurality of sub-pixels, located in the display area; A plurality of data lines, located in the display area, configured to provide data signals to the plurality of sub-pixels; A plurality of first power supply lines, located in the display area, configured to provide power supply signals to the plurality of sub-pixels; A plurality of data line leads, located in the peripheral area and electrically connected to the plurality of data lines; A plurality of selection switches, located in the peripheral area and arranged at intervals, the plurality of selection switches being on the side of the plurality of data line leads away from the display area, and at least each of at least some of the plurality of selection switches electrically connecting at least two of the plurality of data line leads; A plurality of data signal input lines, located in the peripheral area and on the side of the plurality of selection switches away from the display area, and at least each of at least some of the plurality of selection switches electrically connecting one of the plurality of data signal input lines; A first power supply bus, located in the peripheral area and on the side of the plurality of selection switches away from the display area; A plurality of connection parts, electrically connected to the first power supply bus and electrically connected to the plurality of first power supply lines, the plurality of connection parts extending towards the display area along the area between the plurality of selection switches.

2. The array substrate according to claim 1, characterized in that, Further comprising a second power supply bus located between the plurality of selection switches and the display area; Wherein, the plurality of connection parts are respectively electrically connected to the first power supply bus and the second power supply bus.

3. The array substrate according to claim 2, characterized in that, The first power supply bus and the second power supply bus are located on the same layer.

4. The array substrate according to claim 2, characterized in that, The first power supply bus, the second power supply bus and the plurality of connection parts are located on the same layer.

5. The array substrate according to any one of claims 2 to 4, characterized in that, The first power supply bus, the second power supply bus and the plurality of connection parts define a plurality of first openings arranged in an array, and the orthographic projection of the plurality of selection switches on the substrate is located in the plurality of first openings.

6. The array substrate according to any one of claims 2 to 4, characterized in that, Further comprising a third power supply bus, The orthographic projection of the third power supply bus on the substrate and the orthographic projection of the first power supply bus on the substrate at least partially overlap, and the third power supply bus is electrically connected to the first power supply bus.

7. The array substrate according to claim 6, characterized in that, Further comprising a fourth power supply bus, The orthographic projection of the fourth power supply bus on the substrate and the orthographic projection of the second power supply bus on the substrate at least partially overlap, and the fourth power supply bus is electrically connected to the second power supply bus.

8. The array substrate according to claim 7, characterized in that, The third power supply bus and the fourth power supply bus are located on the same layer.

9. The array substrate according to any one of claims 2 to 4, characterized in that, At least one of the plurality of sub-pixels includes a driving thin film transistor and a connection electrode; The driving thin film transistor includes a driving active layer located on the substrate, a driving gate on the side of the driving active layer away from the substrate, a driving source electrode and a driving drain electrode on the side of the driving gate away from the substrate; The connection electrode is located on the side of the driving source electrode and the driving drain electrode away from the substrate; The first power supply bus and the second power supply bus are located on the same layer as the connection electrode.

10. The array substrate according to any one of claims 7 to 8, characterized in that, At least one of the plurality of sub-pixels includes a driving thin film transistor and a connection electrode; The driving thin-film transistor includes a driving active layer located on the substrate, a driving gate located on a side of the driving active layer away from the substrate, and a driving source electrode and a driving drain electrode located on a side of the driving gate away from the substrate; the connecting electrode is located on a side of the driving source electrode and the driving drain electrode away from the substrate; The third power supply bus and the fourth power supply bus are on the same layer as the driving source electrode, or the third power supply bus and the fourth power supply bus are on the same layer as the driving drain electrode.

11. The array substrate according to any one of claims 2 to 4, characterized in that, The selection switch includes: A first active layer located on the substrate; A first gate electrode and a second gate electrode located on a side of the first active layer away from the substrate, the first gate electrode and the second gate electrode being on the same layer and non-overlapping; A first source electrode, a first drain electrode, and a second drain electrode located on a side of the first gate electrode and the second gate electrode away from the substrate, the first source electrode, the first drain electrode, and the second drain electrode being on the same layer and non-overlapping, and the first source electrode being located between the first drain electrode and the second drain electrode; The first source electrode is electrically connected to one of the plurality of data signal input lines, and the first drain electrode and the second drain electrode are electrically connected to one of the plurality of data line leads.

12. The array substrate according to claim 11, wherein, The orthographic projection of each of the first gate electrode and the second gate electrode on the substrate does not overlap with the orthographic projection of the first source electrode, the first drain electrode, and the second drain electrode on the substrate.

13. The array substrate according to claim 12, wherein, It further includes a first control line and a second control line; The first control line is electrically connected to the first gate electrode, and the second control line is electrically connected to the second gate electrode; The first power supply bus, the second power supply bus, and the plurality of connection portions define a plurality of first openings arranged in an array, and the orthographic projection of the first control line and the second control line on the substrate overlaps with the orthographic projection of the plurality of first openings on the substrate.

14. The array substrate according to claim 13, wherein, At least one of the plurality of connection portions includes a second opening, and the orthographic projection of the second opening on the substrate overlaps with the orthographic projections of the first control line and the second control line on the substrate.

15. The array substrate according to claim 11, wherein, The plurality of data line leads are on the same layer as the first gate electrode or the second gate electrode.

16. The array substrate according to claim 11, wherein, The plurality of data signal input lines include a first data signal input line and a second data signal input line, the first data signal input line and the second data signal input line are alternately arranged, and the first data signal input line and the second data signal input line are on different layers.

17. The array substrate according to claim 16, wherein, At least one of the plurality of sub-pixels includes a driving thin-film transistor, a connecting electrode, and a storage capacitor; The driving thin-film transistor includes a driving active layer located on the substrate, a driving gate located on a side of the driving active layer away from the substrate, a gate insulating layer located on a side of the driving gate away from the substrate, an interlayer dielectric layer located on a side of the gate insulating layer away from the substrate, and a driving source electrode and a driving drain electrode located on a side of the interlayer dielectric layer away from the substrate; the connecting electrode is located on a side of the driving source electrode and the driving drain electrode away from the substrate; The storage capacitor includes a first capacitor electrode and a second capacitor electrode. The first capacitor electrode is on the same layer as the driving gate, and the second capacitor electrode is located between the gate insulating layer and the interlayer dielectric layer; The first data signal input line is on the same layer as the driving gate, and the second data signal input line is on the same layer as the second capacitor electrode.

18. The array substrate according to claim 17, wherein, The first active layer is on the same layer as the driving active layer, the first gate is on the same layer as the driving gate, and the first source electrode is on the same layer as the driving source electrode.

19. The array substrate according to claim 17 or 18, wherein, At least one of the plurality of sub-pixels further includes: a light-emitting diode located on a side of the connecting electrode away from the substrate, and the driving drain electrode, the connecting electrode, and the light-emitting diode are connected in sequence.

20. A display device, wherein, An array substrate according to any one of claims 1 to 19.

Images