A synchronization method to overcome asynchronous escape

Abstract

The present application belongs to the technical field of airborne computer, and particularly relates to a synchronous method for overcoming asynchronous escape, which is used for synchronous control of at least two synchronous computers; each of the synchronous computers performs a handshaking operation after completing each task to realize synchronization; each of the synchronous computers sends result data of whether the historical handshaking is normally completed each time the handshaking is performed; when the current handshaking is normal and it is detected that the historical handshaking is normally completed, it is determined that the synchronous computers are successfully synchronized; the present application can ensure the accuracy and completeness of the synchronization between different computers with different redundancies, and can maximally overcome the occurrence of asynchronous escape phenomenon.

Description

Technical Field

[0001] This invention belongs to the field of airborne computer technology, and specifically relates to a synchronization method to overcome asynchronous escape. Background Technology

[0002] The hardware synchronization indicator circuit is a dedicated hardware function circuit that must be present in each redundant computer within an onboard redundant fault-tolerant computer. This circuit, in conjunction with the software synchronization algorithm, enables task synchronization between redundant computers. The purpose of synchronization is to ensure that different redundant computer units are in a synchronized running state while executing the same task. This synchronization of running state, by default, includes synchronization of the execution cycle and synchronization of execution steps; that is, in the ideal state, different redundant computer units should be executing the same task process instructions at the same time. While the hardware synchronization algorithm itself is mature in traditional designs, it is incomplete from a practical standpoint. Even if hardware synchronization is successful, can it accurately indicate that different redundant computer units are currently in the same task process execution state? Obviously not. Within a computer, there are usually multiple processes requiring synchronization. If two redundant channels exhibit significant asynchronous differences under certain abnormal conditions—for example, redundant channel A is preparing to execute task process n, while redundant channel B is preparing to execute task process m—both processes need to perform synchronization operations. At this point, redundant channels A and B might successfully complete the traditional hardware synchronization algorithm, but they would be executing different task processes. This is because traditional hardware synchronization algorithms do not include the identification of task process states, leading to this asynchronous escape phenomenon. Therefore, it is necessary to provide a more robust synchronization algorithm to compensate for the shortcomings of traditional methods and overcome the asynchronous escape phenomenon. Summary of the Invention

[0003] In view of this, the present invention proposes a synchronization method to overcome asynchronous escape, which can ensure the accuracy and completeness of synchronization between computers with different redundancy and overcome the occurrence of asynchronous escape to the greatest extent.

[0004] To achieve the above-mentioned technical objectives, the specific technical solution adopted by the present invention is as follows:

[0005] A synchronization method to overcome asynchronous escape for synchronous control of at least two synchronous computers;

[0006] After each task is completed, each of the synchronous computers performs a handshake operation to achieve synchronization; during each handshake, each of the synchronous computers sends the result data of whether the previous handshake was completed normally.

[0007] When the current handshake is successful and all previous handshakes are detected to have been successfully completed, it is determined that the synchronization computers have successfully synchronized.

[0008] If the current handshake is abnormal or if a previous handshake is detected as not being completed properly, the synchronization of each of the aforementioned synchronization computers is determined to have failed.

[0009] Furthermore, the synchronization method for overcoming asynchronous escape is based on processor circuitry, large-scale programming logic circuitry, and four data buffer isolation circuits.

[0010] Furthermore, the control bus, data bus, and address bus of the processor circuit are all connected to the large-scale programming logic circuit.

[0011] Furthermore, the synchronization state logic level signal output by the large-scale programming logic circuit is connected to a data buffer isolation circuit and then to a synchronization indicator drive output circuit to generate a local synchronization indicator output signal; the large-scale programming logic circuit receives the synchronization indicator signal from the processor circuit, which is then connected to a data buffer isolation circuit and then input to the large-scale programming logic circuit.

[0012] Furthermore, the serial signal output by the large-scale programming logic circuit is connected to a data buffer isolation circuit and then connected to a differential output driving circuit to complete the serial data transmission.

[0013] The differential input to single-ended circuit receives the serial data from the processor circuit, converts it into a single-ended signal, passes it through a data buffer isolation circuit, and then connects it to the large-scale programming logic circuit.

[0014] Furthermore, the software process for implementing synchronization methods to overcome asynchronous escape includes the following steps:

[0015] Step 1: Start;

[0016] Step 2: Update parameter L_Num, assigning the current task process number to L_Num;

[0017] Step 3: Initiate hardware instruction synchronization;

[0018] Step 4: Determine if the hardware synchronization is successful. If yes, proceed to Step 5; otherwise, proceed to Step 9.

[0019] Step 5: The content of the local status flag parameter L_Num is sent via serial data;

[0020] Step 6: The status flag sent by the serial data receiving processor circuit is stored in the parameter F_Num;

[0021] Step 7: Check if the contents of parameters L_Num and F_Num are equal. If yes, proceed to step 8; otherwise, proceed to step 9.

[0022] Step 8: Begin executing this task process;

[0023] Step 9: Execute the synchronization failure handling process;

[0024] Step 10: End the current task process;

[0025] Before step 1, each task process is assigned a number, and dynamic parameters L_Num and F_Num are set. L_Num represents the number of the task process that the local computer needs to execute, and F_Num represents the number of the task process that the processor circuit computer is currently executing. Attached Figure Description

[0026] To more clearly illustrate the technical solutions of the embodiments of this disclosure, the drawings used in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this disclosure. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0027] Figure 1 This is a hardware architecture diagram of a synchronization method for overcoming asynchronous escape in a specific embodiment of the present invention;

[0028] Figure 2 This is a software workflow diagram illustrating the synchronization method for overcoming asynchronous escape in a specific embodiment of the present invention. Detailed Implementation

[0029] The embodiments of this disclosure will now be described in detail with reference to the accompanying drawings.

[0030] The following specific examples illustrate the implementation of this disclosure. Those skilled in the art can easily understand other advantages and effects of this disclosure from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of this disclosure, and not all of them. This disclosure can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this disclosure. It should be noted that, in the absence of conflict, the following embodiments and features in the embodiments can be combined with each other. Based on the embodiments in this disclosure, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this disclosure.

[0031] It should be noted that various aspects of embodiments within the scope of the appended claims are described below. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any particular structure and / or function described herein is merely illustrative. Based on this disclosure, those skilled in the art will understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number of aspects set forth herein can be used to implement the device and / or practice the method. Additionally, this device and / or method can be implemented using other structures and / or functionalities besides one or more of the aspects set forth herein.

[0032] It should also be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this disclosure. The illustrations only show the components related to this disclosure and are not drawn according to the number, shape and size of the components in actual implementation. In actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.

[0033] Furthermore, specific details are provided in the following description to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that the described aspects can be practiced without these specific details.

[0034] In one embodiment of the present invention, a synchronization method for overcoming asynchronous escape is proposed for the synchronization control of at least two synchronous computers.

[0035] After each task is completed, each of the synchronous computers performs a handshake operation to achieve synchronization; during each handshake, each of the synchronous computers sends the result data of whether the previous handshake was completed normally.

[0036] When the current handshake is successful and all previous handshakes are detected to have been successfully completed, it is determined that the synchronization computers have successfully synchronized.

[0037] If the current handshake is abnormal or if a previous handshake is detected as not being completed properly, the synchronization of each of the aforementioned synchronization computers is determined to have failed.

[0038] In this embodiment, as Figure 1 As shown, the synchronization method for overcoming asynchronous escape is based on processor circuitry, large-scale programming logic circuitry, and four data buffer isolation circuits.

[0039] The control bus, data bus, and address bus of the processor circuit are all connected to the large-scale programming logic circuit.

[0040] The synchronization state logic level signal output by the large-scale programming logic circuit is connected to a data buffer isolation circuit and then to a synchronization indicator drive output circuit to generate a local synchronization indicator output signal; the large-scale programming logic circuit receives the synchronization indicator signal from the processor circuit, which is then connected to a data buffer isolation circuit and then input to the large-scale programming logic circuit.

[0041] The serial signal output by the large-scale programmable logic circuit is connected to a data buffer isolation circuit, and then connected to a differential output driver circuit to complete the serial data transmission.

[0042] The differential input to single-ended circuit receives the serial data from the processor circuit, converts it into a single-ended signal, passes it through a data buffer isolation circuit, and then connects it to the large-scale programming logic circuit.

[0043] In this embodiment, as Figure 2 As shown, the software execution flow of the synchronization method for overcoming asynchronous escape includes the following steps:

[0044] Step 1: Start;

[0045] Step 2: Update parameter L_Num, assigning the current task process number to L_Num;

[0046] Step 3: Initiate hardware instruction synchronization;

[0047] Step 4: Determine if the hardware synchronization is successful. If yes, proceed to Step 5; otherwise, proceed to Step 9.

[0048] Step 5: The content of the local status flag parameter L_Num is sent via serial data;

[0049] Step 6: The status flag sent by the serial data receiving processor circuit is stored in the parameter F_Num;

[0050] Step 7: Check if the contents of parameters L_Num and F_Num are equal. If yes, proceed to step 8; otherwise, proceed to step 9.

[0051] Step 8: Begin executing this task process;

[0052] Step 9: Execute the synchronization failure handling process;

[0053] Step 10: End the current task process;

[0054] Before step 1, each task process is assigned a number, and dynamic parameters L_Num and F_Num are set. L_Num represents the number of the task process that the local computer needs to execute, and F_Num stores the task process number transmitted to the local computer by the processor circuit. F_Num represents the number of the task process that the processor circuit is currently executing.

[0055] The above description is merely a specific embodiment of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.

Claims

1. A synchronization method to overcome asynchronous escape, characterized in that, Synchronization control for at least two synchronous computers; After each task is completed, each of the synchronous computers performs a handshake operation to achieve synchronization; during each handshake, each of the synchronous computers sends the result data of whether the previous handshake was completed normally. When the current handshake is successful and all previous handshakes are detected to have been successfully completed, it is determined that the synchronization computers have successfully synchronized. If the handshake is abnormal or if a previous handshake is detected as not being completed properly, the synchronization of each of the aforementioned synchronization computers is deemed to have failed. The software process for implementing a synchronization method to overcome asynchronous escape includes the following steps: Step 1: Start; Step 2: Update parameter L_Num, assigning the current task process number to L_Num; Step 3: Initiate hardware instruction synchronization; Step 4: Determine if the hardware synchronization is successful. If yes, proceed to Step 5; otherwise, proceed to Step 9. Step 5: The content of the local status flag parameter L_Num is sent via serial data; Step 6: Receive the status flag sent by the remote end via serial data and store it in the parameter F_Num; Step 7: Check if the contents of parameters L_Num and F_Num are equal. If yes, proceed to step 8; otherwise, proceed to step 9. Step 8: Begin executing this task process; Step 9: Execute the synchronization failure handling procedure; Step 10: End the current task process; Before step 1, each task process is assigned a number, and dynamic parameters L_Num and F_Num are set. L_Num represents the number of the task process that the local computer needs to execute, and F_Num represents the number of the task process that the remote computer is currently executing.

2. The synchronization method for overcoming asynchronous escape according to claim 1, characterized in that, The synchronization method for overcoming asynchronous escape is implemented based on processor circuitry, large-scale programmable logic circuitry, and four data buffer isolation circuits.

3. The synchronization method for overcoming asynchronous escape according to claim 2, characterized in that, The control bus, data bus, and address bus of the processor circuit are all connected to the large-scale programming logic circuit.

4. The synchronization method for overcoming asynchronous escape according to claim 3, characterized in that, The synchronization state logic level signal output by the large-scale programming logic circuit is connected to a data buffer isolation circuit and then to a synchronization indicator drive output circuit to generate a local synchronization indicator output signal; the synchronization indicator input isolation circuit receives the remote synchronization indicator signal and then connects to a data buffer isolation circuit, which is then input to the large-scale programming logic circuit.

5. The synchronization method for overcoming asynchronous escape according to claim 4, characterized in that, The serial signal output by the large-scale programmable logic circuit is connected to a data buffer isolation circuit, and then connected to a differential output driver circuit to complete the serial data transmission. The differential input to single-ended circuit receives serial data from the processor circuit, converts it into a single-ended signal, passes it through a data buffer isolation circuit, and then connects it to the large-scale programming logic circuit.

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