Method for automatic optimization of layout for timing insensitive digital circuits in integrated circuits
By constructing a hypergraph network and using genetic algorithms or simulated annealing to optimize the layout of analog integrated circuits, the problem of high computational cost in the layout of timing-insensitive digital circuits is solved, achieving optimization of layout area and improvement of efficiency.
Patent Information
- Application Number
- CN202211333547.4
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2022-10-28
- Publication Date
- 2026-08-25
- Estimated Expiration
- 2042-10-28
AI Technical Summary
In existing technologies, the layout optimization process for timing-insensitive digital circuits in analog integrated circuits involves a large amount of computation, which increases exponentially with the size of the circuit, resulting in slow optimization speed.
By acquiring circuit device information icons, a hypergraph network is constructed, strong signal flow device groups and weak signal flow devices are extracted, and one-dimensional relative position data is constructed using genetic algorithms or simulated annealing methods. This data is then converted into a two-dimensional layout and adjusted to match the wiring space and optimize the layout area.
By optimizing the layout process, the layout area of strong signal flow devices and weak signal flow devices is reduced, the circuit layout efficiency is improved, and the amount of computation and optimization time are reduced.
Smart Images
Figure CN115688667B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of circuit layout technology, specifically to an automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits. Background Technology
[0002] Analog integrated circuits typically contain multiple small-scale digital circuits that are not time-sensitive. Analog layout engineers generally place these circuits manually, following the pattern of analog circuits. Based on the circuit schema and netlist provided by the designer, layout engineers rely on experience and iterative attempts to arrange the circuits according to layout requirements. Essentially, this is a high-dimensional, multi-objective combinatorial optimization problem, which can be transformed into a constrained nonlinear programming problem and solved using optimization algorithms.
[0003] Combinatorial optimization algorithms require a large amount of computation. As the circuit size increases, the amount of computation increases exponentially, and the time required for optimization also increases exponentially, which seriously slows down the optimization speed. Summary of the Invention
[0004] In view of this, the purpose of the present invention is to provide an automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits, which can improve the efficiency of circuit layout.
[0005] To achieve the above objectives, the present invention adopts the following technical solution:
[0006] The automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits of the present invention includes the following steps:
[0007] Obtain information icons of the circuit components to be laid out;
[0008] A hypergraph network is constructed using the aforementioned information icons to obtain an initial layout;
[0009] Extract strong signal flow device groups and weak signal flow devices from the initial layout, and construct one-dimensional relative position data of the strong signal flow device groups and the weak signal flow devices;
[0010] The one-dimensional relative position data is converted into a two-dimensional layout, and the two-dimensional layout is adjusted so that the adjusted two-dimensional layout matches the preset wiring space.
[0011] Further, extracting strong signal flow device groups and weak signal flow devices from the initial layout includes:
[0012] The signal icons in the initial layout are filtered according to a preset signal flow threshold to obtain strong signal flow devices and weak signal flow devices; signal icons with a signal flow strength greater than or equal to the signal flow threshold are strong signal flow devices, and signal icons with a signal flow strength less than the signal flow threshold are weak signal flow devices.
[0013] The strong signal flow devices in the initial layout are extracted using the directed graph longest path algorithm to obtain the strong signal flow device group.
[0014] Furthermore, constructing one-dimensional relative position data for the strong signal flow device and the weak signal flow device includes:
[0015] A one-dimensional relative position data of the strong signal flow device and the weak signal flow device is constructed using a genetic algorithm or simulated annealing method, so as to minimize the winding space of the strong signal flow device and the weak signal flow device arranged according to the one-dimensional relative position data.
[0016] Further, converting the one-dimensional relative position data into a two-dimensional layout includes:
[0017] Calculate the area of the preset wiring space;
[0018] A two-dimensional coordinate system is established based on the area of the wiring space. The strong signal flow devices and weak signal flow devices, which are laid out according to the one-dimensional relative position data, are folded and mapped into the two-dimensional coordinate system to obtain multiple rows of circuit devices.
[0019] By adding trace channels between adjacent rows of circuit components, a two-dimensional layout is obtained.
[0020] Furthermore, adjustments are made to the two-dimensional layout, including:
[0021] The lengths of the multiple rows of circuit devices in the two-dimensional layout are statistically analyzed.
[0022] Based on the uniformity of the length distribution of the multi-row circuit devices;
[0023] Adjust the last circuit device in each row of circuit devices so that the uniformity is higher than a preset uniformity threshold.
[0024] The beneficial effects of this invention are as follows: The automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits of this invention obtains information icons of the circuit devices to be laid out; constructs a hypergraph network using the information icons to obtain an initial layout; extracts strong signal flow device groups and weak signal flow devices from the initial layout, and constructs one-dimensional relative position data of the strong signal flow device groups and weak signal flow devices; converts the one-dimensional relative position data into a two-dimensional layout, and adjusts the two-dimensional layout so that the adjusted two-dimensional layout matches the preset wiring space. This invention first extracts the strong signal flow device groups and weak signal flow devices, and arranges the strong signal flow device groups and weak signal flow devices in one dimension with the goal of minimizing wiring, and then arranges them in two dimensions to minimize the layout area of the strong signal flow device groups and weak signal flow devices. This improves circuit layout efficiency while ensuring a reasonable layout. Attached Figure Description
[0025] The present invention will be further described below with reference to the accompanying drawings and embodiments:
[0026] Figure 1 This is a flowchart illustrating an automatic optimization method for the placement of timing-insensitive digital circuits in integrated circuits.
[0027] Figure 2 This is a schematic diagram illustrating the implementation process of converting a one-dimensional layout into a two-dimensional layout in this application;
[0028] Figure 3 This is a schematic diagram illustrating the implementation process of an automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits.
[0029] Figure 4 This is a flowchart illustrating the genetic algorithm used in one embodiment of the application;
[0030] Figure 5 This is a schematic diagram of the layout optimization result in one embodiment of this application. Detailed Implementation
[0031] The following specific examples illustrate the implementation of this application. Those skilled in the art can easily understand other advantages and effects of this application from the content disclosed in this specification. This application can also be implemented or applied through other different specific embodiments, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of this application. It should be noted that, unless otherwise specified, the following embodiments and features in the embodiments can be combined with each other.
[0032] It should be noted that the illustrations provided in the following embodiments are only schematic representations of the basic concept of this application. Therefore, the drawings only show the components related to this application and are not drawn according to the actual number, shape and size of the components in the actual implementation. In the actual implementation, the form, quantity and proportion of each component can be arbitrarily changed, and the layout of the components may also be more complex.
[0033] Numerous details are explored in the following description to provide a more thorough explanation of embodiments of this application; however, it will be apparent to those skilled in the art that embodiments of this application may be practiced without these specific details.
[0034] like Figure 1 As shown, the automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits in this embodiment includes the following steps:
[0035] S110, Obtain information icons of the circuit components to be laid out;
[0036] S120, Construct a hypergraph network using the information icons to obtain the initial layout; In mathematics, a hypergraph is a generalization of a graph, where an edge can connect any number of vertices. Formally, a hypergraph H is a pair H = (X, E), where X is a set of elements called nodes or vertices, and E is a non-empty subset of X called hyperedges or links.
[0037] S130, extract strong signal flow device groups and weak signal flow devices from the initial layout, and construct one-dimensional relative position data of the strong signal flow device groups and the weak signal flow devices; use graph algorithm to extract several strong signal flow device groups, and the remaining devices are weak signal flow devices;
[0038] S140, the one-dimensional relative position data is converted into a two-dimensional layout, and the two-dimensional layout is adjusted to match the preset wiring space. Based on the placement target and the size of the components, the one-dimensional relative position is converted into a two-dimensional layout, and the layout is automatically fine-tuned according to the required wiring space.
[0039] This invention provides an automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits. The method involves: acquiring information icons of the circuit devices to be laid out; constructing a hypergraph network using these icons to obtain an initial layout; extracting strong signal flow device groups and weak signal flow devices from the initial layout and constructing one-dimensional relative position data for these devices; converting the one-dimensional relative position data into a two-dimensional layout and adjusting the two-dimensional layout to match a preset routing space. This invention first extracts the strong signal flow device groups and weak signal flow devices, then arranges them one-dimensionally with the goal of minimizing routing, followed by a two-dimensional arrangement, thus minimizing the layout area of the strong signal flow device groups and weak signal flow devices. This improves circuit layout efficiency while ensuring a reasonable layout.
[0040] In some embodiments, the process of extracting the strong signal flow device group and the weak signal flow device from the initial layout includes:
[0041] S210, the signal icons in the initial layout are filtered according to a preset signal flow threshold to obtain strong signal flow devices and weak signal flow devices; signal icons with a signal flow strength greater than or equal to the signal flow threshold are strong signal flow devices, and signal icons with a signal flow strength less than the signal flow threshold are weak signal flow devices.
[0042] S220: Strong signal flow devices in the initial layout are extracted using the directed graph longest path algorithm to obtain a strong signal flow device group. The directed graph longest path algorithm is an existing algorithm, and its steps generally include: inputting the number of nodes / edges, inputting edge information, storing the directed graph information as an adjacency list, calculating the latest start time of each node forward, determining if there are loops, calculating the earliest start time of each node backward if loops exist, determining if each node is a critical node, and outputting the longest path and its length. In this embodiment, circuit devices are treated as nodes, and the output longest path obtained by the directed graph longest path algorithm is the strong signal flow device group.
[0043] In this embodiment, a graph algorithm is used to extract several candidate strong signal flow device groups. Based on the strength of the signal flow and the required winding space, the optimal mutually exclusive strong signal flow device group is selected.
[0044] In some embodiments, constructing one-dimensional relative position data of the strong signal flow device and the weak signal flow device includes:
[0045] S310, a one-dimensional relative position data of the strong signal flow device and the weak signal flow device is constructed using a genetic algorithm or simulated annealing method, so as to minimize the winding space of the strong signal flow device and the weak signal flow device arranged according to the one-dimensional relative position data.
[0046] In this embodiment, artificial intelligence or other methods are used to obtain the relative position values of the devices to be placed in one-dimensional space through concurrent computer calculations, and optimization algorithms are used to reduce the space required for placement and wiring. Specifically, a genetic algorithm or simulated annealing method is employed.
[0047] Genetic Algorithm (GA) was first proposed by John Holland in the 1970s. This algorithm is designed based on the laws of biological evolution in nature. It is a computational model that simulates the biological evolutionary process of natural selection and genetic mechanisms in Darwin's theory of evolution. It is a method for searching for optimal solutions by simulating the natural evolutionary process. This algorithm uses mathematical methods and computer simulation to transform the problem-solving process into processes similar to the crossover and mutation of chromosomes and genes in biological evolution. When solving complex combinatorial optimization problems, it can usually obtain better optimization results faster than some conventional optimization algorithms. Genetic algorithms have been widely used in combinatorial optimization, machine learning, signal processing, adaptive control, and artificial life.
[0048] Simulated Annealing (SAA) is a general probabilistic algorithm used to find the optimal solution to a problem within a large search space. It was invented by S. Kirkpatrick, C.D. Gelatt, and M.V. C. in 1983. He also independently invented this algorithm in 1985. Simulated annealing is one of the effective methods for solving the TSP problem.
[0049] In some embodiments, converting the one-dimensional relative position data into a two-dimensional layout includes:
[0050] S410, calculate the area of the preset wiring space;
[0051] S420, establish two-dimensional coordinates based on the area of the wiring space, and fold and map the strong signal flow devices and weak signal flow devices that are laid out according to the one-dimensional relative position data into the two-dimensional coordinates to obtain multiple rows of circuit devices;
[0052] S430 adds routing channels between adjacent rows of circuit devices to obtain a two-dimensional layout.
[0053] In this embodiment, the two-dimensional layout is obtained by mapping the devices in the two-dimensional layout to two-dimensional coordinates. In some embodiments, the devices in the one-dimensional layout are arranged in a single row, while the two-dimensional layout is arranged in multiple rows.
[0054] like Figure 2As shown, in this embodiment, the circuit devices that were originally laid out in a single row are converted into a three-row layout, which effectively saves the layout area.
[0055] In some embodiments, adjusting the two-dimensional layout includes:
[0056] S510, The lengths of the multi-row circuit devices in the two-dimensional layout are statistically analyzed;
[0057] S520, based on the uniformity of the length distribution of the multi-row circuit devices;
[0058] S530, adjust the last circuit device in each row of circuit devices so that the uniformity is higher than a preset uniformity threshold.
[0059] In this embodiment, artificial intelligence or other methods are used to perform concurrent computer calculations and optimize the device positions in a two-dimensional plane based on the layout target using a fine-tuning algorithm.
[0060] like Figure 2 As shown, the original length of the second row was relatively long. After swapping the positions of device 6 in the second row with device 16 in the first row and device 16 in the third row, the layout area was further saved.
[0061] like Figure 3 As shown, in another embodiment of this application, the implementation steps of the automatic optimization method for the layout of timing-insensitive digital circuits in an integrated circuit are as follows:
[0062] 1. Enter the placement target of the map layout, and you can select the number of rows, aspect ratio, etc.;
[0063] 2. Input the threshold defined by the strong signal flow, or you can set the default value and let the algorithm find the definition itself;
[0064] 3. Input the various parameters that need to be defined for the artificial intelligence algorithm and optimization algorithm, as well as the number of CPUs that can be used for parallel computing;
[0065] 4. Submit a layout optimization task.
[0066] This embodiment uses discrete circuit components and graph algorithms to extract strong signal flow groups based on the signal flow, solving the problem that the number of combinatorial optimizations increases exponentially as the circuit size increases, and reducing the optimization time consumption.
[0067] Figure 4This is a flowchart illustrating the genetic algorithm used in this embodiment, which includes the following steps: randomly generating several individuals based on the input parameters; calculating the target value of each individual based on the objective function; determining whether the number of iterations has been reached or the optimization objective has remained stable; optimizing the one-dimensional / two-dimensional relative position when the number of iterations has been reached or the optimization objective has remained stable; otherwise, individual mutations generate several new individuals.
[0068] Figure 5 This diagram illustrates the layout optimization result in one embodiment of this application. Before optimization, two additional routing channels were required; after optimization, only one routing channel is needed, thus saving wiring area.
[0069] This embodiment can simultaneously optimize important indicators such as total winding length, winding space, and signal flow, so that the placement can meet the layout habits and design requirements of analog circuit layout engineers.
[0070] This embodiment employs parallel optimization computation, which significantly improves the optimization speed, enabling tasks that would normally take hours or days to complete to be finished in minutes.
[0071] Compared to manual placement, this embodiment verifies the area occupied by a single device (layout area divided by the total number of devices) across multiple products, showing stable output results without significant fluctuations. In contrast, manual placement heavily relies on the experience of the layout engineer and the available time, resulting in highly volatile placement outcomes.
[0072] In the above embodiments, although the present application has been described in conjunction with specific embodiments thereof, many substitutions, modifications, and variations of these embodiments will be apparent to those skilled in the art based on the foregoing description. The embodiments of the present application are intended to cover all such substitutions, modifications, and variations falling within the broad scope of the appended claims.
[0073] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Any person skilled in the art can modify or alter the above embodiments without departing from the spirit and scope of this application. Therefore, all equivalent modifications or alterations made by those skilled in the art without departing from the spirit and technical concept disclosed in this application should still be covered by the claims of this application.
Claims
1. An automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits, characterized in that: Including the following steps: Obtain information icons of the circuit components to be laid out; A hypergraph network is constructed using the aforementioned information icons to obtain an initial layout; Extracting strong signal flow device groups and weak signal flow devices from the initial layout, and constructing one-dimensional relative position data for the strong signal flow device groups and weak signal flow devices, the extraction of strong signal flow device groups and weak signal flow devices from the initial layout includes: filtering signal icons in the initial layout according to a preset signal flow threshold to obtain strong signal flow devices and weak signal flow devices; signal icons with signal flow strength greater than or equal to the signal flow threshold are strong signal flow devices, and signal icons with signal flow strength less than the signal flow threshold are weak signal flow devices; extracting strong signal flow devices from the initial layout according to a directed graph longest path algorithm to obtain strong signal flow device groups; The one-dimensional relative position data is converted into a two-dimensional layout, and the two-dimensional layout is adjusted to match a preset wiring space. Converting the one-dimensional relative position data into a two-dimensional layout includes: calculating the area of the preset wiring space; establishing two-dimensional coordinates based on the area of the wiring space; folding and mapping strong signal flow devices and weak signal flow devices laid out according to the one-dimensional relative position data into the two-dimensional coordinates to obtain multiple rows of circuit devices; adding routing channels between adjacent rows of circuit devices to obtain a two-dimensional layout; adjusting the two-dimensional layout includes: statistically analyzing the lengths of the multiple rows of circuit devices in the two-dimensional layout; adjusting the last circuit device in each row of circuit devices based on the uniformity of the length distribution of the multiple rows of circuit devices, so that the uniformity is higher than a preset uniformity threshold.
2. The automatic optimization method for the layout of timing-insensitive digital circuits in integrated circuits according to claim 1, characterized in that: Constructing the one-dimensional relative position data of the strong signal flow device and the weak signal flow device includes: A one-dimensional relative position data of the strong signal flow device and the weak signal flow device is constructed using a genetic algorithm or simulated annealing method, so as to minimize the winding space of the strong signal flow device and the weak signal flow device arranged according to the one-dimensional relative position data.