A method and system for intelligent identification of wafer defects
By combining a smart wafer defect identification method with localization registration and an improved Faster R-CNN convolutional neural network, the problems of low accuracy and complexity in existing equipment are solved, achieving efficient and accurate wafer defect detection.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- SHENGJISHENG (NINGBO) SEMICON TECH CO LTD
- Filing Date
- 2022-09-23
- Publication Date
- 2026-06-30
AI Technical Summary
Existing wafer defect detection equipment has low accuracy, poor adaptability, is complex to use, and takes a long time to set parameters.
A wafer defect intelligent identification method is adopted. By acquiring wafer surface images and standard template images for localization and registration, calculating the difference in grayscale histograms, and using an improved Faster R-CNN convolutional neural network classifier to identify defect categories, the defect regions are filtered by combining non-maximum suppression algorithm and probability threshold.
It achieves high-speed and accurate identification of wafer defects, simplifies the setup process, improves detection efficiency and accuracy, and is suitable for the detection of various defect categories with an accuracy rate of 90%-95%.
Smart Images
Figure CN115690670B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to defect detection and identification in semiconductor manufacturing processes such as pre-processing and post-processing, and particularly to a smart wafer defect identification method and system. Background Technology
[0002] Conventional wafer surface defect inspection involves illuminating the wafer surface with an inspection lamp, which then refracts the light, allowing operators to visually identify surface defects. This is considered the gold standard for wafer defect inspection. Besides visual inspection by operators, various inspection devices have been developed to improve efficiency.
[0003] As semiconductor manufacturing processes continue to improve, the manufacturing process requires more accurate defect identification equipment to increase production yield and achieve better profit returns. However, existing inspection equipment and systems have the following problems: insufficient accuracy in defect identification, poor adaptability, and complexity in use, requiring a significant amount of time to set parameters. Summary of the Invention
[0004] To address at least one of the problems existing in the prior art described above, the present invention provides a method and system for intelligent identification of wafer defects.
[0005] In a first aspect, the present invention provides a method for intelligent identification of wafer defects, comprising the following steps:
[0006] Obtain surface images of the wafer;
[0007] The surface image of the wafer and the standard template image are positioned and registered;
[0008] Calculate the grayscale histograms of the surface image of the wafer and the standard template image respectively, and calculate the maximum value in each grayscale histogram, and then calculate the difference between the two maximum values;
[0009] The difference is added to the grayscale value of each pixel within the effective area of the surface image of the wafer, and compared with the grayscale value of the corresponding position in the standard template image. Pixels with a difference greater than a set threshold are marked as defective pixels.
[0010] The area of the connected region of each defect is calculated based on the defect pixel to obtain the defect image;
[0011] Each detected defect image is sequentially input into a convolutional neural network classifier to identify the category of each defect;
[0012] The product is graded based on the identified defect type and quantity.
[0013] The standard template image is selected from a flawless image of a normal wafer surface. Positioning and registration refers to cropping a fixed-size image (e.g., 400×400 pixels) from a pre-defined position in the standard template image, and then using a template matching algorithm on the wafer surface image to calculate the positional difference between the wafer surface image and the standard template image, thus achieving precise registration. Template matching is one of the most common and universal pattern recognition algorithms. Simply put, it's a technique that finds the most similar part in one image to another template image and evaluates the similarity. It's often used in projects requiring visual guidance, such as guiding robots to grasp and sort products, or guiding robots to perform SMT surface mount technology. Template matching algorithms are generally divided into grayscale-based template matching, shape-based template matching, and edge feature point-based template matching. The template matching algorithm used in this invention is grayscale-based template matching.
[0014] In some implementations, the convolutional neural network classifier is a classification model obtained by training and validating an improved Faster R-CNN convolutional neural network.
[0015] In some implementations, the set threshold is a grayscale value, ranging from 10 to 255 (preferably 15-30, or 20-40, or 20).
[0016] In some implementations, the convolutional neural network classifier identifies the category of each defect, comprising the following steps:
[0017] The input image is converted into a feature map using the ResNet-101 convolutional network.
[0018] The region recommendation network selects the region of interest most likely to contain defects from a sliding window based on the feature map;
[0019] The pooling layer extracts corresponding features from the feature map based on the region of interest to form a feature vector. The detection network then uses this feature vector to determine the defect category and performs boundary regression.
[0020] The candidate defect regions are filtered using a nonmaximum suppression algorithm and a probability threshold to obtain the final defect region location and defect category.
[0021] Secondly, the present invention provides a wafer defect intelligent identification system, comprising the following mutually communicating units:
[0022] The image acquisition module is used to acquire surface images of the wafer;
[0023] The positioning and registration module is used for positioning and registration between the surface image of the wafer and the standard template image;
[0024] The processing module is used to calculate the grayscale histogram of the wafer surface image and the grayscale histogram of the standard template image, and calculate the maximum value in each grayscale histogram, and then calculate the difference between the two maximum values; add the difference to the grayscale value of each pixel in the effective area of the wafer surface image, compare it with the grayscale value of the corresponding position in the standard template image, and mark pixels with a difference greater than a set threshold as defect pixels; calculate the area of the connected region of each defect based on the defect pixels to obtain a defect image;
[0025] A convolutional neural network classifier is used to identify the category of each defect in a defect image; based on the identified defect category and quantity, the product is graded.
[0026] In some implementations, the set threshold is a grayscale value, ranging from 10 to 255 (preferably 15-30, or 20-40, or 20).
[0027] In some implementations, the convolutional neural network classifier identifies the category of each defect, comprising the following steps:
[0028] The input image is converted into a feature map using the ResNet-101 convolutional network.
[0029] The region recommendation network selects the region of interest most likely to contain defects from a sliding window based on the feature map;
[0030] The pooling layer extracts corresponding features from the feature map based on the region of interest to form a feature vector. The detection network then uses this feature vector to determine the defect category and performs boundary regression.
[0031] The candidate defect regions are filtered using a nonmaximum suppression algorithm and a probability threshold to obtain the final defect region location and defect category.
[0032] In some implementations, the image acquisition module includes a camera (preferably an industrial camera) and a light source;
[0033] The intelligent wafer defect recognition system includes a host computer; the positioning and registration module, the computation and processing module, and the convolutional neural network classifier are all located in the host computer.
[0034] Thirdly, the present invention provides a smart wafer defect identification device, comprising:
[0035] A camera (preferably an industrial camera) is used to acquire images of the wafer surface;
[0036] A light source is used to illuminate the wafer placed within the field of view of the camera;
[0037] A host computer has a processor and a memory, wherein a computer program is stored in the memory, and the computer program, when executed by the processor, implements the method as described in any embodiment of the first aspect.
[0038] The camera communicates with the host computer.
[0039] Fourthly, the present invention provides a chip comprising: a processor for calling and running a computer program from a memory, causing a device having the chip mounted to perform: the method as described in any embodiment of the first aspect.
[0040] Fifthly, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the method as described in any embodiment of the first aspect.
[0041] In a sixth aspect, the present invention provides a computer program product including computer program instructions that cause a computer to perform the method as described in any embodiment of the first aspect.
[0042] The beneficial effects of this invention are:
[0043] 1. This invention can identify wafer defects and determine the quality level of wafer products by intelligently analyzing the surface image of the wafer.
[0044] 2. The setup process has been simplified, saving time and avoiding errors caused by overly complex setup procedures.
[0045] 3. Suitable for inspecting wafer products with various defect types, such as microparticles, short circuits, and broken wires, with accuracy rates of 90%, 97%, and 95%, respectively. Accuracy for normal, defect-free wafers reaches 99%.
[0046] 4. The area of the defect can be accurately determined.
[0047] The wafer manufacturing industry continues to evolve in accordance with Moore's Law, with process technology shrinking from the micrometer level to the single-digit nanometer level. Advanced processes mean more complex patterns, which in turn require more sophisticated defect detection and classification technologies. Users have increasingly higher yield requirements, and these higher yield demands necessitate more accurate defect identification.
[0048] Wafer defects exist in various ways and are of diverse types. The process of acquiring wafer images is affected by external factors, leading to numerous interfering elements. Therefore, identifying wafer surface defects presents challenges such as high classification difficulty and a high misclassification rate.
[0049] To address these issues, this invention proposes for the first time to combine wafer defect recognition with neural networks. It involves wafer image localization and registration, grayscale processing, and operations such as difference and discrepancy to obtain defect images which are then incorporated into the neural network. Furthermore, the improved Faster R-CNN, with its superior feature extraction network structure, generates multi-layer feature maps more conducive to multi-scale and small target recognition. Compared to other conventional one-stage convolutional neural networks, the two-stage network of the improved Faster R-CNN is more accurate and better suited for high-precision, multi-scale, and small target recognition problems.
[0050] The following will further explain the concept, specific structure, and technical effects of the present invention in conjunction with the accompanying drawings, so as to fully understand the purpose, features, and effects of the present invention. Attached Figure Description
[0051] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0052] Figure 1 A flowchart illustrating an embodiment of the intelligent wafer defect identification method of the present invention;
[0053] Figure 2 This is a schematic diagram of the structural composition of an embodiment of the intelligent wafer defect recognition system of the present invention. Detailed Implementation
[0054] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0055] Example 1
[0056] Figure 1 The flowchart of the intelligent wafer defect recognition method of this embodiment is shown, and is described in detail below:
[0057] The intelligent wafer defect identification method provided in this embodiment includes the following steps:
[0058] S1. Obtain a surface image of the wafer;
[0059] S2. The surface image of the wafer and the standard template image are positioned and registered;
[0060] S3. Calculate the grayscale histograms of the surface image of the wafer and the standard template image respectively, and calculate the maximum value in each grayscale histogram, and then calculate the difference between the two maximum values.
[0061] S4. Add the difference to the grayscale value of each pixel in the effective area of the surface image of the wafer, compare it with the grayscale value of the corresponding position in the standard template image, and mark the pixels with a difference greater than a set threshold as defective pixels.
[0062] S5. Calculate the area of the connected region of each defect based on the defect pixel to obtain the defect image;
[0063] S6. Input each detected defect image into a convolutional neural network classifier in sequence to identify the category of each defect;
[0064] S7. Determine the grade of the product based on the identified defect type and quantity.
[0065] In step S3, "calculate the maximum value in each grayscale histogram" refers to calculating the maximum value (A) in the set (let's say set A) formed by the grayscale values of each pixel in the surface image of the wafer. max The maximum value in the set (let's call it set B) formed by the grayscale values of each pixel in the standard template image, and the grayscale values of each pixel in the standard template image. max The difference between the two (C = A) max –B max ).
[0066] Step S4 refers to the grayscale value (A) of each pixel within the effective area of the wafer surface image. i Adding C gives us A' i ;A' i The grayscale value (B) at the position corresponding to the standard template image i If we make a comparison, and the difference is (Y=∣A') i –B i If | is greater than the set threshold, then A i The pixel within the effective area of the surface image of the wafer it represents is marked as a defect pixel.
[0067] The convolutional neural network classifier identifies the category of each defect, comprising the following steps:
[0068] S6.1. Use the ResNet-101 convolutional network to convert the input image into a feature map;
[0069] S6.2 The region recommendation network selects the region of interest most likely to have defects from the sliding window based on the feature map;
[0070] S6.3 The pooling layer extracts corresponding features from the feature map based on the region of interest to form a feature vector. The detection network determines the defect category based on the feature vector and performs boundary regression.
[0071] S6.4. The candidate defect regions are filtered using a non-maximum suppression algorithm and a probability threshold to obtain the final defect region location and defect category.
[0072] The convolutional neural network classifier is a classification model obtained by training and validating an improved Faster R-CNN convolutional neural network. (one)
[0074] Using pre-labeled (gold standard inspection) wafer fab sample images (wafer surface images), including 5219 images of dust particles, 3708 images of short circuits, 3592 images of broken wires, and 5010 images of normal operation, an improved Faster R-CNN convolutional neural network was trained to generate neural network model parameters, thereby obtaining the convolutional neural network classifier (the final complete improved Faster R-CNN model).
[0075] Training steps:
[0076] 1. Training the region recommendation network: Initialize the weights of the feature extraction convolutional network and the region recommendation network, and train the region recommendation network end-to-end to generate candidate regions;
[0077] 2. Training Faster R-CNN: Lock the weights of the region recommendation network trained in step 1, and train the Faster R-CNN network by combining the candidate regions obtained from the region recommendation network;
[0078] 3. Optimize the region recommendation network: Initialize the region recommendation network using the R-CNN trained in step 2, fix the feature extraction convolutional network, and continue training the region recommendation network;
[0079] 4. Optimize Faster R-CNN: Initialize Faster R-CNN using the region recommendation network trained in step 3, and continue to train and fine-tune Faster R-CNN to obtain the final complete improved Faster R-CNN model. (two)
[0081] The accuracy of the method in this embodiment was verified using wafer image samples (surface images of wafers) containing various defect categories such as dust particles, short circuits, and broken wires. The results are shown in Table 1.
[0082] Table 1. Verification Results
[0083] micro dust particles Short circuit Broken wire normal total micro dust particles 194 4 2 1 201 Short circuit 11 182 7 0 200 Broken wire 9 2 188 1 200 normal 2 0 0 199 201 total 216 188 197 201 802 accuracy 89.8％ 96.8％ 95.4％ 99.0％ 95.1％ Recall rate 96.5％ 91.0％ 94.0％ 99.0％ 95.1％
[0084] The validation set included 201, 200, 200, and 201 surface images of wafers with microparticles, short circuits, open circuit defects, and normal wafers (obtained through gold standard testing), respectively. The method of this invention detected 216, 188, 197, and 201 surface images of wafers with microparticles, short circuits, open circuit defects, and normal wafers, respectively. The recognition accuracy rates for these surface images were 89.8%, 96.8%, 95.4%, and 99.0%, respectively, with an average of 95.1%. The recall rates were 96.5%, 91.0%, 94.0%, and 99.0%, respectively, with an average of 95.1%. The accuracy rate is calculated by dividing the number of true positives by the total number of detected defects of that type, and taking 100%. For example, the accuracy rate for the microparticles in this invention is 194 / 216 × 100% = 89.8%. The recall rate is calculated by dividing the number of true positives by the actual number of defects of that type, and taking 100%. For example, the accuracy rate for the microparticles in this invention is 194 / 201 × 100% = 96.5%. The average accuracy rate for identifying multiple types of defects in traditional wafer inspection systems is generally between 85% and 92%. The method of this invention for identifying wafer defects outperforms the accuracy rate of traditional wafer inspection systems.
[0085] Example 2
[0086] This embodiment provides a wafer defect intelligent identification system, including the following interconnecting units:
[0087] The image acquisition module is used to acquire surface images of the wafer;
[0088] The positioning and registration module is used for positioning and registration between the surface image of the wafer and the standard template image;
[0089] The processing module is used to calculate the grayscale histogram of the wafer surface image and the grayscale histogram of the standard template image, and calculate the maximum value in each grayscale histogram, and then calculate the difference between the two maximum values; add the difference to the grayscale value of each pixel in the effective area of the wafer surface image, compare it with the grayscale value of the corresponding position in the standard template image, and mark pixels with a difference greater than a set threshold as defect pixels; calculate the area of the connected region of each defect based on the defect pixels to obtain a defect image;
[0090] A convolutional neural network classifier is used to identify the category of each defect in a defect image; based on the identified defect category and quantity, the product is graded.
[0091] The set threshold is a grayscale value, ranging from 10 to 255 (preferably 15-30, or 20-40, or 20). The convolutional neural network classifier identifies the category of each defect, comprising the following steps:
[0092] The input image is converted into a feature map using the ResNet-101 convolutional network.
[0093] The region recommendation network selects the region of interest most likely to contain defects from a sliding window based on the feature map;
[0094] The pooling layer extracts corresponding features from the feature map based on the region of interest to form a feature vector. The detection network then uses this feature vector to determine the defect category and performs boundary regression.
[0095] The candidate defect regions are filtered using a nonmaximum suppression algorithm and a probability threshold to obtain the final defect region location and defect category.
[0096] like Figure 2 As shown, the image acquisition module includes a camera 1 (preferably an industrial camera) and a light source 2; the wafer defect intelligent recognition system includes a host computer 3; the positioning and registration module, the computation and processing module, and the convolutional neural network classifier are all located in the host computer 3.
[0097] The following is an explanation, through examples, of how the computational processing module calculates and marks defective pixels to better understand the invention: "Calculating the maximum value in each grayscale histogram" refers to calculating the maximum value (A) in the set (let's say set A) formed by the grayscale values of each pixel in the surface image of the wafer. max The maximum value in the set (let's call it set B) formed by the grayscale values of each pixel in the standard template image, and the grayscale values of each pixel in the standard template image. max The difference between the two (C = A) max –B max The grayscale value (A) of each pixel within the effective area of the wafer surface image. i Adding C gives us A' i ;A' i The grayscale value (B) at the position corresponding to the standard template image i If we make a comparison, and the difference is (Y=∣A') i –B i If | is greater than the set threshold, then A i The pixel within the effective area of the surface image of the wafer it represents is marked as a defect pixel.
[0098] Example 3
[0099] This embodiment provides a smart wafer defect recognition device, including:
[0100] A camera (preferably an industrial camera) is used to acquire images of the wafer surface;
[0101] A light source is used to illuminate the wafer placed within the field of view of the camera;
[0102] The host computer has a processor and a memory, wherein the memory stores a computer program, and the computer program, when executed by the processor, implements the method described in Embodiment 1.
[0103] The camera communicates with the host computer.
[0104] The system includes memory and processors, with at least one processor. Processors and memory can be configured separately or integrated together.
[0105] For example, memory may include random access memory, flash memory, read-only memory, programmable read-only memory, non-volatile memory, or registers. The processor may be a central processing unit (CPU), or a graphics processing unit (GPU). Memory can store executable instructions. The processor can execute the executable instructions stored in memory to implement the various processes described herein.
[0106] It is understood that the memory in this embodiment can be volatile memory or non-volatile memory, or may include both. The non-volatile memory can be ROM (Read-Only Memory), PROM (Programmable ROM), EPROM (Erasable PROM), EEPROM (Electrically Erasable EPROM), or flash memory. The volatile memory can be RAM (Random Access Memory), which is used as an external cache. By way of example, but not limitation, many forms of RAM are available, such as SRAM (Static RAM), DRAM (Dynamic RAM), SDRAM (Synchronous DRAM), DDR SDRAM (Double Data Rate SDRAM), ESDRAM (Enhanced SDRAM), SLDRAM (Synchlink DRAM), and DRRAM (Direct Rambus RAM). The memories described herein are intended to include, but are not limited to, these and any other suitable types of memory.
[0107] In some implementations, the memory stores elements such as upgrade packages, executable units, or data structures, or subsets thereof, or extended sets thereof: operating systems and applications.
[0108] The operating system includes various system programs, such as the framework layer, core library layer, and driver layer, used to implement various basic business functions and handle hardware-based tasks. The application programs include various applications used to implement various application functions. Programs implementing the methods of this invention can be included within these application programs.
[0109] In this embodiment of the invention, the processor executes the method steps provided in Embodiment 1 by calling programs or instructions stored in the memory, specifically programs or instructions stored in the application program.
[0110] Example 4
[0111] This embodiment provides a chip for executing the method in Embodiment 1. Specifically, the chip includes a processor for calling and running a computer program from a memory, causing a device equipped with the chip to execute the method in Embodiment 1.
[0112] Example 5
[0113] This embodiment provides a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, it implements the steps of the method of embodiment 1.
[0114] For example, machine-readable storage media can include, but are not limited to, various known and unknown types of non-volatile memory.
[0115] Example 6
[0116] This embodiment provides a computer program product, including computer program instructions that cause a computer to execute the method of embodiment 1.
[0117] Those skilled in the art will understand that the units and algorithm steps of the various examples described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or a combination of software and electronic hardware. Whether these functions are implemented in hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can implement the described functions in different ways for each specific application, but such implementation should not be considered beyond the scope of this application.
[0118] In the embodiments of this application, the disclosed systems, apparatuses, and methods can be implemented in other ways. For example, the division of units is merely a logical functional division, and other division methods may exist in actual implementation. For example, multiple units or components may be combined or integrated into another system. Furthermore, the coupling between the various units can be direct coupling or indirect coupling. Additionally, the functional units in the embodiments of this application can be integrated into a processing unit, or they can exist as separate physical entities, etc.
[0119] It should be understood that in the various embodiments of this application, the sequence number of each process does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.
[0120] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a machine-readable storage medium. Therefore, the technical solution of this application can be embodied in the form of a software product, which can be stored in a machine-readable storage medium. This software product may include several instructions to cause an electronic device to execute all or part of the processes of the technical solution described in the embodiments of this application. The aforementioned storage medium may include various media capable of storing program code, such as ROM, RAM, removable disk, hard disk, magnetic disk, or optical disk.
[0121] The above description is merely a specific embodiment of this application, and the scope of protection of this application is not limited thereto. Those skilled in the art can make changes or substitutions within the technical scope disclosed in this application, and all such changes or substitutions should be within the scope of protection of this application.
Claims
1. A method for intelligent identification of wafer defects, characterized in that, Includes the following steps: Obtain surface images of the wafer; The surface image of the wafer and the standard template image are positioned and registered; Calculate the grayscale histograms of the surface image of the wafer and the standard template image respectively, and calculate the maximum value in each grayscale histogram, and then calculate the difference between the two maximum values; The difference is added to the grayscale value of each pixel within the effective area of the surface image of the wafer, and compared with the grayscale value of the corresponding position in the standard template image. Pixels with a difference greater than a set threshold are marked as defective pixels. The area of the connected region of each defect is calculated based on the defect pixel to obtain the defect image; Each detected defect image is sequentially input into a convolutional neural network classifier to identify the category of each defect; the convolutional neural network classifier is a classification model obtained by training and validating an improved Faster R-CNN convolutional neural network. The product is graded based on the identified type and quantity of defects; The convolutional neural network classifier identifies the category of each defect, comprising the following steps: The input image is converted into a feature map using the ResNet-101 convolutional network. The region recommendation network selects the region of interest most likely to contain defects from a sliding window based on the feature map; The pooling layer extracts corresponding features from the feature map based on the region of interest to form a feature vector. The detection network determines the defect category based on the feature vector and performs boundary regression. The candidate defect region is filtered by a non-maximum suppression algorithm and a probability threshold to obtain the final defect region location and defect category.
2. The intelligent wafer defect identification method as described in claim 1, characterized in that, The set threshold is a grayscale value, ranging from 10 to 255.
3. A wafer defect intelligent identification system, characterized in that, Includes the following interconnecting units: The image acquisition module is used to acquire surface images of the wafer; The positioning and registration module is used for positioning and registration between the surface image of the wafer and the standard template image; The processing module is used to calculate the grayscale histogram of the wafer surface image and the grayscale histogram of the standard template image, and calculate the maximum value in each grayscale histogram, and then calculate the difference between the two maximum values; add the difference to the grayscale value of each pixel in the effective area of the wafer surface image, compare it with the grayscale value of the corresponding position in the standard template image, and mark pixels with a difference greater than a set threshold as defect pixels; calculate the area of the connected region of each defect based on the defect pixels to obtain a defect image; A convolutional neural network classifier is used to identify the category of each defect from defect images; the product is graded based on the identified defect category and quantity; the convolutional neural network classifier is a classification model obtained by training and validating an improved Faster R-CNN convolutional neural network. The convolutional neural network classifier identifies the category of each defect, comprising the following steps: The input image is converted into a feature map using the ResNet-101 convolutional network. The region recommendation network selects the region of interest most likely to contain defects from a sliding window based on the feature map; The pooling layer extracts corresponding features from the feature map based on the region of interest to form a feature vector. The detection network determines the defect category based on the feature vector and performs boundary regression. The candidate defect region is filtered by a non-maximum suppression algorithm and a probability threshold to obtain the final defect region location and defect category.
4. The intelligent wafer defect recognition system as described in claim 3, characterized in that, The set threshold is a grayscale value, ranging from 10 to 255.
5. The intelligent wafer defect recognition system as described in claim 3, characterized in that, The image acquisition module includes a camera and a light source; The intelligent wafer defect recognition system includes a host computer; the positioning and registration module, the computation and processing module, and the convolutional neural network classifier are all located in the host computer.
6. A smart wafer defect identification device, characterized in that, include: A camera used to capture images of the wafer surface; A light source is used to illuminate the wafer placed within the field of view of the camera; A host computer has a processor and a memory, wherein a computer program is stored in the memory, and the computer program, when executed by the processor, implements the method as described in claim 1 or 2. The camera communicates with the host computer.
7. A chip, characterized in that, include: A processor for retrieving and running a computer program from memory, causing a device on which the chip is mounted to perform the method as described in claim 1 or 2.
8. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the method as described in claim 1 or 2 above.