Driving method of display panel, display panel and display device

Abstract

The present disclosure provides a display panel driving method, a display panel and a display device, and belongs to the technical field of display. The display panel driving method can solve the problem of display panel that is prone to horizontal crosstalk and line residual image and other display defects. The display panel driving method comprises: judging whether the gray scale value difference of data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than a threshold value according to the data signals transmitted in the data line; n is a positive integer less than or equal to N; if the gray scale value difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than the threshold value, the phase of the clock signal input by the nth shift register is adjusted, so that the falling edge time of the pull-up node of the nth shift register is delayed to output the phase-delayed scanning signal.

Description

TECHNICAL FIELD

[0001] The present disclosure belongs to the technical field of display, and particularly relates to a driving method of a display panel, the display panel and a display device. BACKGROUND

[0002] With the continuous development of display technology, the development of display in recent years gradually presents a development trend of high integration and low cost. One of the very important technologies is the realization of mass production of the Gate Driver on Array (GOA) technology. The gate switch circuit composed of thin film transistors (TFT) is integrated on the array substrate of the display panel to form a scanning drive for the display panel by using the GOA technology, so that the gate drive integrated circuit part can be omitted. This not only can reduce the product cost from the aspects of material cost and manufacturing process, but also the display panel can be designed to be symmetrical on both sides and narrow frame.

[0003] The current development direction of large-size display products, such as TVs, is high resolution and high refresh rate. The high-end TV products have developed to 8K 120Hz, or even 8K 240Hz. However, in the display process of large-size display products, especially when the data signal is switched between high and low gray scales, horizontal crosstalk, line residual image and other display defects are prone to occur, which seriously affects the quality of large-size display products and reduces the yield of large-size display products. SUMMARY

[0004] The present disclosure aims to at least solve one of the technical problems existing in the prior art, and provides a driving method of a display panel, the display panel and a display device.

[0005] In a first aspect, the embodiments of the present disclosure provide a driving method of a display panel, the display panel comprising: N gate lines and M data lines arranged in a cross manner, and pixel units located in a region defined by the gate lines and the data lines; the display panel further comprising: N shift registers and P clock signal lines; each adjacent P shift registers in the N shift registers are connected to the P clock signal lines respectively; the signal output ends of the N shift registers are connected to the N gate lines one by one respectively; wherein P is an even number greater than or equal to 2; N is an integer greater than or equal to P; M is a positive integer; the driving method of the display panel comprises:

[0006] According to the data signal transmitted in the data line, it is judged whether the gray scale value difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than a threshold value; n is a positive integer less than or equal to N;

[0007] If the gray scale difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than a threshold value, the phase of the clock signal input by the nth shift register is adjusted, so that the falling edge time of the pull-up node of the nth shift register is delayed to output a phase-delayed scan signal.

[0008] Optionally, if the gray scale difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than a threshold value, the time interval between the data signal input by the nth row of pixel units and the falling edge time of the pull-up node of the nth shift register is greater than 1H, where 1H is the charging time of one row of pixel units.

[0009] Optionally, the adjusting of the phase of the clock signal input by the nth shift register comprises:

[0010] The non-working level maintenance time of the clock signal input by the nth shift register is extended.

[0011] Optionally, the non-working level maintenance time of the clock signal input by the nth shift register is extended by 1H to 2H compared with the non-working level maintenance time of a preset clock signal.

[0012] Optionally, the non-working level maintenance time of the clock signal input by the nth shift register is equal to the pre-charge maintenance time of the pull-up node.

[0013] Optionally, the adjusting of the phase of the clock signal input by the nth shift register comprises:

[0014] The working level maintenance time of the clock signal input by the nth shift register is extended.

[0015] Optionally, the working level maintenance time of the clock signal input by the nth shift register is extended by 1H to 2H compared with the working level maintenance time of a preset clock signal.

[0016] Optionally, the working level maintenance time of the clock signal input by the nth shift register is equal to the charging time of the pull-up node.

[0017] Optionally, the time of the data signal input by the nth row of pixel units overlaps with the charging time of the pull-up node, and the overlapping time is greater than or equal to 2H.

[0018] Optionally, the driving method of the display panel further comprises:

[0019] According to the data signal transmitted in the data line, it is judged whether the gray scale difference of the data signals input by the (n+m)th row of pixel units and the (n+m-1)th row of pixel units is greater than a threshold value; n+m is a positive integer less than or equal to N;

[0020] If the gray scale value difference of the data signals input by the (n+m)th row pixel unit and the (n+m-1)th row pixel unit is less than or equal to a threshold value, a clock signal of an initial phase is input to the (n+m)th shift register.

[0021] In a second aspect, the embodiments of the present disclosure provide a display panel, which comprises a detection module configured to detect whether a gray scale value difference of data signals input by an nth row pixel unit and an (n-1)th row pixel unit is greater than a threshold value; if the gray scale value difference of the data signals input by the nth row pixel unit and the (n-1)th row pixel unit is greater than the threshold value, a phase of a clock signal input by an nth shift register is adjusted, so that a falling edge time of a pull-up node of the nth shift register is delayed to output a phase-delayed scan signal.

[0022] Optionally, each of the N shift registers comprises an input sub-circuit, an output sub-circuit and a pull-up reset sub-circuit.

[0023] The input sub-circuit is configured to respond to an input signal of a signal input end and write the input signal to the pull-up node.

[0024] The output sub-circuit is configured to respond to a potential of the pull-up node and output a clock signal input by a clock signal end through a signal output end.

[0025] The pull-up reset sub-circuit is configured to respond to a pull-up reset signal input by a pull-up reset signal end and reset the potential of the pull-up node by a non-working level signal.

[0026] Optionally, a signal output end of an ith shift register is connected to a signal input end of an (i+p)th shift register; wherein P / 2≤p<N; i≤N-p.

[0027] A pull-up reset signal end of a jth shift register is connected to a signal output end of a (j+q)th shift register; 2≤q-p<N / 2; j≤N-q.

[0028] Optionally, the display panel further comprises a first frame-on signal line and a second frame-on signal line.

[0029] Signal input ends of odd rows in the first to N / 2th shift registers are all connected to the first frame-on signal line.

[0030] Signal input ends of even rows in the first to N / 2th shift registers are all connected to the second frame-on signal line.

[0031] In a third aspect, the embodiments of the present disclosure provide a display device, which comprises the display panel provided in the above aspects. BRIEF DESCRIPTION OF DRAWINGS

[0032] Figure 1 A timing diagram of scan signal, data signal and common electrode signal of a display panel for an example embodiment;

[0033] Figure 2 A structural diagram of a shift register provided by an example embodiment of the present disclosure;

[0034] Figure 3 A structural diagram of a starting portion row in a gate driving circuit provided by an example embodiment of the present disclosure;

[0035] Figure 4 A structural diagram of multiple redundant shift registers in a gate driving circuit provided by an example embodiment of the present disclosure;

[0036] Figure 5 A timing diagram of input signals of a display panel containing 12 clock signal lines provided by an example embodiment of the present disclosure;

[0037] Figure 6 Another timing diagram of input signals of a display panel containing 12 clock signal lines provided by an example embodiment of the present disclosure;

[0038] Figure 7 A timing diagram of scan signal, data signal and common electrode signal of a display panel containing 12 clock signal lines provided by an example embodiment of the present disclosure;

[0039] Figure 8 A timing diagram of input signals of a display panel containing 6 clock signal lines provided by an example embodiment of the present disclosure;

[0040] Figure 9 Still another timing diagram of input signals of a display panel containing 12 clock signal lines provided by an example embodiment of the present disclosure;

[0041] Figure 10 Yet another timing diagram of input signals of a display panel containing 12 clock signal lines provided by an example embodiment of the present disclosure;

[0042] Figure 11 Another timing diagram of scan signal, data signal and common electrode signal of a display panel containing 12 clock signal lines provided by an example embodiment of the present disclosure;

[0043] Figure 12 Still another timing diagram of input signals of a display panel containing 6 clock signal lines provided by an example embodiment of the present disclosure;

[0044] Figure 13 A structural diagram of a display panel provided by an example embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0046] Unless otherwise defined, the technical or scientific terms used in this disclosure shall have the ordinary meaning understood by one of ordinary skill in the art to which this disclosure pertains. The terms “first,” “second,” and similar terms used in this disclosure do not indicate any order, quantity, or importance, but are merely used to distinguish different components. Similarly, the terms “an,” “a,” or “the,” and similar terms do not indicate a quantity limitation, but rather indicate the presence of at least one. The terms “including,” “comprising,” or “containing,” and similar terms mean that the element or object preceding the word encompasses the elements or objects listed following the word and their equivalents, without excluding other elements or objects. The terms “connected,” “linked,” or similar terms are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. The terms “upper,” “lower,” “left,” and “right,” etc., are used only to indicate relative positional relationships, and these relative positional relationships may change accordingly when the absolute position of the described objects changes.

[0047] Figure 1 A timing diagram of the scan signal and data signal of an exemplary display panel, such as... Figure 1 As shown, when the data signal Data undergoes a grayscale transition, for example, switching from L63 to L0, or from L127 to L255, or from L0 to L255, the switching of the data signal Data can easily cause the common electrode signal Vcom in the display panel to be pulled due to capacitive coupling. This causes fluctuations in the common electrode signal Vcom. When the scan signal Gate is turned off, the common electrode signal Vcom does not return to its original state, resulting in a difference between the common electrode signal Vcom corresponding to the pixel unit in that row and the common electrode signal Vcom at other locations, leading to display defects such as horizontal crosstalk. On the other hand, when the data signal Data changes, the pixel units in that row may not be pre-charged or may undergo reverse pre-charge, resulting in a lower charging rate for the pixel units in that row, which can easily lead to display defects such as line retention.

[0048] To at least solve one of the above-mentioned technical problems, this disclosure provides a driving method for a display panel, a display panel, and a display device. The driving method for a display panel, the display panel, and the display device provided in this disclosure will be described in further detail below with reference to the accompanying drawings and specific embodiments.

[0049] It should be noted that the transistor used in the embodiments of the present disclosure can be a thin film transistor or a field effect transistor or other devices with the same characteristics. Since the source and drain of the transistor used are symmetrical, the source and drain are not distinguished. In the embodiments of the present disclosure, one of the poles is referred to as the first pole, the other pole is referred to as the second pole, and the gate is referred to as the control pole. In addition, according to the characteristics of the transistor, the transistor can be divided into N-type and P-type. The following embodiments are described by taking the N-type transistor as an example. When the N-type transistor is used, the first pole is the source of the N-type transistor, the second pole is the drain of the N-type transistor, and the gate is input with a high level. The source and drain are turned on, and the P-type is opposite. It is conceivable that the P-type transistor can be easily thought of by those skilled in the art without creative labor, and therefore it is also within the protection scope of the embodiments of the present disclosure.

[0050] In the embodiments of the present disclosure, since the transistor used is an N-type transistor, the working level signal in the embodiments of the present disclosure refers to a high level signal, and the non-working level signal is a low level signal. The working level end is a high level signal end, and the non-working level end is a low level signal end.

[0051] Generally, the display panel includes a plurality of gate lines and a plurality of data lines. The gate lines and the data lines are arranged in a cross manner to define a plurality of pixel regions. Each pixel region is provided with a pixel unit. Taking the extension direction of each gate line as the row direction and the extension direction of each data line as the column direction as an example, the structure of the display panel is described. When driving the display panel to display, a scanning signal can be written into the gate line line by line according to the to-be-displayed picture, and a data signal is written into each data line at the same time, so that the pixel units in the display panel are lit line by line.

[0052] The gate driving signal is provided by the gate driving circuit, and the data signal is provided by the source driving circuit. In the related art, the gate driving circuit can be integrated in a gate driving chip, and the source driving circuit can be integrated in a source driving chip. At present, in order to reduce the number of chips and realize a narrow frame or no frame, a Gate On Array (GOA) technology is provided. The gate driving circuit includes a plurality of cascaded shift registers integrated on the array substrate. Each shift register is connected to a gate line in one-to-one correspondence, and is configured to provide a scanning signal for the gate line connected thereto.

[0053] In order to more clearly illustrate how the shift register realizes the output of the scanning signal, the following describes a specific example of the shift register.

[0054] Figure 2 A structure diagram of a shift register provided by the embodiments of the present disclosure is shown in FIG. 1. Figure 2As shown, the shift register comprises: an input sub-circuit, an output sub-circuit, and a pull-up reset sub-circuit; wherein the input sub-circuit is configured to respond to an input signal input by a signal input end INPUT and write the input signal to a pull-up node PU to charge the pull-up node PU; the output sub-circuit is configured to respond to a potential of the pull-up node PU and output a clock signal input by a clock signal end CLK through a signal output end OUTPUT; and the pull-up reset sub-circuit is configured to respond to a pull-up reset signal output by a pull-up reset signal end RESET_PU and reset the potential of the pull-up node PU through a low-level signal.

[0055] Specifically, as shown in the figure, Figure 2 the input sub-circuit comprises a first transistor M1; the pull-up reset sub-circuit comprises a second transistor M2; and the output sub-circuit comprises a third transistor M3 and a storage capacitor C; wherein a gate and a source of the first transistor M1 are connected to the signal input end INPUT, and a drain thereof is connected to the pull-up node PU; a gate of the second transistor M2 is connected to the pull-up reset signal end RESET_PU, a source thereof is connected to the pull-up node PU, and a drain thereof is connected to a low-level signal end VGL; a gate of the third transistor M3 is connected to the pull-up node PU, a source thereof is connected to the clock signal end CLK, and a drain thereof is connected to the signal output end OUTPUT; and a first end of the storage capacitor C is connected to the pull-up node PU, and a second end thereof is connected to the signal output end OUTPUT.

[0056] It should be noted that after the pull-up node PU is reset in the reset phase, the pull-up node PU is at a low level, at this time the third transistor M3 is turned off, and the signal output end OUTPUT no longer outputs, so as to complete the reset of the signal output end OUTPUT.

[0057] As shown in the figure, Figure 2 the shift register further comprises: a first pull-down control sub-circuit, a second pull-down control sub-circuit, a first pull-down sub-circuit, a second pull-down sub-circuit, a first noise reduction sub-circuit, a second noise reduction sub-circuit, a discharge sub-circuit, a first auxiliary sub-circuit, a second auxiliary sub-circuit, and a cascading sub-circuit. The discharge sub-circuit responds to a frame start signal input by a frame start signal end STV and discharges the pull-up node PU through a low-level signal input by a low-level signal end VGL; the first pull-down control sub-circuit and the second pull-down control sub-circuit are the same in structure and function, and only work at different times; similarly, the first pull-down sub-circuit and the second pull-down sub-circuit are the same in structure and function; the first auxiliary sub-circuit and the second auxiliary sub-circuit are the same in structure and function; and the first noise reduction sub-circuit and the second noise reduction sub-circuit are the same in structure and function. The input sub-circuit, the output sub-circuit, and the pull-up reset sub-circuit are the same in structure and function, and thus are not repeated here.

[0058] The first auxiliary sub-circuit and the second auxiliary sub-circuit are configured to respond to an input signal input by the signal input terminal INPUT, and respectively pull down the potential of the first pull-down node PD1 and the potential of the second pull-down node PD2 by a low-level signal; the first pull-down control sub-circuit is configured to respond to a first power voltage input by the first power voltage signal terminal VDDO, to control the potential of the first pull-down node PD1; the second pull-down control sub-circuit is configured to respond to a second power voltage input by the second power voltage signal terminal VDDE, to control the potential of the second pull-down node PD2; the first pull-down sub-circuit is configured to respond to the potential of the pull-up node PU, and pull down the potential of the first pull-down node PD1 and the first pull-down control node PD CN1 by a low-level signal input by the low-level signal terminal VGL; the second pull-down sub-circuit is configured to respond to the potential of the pull-up node PU, and pull down the potential of the second pull-down node PD2 and the second pull-down control node PD CN2 by a low-level signal input by the low-level signal terminal VGL; the first noise reduction sub-circuit is configured to respond to the potential of the first pull-down node PD1, and reduce noise of a signal output by the signal output terminal OUTPUT and the pull-up node PU by a low-level signal input by the low-level signal terminal VGL. The cascade sub-circuit is configured to respond to the potential of the pull-up node PU, and output a clock signal input by the clock signal terminal CLK to other shift registers in cascade through the cascade signal output terminal OUT C.

[0059] It should be noted that the signals output by the cascade signal output terminal OUT C and the signal output terminal OUTPUT are the same, except that two output terminals are provided in the shift register unit, one is the signal output terminal OUTPUT connected with the gate line, and the other is the cascade signal output terminal OUT C for cascade. The reason for separately providing the cascade sub-circuit is to reduce the load of the signal output terminal OUTPUT, so as to avoid affecting the scanning signal output by the signal output terminal OUTPUT.

[0060] Specifically, as shown in FIG. 1, the shift register unit comprises a first auxiliary sub-circuit 10, a second auxiliary sub-circuit 20, a first pull-down control sub-circuit 30, a second pull-down control sub-circuit 40, a first pull-down sub-circuit 50, a second pull-down sub-circuit 60, a first noise reduction sub-circuit 70, a pull-up node PU, a signal output terminal OUTPUT, a low-level signal terminal VGL, a first pull-down node PD1, a first pull-down control node PD CN1, a second pull-down node PD2, a second pull-down control node PD CN2, a clock signal terminal CLK, and a cascade signal output terminal OUT C. Figure 2As shown, the first pull-down control sub-circuit and the second pull-down control sub-circuit each include a fifth transistor and a ninth transistor; wherein the fifth transistor in the first pull-down control sub-circuit and the second pull-down control sub-circuit are denoted as M5 and M5' respectively, and the ninth transistor are denoted as M9 and M9' respectively. The first pull-down sub-circuit and the second pull-down sub-circuit each include a sixth transistor and an eighth transistor; wherein the sixth transistor in the first pull-down sub-circuit and the second pull-down sub-circuit are denoted as M6 and M6' respectively, and the eighth transistor are denoted as M8 and M8' respectively. The first noise reduction sub-circuit and the second noise reduction sub-circuit each include a tenth transistor, an eleventh transistor and a twelfth transistor; wherein the tenth transistor in the first noise reduction sub-circuit and the second noise reduction sub-circuit are denoted as M10 and M10' respectively, and the eleventh transistor are denoted as M11 and M11' respectively; the discharge sub-circuit includes a seventh transistor M7. The first auxiliary sub-circuit and the second auxiliary sub-circuit each include a sixteenth transistor, denoted as M16 and M16' respectively.

[0061] The gate and source of the fifth transistor M5 are connected with the first power voltage terminal VDDO, and the drain is connected with the first pull-down control node PD CN1; the gate of the ninth transistor M9 is connected with the first pull-down control node PD CN1, the source is connected with the first power voltage terminal VDDO, and the drain is connected with the first pull-down node PD1; the gate and source of the fifth transistor M5' are connected with the second power voltage terminal VDDE, and the drain is connected with the second pull-down control node PD CN2; the gate of the ninth transistor M9' is connected with the second pull-down control node PD CN2, the source is connected with the second power voltage terminal, and the drain is connected with the first pull-down node PD1; the gate of the sixth transistor M6 is connected with the pull-up node PU, the source is connected with the first pull-down node PD1, and the drain is connected with the low-level signal terminal; the gate of the eighth transistor M8 is connected with the pull-up node PU, the source is connected with the first pull-down control node PD CN1, and the drain is connected with the low-level signal terminal VGL; the gate of the sixth transistor M6' is connected with the pull-up node PU, the source is connected with the second pull-down node PD2, and the drain is connected with the low-level signal terminal VGL; the gate of the eighth transistor M8' is connected with the pull-up node PU, the source is connected with the second pull-down control node PD CN2, and the drain is connected with the low-level signal terminal; the gate of the tenth transistor M10 is connected with the first pull-down node PD1, the source is connected with the pull-up node PU, and the drain is connected with the low-level signal terminal VGL; the gate of the eleventh transistor M11 is connected with the first pull-down node PD1, the source is connected with the signal output terminal OUTPUT, and the drain is connected with the low-level signal terminal VGL; the gate of the tenth transistor M10' is connected with the second pull-down node PD2, the source is connected with the pull-up node PU, and the drain is connected with the low-level signal terminal VGL; the gate of the eleventh transistor M11' is connected with the second pull-down node PD2, the source is connected with the signal output terminal OUTPUT, and the drain is connected with the low-level signal terminal; the gate of the seventh transistor M7 is connected with the frame opening signal terminal STV, the source is connected with the pull-up node PU, and the drain is connected with the low-level signal terminal VGL; the gate of the thirteenth transistor M13 is connected with the pull-up node PU, the source is connected with the clock signal terminal CLK, and the drain is connected with the cascade signal output terminal OUT C. The gate of the sixteenth transistor M16 is connected with the signal input terminal INPUT, the source is connected with the first pull-down node PD1, and the drain is connected with the low-level signal terminal. The gate of the sixteenth transistor M16' is connected with the signal input terminal INPUT, the source is connected with the second pull-down node PD2, and the drain is connected with the low-level signal terminal VGL.

[0062] The fifth transistor M5 and the ninth transistor M9 constitute a first pull-down control sub-circuit, and the fifth transistor M5' and the ninth transistor M9' constitute a second pull-down control sub-circuit, which work in time division (i.e. alternately). Correspondingly, the first noise reduction sub-circuit composed of the tenth transistor M10 and the eleventh transistor M11 and the second noise reduction sub-circuit composed of the tenth transistor M10' and the eleventh transistor M11' are controlled by the first pull-down control sub-circuit and the second pull-down control sub-circuit respectively, so the first noise reduction sub-circuit and the second noise reduction sub-circuit also work in time division. The working principle of the first pull-down control sub-circuit and the second pull-down control sub-circuit is the same, and the working principle of the first noise reduction sub-circuit and the second noise reduction sub-circuit is the same. Therefore, the working principle of the shift register is described below when the first pull-down control sub-circuit and the first noise reduction sub-circuit work. It should be noted that, Figure 2 In the circuit structure shown, the part of the low-level signal end VGL can also be represented as LVGL, which can provide a signal with a lower potential of the low-level signal end VGL, and can more fully pull down the potential of the corresponding point.

[0063] In the discharge phase, i.e. before display, a high-level signal is input to the frame start signal end STV, the seventh transistor M7 is turned on, and the low-level signal input by the low-level signal end VGL is used to discharge the pull-up node PU, so as to prevent the residual charge of the pull-up node PU from causing display abnormalities.

[0064] In the input phase, a high-level signal is written to the signal input end INPUT, the first transistor M1 is turned on, the potential of the pull-up node PU is pulled up by the high-level signal, and the storage capacitor C is charged.

[0065] In the output phase, since the potential of the pull-up node PU is pulled up in the input phase, the third transistor M3 is turned on, and the high-level signal input by the clock signal end CLK is output to the gate line connected with the shift register through the signal output end OUTPUT.

[0066] In the reset phase, a high-level signal is input to the pull-up reset signal end RESET_PU, the second transistor M2 is turned on, and the low-level signal input by the low-level signal end VGL is used to pull down the potential of the pull-up node PU, so as to reset the pull-up node PU. Since the pull-up node PU is pulled down, the third transistor M3 is turned off, and the signal output end OUTPUT and the cascade signal output end OUT_C no longer output high-level signals. At the same time, the first pull-down control node PD_CN1 and the pull-down node are high-level signals, the tenth transistor M10 and the eleventh transistor M11 are turned on, and the output of the pull-up node PU, the signal output end OUTPUT and the cascade signal output end OUT_C are noise reduced, until the potential of the pull-up node PU is pulled up at the beginning of the next frame scanning.

[0067] AsFigure 2 As shown in the figure, in order to reduce the load of the signal output end OUTPUT, the signal output by the signal output end OUTPUT is only used to control the gating and turning off of the gate line, and a cascade sub-circuit is further arranged in the shift register; the cascade sub-circuit responds to the potential of the pull-up node PU and outputs the clock signal input by the clock signal end CLK through the cascade signal output end OUT_C. The cascade signal output end OUT_C is the same as the signal output by the signal output end OUTPUT, that is, a high-level signal is output to the pull-up reset signal end RESET_PU of other shift registers in cascade and the signal input end INPUT of other shift registers in cascade. The cascade sub-circuit includes a thirteenth transistor M13, the gate of the thirteenth transistor M13 is connected with the pull-up node PU, the source is connected with the clock signal end CLK, and the drain is connected with the cascade signal output end OUT_C. At the same time, the twelfth transistor is further arranged in the first noise reduction sub-circuit and the second noise reduction sub-circuit, which are represented by M12 and M12', respectively, for noise reduction of the signal output by the cascade signal output end OUT_C. The gate of the twelfth transistor M12 is connected with the first pull-down node PD1, the source is connected with the cascade signal output end OUT_C, and the drain is connected with the low-level signal end; the gate of the twelfth transistor M12' is connected with the second pull-down node PD2, the source is connected with the cascade signal output end OUT_C, and the drain is connected with the low-level signal end VGL.

[0068] Figure 3 A structure diagram of a starting part row in a gate drive circuit provided by the embodiment of the present disclosure is shown in the figure, and the gate drive circuit includes N shift registers and P clock signal lines. Figure 3 As shown in the figure, the N shift registers are connected with the P clock signal lines respectively, the signal output ends of the N shift registers are connected with the N gate lines respectively, P is an even number greater than or equal to 6, N is an integer greater than or equal to P, and M is a positive integer.

[0069] In the embodiment of the present disclosure, the number of clock signal lines is taken as 12 as an example, the duty cycle of the clock signal input in each clock signal line can be 1 / 12 to 1 / 2, that is, the high-level maintenance time of the clock signal is 1H to 6H, and the duty cycle of the clock signal is taken as 1 / 2 as an example in the embodiment of the present disclosure. For an 8K / 120Hz display panel, the 1H time is 1.85 microseconds (μs). It can be understood that the number of clock signal lines in the gate drive circuit provided by the embodiment of the present disclosure can also be 4, 6, 8, 10, 14, 16 and other numbers, which can be set according to actual needs.

[0070] In some embodiments, the signal output end of the i-th shift register is connected to the signal input end of the i+p-th shift register; wherein P / 2≤p<N; i≤N-p; the pull-up reset signal end of the j-th shift register is connected to the signal output end of the j+q-th shift register; 2≤q-p<N / 2; j≤N-q.

[0071] In the embodiments of the present disclosure, the value of p is 6 and the value of q is 8, for example, the signal output end OUTPUT of the first shift register is connected to the input end INPUT of the seventh shift register, the signal output end OUTPUT of the second shift register is connected to the input end INPUT of the eighth shift register, and the pull-up reset signal end RESET_PU of the ninth shift register is connected to the signal output end OUTPUT of the first shift register, the pull-up reset signal end RESET_PU of the tenth shift register is connected to the signal output end OUTPUT of the second shift register, and so on, to form the entire gate drive circuit. In this way, the pull-up reset signal end RESET_PU of the first shift register can be delayed by 2H to be written into a high-level signal, that is, the potential of the pull-up node PU can be delayed by 2H to be pulled down, so that the output sub-circuit of the first shift register can work for 2H, and the low-level signal written by the clock signal line can discharge the signal output end OUTPUT, thereby alleviating the tailing phenomenon of the falling edge of the signal output end OUTPUT.

[0072] It should be noted that in the embodiments of the present disclosure, q-p≥2, at this time, the potential of the pull-up node PU of each shift register can be at least delayed by 2H to be pulled down, of course, the relationship between q and p also needs to satisfy q-p<N / 2, in this way, the potential of the pull-up node PU is avoided from being reset when the next frame signal is written into a high level.

[0073] In some embodiments, the display panel further comprises: a first frame start signal line and a second frame start signal line; the signal input ends of the odd rows in the first shift register to the N / 2-th shift register are all connected to the first frame start signal line; and the signal input ends of the even rows in the first shift register to the N / 2-th shift register are all connected to the second frame start signal line.

[0074] The first frame start signal line STV1 can provide frame start signals for the signal input ends INPUT of the odd-numbered rows in the first to N / 2th shift registers, and the second frame start signal line STV2 can provide frame start signals for the signal input ends INPUT of the even-numbered rows in the first to N / 2th shift registers, so that the gate driving circuit can normally work. It should be noted that the first frame start signal line STV1 and the second frame start signal line STV2 have the same function, and they can work in time division (i.e., work in turns) to reduce the load of one of them, so as to avoid affecting the frame start signals output by the signal input ends INPUT. On the other hand, the first frame start signal line STV1 and the second frame start signal line STV2 can also input high-level signals to the frame start signal ends STV in the gate driving circuit before display, so that the corresponding transistors are turned on, the pull-up nodes PU are discharged by low-level signals, and the residual charges of the pull-up nodes PU are prevented from causing display abnormalities.

[0075] In order to ensure the normal work of the last plurality of shift registers in the display panel, a plurality of redundant shift registers are also needed to be arranged in the display panel in the embodiment of the present disclosure. In the embodiment of the present disclosure, the function of the redundant registers is only to provide cascade signals for the last plurality of shift registers, and the output signals of the redundant registers are not connected to the gate lines of the display panel. Figure 4 A structure diagram of a plurality of redundant shift registers in a gate driving circuit provided by the embodiment of the present disclosure is shown in FIG. 6. Figure 4 In the embodiment of the present disclosure, 12 redundant shift registers are taken as an example for description, the clock signal ends CLK of the 12 redundant shift registers are respectively connected to 12 clock signals, and the pull-up reset signal ends RESET_PU of the 12 redundant shift registers are all connected to the third frame start signal line STV0. The signal output ends OUTPUT of the first to sixth redundant shift registers are respectively connected to the pull-up reset signal ends RESET_PU of the N-5th to Nth shift registers, and the signal output ends OUTPUT of the seventh to twelfth redundant shift registers are respectively connected to the pull-up reset signal ends RESET_PU of the first to sixth redundant shift registers. The third frame start signal line can reset the potentials of the pull-up nodes PU of the 12 redundant shift registers, and the cascade output signals output by the signal output ends OUTPUT of the first to sixth redundant shift registers can reset the pull-up nodes PU of the last six shift registers in the N shift registers, and the cascade output signals output by the signal output ends OUTPUT of the seventh to twelfth redundant shift registers can reset the pull-up nodes PU of the first to sixth redundant shift registers, so as to ensure the normal operation of the gate driving circuit.

[0076] The embodiment of the present disclosure also provides a driving method of a display panel, which comprises the following steps:

[0077] In step S101, according to the data signal transmitted in the data line, it is judged whether the gray scale value difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than a threshold value; n is a positive integer less than or equal to N.

[0078] If the gray scale difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than the threshold value, step S102 is executed. In step S102, the phase of the clock signal input by the nth shift register is adjusted, so that the falling edge time of the pull-up node of the nth shift register is delayed, to output a phase-delayed scanning signal.

[0079] It is to be noted that the threshold value involved in the embodiments of the present disclosure is a preset value of the difference between the data signals input by adjacent two rows, and the threshold value is greater, which indicates that the data signals input by adjacent two rows of pixel units are suddenly changed, and in the display picture, the luminance of the pixel units of adjacent two rows is greatly different. Specifically, the threshold value can be set to 63, 128 or 255, etc. For example, the data signal is switched from L63 to L0, or from L127 to L255, or from L0 to L255, etc. which can be considered as high and low gray scale switching of the data signal, and the size of the threshold value can be reasonably set according to actual needs. In actual application, the phase of the clock signal input by the nth shift register can be adjusted by extending the low level maintaining time of the clock signal input by the nth shift register by 1H to 2H, or by extending the high level maintaining time of the clock signal input by the nth shift register by 1H to 2H. In the embodiments of the present disclosure, the low level maintaining time of the clock signal input by the nth shift register is extended by 1H and the high level maintaining time of the clock signal input by the nth shift register is extended by 1H as an example.

[0080] The timing of the signals input by the display panel will be described in detail below, Figure 5 A timing diagram of the signals input by the display panel provided by the embodiments of the present disclosure containing 12 clock signal lines is shown in FIG. 1. Figure 5As shown, taking the working timing of the Gn row GOA corresponding to CLK7 as an example. In the input stage, the timing controller monitors that the data signal line inputs the data signal of the 7th row pixel unit to have high-low gray level switching, or the 6th and 7th rows have high-low gray level switching, and can adjust the timing of the clock signal in the clock signal line CLK7 connected to the 7th shift register, so that the low level of the clock signal in CLK7 is extended from the original 6H to 7H, and the low level of the clock signal in CLK6 is more than 1H, the output signal of the signal output end OUTPUT of the 1st shift register is input to the signal input end INPUT as the input signal of the shift register, at this time the first transistor M1 is opened, the pull-up node PU is pre-charged, the low level of the clock signal input by the 7th shift register is equal to the pre-charging time of the pull-up node PU, the potential of the pull-up node PU is lifted, the third transistor M13 and the thirteenth transistor M13 are opened, because the clock signal of the shift register in the row is low, therefore the output of the scan signal of the signal output end OUTPUT still maintains low potential, the low level is more than 1H, but the timing of the data signal is unchanged, the potential of the pull-up node PU is raised at the same time, the sixth transistor M6 and the eighth transistor M8 are opened, and the potential of the pull-down node PD is pulled down.

[0081] In the output stage, the high level of the pull-up node PU opens the third transistor M3, at this time the clock signal is high, the potential of the signal output end OUTPUT is raised, the scan signal is output, and at the same time, due to the capacitor bootstrap effect, the potential of the pull-up node PU continues to rise; the sixth transistor M6 and the eighth transistor M8 remain open, the potential of the pull-down node PD maintains low level and the low level maintains time more than 1H, the timing of the scan signal of the 7th row is delayed 1H relative to the data signal, so that the pixel unit of the 7th row has 1H more pre-charging time, or as Figure 6 shown, wherein the potential of the pull-down node PD maintains low level and the low level maintains time more than 2H, the timing of the scan signal of the 7th row is delayed 2H relative to the data signal, so that the 7th row has 2H more pre-charging time, after the data signal is switched, for example, the time of the data signal switched to L255 and the timing of the Gn output signal overlap more than or equal to 2H, so that the pixel unit of the row has more than or equal to 1H pre-charging time than the pixel unit of other rows, when the real signal is input, the pixel unit is at a higher potential, so that the charging rate of the row can be improved, and display defects such as line ghosting can be avoided.

[0082] It should be noted that the potential change of the pull-up node PUn of the nth shift register, i.e. the pull-up node PU of the 7th shift register, can be divided into three stages, as Figure 5 and Figure 6As shown, in the pre-charge phase of the pull-up node PU in the low level maintaining phase, the potential of the pull-up node PU is pulled up for the first time due to the high level signal input from the input signal terminal INPUT. In the pre-charge phase of the pull-up node PU in the high level maintaining phase, the potential of the pull-up node PU is pulled up for the second time due to the bootstrap effect of the capacitor. In the charging phase of the pull-up node PU in the high level maintaining phase, the potential of the pull-up node PU is pulled down but still maintains a high level for a certain time due to the storage effect of the capacitor. In the discharging phase of the pull-up node in the high level maintaining phase. In the embodiment of the present disclosure, the falling edge time of the pull-up node PU can be the time when the potential of the pull-up node PU starts to be pulled down in the charging phase of the pull-up node PU, for example, the time when the first time step ends as shown in Figure 5 and Figure 6 the second time step ends as shown in

[0083] On the other hand, as shown in Figure 7 , the falling edge time of the pull-up node PU in the 7th shift register is delayed by 1H, so that the high level maintaining time of the corresponding scan signal is also delayed by 1H, which is equivalent to that the pulling of the common electrode signal is advanced due to the high-low gray scale switching of the data signal, that is, the interval between the time of the high-low switching of the data signal and the end time of the scan signal is at least 1H, and the interval time is far away, which avoids the influence of the fluctuation of the common electrode signal on the charging of the pixel units in this row, so that the horizontal direction crosstalk and other display defects can be avoided.

[0084] Figure 8 A timing diagram of the input signals of the display panel provided by the embodiment of the present disclosure containing 6 clock signal lines is shown in Figure 8 , the number of clock signal lines of the display panel is 6, and the high-low gray scale switching of the data signal input by the 4th row of pixel units is taken as an example. It can be seen that the timing of the scan signal of the 4th row is delayed by 1H relative to the data signal, so that the pixel units of the 4th row have an additional 1H pre-charge time. After the high-low switching of the data signal, for example, the time when the data signal is switched to L255 and the Gn output signal overlap in time sequence for more than or equal to 2H, so that the pixel units in this row have more than or equal to 1H pre-charge time than the pixel units in other rows. When the real signal is input, the pixel units are already at a higher potential, so that the charging rate of this row can be improved, and display defects such as line ghosting can be avoided.

[0085] Figure 9 Another timing diagram of the input signals of the display panel containing 12 clock signal lines provided by the embodiment of the present disclosure is shown in Figure 9As shown, taking the working timing of the Gn row GOA corresponding to CLK7 as an example. In the input stage, the timing controller monitors that the data signal line inputs the data signal of the 7th row pixel unit to switch the high and low gray scale, can adjust the timing of the clock signal in the clock signal line CLK7 connected with the 7th shift register, so that the high level of the clock signal in CLK7 is prolonged from the original 6H to 7H, the output signal of the signal output end OUTPUT of the 1st shift register is input to the signal input end INPUT as the input signal of the shift register at this level, at this time, the first transistor M1 is opened, the pull-up node PU is pre-charged, the pull-up node PU potential is lifted, and at the same time, due to the capacitor bootstrap effect, the pull-up node PU potential continues to rise, the third transistor M13 and the thirteenth transistor M13 are opened, the pull-up node PU is charged, and the high level of the clock signal input by the 7th shift register is maintained for the same time as the charging time of the pull-up node PU. Because the clock signal of the shift register at this row is low, the output of the scan signal of the signal output end OUTPUT still maintains low potential, and the pull-up node PU potential rises at the same time to open the sixth transistor M6 and the eighth transistor M8, and the potential of the pull-down node PD is pulled down.

[0086] In the output stage, the high level of the pull-up node PU opens the third transistor M3, at this time, the clock signal is high, the potential of the signal output end OUTPUT rises, and the scan signal is output, and at the same time, due to the capacitor bootstrap effect, the potential of the pull-up node PU continues to rise, at this time, because the high level of the clock signal in CLK7 is maintained for 1H longer, the bootstrap time of its capacitor is also 1H longer; the sixth transistor M6 and the eighth transistor M8 still remain open, the potential of the pull-down node PD maintains low level, and because the bootstrap time of the capacitor is 1H longer, the charging time of the pull-up node PU is 1H longer, accordingly, the high level time of the scan signal Gn of this row is 1H longer, so that the opening time of the driving transistor in the 7th row pixel unit is 1H longer, or as shown in the figure, the bootstrap time of the capacitor is 2H longer, the charging time of the pull-up node PU is 2H longer, accordingly, the high level time of the scan signal Gn of this row is also 2H longer, after the high and low switching of the data signal, for example, the time of the data signal switching to L255 and the output signal of Gn overlap in timing for greater than or equal to 2H, so that the charging time of the pixel unit of this row is greater than or equal to 1H longer than that of other rows, so that the charging rate of this row can be improved, and display defects such as line residual image can be avoided. Figure 10

[0087] On the other hand, as shown in the figure, Figure 11 ​As shown, due to the falling edge time delay of 2H of the pull-up node PU in the 7th shift register, the high level maintenance time of the corresponding scan signal is also delayed by 2H, which is equivalent to that the pull-up of the common electrode signal is advanced due to the high-low gray level switching of the data signal, that is, the time interval between the high-low switching of the data signal and the end time of the scan signal is at least 2H, the interval time is far away, the fluctuation of the common electrode signal is avoided to affect the charging of the pixel units in the row, so that the horizontal direction crosstalk and other display defects can be avoided.

[0088] Figure 12 Another timing diagram of input signals of the display panel provided by the embodiment of the present disclosure contains 6 clock signal lines, in Figure 12 The number of clock signal lines of the display panel is 6, and the high-low gray level switching of the data signal input by the 4th row of pixel units is taken as an example. It can be seen that due to the self-boosting time of the capacitor being 1H, the charging time of the pull-up node PU is 1H, and correspondingly, the high level time of the scan signal Gn of the 4th row is 1H. Thus, the opening time of the driving transistor in the pixel units of the 4th row is 1H more than that of other rows. After the high-low switching of the data signal, for example, the time of the data signal switched to L255 and the output signal of Gn overlap in time sequence by more than or equal to 2H, so that the pixel units in the row have more charging time than the pixel units in other rows by more than or equal to 1H, so that the charging rate of the row can be improved, and display defects such as line ghosting can be avoided.

[0089] In some embodiments, the driving method of the display panel further includes the following steps:

[0090] In step S103, according to the data signal transmitted in the data line, it is judged whether the gray level value difference of the data signals input by the nth+m row of pixel units and the nth+m-1 row of pixel units is greater than a threshold value; n+m is a positive integer less than or equal to N.

[0091] If the gray level value difference of the data signals input by the nth+m row of pixel units and the nth+m-1 row of pixel units is less than or equal to the threshold value, then step S104 is executed. In step S104, the initial phase clock signal is input to the nth+m shift register.

[0092] After the high-low gray level switching, it can be continued to detect whether the data signal input by the pixel units of the adjacent rows is switched in high-low gray level. If the high-low gray level switching of the data signal does not occur, the clock signal line can be input with the initial phase clock signal until the next high-low switching of the data signal is detected to adjust the timing, so as to avoid the disorder of the clock signal, cause the wrong charging, and affect the display effect of the display picture. In addition, for example, the shift register with 12 clock signals as a group is selected. If the high-low gray level switching of the sixth and seventh row signals is detected, the timing of the clock signal of the seventh row can be adjusted, and then the timing of the clock signal of the previous six rows is consistent. Here, the consistency refers to the consistency of the high level time and the low level time of the clock signal (6H high level and 6H low level). Then, from the seventh row to the twelfth row, the clock signal is adjusted in timing. When the first row is scanned again, the first row to the twelfth row are restored to the timing before the high-low switching without adjusting the timing (6H high level and 6H low level). Of course, for example, the high-low gray level switching of the sixth and seventh rows can be detected, and the timing of the clock signal of the seventh row can be adjusted. If no high-low gray level switching of the adjacent rows is detected, for example, when the ninth row is scanned, the clock signal of the seventh row can be restored to the initial timing (6H high level and 6H low level). The recovery time can be set according to actual needs, which is not limited here. It can be seen that when the data signal in the data line of the display panel is switched in high-low gray level, the phase of the clock signal input by the shift register corresponding to the pixel units of the row is adjusted, so that the falling edge time of the pull-up node of the corresponding shift register is delayed to output the scanning signal with delayed phase, and the subsequent clock signal is also adjusted in the same way, and the previous clock signal is not adjusted. If no high-low gray level switching of the adjacent rows is detected subsequently, the data signal in all data signal lines is restored to the initial phase to avoid the disorder of the clock signal, cause the disorder of the scanning signal output, cause the wrong charging, and affect the display effect.

[0093] The display panel provided by the embodiments of the present disclosure also has the advantages that Figure 13 A structural schematic diagram of a display panel provided by the embodiments of the present disclosure is shown in Figure 13As shown, the display panel comprises N gate lines S and M data lines D arranged in cross, and pixel units located in the area defined by the gate lines and the data lines; the display panel further comprises N shift registers GOA and P clock signal lines; every adjacent P shift registers in the N shift registers are connected to the P clock signal lines respectively; the signal output ends of the N shift registers are connected to the N gate lines one by one respectively; wherein, P is an even number greater than or equal to 2; N is an integer greater than or equal to P; M is a positive integer; the display panel further comprises a detection module Z, which is configured to perform steps S101 to S104 in the driving method of the display panel provided in any one of the above embodiments, and the implementation principle is the same as that of the driving method of the display panel described above, which will not be repeated here. The detection module Z can be a timing controller T-CON, which can be arranged on the mainboard of the display panel and electrically connected to the display panel through the mainboard. The detection module can also be arranged on a mainboard B of the timing controller and electrically connected to the display panel. The connection between the display panel and the detection module can be direct connection or through a flexible printed circuit board FPC, which is not limited here. The display panel further comprises a driving chip IC, which can be arranged on the display panel, such as Figure 13 As shown, the detection module Z can also be arranged on the FPC. In addition, the signals of the timing controller can be electrically connected to the driving chip IC through a lead or the like to realize electrical connection with the display panel.

[0094] The display device provided by the embodiments of the present disclosure comprises the display panel provided in any one of the above embodiments, and can be any product or component with display function, such as a television, a mobile phone, a display, a notebook computer, a digital photo frame, a navigator, etc. The implementation principle is similar to that of the display panel described above, which will not be repeated here.

[0095] It can be understood that the above embodiments are only exemplary embodiments adopted to illustrate the principles of the present disclosure, but the present disclosure is not limited thereto. Various modifications and improvements can be made by those skilled in the art without departing from the spirit and essence of the present disclosure, and these modifications and improvements are also regarded as the protection scope of the present disclosure.

Claims

1. A driving method of a display panel, the display panel comprising: N gate lines and M data lines are arranged in a cross manner, and pixel units are located in a region defined by the gate lines and the data lines; The display panel further comprises N shift registers and P clock signal lines; every adjacent P shift registers in the N shift registers are connected to the P clock signal lines respectively; signal output ends of the N shift registers are connected to the N gate lines one by one; wherein, P is an even number greater than or equal to 2; N is an integer greater than or equal to P; M is a positive integer; and the driving method of the display panel comprises: According to the data signal transmitted in the data line, it is judged whether the gray scale value difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than a threshold value; n is a positive integer less than or equal to N; If the gray scale difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than the threshold value, the non-working level maintaining time of the clock signal input by the nth shift register is extended, so that the falling edge time of the pull-up node of the nth shift register is delayed to output a phase-delayed scanning signal; According to the data signal transmitted in the data line, it is judged whether the gray scale value difference of the data signals input by the (n+m)th row of pixel units and the (n+m-1)th row of pixel units is greater than a threshold value; n+m is a positive integer less than or equal to N; If the gray scale value difference of the data signals input by the (n+m)th row of pixel units and the (n+m-1)th row of pixel units is less than or equal to the threshold value, an initial phase clock signal is input to the (n+m)th shift register.

2. The driving method of a display panel according to claim 1, wherein If the gray scale difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than the threshold value, the time interval between the data signal input by the nth row of pixel units and the falling edge time of the pull-up node of the nth shift register is greater than 1H; wherein, 1H is the charging time of one row of pixel units.

3. The driving method of a display panel according to claim 1, wherein The non-working level maintaining time of the clock signal input by the nth shift register is extended by 1H to 2H compared with the non-working level maintaining time of a preset clock signal.

4. The driving method of a display panel according to claim 1, wherein The non-working level maintaining time of the clock signal input by the nth shift register is equal to the pre-charge maintaining time of the pull-up node.

5. The driving method of a display panel according to claim 1, wherein The working level maintaining time of the clock signal input by the nth shift register is extended by 1H to 2H compared with the working level maintaining time of a preset clock signal.

6. The driving method of a display panel according to claim 1, wherein The working level maintaining time of the clock signal input by the nth shift register is equal to the charging time of the pull-up node.

7. The driving method of the display panel according to claim 1, wherein The time of the data signal input by the nth row of pixel units overlaps with the charging time of the pull-up node, and the overlapping time is greater than or equal to 2H.

8. A display panel comprising: N gate lines and M data lines are arranged in a cross manner, and pixel units are located in a region defined by the gate lines and the data lines; The display panel further comprises N shift registers and P clock signal lines; each adjacent P shift registers in the N shift registers are connected to the P clock signal lines respectively; signal output ends of the N shift registers are connected to the N gate lines one by one; wherein P is an even number greater than or equal to 2; N is an integer greater than or equal to P; M is a positive integer; characterized in that the display panel further comprises a detection module configured to detect whether a gray scale value difference of data signals input by an nth row of pixel units and an (n-1)th row of pixel units is greater than a threshold value; if the gray scale value difference of the data signals input by the nth row of pixel units and the (n-1)th row of pixel units is greater than the threshold value, a non-working level or working level maintenance time of a clock signal input by an nth shift register is extended, so that a falling edge time of a pull-up node of the nth shift register is delayed to output a phase-delayed scanning signal; the detection module is further configured to detect whether a gray scale value difference of data signals input by an (n+m)th row of pixel units and an (n+m-1)th row of pixel units is greater than a threshold value; n+m is a positive integer less than or equal to N; if the gray scale value difference of the data signals input by the (n+m)th row of pixel units and the (n+m-1)th row of pixel units is less than or equal to the threshold value, an initial phase clock signal is input to an (n+m)th shift register.

9. The display panel of claim 8, wherein, Each shift register in the N shift registers comprises an input sub-circuit, an output sub-circuit and a pull-up reset sub-circuit; The input sub-circuit is configured to respond to an input signal of a signal input end and write the input signal to a pull-up node; The output sub-circuit is configured to respond to a potential of the pull-up node and output a clock signal input by a clock signal end through a signal output end; The pull-up reset sub-circuit is configured to respond to a pull-up reset signal input by a pull-up reset signal end and reset the potential of the pull-up node by a non-working level signal.

10. The display panel of claim 9, wherein, A signal output end of an ith shift register is connected to a signal input end of an (i+p)th shift register; wherein P / 2≤p<N; i≤N-p; A pull-up reset signal end of a jth shift register is connected to a signal output end of a (j+q)th shift register; 2≤q-p<N / 2; j≤N-q.

11. The display panel of claim 9, wherein, The display panel further comprises a first frame opening signal line and a second frame opening signal line; Signal input ends of odd rows in the 1st to N / 2th shift registers are all connected to the first frame opening signal line; Signal input ends of even rows in the 1st to N / 2th shift registers are all connected to the second frame opening signal line.

12. A display device, characterized by comprising: The display device comprises the display panel of any one of claims 8-11.

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