Method for Solving Flicker Caused by PWM Data Switching in Area Backlight Adjustment

Abstract

The present invention belongs to the field of LED driver technology, and more particularly, relates to a method for resolving flicker caused by PWM data switching during regional backlight adjustment. The present invention divides the PWM cycle into sub-cycles, maintaining the duty cycle of each sub-cycle consistent with the original PWM data. At data switching points, the sub-cycle in which the switching occurs is completed before switching to the new PWM data. This ensures that the PWM duty cycle and refresh rate remain unchanged during this period, reducing the impact of low-frequency components in traditional methods. This significantly reduces flicker caused by low-frequency components and the problem of inconsistent brightness between chips.

Description

Technical Field

[0001] The present invention belongs to the technical field of LED driving, and in particular relates to a method for solving flickering caused by switching of PWM data for regional backlight regulation. Background Art

[0002] Local backlight modulation is an emerging technology for LCD backlight adjustment. This technology independently adjusts the brightness of LEDs in different zones, thereby improving image contrast and image quality. Therefore, this technology is gradually being widely adopted in various LCD products. Pulse width modulation (PWM) is a method used in most current LED driver chips to adjust LED brightness. In the entire LCD display system, images are transmitted at a certain frame rate, which is the display frame rate. Correspondingly, for each image frame, the corresponding backlight brightness is also frame-by-frame.

[0003] The frame synchronization signal, namely the VSYNC signal, is sent from the front-end timing control chip (TCON) or display processing chip (Scaler) to the backlight control chip or system. The chip or system uses this signal to determine when to switch the brightness data corresponding to PWM to generate a new brightness.

[0004] Taking the 12-bit precision area backlight system as an example, other lower or higher precision application scenarios can be analyzed using the same method. The current 12-bit precision area backlight solution processing waveform is as follows Figure 1 LED driver chips generally use the clock generated by the internal oscillator (OSC) and then implement the corresponding PWM algorithm based on the 12-bit brightness information input from the previous stage. Due to the clock deviation of different LED driver chips and the deviation between each LED driver chip and the system frame clock, there is no way to ensure that the time interval between each two VSYNC signals is an integer multiple of the PWM period. For the PWM brightness data of the 12-bit precision backlight system, the relationship between the time interval between the two VSYNC signals and the number of OSC clock cycles inside the LED driver chip can be expressed as

[0005] T VSYNC =N*(4096*T OSC )+M*T OSC ,(M<4096)

[0006] The N in the formula represents the number of 12-bit precision PWM cycles that can be repeated (4096 = 2^12), M*T OSC Indicates the number of incomplete PWM cycle clocks due to synchronization failures caused by clock deviations between different LED driver chips and deviations between each LED driver chip and the system frame clock. M < 4096.

[0007] Figure 2 This shows the problem caused by the traditional solution for handling the asynchrony between VYSNC and the OSC clock inside the LED driver chip. It can be seen that the last PWM cycle of each frame is directly truncated due to the sudden arrival of VSYNC, resulting in a sudden change in the duty cycle. The traditional processing method not only leads to large errors in the actual brightness display and poor consistency between multiple chips, that is, the actual average brightness is the average of the VSYNC cycle, that is, the average of N 12-bit precision completed cycles and one incomplete error cycle. At the same time, the truncation here also generates a low-frequency flicker noise with the same frequency as VSYNC. The low-frequency component generated by this low-frequency flicker noise can be perceived by the human eye or professional equipment and cause damage, ultimately making the system fail some professional eye protection certifications, such as the Rhine Eye Protection Certification. Summary of the Invention

[0008] In view of the above problems, the present invention proposes a method for solving the flickering caused by switching of PWM data in regional backlight adjustment.

[0009] The technical solution of the present invention is:

[0010] A method for resolving flickering caused by switching of PWM data for regional backlight adjustment includes the following steps:

[0011] S1. Define the PWM data received by the LED chip as 12 bits, corresponding to the internal oscillation period T OSC , then each complete PWM cycle T PWM It is 4096 T OSC , that is, T PWM =4096*T OSC , the PWM brightness information required to be displayed in each PWM cycle is divided into J segments, each segment consists of K T OSC composition:

[0012] T PWM =J*K*T OSC

[0013] S2. The time interval between two adjacent frames of images is defined as:

[0014] T VSYNC =N*(4096*T OSC )+M*T OSC

[0015] Among them, T VSYNCT is the time interval between two adjacent frames controlled by the VSYNC signal. N represents the number of 12-bit precision PWM cycles that can be repeated, and M represents the number of 12-bit precision PWM cycles that cannot be repeated. M < 4096. According to the definition of S1, we can get:

[0016] T VSYNC = N * (J * K * T OSC ) + M * T OSC

[0017] S3. Divide M according to the composition method of each segment consisting of K cycles of T OSC . Define the last segment as the S segment. If the length of the S segment is less than K * T OSC ,补足其长度至K * T OSC , and S < J, then the new time interval between two adjacent frames is obtained as:

[0018] T1 VSYNC = N * (J * K * T OSC ) + S * K * T OSC

[0019] S4. For the received VSYNC signal, perform PWM signal processing according to the definition of T1 VSYNC , that is, after generating a total of N * J + S segments of K clock cycle signals, switch to the next VSYNC signal.

[0020] The beneficial effect of the present invention is that the present invention adopts the method of dividing the PWM cycle into sub-cycles, making the duty cycle in each sub-cycle consistent with the original PWM data, and letting the sub-cycle where the switch is located complete first before switching to the new PWM data at the data switching point. This switching method does not have the flicker caused by the sudden change of the duty cycle. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 is the method for processing data switching between frames;

[0022] Figure 2 is a schematic diagram of the problems caused by the traditional data switching processing method;

[0023] Figure 3 is a schematic diagram of the processing of a complete PWM cycle;

[0024] Figure 4 is a schematic diagram of the processing of an incomplete PWM cycle;

[0025] Figure 5 is a schematic diagram of the PWM duty cycle remaining unchanged within one frame time plus an incomplete cycle. [[ID= / / ID=56]] DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] The technical solution of the present invention will be described in detail below with reference to the accompanying drawings.

[0027] For the convenience of description, it is defined in the present invention that the PWM data received by the LED chip is 12 bits, and each complete PWM cycle T PWM is 4096 Ts OSC , that is, T PWM = 4096*T OSC , the PWM brightness information to be displayed in each PWM cycle is roughly evenly divided into J segments, and each segment is composed of K cycles T OSC , as shown in Formula 2, and at the same time, the average display brightness of each sub-cycle of each "J" is approximately the same

[0028] T PWM = J*K*T OSC

[0029] It can be seen from Figure 3 that the time of each frame also includes N complete PWM cycles and 1 incomplete PWM cycle. As described above, for the N complete cycles, each complete cycle is divided into J sub-cycles with approximately the same brightness, and the duty cycle of the sub-cycle is approximately the same as the duty cycle represented by the PWM data. As Figure 1 shown, there is also an incomplete PWM cycle in one frame, and its processing method is as Figure 4 shown. Since it is an incomplete PWM cycle, that is, M*T OSC <T PWM , and T PWM = J*K*T OSC , so M < J*K, that is, 1 incomplete cycle can be decomposed into several complete sub-cycles of "K clock cycles" and one remaining incomplete sub-cycle. When the driving chip sees the VSYNC signal, the last sub-segment S (S is less than or equal to J) it is in, and this sub-cycle is made to complete the current sub-cycle, that is, it is supplemented to K clock cycles for processing.

[0030] It can be seen from Figure 5 that compared with the traditional error (such as Figure 2 , the error ratio is an incomplete cycle averaged into N complete cycles), the scheme proposed by the present invention includes N*J + S segments of PWM sub-cycles in two VSYNC signals, and compared with the traditional scheme where the arrival of VSYNC will immediately interrupt the current PWM cycle, this scheme will continue to process the currently averaged and split sub-cycles until they are completed, ensuring that during this period, the duty cycle of PWM remains unchanged and the refresh rate remains unchanged, weakening the influence of the low-frequency components of the traditional method, that is, greatly reducing the problems of flicker and inconsistent brightness between chips caused by low-frequency components.

Claims

1. A method for resolving flickering caused by switching of PWM data for regional backlight adjustment, characterized in that: The following steps are involved: S1. Define the PWM data received by the LED chip as 12 bits, corresponding to the internal oscillation period T OSC , then each complete PWM cycle T PWM It is 4096 T OSC , that is, T PWM =4096*T OSC , the PWM brightness information required to be displayed in each PWM cycle is divided into J segments, each segment consists of K T OSC composition: T PWM =J*K*T OSC S2. Define the time interval between two adjacent frames of image as: T VSYNC =N*(4096*T OSC )+M*T OSC Among them, T VSYNC is the time interval between two adjacent frames of images controlled by the VSYNC signal, N is the number of 12-bit precision PWM cycles that can be repeated, and M is the number of 12-bit precision PWM cycles that cannot be repeated. M<4096. According to the definition of S1, we can get: T VSYNC =N*(J*K*T OSC )+M*T OSC S3. Divide M according to the composition method that each segment consists of K periods T OSC Define the last segment as the S segment. If the length of the S segment is less than K*T OSC ,补足其长度至K*T OSC , and if S < J, then the time interval between the new adjacent two frames of images is: T1 VSYNC =N*(J*K*T OSC )+S*K*T OSC S4, for the received VSYNC signal, make it follow T1 VSYNC PWM signal processing is performed according to the definition of , that is, after generating a total of K clock cycle signals of N*J+S segments, it switches to the next VSYNC signal.

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