Display device, data driving circuit, and display driving method

Abstract

Various embodiments of the present disclosure relate to a display apparatus, a data driving circuit, and a display driving method. More particularly, a display apparatus, a data driving circuit, and a display driving method can be provided, the data driving circuit including a gamma driving power detection circuit for detecting a gamma driving power for driving the data driving circuit, and digital image data supplied to the data driving circuit can be controlled according to a gamma driving power measurement value detected by the gamma driving power detection circuit, thereby reducing an increase in temperature of the data driving circuit and improving image quality.

Description

[0001] Cross-references to related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0099714, filed on July 29, 2021, which is incorporated herein by reference for all purposes, as fully set forth herein. Technical Field

[0003] Embodiments of this disclosure relate to a display device, a data driving circuit, and a display driving method that can mitigate temperature rise in the driving circuit based on changes in data. Background Technology

[0004] With the development of the information society, the demand for display devices for displaying images is constantly increasing, and various types of display devices are used, such as liquid crystal displays (LCDs) and organic light-emitting displays (OLEDs).

[0005] Among these display devices, organic light-emitting displays use organic light-emitting diodes, thus offering various advantages in terms of fast response and contrast, luminous efficiency, brightness, and viewing angle.

[0006] An organic light-emitting display includes organic light-emitting diodes (OLEDs) arranged in subpixels on a display panel, and emits light by controlling the current flowing to the OLEDs when displaying an image, thereby controlling the brightness represented by each subpixel.

[0007] Subpixels are driven by a scan signal applied through gate lines, and gray levels are represented by data voltages applied through data lines based on timing when the scan signal is applied, thereby displaying an image. One data line can be arranged for each subpixel column to apply the data voltage.

[0008] Display panels can have various structures. As display performance improves, the demand for large-scale, high-resolution display panels is gradually increasing.

[0009] As the area and resolution of display panels increase, the amount of image data displayed through the display panel increases, and the image data transitions more frequently. Consequently, the temperature of the display panel and the data driving circuitry used to supply the data voltage rises. Summary of the Invention

[0010] Therefore, as the image data supplied to the display device changes, the temperature of the data driving circuit and the display panel rises, thereby reducing image quality. Therefore, the inventors of this disclosure have invented a display device, a data driving circuit, and a display driving method that can reduce the temperature increase of the data driving circuit due to image data changes.

[0011] Embodiments of this disclosure may provide a display device, a data driving circuit, and a display driving method that can reduce the increase in temperature of the data driving circuit by controlling the data voltage according to the change in the gamma driving power applied to the data driving circuit.

[0012] Embodiments of this disclosure may provide a display device, a data driving circuit, and a display driving method that can reduce the increase in temperature of the data driving circuit by controlling the level or refresh rate of the data voltage according to the change in the gamma driving power applied to the data driving circuit.

[0013] Embodiments of this disclosure may provide a display device, a data driving circuit, and a display driving method that can effectively reduce the temperature increase of the data driving circuit by detecting changes in the gamma driving power applied to the data driving circuit, regardless of the structure of the sub-pixels constituting the display panel.

[0014] Embodiments of this disclosure may provide a display device comprising: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels; a gate driving circuit for supplying scan signals to the plurality of gate lines; a data driving circuit configured to convert digital image data into analog data voltage and supply the analog data voltage to the plurality of data lines; a power management circuit configured to supply gamma driving power to the data driving circuit for driving the data driving circuit and configured to include a gamma driving power detection circuit for detecting the gamma driving power; and a timing controller configured to control the gate driving circuit and control the data driving circuit to change the analog data voltage supplied to the display panel according to a gamma driving power measurement value detected by the gamma driving power detection circuit.

[0015] Embodiments of this disclosure may provide a data driving circuit comprising: a shift register configured to convert digital image data received serially into image data in parallel form and output the image data; a latch circuit configured to transmit the image data in parallel form on a per-line basis to simultaneously supply the image data to multiple source driver integrated circuits; a gamma circuit configured to generate multiple gamma reference voltages using gamma drive power; a digital-to-analog converter configured to convert the image data in parallel form into analog data voltages in response to the multiple gamma reference voltages transmitted from the gamma circuit; an output buffer that supplies the analog data voltages to a display panel via multiple data lines; and a gamma drive power detection circuit configured to detect the gamma drive power.

[0016] Embodiments of this disclosure may provide a display driving method for driving a display device, the display device comprising: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels; a gate driving circuit supplying scan signals to the plurality of gate lines; and a data driving circuit that converts digital image data into analog data voltage and supplies the analog data voltage to the plurality of data lines. The method includes: detecting gamma driving power supplied to the data driving circuit; comparing a measured value of the gamma driving power with a reference value; controlling the analog data voltage when the measured value of the gamma driving power exceeds the reference value; and supplying the analog data voltage to the display panel.

[0017] According to embodiments of this disclosure, a display device, a data driving circuit, and a display driving method can be provided, which can reduce the increase in temperature of the data driving circuit due to changes in image data.

[0018] According to embodiments of this disclosure, a display device, a data driving circuit, and a display driving method can be provided, which can reduce the increase in temperature of the data driving circuit by controlling the data voltage according to the change in the gamma driving power applied to the data driving circuit.

[0019] According to embodiments of this disclosure, a display device, a data driving circuit, and a display driving method can be provided, which can reduce the increase in temperature of the data driving circuit by controlling the level or refresh rate of the data voltage according to the change of the gamma driving power applied to the data driving circuit.

[0020] According to embodiments of the present disclosure, a display device, a data driving circuit, and a display driving method can be provided that can effectively reduce the temperature increase of the data driving circuit by detecting changes in the gamma driving power applied to the data driving circuit, regardless of the structure of the sub-pixels constituting the display panel. Attached Figure Description

[0021] The above and other objects, features and advantages of the invention will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0022] Figure 1 This is a diagram schematically illustrating the configuration of a display device according to various embodiments of the present disclosure;

[0023] Figure 2 This is a diagram illustrating an example of a system of display devices according to embodiments of the present disclosure;

[0024] Figure 3 This is a diagram illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure;

[0025] Figure 4 This is a diagram illustrating an example of changes in the image displayed on the display panel in a display device according to an embodiment of the present disclosure;

[0026] Figure 5 This is a diagram illustrating an example of how the temperature of the display panel in a display device according to an embodiment of the present disclosure increases due to changes in data voltage;

[0027] Figure 6 This is a diagram schematically illustrating the configuration of the data driving circuitry in a display device according to an embodiment of the present disclosure;

[0028] Figure 7 This is a diagram showing a partial configuration of the data driving circuitry in a display device according to an embodiment of the present disclosure;

[0029] Figure 8 This is a diagram illustrating an example of how the current of the gamma drive power applied to the data drive circuit in a display device according to an embodiment of the present disclosure changes due to changes in image data.

[0030] Figure 9 This is a diagram illustrating an example of a subpixel structure driven by a DRD scheme in a display device according to an embodiment of the present disclosure;

[0031] Figure 10This is a system block diagram illustrating the structure of an image data control circuit in a display device that detects changes in gamma drive power according to an embodiment of the present disclosure.

[0032] Figure 11 This is a diagram illustrating an example of a gamma drive power detection circuit in a display device according to an embodiment of the present disclosure;

[0033] Figure 12 This is a diagram illustrating an example of how the level of image data changes according to a change in gamma drive power in a display device according to an embodiment of the present disclosure;

[0034] Figure 13 This is a diagram illustrating an example of how the refresh rate of image data changes according to a change in gamma drive power in a display device according to an embodiment of the present disclosure.

[0035] Figure 14 This is a diagram illustrating an example of the connection structure of a power management circuit disposed on a control printed circuit board and a plurality of source driver integrated circuits disposed on a source printed circuit board in a display device according to various embodiments.

[0036] Figure 15 This is a system block diagram illustrating the structure of an image data in a data drive circuit of a display device that detects changes in gamma drive power and thereby controls the image data according to an embodiment of the present disclosure; and

[0037] Figure 16 This is a flowchart illustrating a display driving method according to an embodiment of the present disclosure. Detailed Implementation

[0038] In the following description, some embodiments of this disclosure will be described in detail with reference to exemplary accompanying drawings. In the following description of examples or embodiments of the invention, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are illustrated by way of illustration, and in which the same reference numerals may be used to denote the same or similar components, even if they are shown in different drawings. Furthermore, in the following description of examples or embodiments of the invention, detailed descriptions of well-known functions and components incorporated herein will be omitted when it is determined that the description may make the subject matter of some embodiments of the invention considerably unclear. Terms such as “comprising,” “having,” “including,” “constituting,” “made of,” and “formed from” as used herein are generally intended to allow for the addition of additional components, unless these terms are used in conjunction with the term “only.” As used herein, singular forms are intended to include plural forms unless the context clearly indicates otherwise.

[0039] In this document, terms such as “first,” “second,” “A,” “B,” “(A),” or “(B)” may be used to describe elements of the invention. Each of these terms is not intended to define the nature, order, sequence, or number of elements, but only to distinguish the corresponding element from other elements.

[0040] When referring to a first element as "connected or coupled to," "in contact with," or "overlapping" with a second element, it should be understood that not only can the first element be "directly connected or coupled to" or "directly in contact with or overlap with" the second element, but a third element can be "inserted" between the first and second elements, or the first and second elements can be "connected or coupled," "in contact with," or "overlapping" with each other via a fourth element. Here, a second element can be included in at least one of two or more elements that are "connected or coupled," "in contact with," or "overlapping" with each other.

[0041] When time-related terms such as “after,” “follow,” “next,” or “before” are used to describe the handling or operation of an element or configuration, or a process or step in an operation, handling, or manufacturing method, these terms may be used to describe non-continuous or non-sequential handling or operation unless the terms are used together with “directly” or “immediately”.

[0042] Furthermore, when referring to any size, relative size, etc., it should be assumed that the numerical values ​​or corresponding information (e.g., levels, ranges, etc.) of an element or feature include tolerances or error ranges that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all the meanings of the term "able to".

[0043] In the following, various embodiments of this disclosure will be described in detail with reference to the accompanying drawings.

[0044] Figure 1 This is a diagram schematically illustrating the configuration of a display device according to various embodiments of the present disclosure.

[0045] Reference Figure 1 The display device 100 according to embodiments of the present disclosure may include: a display panel 110, wherein a plurality of gate lines GL and a plurality of data lines DL are connected, and a plurality of sub-pixels SP are arranged in a matrix; a gate driving circuit 120 for driving the plurality of gate lines GL; a data driving circuit 130 for supplying data voltage through the plurality of data lines DL; a timing controller 140 for controlling the gate driving circuit 120 and the data driving circuit 130; and a power management circuit 150.

[0046] The display panel 110 displays images based on scan signals transmitted from the gate drive circuit 120 through multiple gate lines GL and data voltages transmitted from the data drive circuit 130 through multiple data lines DL.

[0047] In the case of a liquid crystal display, the display panel 110 may include a liquid crystal layer formed between two substrates and can operate in any known mode, such as twisted nematic phase (TN) mode, vertical alignment (VA) mode, in-plane switching (IPS) mode, or rim field switching (FFS) mode. In the case of an organic light-emitting display, the display panel 110 may be implemented as a top-emitting scheme, a bottom-emitting scheme, or a dual-emitting scheme.

[0048] In the display panel 110, multiple pixels can be arranged in a matrix, and each pixel can include sub-pixels SP with different colors, such as white sub-pixels, red sub-pixels, green sub-pixels and blue sub-pixels, and each sub-pixel SP can be defined by multiple data lines DL and multiple gate lines GL.

[0049] A sub-pixel SP may include, for example, a thin-film transistor (TFT) formed at the intersection between a data line DL and a gate line GL, a light-emitting element (e.g., an organic light-emitting diode) charged with a data voltage, and a storage capacitor electrically connected to the light-emitting element to maintain the voltage.

[0050] For example, when a display device 100 with a resolution of 2160x3840 includes four sub-pixels SP representing white (W), red (R), green (G), and blue (B), 3840 data lines DL can be connected to 2160 gate lines GL and the four sub-pixels WRGB, thus providing 3840 x 4 = 15360 data lines DL. Each sub-pixel SP is positioned at the intersection between the gate line GL and the data line DL.

[0051] The gate drive circuit 120 can be controlled by the controller 140 to sequentially output scan signals to multiple gate lines GL disposed in the display panel 110, thereby controlling the driving timing of multiple sub-pixels SP.

[0052] In a display device 100 with a resolution of 2160x3840, sequentially outputting scan signals from the first gate line to the 2160th gate line to 2160 gate lines GL can be referred to as 2160-phase driving. Sequentially outputting scan signals to each of the four gate lines GL (for example, sequentially outputting scan signals to the fifth to eighth gate lines after sequentially outputting scan signals to the first to fourth gate lines) is referred to as four-phase driving. In other words, sequentially outputting scan signals to every N gate lines GL can be referred to as N-phase driving.

[0053] The gate driving circuit 120 may include one or more gate driving integrated circuits (GDICs). Depending on the driving scheme, the gate driving circuit 120 may be located only on one side of the display panel 110 or on each of the opposite sides. The gate driving circuit 120 may be implemented as an in-board gate (GIP) embedded in the bezel region of the display panel 110.

[0054] The data driving circuit 130 receives image data DATA from the timing controller 140 and converts the received image data DATA into an analog data voltage. Then, when the data voltage is output to each data line DL according to the timing of the scan signal applied through the gate line GL, each sub-pixel SP connected to the data line DL displays a light-emitting signal with a brightness corresponding to the data voltage.

[0055] Similarly, the data driving circuit 130 may include one or more source driver integrated circuits (SDICs), and the source driver integrated circuits (SDICs) may be connected to the bonding pads of the display panel 110 in a tape auto-bonding (TAB) type or a chip-on-glass (COG) type, or may be directly disposed on the display panel 110.

[0056] In some cases, each source driver integrated circuit (SDIC) can be integrated and disposed on the display panel 110. Furthermore, each source driver integrated circuit (SDIC) can be implemented as a chip-on-film (COF) type, and in this case, each source driver integrated circuit (SDIC) can be mounted on a circuit film and electrically connected to the data line DL of the display panel 110 via the circuit film.

[0057] The timing controller 140 supplies various control signals to the gate drive circuit 120 and the data drive circuit 130, and controls the operation of the gate drive circuit 120 and the data drive circuit 130. In other words, the timing controller 140 can control the gate drive circuit 120 to output a scan signal according to the timing implemented in each frame, and on the other hand, transmit the image data DATA received from the outside to the data drive circuit 130.

[0058] In this case, the timing controller 140 receives several timing signals from the external host system 200, such as the vertical synchronization signal Vsync, the horizontal synchronization signal Hsync, the data enable signal DE, the master clock MCLK, and the image data DATA.

[0059] The host system 200 can be any of a television (TV) system, set-top box, navigation system, personal computer (PC), home theater system, mobile device, and wearable device.

[0060] Therefore, the timing controller 140 can generate control signals based on various timing signals received from the host system 200, and transmit the control signals to the gate drive circuit 120 and the data drive circuit 130.

[0061] For example, timing controller 140 outputs several gate control signals to control gate drive circuit 120. These signals include, for example, a gate start pulse (GSP), a gate clock (GCLK), and a gate output enable signal (GOE). The gate start pulse (GSP) controls the timing of the start of operation of one or more gate driver integrated circuits (GDICs) constituting gate drive circuit 120. The gate clock (GCLK) is a clock signal that is commonly input to one or more gate driver integrated circuits (GDICs) and controls the shift timing of the scan signal. The gate output enable signal (GOE) specifies timing information regarding one or more gate driver integrated circuits (GDICs).

[0062] The timing controller 140 outputs various data control signals to control the data drive circuit 130. These signals include, for example, the source start pulse SSP, the source sampling clock SCLK, and the source output enable signal SOE. The source start pulse SSP controls the timing of data sampling for one or more source driver integrated circuits (SDICs) constituting the data drive circuit 130. The source sampling clock SCLK is a clock signal that controls the timing of the sampled data in the source driver integrated circuits (SDICs). The source output enable signal SOE controls the output timing of the data drive circuit 130.

[0063] The display device 100 may also include a power management circuit 150 that supplies various voltages or currents to, for example, the display panel 110, the gate drive circuit 120, and the data drive circuit 130, or controls the various voltages or currents to be supplied.

[0064] The power management circuit 150 adjusts the DC input voltage Vin supplied from the host system 200 to generate the power required to drive the display panel 100, the gate drive circuit 120, and the data drive circuit 130.

[0065] Subpixels SP are located at the intersection between gate line GL and data line DL, and light-emitting elements can be disposed in each subpixel SP. For example, an organic light-emitting display can include a light-emitting element, such as an organic light-emitting diode, in each subpixel SP, and an image can be displayed by controlling the current flowing to the light-emitting element according to the data voltage.

[0066] The display device 100 can be one of various types of devices, such as a liquid crystal display, an organic light-emitting display, or a plasma display panel.

[0067] Figure 2This is a diagram illustrating an example of a system of display devices according to an embodiment of the present disclosure.

[0068] Reference Figure 2 In the display device 100 according to an embodiment of the present disclosure, the source driver integrated circuit SDIC included in the data driver circuit 130 and the gate driver integrated circuit GDIC included in the gate driver circuit 120 are implemented as chip-on-film (COF) of various types (e.g., TAB, COG or COF).

[0069] One or more gate driving integrated circuits (GDICs) included in the gate driving circuit 120 can be mounted on the gate film GF, and one side of the gate film GF can be electrically connected to the display panel 110. Lines for electrically connecting the gate driving integrated circuits (GDICs) and the display panel 110 can be provided on the gate film GF.

[0070] Similarly, one or more source driver integrated circuits (SDICs) included in the data driver circuit 130 can be mounted on the source film SF, and one side of the source film SF can be electrically connected to the display panel 110. Lines for electrically connecting the source driver integrated circuits (SDICs) and the display panel 110 can be provided on the source film SF.

[0071] The display device 100 may include at least one source printed circuit board (SPCB) for circuit connections between multiple source driver integrated circuits (SDICs) and other devices, and a control printed circuit board (CPCB) for mounting control components and various electrical devices.

[0072] The other side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be connected to at least one source printed circuit board SPCB. In other words, one side of the source film SF, on which the source driver integrated circuit SDIC is mounted, can be electrically connected to the display panel 110, and the other side can be electrically connected to the source printed circuit board SPCB.

[0073] The timing controller 140 and the power management circuit (power management IC) 150 can be mounted on a control printed circuit board (CPCB). The timing controller 140 can control the operation of the data drive circuit 130 and the gate drive circuit 120. The power management circuit 150 can supply drive voltage or current to the display panel 110, the data drive circuit 130, and the gate drive circuit 120, and control the supplied voltage or current.

[0074] At least one source printed circuit board (SPCB) and a control printed circuit board (CPCB) can be circuitally connected via at least one connecting member. The connecting member may include, for example, a flexible printed circuit (FPC) or a flexible flat cable (FFC). In this case, the connecting member connecting the at least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may vary depending on the size and type of the display device 100. At least one source printed circuit board (SPCB) and the control printed circuit board (CPCB) may be integrated into a single printed circuit board.

[0075] In the display device 100 configured in this way, the power management circuit 150 transmits the drive voltage required for display driving or feature sensing to the source printed circuit board SPCB via a flexible printed circuit (FPC) or a flexible flat cable (FFC). The drive voltage transmitted to the source printed circuit board SPCB is supplied by the source driver integrated circuit (SDIC) to emit light or sense specific sub-pixels (SPs) in the display panel 110.

[0076] Each sub-pixel SP arranged in the display panel 110 of the display device 100 may include an organic light-emitting diode as a light-emitting element and circuit elements for driving the organic light-emitting diode, such as a driving transistor.

[0077] The type and number of circuit elements that make up each sub-pixel SP can vary depending on the functions and design schemes to be provided.

[0078] Figure 3 This is a diagram illustrating an example of a circuit constituting a sub-pixel in a display device according to an embodiment of the present disclosure.

[0079] Reference Figure 3 In the display device 100 according to the embodiments of the present disclosure, the sub-pixel SP may include one or more transistors, capacitors and organic light-emitting diodes (OLEDs) as light-emitting elements.

[0080] For example, a subpixel SP may include a driving transistor DRT, a switching transistor SWT, a sensing transistor SENT, a storage capacitor Cst, and an organic light-emitting diode OLED.

[0081] The driving transistor DRT includes a first node N1, a second node N2, and a third node N3. The first node N1 of the driving transistor DRT can be the gate node to which the data voltage Vdata is applied from the data driving circuit 130 via the data line DL when the switching transistor SWT is turned on. The second node N2 of the driving transistor DRT can be electrically connected to the anode electrode of the organic light-emitting diode (OLED) and can be either a source node or a drain node. The third node N3 of the driving transistor DRT can be electrically connected to the driving voltage line DVL to which the sub-pixel driving voltage EVDD is applied and can be either a drain node or a source node.

[0082] In this scenario, during display driving, the subpixel driving voltage EVDD required for displaying the image can be supplied to the drive voltage line DVL. For example, the subpixel driving voltage EVDD required for displaying the image could be 27V.

[0083] The switching transistor SWT is electrically connected between the first node N1 of the driving transistor DRT and the data line DL, and the gate line GL is connected to the gate node. Therefore, the switching transistor SWT is operated according to the scan signal SCAN supplied through the gate line GL. When turned on, the switching transistor SWT transmits the data voltage Vdata supplied through the data line DL to the gate node of the driving transistor DRT, thereby controlling the operation of the driving transistor DRT.

[0084] The sensing transistor SENT is electrically connected between the second node N2 of the driving transistor DRT and the reference voltage line RVL, and the gate line GL is connected to the gate node. The sensing transistor SENT is operated according to the sensing signal SENSE supplied through the gate line GL. When the sensing transistor SENT is turned on, the sensing reference voltage Vref supplied through the reference voltage line RVL is transmitted to the second node N2 of the driving transistor DRT.

[0085] In other words, as the switching transistor SWT and the sensing transistor SENT are controlled, the voltage of the first node N1 and the second node N2 of the driving transistor DRT are controlled, so that current can be supplied to drive the organic light-emitting diode OLED.

[0086] The gate nodes of the switching transistor SWT and the sensing transistor SENT can be connected to a common gate line GL, or they can be connected to different gate lines GL. An example is shown in which the switching transistor SWT and the sensing transistor SENT are connected to different gate lines GL. In this case, the switching transistor SWT and the sensing transistor SENT can be independently controlled by a scan signal SCAN and a sensing signal SENSE transmitted through different gate lines GL.

[0087] In contrast, if the switching transistor SWT and the sensing transistor SENT are connected to a gate line GL, the switching transistor SWT and the sensing transistor SENT can be simultaneously controlled by a scan signal SCAN or a sensing signal SENSE transmitted through a gate line GL, and the aperture ratio of the sub-pixel SP can be increased.

[0088] The transistor set in the sub-pixel SP can be an n-type transistor or a p-type transistor, and in the example shown, the transistor is an n-type transistor.

[0089] The storage capacitor Cst is electrically connected between the first node N1 and the second node N2 of the driving transistor DRT, and holds the data voltage Vdata during one frame.

[0090] Depending on the type of driving transistor DRT, the storage capacitor Cst can also be connected between the first node N1 and the third node N3 of the driving transistor DRT. The anode of the organic light-emitting diode (OLED) can be electrically connected to the second node N2 of the driving transistor DRT, and the base voltage EVSS can be applied to the cathode of the organic light-emitting diode (OLED).

[0091] The base voltage EVSS can be ground voltage, or a voltage higher or lower than ground voltage. The base voltage EVSS can vary depending on the driving state. For example, the base voltage EVSS during display driving and the base voltage EVSS during sensing driving can be set to be different from each other.

[0092] As an example, the structure of the sub-pixel SP described above is a 3T (transistor) 1C (capacitor) structure. This is merely an example, and it may also include one or more transistors, or in some cases, one or more capacitors. Multiple sub-pixel SPs may have the same structure, or some of the multiple sub-pixel SPs may have different structures.

[0093] In order to effectively sense characteristic values ​​of the driving transistor DRT, such as threshold voltage or mobility, the display device 100 according to an embodiment of the present disclosure can use a method for measuring the current flowing through the voltage that charges the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT, which is called current sensing.

[0094] In other words, the characteristic value or change of characteristic value of the driving transistor DRT in the sub-pixel SP can be calculated by measuring the current flowing through the voltage that charges the storage capacitor Cst during the characteristic value sensing period of the driving transistor DRT.

[0095] In this case, the reference voltage line RVL serves not only as a transmission reference voltage Vref, but also as a sensing line for sensing the characteristic values ​​of the driving transistor DRT in the sub-pixel SP. Therefore, the reference voltage line RVL can also be referred to as a sensing line.

[0096] Figure 4 This is a diagram illustrating an example of changes in the image displayed on the display panel in a display device according to an embodiment of the present disclosure.

[0097] Reference Figure 4 In the display device 100 according to the embodiments of the present disclosure, the flickering of the image displayed on the display panel 110 may be caused by the change of data voltage Vdata, which is caused by the data voltage Vdata of spatially adjacent sub-pixels SP being different from each other or the data voltage Vdata of temporally adjacent frames being different from each other.

[0098] For example, there might be a brightness difference of 58 gray levels between adjacent green sub-pixels G and blue sub-pixels B, a brightness difference of 150 gray levels between red sub-pixels R and green sub-pixels G, and a brightness difference of 25 gray levels between blue sub-pixels B and red sub-pixels R. This brightness difference may be due to deviations in the data voltage Vdata between adjacent sub-pixels SP or between adjacent frames.

[0099] Specifically, when the driving frequency of the display panel 110 is high, users may easily notice changes in the image due to deviations in the data voltage Vdata between adjacent sub-pixels SP or between adjacent frames.

[0100] In contrast, when the drive frequency of the display panel 110 is low, even minute changes in the image between adjacent sub-pixels SP or between adjacent frames may be easily noticed by the user's eye, resulting in screen flickering or flashing.

[0101] This screen flicker occurs when several gray levels are distributed across the display panel 110, and the deviation of the common voltage used as a reference differs for each gray level. The level of image data transition can be controlled by calculating the complexity between adjacent sub-pixels SP or between adjacent frames.

[0102] For example, the timing controller 140 can control the driving frequency of the display panel 110 based on the transitions in image data shown between adjacent sub-pixels SP or between adjacent frames. In this case, the transitions in image data can be calculated as the sum of the grayscale values ​​of the data voltage Vdata between adjacent sub-pixels SP or between adjacent frames.

[0103] Typically, motion pictures with frequent changes in image data may require a drive frequency of 60 Hz or higher to represent smooth motion, while motion pictures or still pictures with little or no changes in image data can be operated at a lower drive frequency because of their less motion.

[0104] Therefore, if the change in data voltage Vdata increases due to the difference between data voltage Vdata of spatially adjacent sub-pixels SP or between data voltage Vdata of temporally adjacent frames, the temperature of the data driving circuit 130 supplying data voltage Vdata to the display panel 110 may increase, thereby degrading the image quality of the display panel 110.

[0105] Figure 5 This is a diagram illustrating an example of how the temperature of the display panel in a display device according to an embodiment of the present disclosure increases due to changes in data voltage.

[0106] Reference Figure 5 In the touch display device 100 according to the embodiments of the present disclosure, the display panel 110 can be one of various types of panels, including a liquid crystal display panel or an organic light-emitting display panel.

[0107] The display panel 110 can not only provide image display function, but also provide touch sensing function via passive stylus (such as finger) or pen touch sensing function via active stylus (pen recognition function).

[0108] In the display panel 110 that provides both image display and touch sensing functions, the common electrode, which forms an electric field together with the pixel electrode by receiving a common voltage during the display driving period, can be divided into multiple blocks to serve as multiple touch electrodes.

[0109] When the display panel 110 is an organic light-emitting diode (OLED) panel, the display device 100 may include a first electrode constituting an OLED, an organic light-emitting layer and a second electrode, an encapsulation layer thereon for providing encapsulation functions, and a touch sensor metal layer thereon. Multiple touch electrodes may be formed on the touch sensor metal layer.

[0110] The data driving circuit 130 may include multiple source driver integrated circuits (SDICs) for driving data lines DL arranged on the display panel 110. The data driving circuit 130 may be disposed on only one side of the display panel 110 or on its opposite sides. In the example shown, the data driving circuit 130 is disposed on the upper side of the display panel 110.

[0111] Source driver integrated circuits (SDICs) can be formed as either chip-on-film (COF) mounted on a film or chip-on-glass (COG) formed on a glass substrate. Although an example of a source driver integrated circuit (SDIC) of the COF type is shown, it will be apparent to those skilled in the art that a source driver integrated circuit (SDIC) can be formed as the COG type.

[0112] The film or glass on which the source driver integrated circuit (SDIC) is mounted can be coupled to each of the bonding portions of the display panel 110 and the source printed circuit board (SPCB).

[0113] The source driver integrated circuit SDIC can be coupled to the readout integrated circuit for touch sensing and implemented as a single integrated circuit.

[0114] In this structure, when the display panel 110 has a large scale and high resolution, the number of source driver integrated circuits SDIC that constitute the data driving circuit 130 increases, and the power consumption and temperature of the source driver integrated circuits SDIC increase due to the change in the data voltage Vdata applied to the display panel 110.

[0115] In other words, as the area and resolution of the display panel increase, the amount of image data displayed through the display panel increases, and the image data transitions more frequently. Therefore, the temperature of the source driver integrated circuit SDIC, which supplies data voltage to the display panel 110, increases, and the temperature of the display panel 110 also increases. Consequently, the characteristic values ​​of the driving transistors constituting the sub-pixels SP are affected, thus degrading image quality.

[0116] Therefore, in several areas of the display panel 110, the temperature in the area adjacent to the source driver integrated circuit SDIC further increases, thereby degrading the image quality.

[0117] This phenomenon may be more pronounced when the image data changes more frequently, such as when the image data is game images or motion images.

[0118] According to embodiments of the present disclosure, the display device 100 can control the refresh rate or level of the data voltage Vdata based on the changes in image data, thereby reducing the increase in temperature of the display panel 110 and improving image quality.

[0119] Figure 6 This is a diagram schematically illustrating the configuration of the data driving circuitry in a display device according to an embodiment of the present disclosure.

[0120] Reference Figure 6In the display device 100 according to an embodiment of the present disclosure, the data driving circuit 130 may include a shift register 131, a latch circuit 132, a gamma circuit 134, a digital-to-analog converter 133, and an output buffer 135.

[0121] Data drive circuit control signals transmitted from timing controller 140 to control data drive circuit 130 may include source start pulse SSP, source sampling clock SCLK, and source output enable signal SOE.

[0122] The source start pulse SSP controls the data sampling start time of the data drive circuit 130. The source sampling clock SCLK is a clock signal that controls the image data sampling operation in the data drive circuit 130 based on the rising or falling edge. The source output enable signal SOE controls the output of the data drive circuit 130.

[0123] In response to the source start pulse SSP and source sampling clock SCLK transmitted from the timing controller 140, shift register 131 shifts the image data DATA received as serial data and then outputs the image data DATA simultaneously.

[0124] Therefore, the image data DATA, which is serial data, is converted into data for a parallel system and then supplied to the latch circuit 132. The latch circuit 132 supplies one line of image data DATA to the digital-to-analog converter 133, so that the image data DATA is simultaneously transmitted to the source driver integrated circuit SDIC according to the source output enable signal SOE.

[0125] At least two latch circuits 132 can be configured, but for ease of description, only one latch circuit 132 is shown.

[0126] Gamma circuit 134 uses the gamma drive power SVDD supplied from timing controller 140 to generate the first gamma reference voltage GMA1 to the nth gamma reference voltage GMAn.

[0127] The digital-to-analog converter 133 converts a line of image data DATA into an analog data voltage Vdata in response to the first gamma reference voltage GMA1 to the nth gamma reference voltage GMAn transmitted from the gamma circuit 134.

[0128] The output buffer 135 amplifies or compensates the analog data voltage Vdata transmitted from the digital-to-analog converter 133 and supplies it to each data line DL.

[0129] The power of the gamma circuit 134, the digital-to-analog converter 133, and the output buffer 135 can be separated from each other, and they can share a gamma drive power SVDD.

[0130] Figure 7This is a diagram showing a partial configuration of the data driving circuitry in a display device according to an embodiment of the present disclosure.

[0131] Reference Figure 7 The data driving circuit 130 in the display device 100 according to the embodiments of the present disclosure may include a gamma circuit 134, a digital-to-analog converter 133, and an output buffer 135.

[0132] In this case, the digital-to-analog converter 133 may include a CMOS transistor in which PMOS transistors and NMOS transistors are connected in parallel with each other.

[0133] The gamma circuit 134, digital-to-analog converter 133, and output buffer 135 constituting the data drive circuit 130 can use the gamma drive power SVDD supplied from the timing controller 140 as the common drive power.

[0134] In contrast, when the gamma circuit 134, the digital-to-analog converter 133, and the output buffer 135 each use different drive powers, the drive power applied to the digital-to-analog converter 133 and the output buffer 135 can be applied to a signal line different from the gamma drive power SVDD, and is supplied with a drive power at a different level than the gamma drive power SVDD.

[0135] Because the gamma circuit 134 generates gamma reference voltages GMA corresponding to multiple levels (e.g., 256 levels), the gamma circuit 134 typically consumes a large amount of current.

[0136] The gamma drive power SVDD can be changed by the timing controller 140, but it is not easy to change by the gamma circuit 134, which consumes a lot of current and is usually fixed at a constant voltage.

[0137] However, if image data with frequent changes, such as motion images, is applied from the host system 200, the current of the output buffer 135 changes dynamically and significantly while the data voltage Vdata is supplied, which increases the power consumption of the data drive circuit 130.

[0138] Figure 8 This is a diagram illustrating an example of how the current of the gamma drive power applied to the data drive circuit in a display device according to an embodiment of the present disclosure changes due to changes in image data.

[0139] Reference Figure 8 In the display device 100 according to the embodiments of the present disclosure, if image data DATA with frequent changes is supplied from the host system 200, the current of the output buffer 135 increases at the rising or falling edge that occurs during the transition of the image data DATA or the data voltage Vdata.

[0140] When the current in the output buffer 135 increases so much during the transition of image data DATA or data voltage Vdata, the gamma drive power SVDD supplied to the gamma circuit 134 and the output buffer 135 increases, or the current Isvdd supplied to the data drive circuit 130 by the gamma drive power SVDD increases.

[0141] The recently adopted structure is the Dual Rate Drive (DRD) type structure, in which a data line DL is set between two adjacent sub-pixels SP, and the drivers are set on two sub-pixels SP on opposite sides of the data line DL, so as to reduce the number of source driver integrated circuits SDIC used to drive the data line DL.

[0142] Figure 9 This is a diagram illustrating an example of a subpixel structure driven by a DRD scheme in a display device according to an embodiment of the present disclosure.

[0143] Reference Figure 9 According to embodiments of the present disclosure, the sub-pixels SP of the display device 100 may include red sub-pixels R, green sub-pixels G, blue sub-pixels B, and white sub-pixels W.

[0144] In the display panel 110 of the display device 100 driven by the DRD scheme, a data line DL is provided for every two columns of sub-pixels SP, and two gate lines GL can be provided above and below each row of sub-pixels SP. In the example shown, the white sub-pixel W and the red sub-pixel R share a data line DL11, and the green sub-pixel G and the blue sub-pixel B share a data line DL12.

[0145] White sub-pixel W and green sub-pixel G can share the same gate lines GL11, GL21, GL31, GL41, GL51... and red sub-pixel R and blue sub-pixel B can share the same gate lines GL12, GL22, GL32, GL42...

[0146] Various modifications can be made to the sub-pixel (SP) structure that shares a data line DL and a gate line GL. White sub-pixel W and green sub-pixel G, or red sub-pixel R and blue sub-pixel B, can share the data line DL, or white sub-pixel W and red sub-pixel R can share a gate line GL.

[0147] In the DRD structure, a data voltage Vdata can be supplied to two sub-pixels SP through a data line DL during a horizontal period (horizontal time), and the gate line GL can be driven at twice the normal driving frequency, thereby applying the scan signal SCAN to each sub-pixel SP.

[0148] To minimize flicker and reduce power consumption, the scan signal SCAN can be controlled to alternately apply a data voltage Vdata to sub-pixels SP located on opposite sides of a data line DL.

[0149] In this case, the display device 100 driven by the DRD scheme can also apply a polarity-inverted data voltage Vdata to each row of sub-pixels SP to reduce power consumption and minimize flicker. Therefore, as the data voltage Vdata applied to the sub-pixel SP, a signal with the same polarity as the data voltage Vdata applied to the previous sub-pixel SP can be applied, or a signal with inverted polarity can be applied.

[0150] Therefore, the sub-pixels SP of the display device 100 can be formed in various structures, and the connection structure between the output buffer 135 of the data driving circuit 130 and the display panel 110 can be changed depending on the structure of the sub-pixels SP.

[0151] Therefore, the transition mode of image data DATA due to increased temperature of data driving circuit 130 may vary depending on the structure of sub-pixels SP. Consequently, it may be difficult to determine the mode of image data DATA due to increased temperature of data driving circuit 130.

[0152] However, despite the structural changes in the sub-pixel SP, the following common phenomenon may occur: the current flowing to the output buffer 135 of the data drive circuit 130 may increase due to the change in image data DATA, thereby increasing the current of the gamma drive power SVDD.

[0153] Therefore, the display device 100 according to the embodiments of the present disclosure reduces the increase in temperature of the data drive circuit 130 by detecting the change in the gamma drive power SVDD applied to the data drive circuit 130 and correspondingly controlling the level or refresh rate of the image data DATA supplied from the timing controller 140 to the data drive circuit 130.

[0154] Figure 10 This is a system block diagram illustrating the structure of an image data in a power management circuit of a display device that detects changes in gamma drive power according to an embodiment of the present disclosure.

[0155] Reference Figure 10 According to embodiments of the present disclosure, the display device 100 may include a gamma drive power detection circuit 152 for measuring gamma drive power SVDD in the power management circuit 150 that generates various types of drive power.

[0156] The gamma drive power detection circuit 152 can be located in the power management circuit 150, and can supply the gamma drive power SVDD generated by the power management circuit 150 to the data drive circuit 130 while measuring the change of the gamma drive power SVDD.

[0157] The gamma drive power measurement value M_SVDD detected by the gamma drive power detection circuit 152 is transmitted to the timing controller 140. The timing controller 140 can change the level or refresh rate of the image data DATA applied to the data drive circuit 130 relative to the gamma drive power measurement M_SVDD transmitted from the power management circuit 150.

[0158] For example, if the gamma drive power measurement value M_SVDD transmitted from the power management circuit 150 is less than the reference value, the timing controller 140 does not change the level or refresh rate of the image data DATA. However, if the gamma drive power measurement value M_SVDD transmitted from the power management circuit 150 exceeds the reference value, the timing controller 140 reduces the level or refresh rate of the image data DATA, thereby suppressing the increase in temperature of the data drive circuit 130.

[0159] In this case, the timing controller 140 can refer to a lookup table stored in a memory (not shown), extract the compensation value corresponding to the gamma drive power measurement value M_SVDD, and apply the extracted compensation value to the image data DATA, thereby changing the level or refresh rate of the image data DATA.

[0160] Specifically, the target to be changed by the timing controller 140 based on the gamma drive power measurement value M_SVDD can be either the level of the image data DATA or the refresh rate of the image data DATA. Alternatively, the timing controller 140 can simultaneously change both the level of the image data DATA and the refresh rate of the image data DATA based on the gamma drive power measurement value M_SVDD.

[0161] When the timing controller 140 changes the level of the image data DATA applied to the data drive circuit 130 according to the gamma drive power measurement value M_SVDD, it will change the level of the data voltage Vdata supplied from the data drive circuit 130 to the display panel 110 according to the level of the image data DATA. Therefore, the timing controller 140 can be regarded as changing the level of the data voltage Vdata supplied to the display panel 110 according to the gamma drive power measurement value M_SVDD.

[0162] Figure 11 This is a diagram illustrating an example of a gamma drive power detection circuit in a display device according to an embodiment of the present disclosure.

[0163] Reference Figure 11In the display device 100 according to an embodiment of the present disclosure, the gamma drive power detection circuit 152 may include a current sensing resistor Rs, an operational amplifier 154, and an analog-to-digital converter 156.

[0164] A current sensing resistor Rs can be connected between the terminal that generates the gamma drive power SVDD and the data drive circuit 130 to generate a bias voltage based on the current flowing through it from the power management circuit 150 to the data drive circuit 130 that supplies the gamma drive power SVDD.

[0165] In this case, the current sensing resistor Rs may have a small resistance, such as 0.01Ω, to minimize the voltage drop of the gamma drive power SVDD.

[0166] Operational amplifier 154 can be connected between the two ends of current sensing resistor Rs to sense and amplify the bias voltage applied between the two ends of current sensing resistor Rs. For example, operational amplifier 154 can amplify the bias voltage applied between the two ends of current sensing resistor Rs by five times or more.

[0167] The analog-to-digital converter 156 converts the current flowing to the data drive circuit 130 into a digital signal based on the bias voltage amplified by the operational amplifier 154 during a frame, generating a gamma drive power measurement value M_SVDD.

[0168] The gamma drive power measurement value M_SVDD is provided to the timing controller 140. The timing controller 140 can change the level or refresh rate of the image data DATA transmitted to the data drive circuit 130 based on the gamma drive power measurement value M_SVDD detected by the power management circuit 150.

[0169] In the example shown, the current is detected by the gamma drive power SVDD, and the current sensing resistor Rs is connected in series between the gamma drive power SVDD and the data drive circuit 130.

[0170] In contrast, when the voltage of the gamma drive power SVDD is detected, a signal line and a virtual channel for transmitting the gamma drive power SVDD can be set in parallel between the gamma drive power SVDD and the data drive circuit 130, and the voltage change of the gamma drive power SVDD can be detected through the virtual channel.

[0171] Figure 12 This is a diagram illustrating an example of how the level of image data changes according to a change in gamma drive power in a display device according to an embodiment of the present disclosure.

[0172] Reference Figure 12In the display device 100 according to the embodiments of the present disclosure, as the area and resolution of the display panel 110 increase, the amount of image data DATA displayed by the display panel 110 may increase, and the changes in image data DATA may be frequent.

[0173] If the transitions of image data DATA increase in this way, the temperature of the source driver IC SDIC, which supplies data voltage to the display panel 110, increases, and the temperature of the display panel 110 also increases. This phenomenon may be more pronounced when the transitions of image data DATA are more frequent, such as when the image data is game images or moving images.

[0174] Therefore, in the display device 100 of this disclosure, when the gamma drive power measurement value M_SVDD increases with the change of image data DATA, the timing controller 140 can reduce the high level DATA_H of the image data DATA to correspond to the gamma drive power measurement value M_SVDD. Figure 12 As shown in case (a), or by increasing the low level of image data DATA_L ( Figure 12 As shown in case (b), this reduces the level of the image data DATA (peak to peak).

[0175] Therefore, when the transition of image data DATA increases, the temperature of the data drive circuit 130 can be suppressed and the image quality improved by reducing the level of image data DATA.

[0176] Figure 13 This is a diagram illustrating an example of how the refresh rate of image data changes according to a change in gamma drive power in a display device according to an embodiment of the present disclosure.

[0177] Reference Figure 13 In the display device 100 according to the embodiments of the present disclosure, when the gamma drive power measurement value M_SVDD increases as the image data DATA changes, the timing controller 140 may reduce the refresh rate of the image data DATA to correspond to the gamma drive power measurement value M_SVDD.

[0178] The following example is shown: the timing controller 140 reduces the refresh rate of the image data DATA while keeping the level of the image data DATA constant.

[0179] In contrast, the timing controller 140 can change the level and refresh rate of the image data DATA based on the gamma drive power measurement value M_SVDD. In this case, in the image data DATA changed by the timing controller 140, the refresh rate can be reduced as the high level DATA_H decreases, and the refresh rate can also be reduced as the low level DATA_L increases. Alternatively, since the high level DATA_H decreases and the low level DATA_L increases under the control of the timing controller 140, the refresh rate can be reduced.

[0180] Therefore, when the conversion of image data DATA increases, the temperature of the data drive circuit 130 can be suppressed and the image quality improved by reducing the refresh rate of image data DATA.

[0181] If the gamma drive power detection circuit 152 is configured in the power management module 150 in this way, the gamma drive power SVDD applied to the data drive circuit 130 can be fully detected, and in this case, the image data DATA can be controlled to correspond to the increase in temperature of the entire display panel 110.

[0182] Meanwhile, the data driving circuit 130 may include a plurality of source driver integrated circuits (SDICs) and can measure the change in gamma driving power (SVDD) applied to each source driver integrated circuit (SDIC) to select any source driver integrated circuit (SDIC) and control the image data (DATA) based on the selected source driver integrated circuit (SDIC).

[0183] Figure 14 This is a diagram illustrating an example of the connection structure of a power management circuit disposed on a control printed circuit board and multiple source driver integrated circuits disposed on a source printed circuit board in a display device according to various embodiments.

[0184] Reference Figure 14 The gamma drive power SVDD generated from the power management circuit 150 located on the control printed circuit board CPCB is transmitted to the gamma circuit 134 of the data drive circuit 130 via the source printed circuit board SPCB.

[0185] The gamma circuit 134 uses multiple linear resistors arranged inside the data drive circuit 130 to divide the gamma drive power SVDD, thereby generating gamma reference voltages GMA1 to GMAan.

[0186] In this case, when multiple source driver integrated circuits (e.g., SDIC#1 to SDIC#4) are arranged in the data driver circuit 130, the gamma drive power detection circuit can be set in the source driver integrated circuit SDIC.

[0187] In this scenario, for each source driver IC (SDIC), the temperature change caused by the image data (DATA) can be detected individually. In this case, the source driver IC (e.g., SDIC #1) with the largest temperature change due to the variation in gamma drive power (SVDD) can be selected from multiple source driver ICs (SDIC #1 to SDIC #4), and the level or refresh rate of the image data (DATA) can be controlled individually relative to the selected source driver IC (SDIC #1).

[0188] Figure 15 This is a system block diagram illustrating the structure of image data in a data drive circuit of a display device for controlling changes in gamma drive power according to an embodiment of the present disclosure.

[0189] Reference Figure 15 According to embodiments of the present disclosure, the display device 100 may include a gamma drive power detection circuit 136 for measuring gamma drive power SVDD in the data drive circuit 130 that supplies data voltage Vdata to the display panel 110.

[0190] More specifically, the gamma drive power detection circuit 136 can be disposed in one of the multiple source drive integrated circuits (SDICs) constituting the data drive circuit 130.

[0191] The gamma drive power detection circuit 136 can be located in the source drive integrated circuit SDIC to measure the change in gamma drive power SVDD transmitted from the power management circuit 150.

[0192] The configuration of the gamma drive power detection circuit 136 can be with Figure 11 The configuration shown is the same.

[0193] The gamma drive power measurement value M_SVDD detected by the gamma drive power detection circuit 136 is transmitted to the timing controller 140. The timing controller 140 can change the level or refresh rate of the image data DATA applied to the corresponding source driver integrated circuit SDIC relative to the gamma drive power measurement value M_SVDD transmitted from the source driver integrated circuit SDIC.

[0194] In this case, the timing controller 140 can refer to a lookup table stored in a memory (not shown) to extract the compensation value corresponding to the gamma drive power measurement value M_SVDD, and apply the extracted compensation value to the image data DATA to be supplied to the source driver integrated circuit SDIC, thereby changing the level or refresh rate of the image data DATA.

[0195] Figure 16 This is a flowchart illustrating a display driving method according to an embodiment of the present disclosure.

[0196] Reference Figure 16 The display driving method according to the embodiments of this disclosure may include: step S100: detecting gamma driving power SVDD; step S200: comparing the measured value of gamma driving power M_SVDD with a reference value; when the measured value of gamma driving power M_SVDD exceeds the reference value, step S300: reducing the level of data voltage Vdata, or step S400: reducing the refresh rate of data voltage Vdata; and step S500: supplying the changed data voltage Vdata.

[0197] When the gamma drive power measurement value M_SVDD exceeds the reference value, the following steps can be executed simultaneously: step 300: reduce the level of the data voltage Vdata, step S400: reduce the refresh rate, or selectively execute only one of steps S300 and S400.

[0198] Furthermore, as described above, when the gamma drive power measurement value M_SVDD exceeds the reference value, the timing controller 140 can control the level or refresh rate of the image data DATA applied to the data drive circuit 130, thereby controlling the level or refresh rate of the data voltage Vdata supplied from the data drive circuit 130 to the display panel 110.

[0199] By displaying the driving process, when the gamma drive power measurement value M_SVDD exceeds the reference value due to the increase in the change of image data DATA, the display device 100 of this disclosure can reduce the level or refresh rate of the image data DATA to correspond to the gamma drive power measurement value M_SVDD, thereby suppressing the increase in temperature of the data drive circuit 130 and improving image quality.

[0200] The above implementation method is briefly described below.

[0201] The display device 100 disclosed herein includes: a display panel 110, wherein a plurality of gate lines GL, a plurality of data lines DL, and a plurality of sub-pixels SP are disposed; a gate driving circuit 120 configured to supply scan signals SCAN to the plurality of gate lines GL; a data driving circuit 130 configured to convert digital image data DATA into analog data voltage Vdata and supply the analog data voltage Vdata to the plurality of data lines DL; a power management circuit 150 configured to supply gamma driving power SVDD to the data driving circuit 130 for driving the data driving circuit 130, and configured to include a gamma driving power detection circuit 152 for detecting the gamma driving power SVDD; and a timing controller 140 configured to control the gate driving circuit 120 and control the digital image data DATA supplied to the data driving circuit 130, such that the analog data voltage Vdata supplied to the display panel 110 is changed according to the gamma driving power measurement value M_SVDD detected by the gamma driving power detection circuit 152.

[0202] The gamma drive power SVDD changes according to the transformation of digital image data DATA.

[0203] The data driving circuit 130 includes: a shift register 131 configured to convert serially received digital image data DATA into parallel image data DATA in response to a control signal transmitted from a timing controller 140, and output the image data DATA; a latch circuit 132 configured to transmit the parallel image data DATA on a per-line basis to simultaneously supply the image data DATA to multiple source driver integrated circuits SDIC; a gamma circuit 134 configured to generate multiple gamma reference voltages GMA using gamma drive power SVDD; a digital-to-analog converter 133 configured to convert the parallel image data DATA into an analog data voltage Vdata in response to the multiple gamma reference voltages GMA transmitted from the gamma circuit 134; and an output buffer 135 configured to supply the analog data voltage Vdata to multiple data lines DL.

[0204] The gamma drive power SVDD is supplied as the drive voltage for the digital-to-analog converter 133 and the output buffer 135.

[0205] The gamma drive power detection circuit 152 includes a current sensing resistor Rs connected in series with the gamma drive power SVDD; an operational amplifier 154 connected between the two ends of the current sensing resistor Rs to sense a bias voltage; and an analog-to-digital converter 156 configured to convert the bias voltage sensed by the operational amplifier 154 into a digital signal to generate a gamma drive power measurement value M_SVDD.

[0206] The timing controller 140 is configured to reduce the level of digital image data DATA when the gamma drive power measurement value M_SVDD exceeds a reference value.

[0207] The timing controller 140 is configured to either decrease the high level of the digital image data DATA or increase the low level of the digital image data DATA when the gamma drive power measurement value M_SVDD exceeds a reference value.

[0208] The timing controller 140 is configured to reduce the refresh rate of the digital image data DATA when the gamma drive power measurement value M_SVDD exceeds a reference value.

[0209] When the data driving circuit includes multiple source driver integrated circuits, the analog data voltage is changed based on the source driver integrated circuit with the largest change in gamma driving power among the multiple source driver integrated circuits.

[0210] The data driving circuit 130 of this disclosure includes: a shift register 131 configured to convert digital image data DATA received in serial form into image data DATA in parallel form and output the image data DATA; a latch circuit 132 configured to transmit the image data DATA in parallel form on a per-line basis to simultaneously supply it to multiple source driver integrated circuits SDIC; a gamma circuit 134 configured to generate multiple gamma reference voltages GMA using gamma drive power SVDD; a digital-to-analog converter 133 configured to convert the image data DATA in parallel form into an analog data voltage Vdata in response to the multiple gamma reference voltages GMA transmitted from the gamma circuit 134; an output buffer 135 configured to supply the analog data voltage Vdata to a display panel 110 through multiple data lines DL; and a gamma drive power detection circuit 136 configured to detect the gamma drive power SVDD.

[0211] The gamma drive power SVDD is supplied as the drive voltage for the digital-to-analog converter 133 and the output buffer 135.

[0212] The gamma drive power detection circuit 136 includes: a current sensing resistor Rs connected in series with the gamma drive power SVDD; an operational amplifier 154 connected between the two ends of the current sensing resistor Rs to sense a bias voltage; and an analog-to-digital converter 156 configured to convert the bias voltage sensed by the operational amplifier 154 into a digital signal to generate a gamma drive power measurement value M_SVDD.

[0213] The analog data voltage Vdata is controlled based on the gamma drive power measurement value M_SVDD detected by the gamma drive power detection circuit 136.

[0214] When the gamma drive power measurement value M_SVDD exceeds the reference value, the level of the analog data voltage Vdata is reduced.

[0215] When the gamma drive power measurement value M_SVDD exceeds the reference value, reduce the refresh rate of the analog data voltage Vdata.

[0216] A method for driving a display device according to the present disclosure, the display device comprising: a display panel having a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels; a gate driving circuit for supplying scan signals to the plurality of gate lines; and a data driving circuit for converting digital image data into analog data voltage and supplying the analog data voltage to the plurality of data lines, the method comprising: detecting gamma driving power supplied to the data driving circuit (S100); comparing a measured value of the gamma driving power with a reference value (S200); controlling the analog data voltage when the measured value of the gamma driving power exceeds the reference value (S300 and S400); and supplying the analog data voltage to the display panel (S500).

[0217] The control of the analog data voltage (S300) includes reducing the level of the analog data voltage Vdata when the gamma drive power measurement exceeds the reference value.

[0218] The control of analog data voltage Vdata (S300) includes reducing the high level of analog data voltage Vdata or increasing the low level of analog data voltage Vdata when the gamma drive power measurement value exceeds the reference value.

[0219] The control of analog data voltage Vdata (S400) includes reducing the refresh rate of analog data voltage Vdata when the gamma drive power measurement value exceeds the reference value.

[0220] When the data driving circuit 130 includes multiple source driver integrated circuits, the analog data voltage is controlled based on the source driver integrated circuit with the largest change in gamma driving power among the multiple source driver integrated circuits.

[0221] The foregoing description has been presented to enable any person skilled in the art to make and use the technical concepts of the invention, and has been provided in the context of a particular application and its requirements. Various modifications, additions, and substitutions to the described embodiments will be apparent to those skilled in the art, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the invention. The foregoing description and figures provide examples of the technical concepts of the invention for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the invention. Therefore, the scope of the invention is not limited to the embodiments shown, but is consistent with the widest scope consistent with the claims. The scope of protection of the invention should be understood based on the appended claims, and all technical concepts within the scope of their equivalents should be understood to be included within the scope of the invention.

Claims

1. A display device, comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels. A gate driving circuit configured to provide multiple scan signals to the plurality of gate lines; A data driving circuit is configured to convert digital image data into analog data voltage and supply the analog data voltage to the plurality of data lines; A power management circuit is configured to supply gamma drive power to the data drive circuit for driving the data drive circuit, and is configured to include a gamma drive power detection circuit for detecting the gamma drive power. as well as A timing controller is configured to control the gate drive circuit and the data drive circuit to change the analog data voltage supplied to the display panel based on a gamma drive power measurement detected by the gamma drive power detection circuit. When the data driving circuit includes multiple source driver integrated circuits, the analog data voltage is changed based on the source driver integrated circuit with the largest change in gamma driving power among the multiple source driver integrated circuits.

2. The display device according to claim 1, wherein, The gamma drive power changes according to the transformation of the digital image data.

3. The display device according to claim 1, wherein, The data driving circuit includes: A shift register, configured to convert digital image data received serially into image data in parallel form in response to a control signal transmitted from the timing controller, and output the image data; A latching circuit is configured to transmit the image data in parallel form on a per-row basis to simultaneously supply the plurality of source driver integrated circuits; A gamma circuit configured to generate multiple gamma reference voltages using the gamma drive power; A digital-to-analog converter configured to convert the parallel-form image data into the analog data voltage in response to a plurality of gamma reference voltages transmitted from the gamma circuit; and An output buffer is configured to supply the analog data voltage to the plurality of data lines.

4. The display device according to claim 3, wherein, The gamma drive power is supplied as the drive voltage for the digital-to-analog converter and the output buffer.

5. The display device according to claim 1, wherein, The gamma drive power detection circuit includes: A current sensing resistor is connected in series with the gamma drive power; An operational amplifier, connected between the two ends of the current-sensing resistor, and configured to sense the bias voltage; and An analog-to-digital converter is configured to convert the bias voltage sensed by the operational amplifier into a digital signal to generate the gamma drive power measurement.

6. The display device according to claim 1, wherein, The timing controller is configured to reduce the level of the digital image data when the measured value of the gamma drive power exceeds a reference value.

7. The display device according to claim 6, wherein, The timing controller is configured to either reduce the high level of the digital image data or increase the low level of the digital image data when the measured value of the gamma drive power exceeds the reference value.

8. The display device according to claim 1, wherein, The timing controller is configured to reduce the refresh rate of the digital image data when the measured value of the gamma drive power exceeds a reference value.

9. A data driving circuit, comprising: A shift register configured to convert digital image data received serially into image data in parallel form, and output the image data; A latching circuit is configured to transmit the image data in parallel form on a per-row basis to simultaneously supply multiple source driver integrated circuits; A gamma circuit configured to generate multiple gamma reference voltages using gamma drive power; A digital-to-analog converter configured to convert the parallel-form image data into analog data voltages in response to a plurality of gamma reference voltages transmitted from the gamma circuit; An output buffer is configured to supply the analog data voltage to the display panel via multiple data lines; A gamma drive power detection circuit, configured to detect the gamma drive power; as well as The plurality of source driver integrated circuits, The analog data voltage is changed based on the source driver integrated circuit with the largest change in gamma drive power among the plurality of source driver integrated circuits.

10. The data driving circuit according to claim 9, wherein, The gamma drive power is supplied as the drive voltage for the digital-to-analog converter and the output buffer.

11. The data driving circuit according to claim 9, wherein, The gamma drive power detection circuit includes: A current sensing resistor is connected in series with the gamma drive power; An operational amplifier connected across the current-sensing resistor to sense a bias voltage; and An analog-to-digital converter is configured to convert the bias voltage sensed by the operational amplifier into a digital signal to generate the gamma drive power measurement.

12. The data driving circuit according to claim 9, wherein, The analog data voltage is controlled based on the gamma drive power measurement value detected by the gamma drive power detection circuit.

13. The data driving circuit according to claim 12, wherein, When the measured value of the gamma drive power exceeds the reference value, the level of the analog data voltage is reduced.

14. The data driving circuit according to claim 12, wherein, When the measured value of the gamma drive power exceeds the reference value, the refresh rate of the analog data voltage is reduced.

15. A method for driving a display device, the display device comprising: The display panel includes multiple gate lines, multiple data lines, and multiple sub-pixels. A gate driving circuit that supplies scan signals to the plurality of gate lines; The method includes a data driving circuit that converts digital image data into analog data voltage and supplies the analog data voltage to the plurality of data lines. Detect the gamma drive power supplied to the data drive circuit; The measured value of the gamma drive power is compared with a reference value; When the measured value of the gamma drive power exceeds the reference value, the analog data voltage is controlled; and The analog data voltage is supplied to the display panel. When the data driving circuit includes multiple source driver integrated circuits, the analog data voltage is controlled based on the source driver integrated circuit with the largest change in gamma driving power among the multiple source driver integrated circuits.

16. The method according to claim 15, wherein, The gamma drive power changes according to the transformation of the digital image data.

17. The method according to claim 15, wherein, Controlling the analog data voltage includes: reducing the level of the analog data voltage when the measured value of the gamma drive power exceeds the reference value.

18. The method according to claim 15, wherein, Controlling the analog data voltage includes: when the measured value of the gamma drive power exceeds the reference value, either reducing the high level of the analog data voltage or increasing the low level of the analog data voltage.

19. The method according to claim 15, wherein, Controlling the analog data voltage includes: reducing the refresh rate of the analog data voltage when the measured value of the gamma drive power exceeds the reference value.

Images