Display driver

Abstract

A display driver includes: a row latch circuit; a first D / A conversion circuit; a second D / A conversion circuit; a first amplifier circuit, the charge of the capacitor of its first switched-capacitor circuit being initialized during a first initialization period and outputting a data voltage during a first output period; a second amplifier circuit, the charge of the capacitor of its second switched-capacitor circuit being initialized during a second initialization period and outputting a data voltage during a second output period; and a control circuit. The control circuit ends the second initialization period of the second amplifier circuit before the output of the first amplifier circuit changes when display data is latched by the row latch circuit at a latch timing.

Description

Technical Field

[0001] The present invention relates to a display driver and the like. Background Art

[0002] Heretofore, a display driver for driving a display panel such as a color liquid crystal panel has been known. As prior art of the display driver, for example, the technologies disclosed in Patent Documents 1 and 2 are available. In the display drivers of Patent Documents 1 and 2, an initialization operation is performed to initialize a capacitor of an amplifier circuit during an initialization period. Then, during an output period, a data voltage is output through an operational amplifier of the amplifier circuit.

[0003] Patent Document 1: Japanese Unexamined Patent Application Publication No. 2017-97174

[0004] Patent Document 2: Japanese Unexamined Patent Application Publication No. 2014-191012

[0005] In a display driver that performs such an initialization operation of the amplifier circuit, it has been found that the display quality of the display panel deteriorates due to noise caused by a latch operation of display data in a row latch circuit. Summary of the Invention

[0006] One aspect of the present invention is a display driver including: a row latch circuit that latches display data for one row; a first D / A conversion circuit that performs D / A conversion on the display data from the row latch circuit; a second D / A conversion circuit that performs D / A conversion on the display data from the row latch circuit; a first amplifier circuit having a first switched capacitor circuit and a first operational amplifier, in a first initialization period, charges of a capacitor of the first switched capacitor circuit are initialized, and in a first output period, the first operational amplifier amplifies an output voltage of the first D / A conversion circuit based on the charges of the capacitor of the first switched capacitor circuit and outputs a data voltage; a second amplifier circuit having a second switched capacitor circuit and a second operational amplifier, in a second initialization period, charges of a capacitor of the second switched capacitor circuit are initialized, and in a second output period, the second operational amplifier amplifies an output voltage of the second D / A conversion circuit based on the charges of the capacitor of the second switched capacitor circuit and outputs a data voltage; and a control circuit that controls the row latch circuit, the first amplifier circuit, and the second amplifier circuit, and the control circuit ends the second initialization period of the second amplifier circuit before an output of the first amplifier circuit changes due to the display data being latched by the row latch circuit at a latch timing. Brief Description of the Drawings

[0007] Figure 1 This is a structural example of the display driver according to this embodiment.

[0008] Figure 2 This is a structural example of an electro-optical device including a display driver.

[0009] Figure 3 This is a detailed structural example of the display driver according to this embodiment.

[0010] Figure 4 This is an explanatory diagram regarding column inversion.

[0011] Figure 5 This is an explanatory diagram regarding three-point inversion.

[0012] Figure 6 This is a signal waveform diagram illustrating the operation of a comparative example.

[0013] Figure 7 This is a signal waveform diagram illustrating the operation of this embodiment.

[0014] Figure 8 This is an explanatory diagram of the switching operation of the amplifier circuits for positive polarity and negative polarity.

[0015] Figure 9 This is an explanatory diagram of the operation of a structural example of the amplifier circuit.

[0016] Figure 10 This is an explanatory diagram of the operation of a structural example of the amplifier circuit.

[0017] Figure 11 This is an explanatory diagram of the operation of a structural example of the amplifier circuit.

[0018] Figure 12 This is an explanatory diagram of the operation of a structural example of the amplifier circuit.

[0019] Figure 13 This is a structural example of the power supply circuit.

[0020] Figure 14 This is an explanatory diagram of the operation of another structural example of the amplifier circuit.

[0021] Figure 15 This is an explanatory diagram of the operation of another structural example of the amplifier circuit.

[0022] Reference numeral description

[0023] 10: Display driver; 20: Row latch circuit; 22: Input latch circuit; 24: Address decoder; 31: First D / A conversion circuit; 32: Second D / A conversion circuit; 41: First amplifier circuit; 42: Second amplifier circuit; 44: Gray-scale voltage generation circuit; 50: Control circuit; 60: Power supply circuit; 62: Switching regulator; 100: Electro-optical device; 110: Display panel; 120: Source driver; 130: Gate driver; 140: Controller; AM; AMM; AMP: Amplifier circuit; BC1 - BC5: Boost circuit; C1, C2, CFA, CIA: Capacitor; CK: Clock signal; DAM, DAP: D / A conversion circuit; DEM, DEP: Conversion circuit; GCM, GCP: Gray-scale voltage generation circuit; GL1 - GLj: Gate line; LP: Latch pulse; MSK: Masking signal; OP: Operational amplifier; OP1: First operational amplifier; OP2: Second operational amplifier; RG1 - RG13: Regulator; SA1 - SA5: Switch; SC: Switched capacitor circuit; SC1: First switched capacitor circuit; SC2: Second switched capacitor circuit; SL1 - SLi: Source line; SMA1, SMA2, SMB2, SPA1, SPB1, SW1 - SW7: Switch; SWA, SWA1, SWA2, SWB, SWB1, SWB2: Switching circuit; TG1: First gate line selection period; TG2: Second gate line selection period; TH1: First horizontal scan period; TH2: Second horizontal scan period; TI1: First initialization period; TI2: Second initialization period; TMK: Masking period; TQ1: First output period; TQ2: Second output period; TS1, TS2: Terminal; VD, VD1, VD2: Data voltage; VDAM, VDAP: Output voltage; VGM, VGP: Gray-scale voltage; t1 - t3: Timing; tm: Latch timing. Detailed implementation manners

[0024] Hereinafter, the present implementation manner will be described. In addition, the present implementation manner described below does not unduly limit the content described in the claims. In addition, all the structures described in the present implementation manner are not necessarily essential components.

[0025] 1. Display driver

[0026] Figure 1 An example of the structure of the display driver 10 of the present implementation manner is shown. The display driver 10 includes a row latch circuit 20, a first D / A conversion circuit 31, a second D / A conversion circuit 32, a first amplifier circuit 41, a second amplifier circuit 42, and a control circuit 50. In addition, the display driver 10 can include a power supply circuit 60. In addition, the display driver 10 is not limited to Figure 1The structure can implement various deformations such as omitting some of its structural elements or adding other structural elements. For example, other circuit blocks can also be provided between the row latch circuit 20 and the first D / A conversion circuit 31 and the second D / A conversion circuit 32, and between the first D / A conversion circuit 31, the second D / A conversion circuit 32 and the first amplifier circuit 41, the second amplifier circuit 42.

[0027] The row latch circuit 20 is a circuit that latches display data. For example, the row latch circuit 20 latches one row of display data. For example, the row latch circuit 20 latches the display data based on the latch pulse LP from the control circuit 50. One row of display data is, for example, the number of display data corresponding to the multiple source lines driven by the display driver 10 during the horizontal scan period. In addition, the row latch circuit 20 only needs to be able to latch at least one row of display data. Each latch of the row latch circuit 20 can be composed of multiple latches implemented by a storage circuit such as a flip-flop circuit.

[0028] The first D / A conversion circuit 31 and the second D / A conversion circuit 32 perform D / A conversion on the display data from the row latch circuit 20. For example, the first D / A conversion circuit 31 performs D / A conversion on the display data corresponding to the source lines driven by the first amplifier circuit 41 provided at the subsequent stage of the first D / A conversion circuit 31. The second D / A conversion circuit 32 performs D / A conversion on the display data corresponding to the source lines driven by the second amplifier circuit 42 provided at the subsequent stage of the second D / A conversion circuit 32. The first D / A conversion circuit 31 and the second D / A conversion circuit 32 output the gray-scale voltage selected from the multiple gray-scale voltages from an unillustrated gray-scale voltage generation circuit according to the display data from the row latch circuit 20 as the output voltage.

[0029] The first amplifier circuit 41 includes a first switched-capacitor circuit SC1 and a first operational amplifier OP1. The first switched-capacitor circuit SC1 is a circuit composed of at least one capacitor and at least one switch, and controls the voltage applied to the capacitor through the on and off of the switch. The first operational amplifier OP1 has an inverting input terminal, a non-inverting input terminal, and an output terminal. For example, at least one of these terminals is connected to the charge storage node of the capacitor of the first switched-capacitor circuit SC1. And in the first amplifier circuit 41, in the following Figure 7During the first initialization period TI1, the charge of the capacitor of the first switched capacitor circuit SC1 is initialized. Thus, by initializing the charge stored in the capacitor during the first initialization period TI1, for example, the offset deviation of the first operational amplifier OP1 can be eliminated. For example, during the first initialization period TI1, by applying a given voltage such as a reference voltage to the capacitor of the first switched capacitor circuit SC1, charge storage for initializing the capacitor is performed. And, in the first amplifier circuit 41, during the first output period TQ1, the first operational amplifier OP1 amplifies the output voltage of the first D / A conversion circuit 31 based on the charge of the capacitor of the first switched capacitor circuit SC1 and outputs a data voltage VD1. The first output period TQ1 is a period following the first initialization period TI1. For example, in a state where charge is stored in the capacitor during the first initialization period TI1, during the first output period TQ1, the output voltage of the first D / A conversion circuit 31 is input to the first amplifier circuit 41, whereby the first operational amplifier OP1 outputs a data voltage VD1 corresponding to the output voltage of the first D / A conversion circuit 31. For example, the data voltage VD1 is a voltage that varies according to the output voltage of the first D / A conversion circuit 31.

[0030] The second amplifier circuit 42 includes a second switched capacitor circuit SC2 and a second operational amplifier OP2. The second switched capacitor circuit SC2 is a circuit composed of at least one capacitor and at least one switch, and controls the voltage applied to the capacitor by turning the switch on and off. The second operational amplifier OP2 has an inverting input terminal, a non-inverting input terminal, and an output terminal, and for example, at least one of these terminals is connected to the charge storage node of the capacitor of the second switched capacitor circuit SC2. And, in the second amplifier circuit 42, during Figure 7During the second initialization period TI2, the charge of the capacitor of the second switched capacitor circuit SC2 is initialized. In this way, by initializing the charge accumulated in the capacitor during the second initialization period TI2, for example, the offset deviation of the second operational amplifier OP2 can be eliminated. For example, during the second initialization period TI2, by applying a given voltage such as a reference voltage to the capacitor of the second switched capacitor circuit SC2, charge accumulation for initializing the capacitor is performed. And, in the second amplifier circuit 42, during the second output period TQ2, the second operational amplifier OP2 amplifies the output voltage of the second D / A conversion circuit 32 based on the charge of the capacitor of the second switched capacitor circuit SC2 and outputs a data voltage VD2. The second output period TQ2 is a period following the second initialization period TI2. For example, in a state where charge is accumulated in the capacitor during the second initialization period TI2, during the second output period TQ2, the output voltage of the second D / A conversion circuit 32 is input to the second amplifier circuit 42, whereby the second operational amplifier OP2 outputs a data voltage VD2 corresponding to the output voltage of the second D / A conversion circuit 32. For example, the data voltage VD2 is a voltage that varies according to the output voltage of the second D / A conversion circuit 32.

[0031] The control circuit 50 controls the row latch circuit 20, the first amplifier circuit 41, and the second amplifier circuit 42. In addition, the control circuit 50 also controls other circuit blocks of the display driver 10 such as the power supply circuit 60. For example, the control circuit 50 controls the latching operation of the row latch circuit 20 by outputting a latch pulse LP to the row latch circuit 20. In addition, the control circuit 50 controls the switched capacitor operations of the first switched capacitor circuit SC1 and the second switched capacitor circuit SC2 by outputting control signals such as switched control signals to the first amplifier circuit 41 and the second amplifier circuit 42. The control circuit 50 is, for example, a logic circuit, and is, for example, a circuit implemented by automatic placement and routing such as a gate array.

[0032] And, as will be described later Figure 7As described above, before the display data is latched by the row latch circuit 20 at the latching timing and the output of the first amplifier circuit 41 changes, the control circuit 50 ends the second initialization period TI2 of the second amplifier circuit 42. For example, at the latching timing tm of the row latch circuit 20 based on the latch pulse LP from the control circuit 50, the display data of the row latch circuit 20 changes, so that the output voltage of the first D / A conversion circuit 31 changes, and thus the output of the first amplifier circuit 41 also changes. Moreover, before the latching timing tm of the row latch circuit 20, the control circuit 50 ends the second initialization period TI2 of the second amplifier circuit 42 so that the change in the output of the first amplifier circuit 41 does not adversely affect the initialization operation during the second initialization period TI2 of the second amplifier circuit 42. Specifically, the control circuit 50, for example, uses the control signal for the initialization operation of the second amplifier circuit 42 to perform the control to end the second initialization period TI2.

[0033] Thereby, it is possible to prevent the noise caused by the change in the output of the first amplifier circuit 41 due to the latching of the display data in the row latch circuit 20 from adversely affecting the initialization operation of the second amplifier circuit 42. For example, it is possible to prevent the following situation: the voltage such as the reference voltage applied to the capacitor of the second switched capacitor circuit SC2 during the second initialization period TI2 of the second amplifier circuit 42 changes due to the noise caused by the change in the output of the first amplifier circuit 41, and the charge stored in the capacitor changes.

[0034] Similarly, before the display data is latched by the row latch circuit 20 at the latching timing and the output of the second amplifier circuit 42 changes, the control circuit 50 ends the first initialization period TI1 of the first amplifier circuit 41. For example, at the latching timing tm of the row latch circuit 20 based on the latch pulse LP from the control circuit 50, the display data of the row latch circuit 20 changes, so that the output voltage of the second D / A conversion circuit 32 also changes, and thus the output of the second amplifier circuit 42 also changes. Moreover, before the latching timing tm of the row latch circuit 20, the control circuit 50 ends the first initialization period TI1 of the first amplifier circuit 41 so that the change in the output of the second amplifier circuit 42 does not adversely affect the initialization operation during the first initialization period TI1 of the first amplifier circuit 41. Specifically, the control circuit 50, for example, uses the control signal for the initialization operation of the first amplifier circuit 41 to perform the control to end the first initialization period TI1.

[0035] Accordingly, it is possible to prevent noise caused by changes in the output of the second amplifier circuit 42 due to the latching of display data in the line latch circuit 20 from having an adverse effect on the initialization operation of the first amplifier circuit 41. For example, it is possible to prevent the following situation: during the first initialization period TI1 of the first amplifier circuit 41, the voltage such as the reference voltage applied to the capacitor of the first switched capacitor circuit SC1 changes due to noise caused by changes in the output of the second amplifier circuit 42, and the charge accumulated in the capacitor changes.

[0036] In addition, the power supply circuit 60 includes a switching regulator 62 and supplies a power supply voltage to the first amplifier circuit 41 and the second amplifier circuit 42. In addition, the power supply circuit 60 also supplies a power supply voltage to circuit modules other than the first amplifier circuit 41 and the second amplifier circuit 42. Moreover, the switching regulator 62 of the power supply circuit 60 performs a switching regulation operation for boosting the voltage based on the power supply voltage, and the power supply voltage based on the voltage generated by this switching regulation operation is supplied to the first amplifier circuit 41 and the second amplifier circuit 42. The power supply voltages supplied to the first amplifier circuit 41 and the second amplifier circuit 42 may be different power supply voltages or the same power supply voltage. The switching regulator 62 is a DC-DC converter that performs a switching regulation operation using, for example, an inductor to convert the input voltage into an output voltage different from the input voltage. The inductor may be an external component of the display driver 10 or an internal component.

[0037] Moreover, as will be described later Figure 7 As shown, the control circuit 50 stops the operation of the switching regulator 62 at least during the second initialization period TI2. For example, during the second initialization period TI2 of the second amplifier circuit 42, the control circuit 50 outputs a mask signal MSK, which is a control signal for prohibiting the operation of the switching regulator 62, to stop the operation of the switching regulator 62. That is, during Figure 7 the masking period TMK, the mask signal MSK becomes an effective level, and thus the operation of the switching regulator 62 stops during the second initialization period TI2.

[0038] If this method is adopted, it is possible to prevent noise generated by the switching regulation operation of the switching regulator 62 from having an adverse effect on the initialization operation of the second amplifier circuit 42 during the second initialization period TI2. For example, it is possible to prevent the following situation: during the second initialization period TI2 of the second amplifier circuit 42, the voltage such as the reference voltage applied to the capacitor of the second switched capacitor circuit SC2 changes due to the noise of the switching regulation operation, and the charge accumulated in the capacitor changes.

[0039] In addition, during the first initialization period TI1, for example, the control circuit 50 also stops the operation of the switching regulator 62. For example, during the first initialization period TI1 of the first amplifier circuit 41, the control circuit 50 outputs a mask signal MSK as a control signal for prohibiting the operation of the switching regulator 62, thereby stopping the operation of the switching regulator 62. That is, during the Figure 7 mask period TMK of, the mask signal MSK becomes an effective level, so that the operation of the switching regulator 62 stops during the first initialization period TI1.

[0040] If this method is adopted, it is possible to prevent the noise generated by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the first amplifier circuit 41 during the first initialization period TI1. For example, it is possible to prevent the following situation: during the first initialization period TI1 of the first amplifier circuit 41, the reference voltage and other voltages applied to the capacitors of the first switched capacitor circuit SC1 change due to the noise of the switching regulation operation, and the charge stored in the capacitors changes.

[0041] Figure 2 FIG. shows a structural example of an electro-optical device 100 including the display driver 10 of the present embodiment. The display driver 10 includes a source driver 120 that drives a plurality of source lines of the display panel 110. In addition, the display driver 10 may also include a gate driver 130 that drives a plurality of gate lines of the display panel 110. Moreover, the electro-optical device 100 includes the display driver 10 and the display panel 110. Additionally, the electro-optical device 100 can include a controller 140.

[0042] The display panel 110 is, for example, a liquid crystal panel. For example, the display panel 110 is an active matrix type TFT liquid crystal panel. The display panel 110 includes a plurality of source lines, a plurality of gate lines, and a plurality of pixels provided at the cross positions of each source line and each gate line corresponding to each pixel. Moreover, the source driver 120 outputs data voltages to the plurality of source lines of the display panel 110, and the gate driver 130 performs gate line selection for sequentially selecting the plurality of gate lines of the display panel 110. The source lines correspond to data lines, the gate lines correspond to scan lines, and the gate line selection corresponds to scan line selection.

[0043] Figure 3 FIG. shows a detailed structural example of the display driver 10 of the present embodiment. In Figure 3In the circuit, an input latch circuit 22 is provided on the front stage side of the line latch circuit 20. The input latch circuit 22 includes a plurality of latches LB1 and latch LB2. The input latch circuit 22 is input with display data DTR1, DTG1, DTB1, DTR2, DTG2, and DTB2, and latches these display data according to a latch signal based on a decoding signal from an address decoder 24 that decodes the address AD and a clock signal CK. DTR1, DTG1, and DTB1 are 8-bit display data of R, G, and B of the first pixel respectively. DTR2, DTG2, and DTB2 are 8-bit display data of R, G, and B of the second pixel respectively.

[0044] The display data latched by the input latch circuit 22 is latched in the line latch circuit 20 based on a latch pulse LP. The line latch circuit 20 includes a plurality of latches LA1 and latch LA2. Moreover, the switching circuit SWB performs the following display data exchange process: in the Nth frame, the display data from the latches LA1 and LA2 are respectively output to the conversion circuits DEP and DEM, and in the (N + 1)th frame, the display data from the latches LA1 and LA2 are respectively output to the conversion circuits DEM and DEP. That is, the switching circuit SWB performs the display data exchange process based on a polarity signal POL. Moreover, the display data from the conversion circuits DEP and DEM are subjected to voltage level shift by level shifters LVP and LVM, and are input to D / A conversion circuits DAP and DAM.

[0045] The D / A conversion circuit DAP for positive polarity outputs, as an output voltage, a gray-scale voltage selected from the positive-polarity gray-scale voltage VGP according to the display data, to the positive-polarity amplifier circuit AMP. The D / A conversion circuit DAM for negative polarity outputs, as an output voltage, a gray-scale voltage selected from the negative-polarity gray-scale voltage VGM based on the display data, to the negative-polarity amplifier circuit AMM. For example, Figure 3 the amplifier circuit AMP corresponds to Figure 1 the first amplifier circuit 41, and the amplifier circuit AMM corresponds to the second amplifier circuit 42, but it can also be the opposite. In addition, Figure 3 the D / A conversion circuit DAP corresponds to Figure 1 the first D / A conversion circuit 31, and the D / A conversion circuit DAM corresponds to the second D / A conversion circuit 32, but it can also be the opposite.

[0046] The switching circuit SWA outputs the data voltage from the amplifier circuit AMP for positive polarity to the terminal TS1 in the Nth frame, and outputs the data voltage from the amplifier circuit AMM for negative polarity to the terminal TS2. Further, the switching circuit SWA outputs the data voltage from the amplifier circuit AMM for negative polarity to the terminal TS1 in the (N + 1)th frame, and outputs the data voltage from the amplifier circuit AMP for positive polarity to the terminal TS2.

[0047] As Figure 3 shown, the switching circuit SWB exchanges the display data frame by frame, and the switching circuit SWA exchanges the data voltages for positive and negative polarities, thereby implementing Figure 4 the column inversion driving of the display driver 10 shown. Figure 4 Among them, SL1 to SLn are source lines corresponding to the data lines, and GL1 to GLm are gate lines corresponding to the scan lines. For example, in Figure 4 in the Nth frame, the odd-numbered source lines are driven with positive polarity, and the even-numbered source lines are driven with negative polarity. Driving with positive polarity means driving with a data voltage of positive polarity, for example, and driving with negative polarity means driving with a data voltage of negative polarity, for example. Further, in the (N + 1)th frame, the odd-numbered source lines are driven with negative polarity, and the even-numbered source lines are driven with positive polarity. Thus, Figure 4 the column inversion driving is performed.

[0048] Thus, in the present embodiment, the first amplifier circuit 41 is the amplifier circuit AMP for positive polarity that outputs a positive voltage, and the second amplifier circuit 42 is the amplifier circuit AMM for negative polarity that outputs a negative voltage. Thereby, it is possible to perform the inversion driving formed by the positive polarity driving based on the amplifier circuit AMP for positive polarity and the negative polarity driving based on the amplifier circuit AMM for negative polarity of the display driver 10. Specifically, it is possible to perform, for example, Figure 4 the column inversion driving shown. Further, the inversion driving of the display driver 10 is not limited to such column inversion driving, and may also be Figure 5 the inversion driving every several points such as the 3-point inversion driving shown. For example, in Figure 5Among them, the pixels corresponding to the intersections of the source line SL1 and the gate lines GL1, GL2, and GL3 are driven with a positive polarity in the Nth frame and with a negative polarity in the (N + 1)th frame. In addition, the pixels corresponding to the intersections of the source line SL2 and the gate lines GL1, GL2, and GL3 are driven with a negative polarity in the Nth frame and with a positive polarity in the (N + 1)th frame. On the other hand, the pixels corresponding to the intersections of the source line SL1 and the gate lines GL4, GL5, and GL6 are driven with a negative polarity in the Nth frame and with a positive polarity in the (N + 1)th frame. In addition, the pixels corresponding to the intersections of the source line SL2 and the gate lines GL4, GL5, and GL6 are driven with a positive polarity in the Nth frame and with a negative polarity in the (N + 1)th frame.

[0049] 2. Operation

[0050] Next, the detailed operation of the display driver 10 of the present embodiment will be described. First, use Figure 6 The operation of the comparative example of the present embodiment will be described. In Figure 6 During the first initialization period TI1, the source line SLi becomes a high impedance state, and the initialization operation of the first amplifier circuit 41 is performed. In addition, during the second initialization period TI2, the adjacent source line SLi+1 of the source line SLi becomes a high impedance state, and the initialization operation of the second amplifier circuit 42 is performed.

[0051] And, in Figure 6 In the comparative example, during the first initialization period TI1, the latch pulse LP becomes valid, and the display data is latched into the row latch circuit 20. In addition, during the second initialization period TI2, the latch pulse LP also becomes valid, and the display data is latched into the row latch circuit 20.

[0052] In this case, for example, when the display data is latched into the row latch circuit 20 during the second initialization period TI2, the display data is output to the first D / A conversion circuit 31, and the output voltage of the first D / A conversion circuit 31 is output to the first amplifier circuit 41, so that the output of the first amplifier circuit 41 changes. Then, the noise caused by the change in the output of the first amplifier circuit 41 has an adverse effect on the second amplifier circuit 42 that performs the initialization operation during the second initialization period TI2, and the display quality is reduced. For example, the following situation occurs: the noise caused by the change in the output of the first amplifier circuit 41 is superimposed on the voltage such as the reference voltage described later of the capacitor of the second switched capacitor circuit SC2 applied to the second amplifier circuit 42 for the initialization operation. As a result, the charge stored in the capacitor of the second switched capacitor circuit SC2 changes, and the data voltage output by the second amplifier circuit 42 during the second output period TQ2 changes, so that the display quality of the display image on the display panel 110 is reduced.

[0053] Similarly, for example, when display data is latched in the line latch circuit 20 during the first initialization, the display data is output to the second D / A conversion circuit 32, and the output voltage of the second D / A conversion circuit 32 is output to the second amplifier circuit 42, so that the output of the second amplifier circuit 42 changes. Then, the noise caused by the change in the output of the second amplifier circuit 42 has an adverse effect on the first amplifier circuit 41 that performs the initialization operation during the first initialization TI1, and the display quality deteriorates. For example, the following situation occurs: for a voltage such as a reference voltage described later applied to the capacitor of the first switched capacitor circuit SC1 of the first amplifier circuit 41 for performing the initialization operation, noise caused by the change in the output of the second amplifier circuit 42 is superimposed. As a result, the charge stored in the capacitor of the first switched capacitor circuit SC1 changes, and the data voltage output by the first amplifier circuit 41 during the first output period TQ1 changes, so that the display quality of the display image on the display panel 110 deteriorates.

[0054] For example, in the case of Figure 4 performing column inversion driving as described above, when the even-numbered second amplifier circuits 42 connected to the even-numbered source lines perform the initialization operation and display data is latched in the line latch circuit 20, the output of the odd-numbered first amplifier circuits 41 connected to the odd-numbered source lines changes. Then, the noise caused by the change in the output of the odd-numbered first amplifier circuits 41 is transmitted to the power supply circuit 60, and the voltage such as the reference voltage supplied by the power supply circuit 60 to the second amplifier circuits 42 changes. As a result, the charge stored in the capacitor of the second switched capacitor circuit SC2 of the even-numbered second amplifier circuits 42 changes during the second initialization period TI2, and the data voltage output by the second amplifier circuits 42 during the second output period TQ2 changes, and the display quality deteriorates. For example, a situation such as generating two horizontal stripes on the display panel 110 occurs.

[0055] Similarly, when the odd-numbered first amplifier circuits 41 perform the initialization operation and display data is latched in the line latch circuit 20, the output of the even-numbered second amplifier circuits 42 changes. Then, the noise caused by the change in the output of the even-numbered second amplifier circuits 42 is transmitted to the power supply circuit 60, and the voltage such as the reference voltage supplied by the power supply circuit 60 to the first amplifier circuits 41 changes. As a result, the charge stored in the capacitor of the first switched capacitor circuit SC1 of the odd-numbered first amplifier circuits 41 changes during the first initialization period TI1, and the data voltage output by the first amplifier circuits 41 during the first output period TQ1 changes, and the display quality deteriorates.

[0056] Therefore, in the present embodiment, a method is adopted in which the initialization period ends before the display data is latched in the row latch circuit 20 at the latching timing. Figure 7 is a signal waveform diagram for explaining the operation of the present embodiment.

[0057] In Figure 7 the period between timings t1 and t2 is the first horizontal scanning period TH1, and the period between timings t2 and t3 is the second horizontal scanning period TH2. In the first horizontal scanning period TH1, the gate line GLj becomes a selected state during the first gate line selection period TG1, and a data voltage is written to the corresponding pixel. Further, in the second horizontal scanning period TH2, the gate line GLj+1 becomes a selected state during the second gate line selection period TG2, and a data voltage is written to the corresponding pixel. The first gate line selection period TG1 and the second gate line selection period TG2 respectively correspond to the first scanning line selection period and the second scanning line selection period.

[0058] During the first initialization period TI1, the source line SLi becomes a high impedance state. For example, the output of the first amplifier circuit 41 that drives the source line SLi becomes a high impedance state. This high impedance state is achieved by turning off the output switch provided at the output node of the first amplifier circuit 41. Further, for example, according to the first initialization signal INP from the control circuit 50, the initialization operation of the first amplifier circuit 41 is performed during the first initialization period TI1. That is, during the first initialization period TI1, the charge stored in the capacitor of the first switched capacitor circuit SC1 of the first amplifier circuit 41 is initialized. Then, during the first output period TQ1 after the first initialization period TI1, the source line SLi is driven with a positive polarity. That is, the first amplifier circuit 41 drives the source line SLi with a positive-polarity voltage. Further, the first amplifier circuit 41 also drives the source line SLi with a positive polarity during the second horizontal scanning period TH2, which is the next period after the first horizontal scanning period TH1.

[0059] During the second initialization period TI2 in TI2, the adjacent source line SLi+1 of the source line SLi becomes a high impedance state. For example, the output of the second amplifier circuit 42 that drives the source line SLi+1 becomes a high impedance state. This high impedance state is achieved by turning off the output switch provided at the output node of the second amplifier circuit 42. Also, for example, based on the second initialization signal INM from the control circuit 50, the initialization operation of the second amplifier circuit 42 is performed during the second initialization period TI2. That is, during the second initialization period TI2, the charge stored in the capacitor of the second switched capacitor circuit SC2 of the second amplifier circuit 42 is initialized. Then, during the second output period TQ2 after the second initialization period TI2, the source line SLi+1 is driven with a negative polarity. That is, the second amplifier circuit 42 drives the source line SLi+1 with a negative-polarity voltage. In addition, the second amplifier circuit 42 also drives the source line SLi with a negative polarity during the next horizontal scan period after the second horizontal scan period TH2.

[0060] Also, as Figure 7 shown, in the present embodiment, before the latch timing tm at which the display data is latched by the row latch circuit 20, the second initialization period TI2 of the second amplifier circuit 42 ends. Similarly, before the latch timing tm at which the display data is latched by the row latch circuit 20, the first initialization period TI1 of the first amplifier circuit 41 ends.

[0061] For example, in Figure 6 the comparative example, during the second initialization period TI2 of the second amplifier circuit 42, the display data is latched by the row latch circuit 20. Therefore, the noise caused by the change in the output of the first amplifier circuit 41 due to the latching of the display data has an adverse effect on the initialization operation of the second amplifier circuit 42 and degrades the display quality. In contrast, in the present embodiment, before the latch timing tm at which the display data is latched by the row latch circuit 20, the second initialization period TI2 of the second amplifier circuit 42 ends. Therefore, at the latch timing tm of the display data, the initialization operation of the second amplifier circuit 42 has ended, so it is possible to prevent the noise caused by the change in the output of the first amplifier circuit 41 due to the latching of the display data from having an adverse effect on the initialization operation of the second amplifier circuit 42, and the display quality can be improved. In addition, in Figure 6In the comparative example, during the first initialization period TI1 of the first amplifier circuit 41, the display data is latched by the row latch circuit 20. Therefore, the noise caused by the change in the output of the second amplifier circuit 42 due to the latching of the display data has an adverse effect on the initialization operation of the first amplifier circuit 41, resulting in a decrease in display quality. In contrast, in the present embodiment, before the latching timing tm at which the display data is latched by the row latch circuit 20, the first initialization period TI1 of the first amplifier circuit 41 ends. Therefore, at the latching timing tm of the display data, the initialization operation of the first amplifier circuit 41 has ended, so it is possible to prevent the noise caused by the change in the output of the second amplifier circuit 42 due to the latching of the display data from having an adverse effect on the initialization operation of the first amplifier circuit 41, and the display quality can be improved.

[0062] In addition, as Figure 1 shown, the display driver 10 includes a power supply circuit 60, which has a switching regulator 62 and supplies a power supply voltage to the first amplifier circuit 41 and the second amplifier circuit 42. Moreover, the control circuit 50 stops the operation of the switching regulator 62 at least during the second initialization period TI2. Specifically, as Figure 7 shown, the control circuit 50 sets the shielding signal MSK to a high level, i.e., an active level, during the second initialization period TI2. In this way, when the shielding signal MSK becomes active, the operation of the switching regulator 62 stops. Thereby, it is possible to prevent the noise generated by the switching regulation operation of the switching regulator 62 from having an adverse effect on the initialization operation of the second amplifier circuit 42, and thus it is possible to prevent a decrease in display quality due to this noise. Similarly, the control circuit 50 stops the operation of the switching regulator 62 at least during the first initialization period TI1. Specifically, as Figure 7 shown, the control circuit 50 sets the shielding signal MSK to an active level during the first initialization period TI1, thereby stopping the operation of the switching regulator 62. Thereby, it is possible to prevent the noise generated by the switching regulation operation of the switching regulator 62 from having an adverse effect on the initialization operation of the first amplifier circuit 41, and thus it is possible to prevent a decrease in display quality due to this noise. In addition, the switching regulator 62 only needs to stop operating at least during the first initialization period TI1 and the second initialization period TI2. For example, in Figure 7 , the shielding period TMK during which the operation of the switching regulator 62 stops becomes a period longer than the first initialization period TI1 and the second initialization period TI2. In addition, even if the operation of the switching regulator 62 stops, the regulated voltage generated by the switching regulation operation is maintained and output.

[0063] In addition, in the present embodiment, as Figure 7As shown, the control circuit 50 alternately performs the initialization operation of the first amplifier circuit 41 during the first initialization period TI1 and the initialization operation of the second amplifier circuit 42 during the second initialization period TI2 in each horizontal scanning period. For example, in Figure 7 , whenever the horizontal scanning period is switched as from the first horizontal scanning period TH1 to the second horizontal scanning period TH2, the initialization operation of the first amplifier circuit 41 during the first initialization period TI1 and the initialization operation of the second amplifier circuit 42 during the second initialization period TI2 are alternately performed. For example, when the initialization operations of both the first amplifier circuit 41 and the second amplifier circuit 42 are performed within the same initialization period, there may be an adverse situation such as a reduction in display quality due to fluctuations in the power supply voltage or the like. Regarding this point, as Figure 7 shown, by alternately performing the initialization operation of the first amplifier circuit 41 and the initialization operation of the second amplifier circuit 42 in each horizontal scanning period, it is possible to prevent the occurrence of such an adverse situation. In addition, in Figure 7 , the initialization operation of the first amplifier circuit 41 is performed before the timing t1 at which the first horizontal scanning period TH1 starts, and the initialization operation of the second amplifier circuit 42 is performed before the timing t2 at which the second horizontal scanning period TH2 starts.

[0064] In addition, in the present embodiment, as Figure 7 shown, after the first gate line selection period TG1 in the first horizontal scanning period TH1, the control circuit 50 performs the initialization operation of the second amplifier circuit 42 during the second initialization period TI2. Then, before the output of the first amplifier circuit 41 changes when the display data is latched by the row latching circuit 20 at the latching timing tm, the control circuit 50 ends the second initialization period TI2 of the second amplifier circuit 42. And after the second gate line selection period TG2 in the second horizontal scanning period TH2, the control circuit 50 performs the initialization operation of the first amplifier circuit 41 during the first initialization period TI1. Then, before the output of the second amplifier circuit 42 changes when the display data is latched by the row latching circuit 20 at the latching timing tm, the control circuit 50 ends the first initialization period TI1 of the first amplifier circuit 41.

[0065] Thus, after writing the data voltage to the pixels selected in TG1 during the first gate line selection of TH1 during the first horizontal scan, the initialization operation of the second amplifier circuit 42 can be performed during the second initialization period TI2. Then, at the latch timing tm after the second initialization period TI2, the display data is latched in the line latch circuit 20, thereby preventing noise caused by the change in the output of the first amplifier circuit 41 due to the latching of the display data from adversely affecting the initialization operation of the second amplifier circuit 42. Then, after the display data is latched in the line latch circuit 20 at the latch timing tm, the data voltage is written to the pixels selected in TG2 during the second gate line selection of TH2 during the second horizontal scan, and the initialization operation of the first amplifier circuit 41 can be performed during the subsequent first initialization period TI1. Then, at the latch timing tm after the first initialization period TI1, the display data is latched in the line latch circuit 20, thereby preventing noise caused by the change in the output of the second amplifier circuit 42 due to the latching of the display data from adversely affecting the initialization operation of the first amplifier circuit 41.

[0066] In addition, in the present embodiment, as Figure 7 shown, before switching from the first horizontal scan period TH1 to the second horizontal scan period TH2, the control circuit 50 ends the second initialization period TI2. Then, after switching from the first horizontal scan period TH1 to the second horizontal scan period TH2, the control circuit 50 performs the latching operation of the line latch circuit 20 during the second horizontal scan period TH2. That is, before the timing t2 when the horizontal scan period is switched from the first horizontal scan period TH1 to the second horizontal scan period TH2, the initialization operation of the second amplifier circuit 42 is ended. Then, after the timing t2 when the horizontal scan period is switched, the line latch circuit 20 performs the latching operation. Similarly, before the timing t1 when the horizontal scan period is switched, the initialization operation of the first amplifier circuit 41 is ended. Then, after the timing t1 when the horizontal scan period is switched, the line latch circuit 20 performs the latching operation. In this way, the latching operation of the line latch circuit 20 can be ended as quickly as possible, the data voltage can be written to the pixels within the subsequent second gate line selection period TG2 or the first gate line selection period TG1, and the writing time of the data voltage can be extended.

[0067] For example, in Figure 6 the comparative example, if only the timing of the latch pulse LP is delayed until after the initialization operation, the writing time of the data voltage becomes shorter corresponding to the amount of delay of the timing of the latch pulse LP. In this way, when the writing time of the data voltage becomes short, the adaptability to the pixels makes it impossible to write the data voltage, resulting in a decrease in image quality.

[0068] Regarding this point, inFigure 7 Among them, before the timings t1 and t2 at which switching is performed during the horizontal scan, the initialization operations of the respective amplifier circuits are completed, and after the timings t1 and t2, the line latch circuit 20 performs a latching operation. That is, the initialization operations of the respective amplifier circuits are performed during the horizontal scan period before the horizontal scan period in which the data voltage is output by the respective amplifier circuits. In this way, it is possible to prevent the adverse effects of noise caused by latching display data to the line latch circuit 20 on the initialization operation, and it is also possible to extend the writing time of the data voltage, and the display quality of the display panel 110 can be improved.

[0069] 3. Amplifier circuit, power supply circuit

[0070] Next, use Figures 8 to 10 to describe the detailed structural examples and operations of the amplifier circuits of the first amplifier circuit 41 and the second amplifier circuit 42 respectively.

[0071] In Figure 8 the display driver 10, there are provided a switching circuit SWA1, SWA2, positive-polarity and negative-polarity amplifier circuits AMP, AMM, positive-polarity and negative-polarity D / A conversion circuits DAP, DAM, a switching circuit SWB1, SWB2, and a grayscale voltage generation circuit 44. The positive-polarity amplifier circuit AMP and the D / A conversion circuit DAP correspond to the first amplifier circuit 41 and the first D / A conversion circuit 31, for example. The negative-polarity amplifier circuit AMM and the D / A conversion circuit DAM correspond to the second amplifier circuit 42 and the second D / A conversion circuit 32, for example. The switching circuit SWA1 includes switches SPA1, SMA1, and the switching circuit SWA2 includes switches SMA2, SPA2. The switching circuit SWB1 includes switches SPB1, SMB1, and the switching circuit SWB2 includes switches SMB2, SPB2. Moreover, the grayscale voltage generation circuit 44 includes a positive-polarity grayscale voltage generation circuit GCP that outputs a plurality of positive-polarity grayscale voltages and a negative-polarity grayscale voltage generation circuit GCM that outputs a plurality of negative-polarity grayscale voltages.

[0072] In a first state where the source lines SL1 and SL2 connected to the terminals TS1 and TS2 are driven with positive and negative polarities respectively, the switches SPA1, SMA2, SPB1, and SMB2 are turned on. In this case, the D / A conversion circuit DAP for positive polarity selects a voltage corresponding to the display data for the source line SL1 from among a plurality of gray-scale voltages for positive polarity. The amplifier circuit AMP for positive polarity drives the source line SL1 with the data voltage VD1 of positive polarity based on the selected voltage. On the other hand, the D / A conversion circuit DAM for negative polarity selects a voltage corresponding to the display data for the source line SL2 from among a plurality of gray-scale voltages for negative polarity. The amplifier circuit AMM for negative polarity drives the source line SL2 with the data voltage VD2 of negative polarity based on the selected voltage.

[0073] On the other hand, in a second state where the source lines SL1 and SL2 are driven with negative and positive polarities, the switches SMA1, SPA2, SMB1, and SPB2 are turned on. In this case, the D / A conversion circuit DAM for negative polarity selects a voltage corresponding to the display data for the source line SL1 from among a plurality of gray-scale voltages for negative polarity. The amplifier circuit AMM for negative polarity drives the source line SL1 with the data voltage VD1 of negative polarity based on the selected voltage. On the other hand, the D / A conversion circuit DAP for positive polarity selects a voltage corresponding to the display data for the source line SL2 from among a plurality of gray-scale voltages for positive polarity. The amplifier circuit AMP for positive polarity drives the source line SL2 with the data voltage VD2 of positive polarity based on the selected voltage.

[0074] Next, use Figure 9 , Figure 10 to describe the structure and operation of the amplifier circuit AMP for positive polarity. As Figure 9 shown, the amplifier circuit AMP for positive polarity includes a first operational amplifier OP1 and a first switched-capacitor circuit SC1 composed of capacitors CIA, CFA, and switches SA1 to SA5. The amplifier circuit AMP for positive polarity is a circuit that receives the output voltage VDAP of the D / A conversion circuit DAP for positive polarity and outputs the data voltage VD1 to drive the data line. The output voltage VDAP of the D / A conversion circuit DAP is, for example, 0V to +6V.

[0075] The capacitor CIA is disposed between the summing node NEGA connected to the inverting input terminal of the first operational amplifier OP1 and the node NA1. The inverting input terminal is the first input terminal. The capacitor CFA is disposed between the summing node NEGA and the node NA2. These capacitors CIA and CFA can each be composed of a plurality of unit capacitors, for example.

[0076] The switch SA1 is set between the input node NIA of the amplifier circuit AMP for positive polarity and the node NA1. The switch SA2 is set between the input node of the reference voltage VDDRMP and the node NA1. The switch SA3 is set between the node NA2 and the output node NQA. The switch SA4 is set between the node NA2 and the input node of the reference voltage VDDRMP. The switch SA5 is set between the summing node NEGA and the output node NQA. These switches SA1 to SA5 can be formed by CMOS transistors, specifically, can be formed by transmission gates composed of P-type transistors and N-type transistors. Moreover, these transistors are turned on or off by the switch control signals output by the control circuit 50. In addition, the reference voltage VDDRMP is, for example, the voltage between the power supply voltage VDD on the high potential side and the power supply voltage VSS on the low potential side. VDD is, for example, +6V, and VSS is, for example, 0V. For example, VDDRMP = (VDD + VSS) / 2, for example, VDDRMP = +3V.

[0077] In addition, the summing node NEGA is connected to the inverting input terminal of the first operational amplifier OP1, the reference voltage VDDRMP is input to the non-inverting input terminal of the first operational amplifier OP1, and the data voltage VD1 is output to the output node NQA. The non-inverting input terminal is the second input terminal. The power supply on the high potential side of the first operational amplifier OP1 is, for example, +6V, and the power supply on the low potential side is, for example, 0V.

[0078] Moreover, as Figure 9 shown, in the amplifier circuit AMP for positive polarity, during the initialization period, the switches SA2, SA4, and SA5 are turned on. By turning on the switch SA2 during the initialization period, the other end of the capacitor CIA whose one end is electrically connected to the summing node NEGA is set to the reference voltage VDDRMP. Similarly, by turning on the switch SA4, the other end of the capacitor CFA whose one end is electrically connected to the summing node NEGA is set to the reference voltage VDDRMP. In addition, by turning on the switch SA5 which is a feedback switch, the output of the first operational amplifier OP1 is fed back to the inverting input terminal, and the summing node NEGA is set to VDDRMP by the virtual short function of the first operational amplifier OP1. Thus, during the initialization period, the data voltage VD1 becomes the same voltage as the reference voltage VDDRMP.

[0079] In addition, as Figure 10As shown, the positive polarity amplifier circuit AMP turns on switches SA1 and SA3 during the output period. By turning on switch SA1 during the output period, the other end of the capacitor CIA connected to the summing node NEGA is set to VDAP. In addition, by turning on switch SA3, the other end of the capacitor CFA connected to the summing node NEGA is set to data voltage VD1. As a result, during the output period, the data voltage VD1 becomes a voltage represented by the following equation (1). In addition, in the following equation (1) and the equation (2) described later, CCIA is the capacitance of the capacitor CIA, and CCFA is the capacitance of the capacitor CFA.

[0080] VD1=VDDRMP-(CCIA / CCFA)×(VDAP-VDDRMP)…(1)

[0081] Next, use Figure 11 , Figure 12 The structure and operation of the negative polarity amplifier circuit AMM are described below. Figure 11 As shown in FIG. 1 , the negative polarity amplifier circuit AMM includes a second operational amplifier OP2, a second switched capacitor circuit SC2 composed of capacitors CIA, CFA, and switches SA1 to SA5. Figure 11 , Figure 12 As shown, the structure and operation of the negative polarity amplifier circuit AMM are the same as those of the positive polarity amplifier circuit AMP. However, in the negative polarity amplifier circuit AMM, a reference voltage VDDRMN is also input as a reference voltage. VDDRMN is, for example, -3V. In addition, the output voltage VDAM of the negative polarity D / A conversion circuit DAM is input to the negative polarity amplifier circuit AMM, and the output voltage VDAM is, for example, 0V to 6V. In addition, the power supply on the high potential side of the second operational amplifier OP2 is, for example, 0V, and the power supply on the low potential side is, for example, -6V. Therefore, during the initialization period, the data voltage VD2 becomes the same voltage as the second reference power supply VDDRMN, and during the output period, the data voltage VD2 becomes the voltage represented by the following formula (2).

[0082] VD2=VDDRMN-(CCIA / CCFA)x(VDAM-VDDRMP)…(2)

[0083] Figure 9 , Figure 10 The positive polarity amplifier circuit AMP is used, for example, with Figure 1 The first amplifier circuit 41 corresponds to the first operational amplifier OP1 and the first switched capacitor circuit SC1 composed of capacitors CIA, CFA and switches SA1 to SA5. Figure 7During the first initialization period TI1, the charges of the capacitors CIA and CFA of the first switched-capacitor circuit SC1 are initialized. For example, by setting the reference voltages VDDRMP at one end and the other end of the capacitors CIA and CFA, the charges stored in the capacitors CIA and CFA are initialized. Then, during the first output period TQ1, the first operational amplifier OP1 amplifies the output voltage VDAP of the D / A conversion circuit DAP for the positive polarity corresponding to the first D / A conversion circuit 31 based on the charges of the capacitors CIA and CFA of the first switched-capacitor circuit SC1 and outputs the data voltage VD1. For example, as shown in the above formula (1), the output data voltage VD1 is expressed as VD1 = VDDRMP - (CCIA / CCFA) × (VDAP - VDDRMP).

[0084] In addition, Figure 11 , Figure 12 the amplifier circuit AMM for the negative polarity, for example, corresponds to Figure 1 the second amplifier circuit 42, and has a second operational amplifier OP2 and a second switched-capacitor circuit SC2 composed of the capacitors CIA, CFA and the switches SA1 to SA5. And, during Figure 7 the second initialization period TI2, the charges of the capacitors CIA and CFA of the second switched-capacitor circuit SC2 are initialized. For example, by setting the reference voltage VDDRMP or the reference voltage VDDRMN at one end and the other end of the capacitors CIA and CFA, the charges stored in the capacitors CIA and CFA are initialized. Then, during the second output period TQ2, the second operational amplifier OP2 amplifies the output voltage VDAM of the D / A conversion circuit DAM for the negative polarity corresponding to the second D / A conversion circuit 32 based on the charges of the capacitors CIA and CFA of the second switched-capacitor circuit SC2 and outputs the data voltage VD2. For example, as shown in the above formula (2), the output data voltage VD2 is expressed as VD2 = VDDRMN - (CCIA / CCFA) × (VDAM - VDDRMP).

[0085] In this way, the capacitors CIA and CFA of the first switched-capacitor circuit SC1 and the second switched-capacitor circuit SC2 are capacitors initialized by being applied with the reference voltages VDDRMP and VDDRMN. For example, as Figure 9 shown, during the first initialization period TI1, the capacitors CIA and CFA of the first switched-capacitor circuit SC1 initialize the stored charges by applying the reference voltage VDDRMP at one end and the other end. In addition, as Figure 11As shown, during the second initialization period TI2 of the second switched capacitor circuit SC2, one end of the capacitor CIA is applied with the reference voltage VDDRMP and the other end is applied with the reference voltage VDDRMN, whereby the stored charge is initialized. During the second initialization period TI2 of the second switched capacitor circuit SC2, the capacitor CFA of the second switched capacitor circuit SC2 initializes the stored charge by applying the reference voltage VDDRMN to both ends. In this way, the reference voltages VDDRMP and VDDRMN of the fixed voltage with a stable potential can be used to initialize the charge stored in the capacitors CIA and CFA. As a result, during the output period, an appropriate data voltage set according to the charge stored in the capacitors CIA and CFA during the initialization period can be output. For example, an appropriate data voltage that eliminates the bias voltage of the first operational amplifier OP1 and the second operational amplifier OP2 can be output.

[0086] For example, when the row latch circuit 20 latches the display data during the initialization period as in Figure 6 the comparative example, noise is generated in the reference voltages VDDRMP and VDDRMN used in the initialization operations of the capacitors CIA and CFA. As a result, the charge stored in the capacitors CIA and CFA fluctuates, causing a problem of reduced display quality. In this regard, in the present embodiment, before the latching timing of the display data by the row latch circuit 20, the initialization period of each amplifier circuit ends. Therefore, it is possible to effectively prevent a reduction in display quality caused by the noise generated by the reference voltages VDDRMP and VDDRMN.

[0087] Figure 13 A detailed structural example of the power supply circuit 60 is shown. The power supply circuit 60 includes boost circuits BC1 to BC5 and regulators RG1 to RG13. For example, the boost circuit BC1 is a circuit that boosts the voltage through a switching regulation operation, and the boost circuits BC2 to BC5 are charge pump circuits. In addition, the regulators RG1 to RG13 are linear regulators. In addition, in Figure 13 the positional relationship of each voltage in the vertical direction of the drawing represents the approximate magnitude relationship of the voltages. For example, VDDL, VLDO, etc. are voltages between VDD and VSS, VOUTM, VOUT3, etc. are voltages lower than VSS, for example, negative voltages, and VOUT, etc. are voltages higher than VDD.

[0088] The regulators RG1, RG2, and RG3 step down VDD and generate VDDL, VLDO1, and VLDO2. VDDL is the power supply voltage of the control circuit 50 that is a logic circuit.

[0089] The boost circuit BC1 boosts VLDO1 to twice its value with respect to VSS to generate VOUT. The regulators RG4, RG5, RG6, RG7, RG8, RG9 step down VOUT to generate VREG, VDDHSP, VDDRHP, VDDRMP, VOFREG, and VONREG. The regulator RG4 generates VREG with respect to the output voltage of a bandgap circuit (not shown). The other regulators RG1 - RG3, RG5 - RG13 output respective voltages with respect to VREG. VDDHSP and VDDRMP are voltages for positive driving. For example, VDDHSP is the power supply voltage of the first operational amplifier OP1 for positive polarity, and VDDRMP is the above-described reference voltage. VDDRHP is the power supply voltage of the grayscale voltage generation circuit.

[0090] The boost circuit BC2 inverts VLDO2 with respect to VSS to generate a negative voltage, namely VOUTM. The regulator RG10 generates VCOM based on VLDO2 and VOUTM. VCOM is the common voltage of the display panel 110. The boost circuit BC3 boosts VDD invertingly to four times its value with respect to VSS to generate a negative voltage, namely VOUT3. The regulator RG11 steps down VOUT3 to generate VDDHSN, and the regulator RG12 steps down VDDHSN to generate VDDRMN. VDDHSN and VDDRMN are voltages for negative driving. For example, VDDHSN is the power supply voltage of the second operational amplifier OP2 for negative polarity, and VDDRMN is the above-described reference voltage.

[0091] The boost circuit BC4 inverts and boosts VOFREG to three times its value with respect to VSS to generate a negative voltage, namely VEE. VEE is the substrate voltage of, for example, the P-type semiconductor substrate of the display driver 10. The regulator RG13 steps down VEE to generate VGL. VGL is the negative power supply voltage of the gate driver 130. The boost circuit BC5 generates VDDHG = VONREG × 2 - VGL based on VONREG and VGL. VDDHG is the positive power supply voltage of the gate driver 130.

[0092] Moreover, in Figure 1 the switching regulator 62 described in Figure 13 is arranged in the boost circuit BC1 as shown, for example. Moreover, in the present embodiment, as described in Figure 7 during the first initialization period TI1 or the second initialization period TI2, the operation of the switching regulator 62 is stopped. By adopting this method, it is possible to prevent the noise generated by the switching regulation operation of the switching regulator 62 from adversely affecting the initialization operation of the first amplifier circuit 41 during the first initialization period TI1 or the initialization operation of the second amplifier circuit 42 during the second initialization period TI2.

[0093] In addition, the structures of the first amplifier circuit 41 and the second amplifier circuit 42 in this embodiment are not limited to Figures 9 to 12 the structures described in, and various modifications can be implemented. For example, Figure 14 , Figure 15 shows another structural example of the amplifier circuit AM. Figure 14 , Figure 15 The amplifier circuit AM of has an operational amplifier OP and a switched-capacitor circuit SC composed of capacitors C1, C2, CC, and switches SW1 to SW7. Moreover, as Figure 14 shown, during the initialization period, switches SW2, SW4, and SW7 are turned on, thereby performing an initialization operation of, for example, initializing the charges of capacitors C1, C2, and CC. For example, one end or the other end of capacitors C1, C2, and CC is set as AGND, which is a reference voltage, to initialize the charges. In addition, as Figure 15 shown, during the output period, switches SW3 and SW6 are turned on. Thereby, the amplifier circuit AM amplifies the output voltage VDAC of the previous-stage D / A conversion circuit according to the charges of capacitors C1, C2, and CC of the switched-capacitor circuit SC and outputs a data voltage VD. For example, when the voltage of AGND is set to VA, the amplifier circuit AM outputs a data voltage VD expressed as VD = VA - (C1 / C2) × (VDAC - VA). According to Figure 14 , Figure 15 the structure of the amplifier circuit AM of, unbiased operation that eliminates the bias voltage of the operational amplifier OP can be achieved.

[0094] As described above, the display driver of the present embodiment includes: a row latch circuit that latches display data for one row; a first D / A conversion circuit that performs D / A conversion on the display data from the row latch circuit; and a second D / A conversion circuit that performs D / A conversion on the display data from the row latch circuit. Further, the display driver includes a first amplifier circuit having a first switched-capacitor circuit and a first operational amplifier. During a first initialization period, the charge of the capacitor of the first switched-capacitor circuit is initialized. During a first output period, the first operational amplifier amplifies the output voltage of the first D / A conversion circuit based on the charge of the capacitor of the first switched-capacitor circuit and outputs a data voltage. In addition, the display driver includes a second amplifier circuit having a second switched-capacitor circuit and a second operational amplifier. During a second initialization period, the charge of the capacitor of the second switched-capacitor circuit is initialized. During a second output period, the second operational amplifier amplifies the output voltage of the second D / A conversion circuit based on the charge of the capacitor of the second switched-capacitor circuit and outputs a data voltage. Further, the display driver includes a control circuit that continuously controls the row latch circuit, the first amplifier circuit, and the second amplifier circuit. The control circuit ends the second initialization period of the second amplifier circuit before the output of the first amplifier circuit changes due to the latching of the display data by the row latch circuit at the latching timing.

[0095] According to the present embodiment, the display data from the row latch circuit is D / A converted by the first D / A conversion circuit and the second D / A conversion circuit. During the first initialization period, the charge of the capacitor of the first switched-capacitor circuit is initialized. During the first output period, a data voltage is output from the first amplifier circuit. During the second initialization period, the charge of the capacitor of the second switched-capacitor circuit is initialized. During the second output period, a data voltage is output from the second amplifier circuit. Moreover, control is performed such that the second initialization period of the second amplifier circuit ends before the display data is latched by the row latch circuit at the latching timing. If this method is adopted, it is possible to prevent a situation where noise caused by a change in the output of the first amplifier circuit due to the latching of the display data in the row latch circuit has an adverse effect on the initialization operation of the second amplifier circuit, and thus it is possible to prevent a reduction in display quality due to the noise.

[0096] In addition, in the present embodiment, it may be configured to include a power supply circuit having a switching regulator and supplying a power supply voltage to the first amplifier circuit and the second amplifier circuit, and the control circuit stops the operation of the switching regulator at least during the second initialization period.

[0097] If this method is adopted, it is possible to prevent the noise generated by the switching regulation operation of the switching regulator from adversely affecting the initialization operation of the second amplifier circuit during the second initialization period, thereby preventing a reduction in display quality caused by such noise.

[0098] In addition, in the present embodiment, it may also be that the first amplifier circuit is a positive-polarity amplifier circuit that outputs a positive-polarity voltage, and the second amplifier circuit is a negative-polarity amplifier circuit that outputs a negative-polarity voltage.

[0099] In this way, it is possible to perform inversion driving of the display driver formed by positive-polarity driving of the positive-polarity amplifier circuit and negative-polarity driving of the negative-polarity amplifier circuit.

[0100] In addition, in the present embodiment, the control circuit may also alternately perform the initialization operation of the first amplifier circuit during the first initialization period and the initialization operation of the second amplifier circuit during the second initialization period for each horizontal scanning period.

[0101] If this method is adopted, it is possible to prevent an adverse situation that occurs when the initialization operations of both the first amplifier circuit and the second amplifier circuit are performed during the same initialization period.

[0102] In addition, in the present embodiment, the control circuit may also perform the following control: after the gate line selection period during the first horizontal scanning period, perform the initialization operation of the second amplifier circuit during the second initialization period, and end the second initialization period of the second amplifier circuit before the output of the first amplifier circuit changes when the display data is latched by the row latching circuit at the latching timing. And the control circuit may also perform the following control: after the gate line selection period during the second horizontal scanning period, perform the initialization operation of the first amplifier circuit during the first initialization period, and end the first initialization period of the first amplifier circuit before the output of the second amplifier circuit changes when the display data is latched by the row latching circuit at the latching timing.

[0103] In this way, it is possible to prevent the noise caused by the change in the output of the first amplifier circuit generated by the latching of the display data from adversely affecting the initialization operation of the second amplifier circuit, and it is possible to prevent the noise caused by the change in the output of the second amplifier circuit generated by the latching of the display data from adversely affecting the initialization operation of the first amplifier circuit.

[0104] In addition, in the present embodiment, the control circuit may also perform the following control: end the second initialization period before switching from the first horizontal scanning period to the second horizontal scanning period, and perform the latching operation of the row latching circuit during the second horizontal scanning period after switching from the first horizontal scanning period to the second horizontal scanning period.

[0105] In this way, the latching operation of the line latching circuit can be ended as quickly as possible, data voltage can be written to the pixel during the subsequent second gate line selection period or the like, and the writing time of the data voltage can be extended.

[0106] In addition, in the present embodiment, the capacitors of the first switched capacitor circuit and the second switched capacitor circuit may also be capacitors that are initialized by being applied with a reference voltage.

[0107] In this way, the charge accumulated in the capacitor can be initialized using the reference voltage, and during the output period, an appropriate data voltage set based on the charge accumulated in the capacitor during the initialization period can be output.

[0108] As described above, the present embodiment has been described in detail, but those skilled in the art can easily understand that various modifications can be made that do not substantially depart from the new matters and effects of the present invention. Therefore, all such modified examples are included in the scope of the present invention. For example, in the specification or the drawings, a term described at least once together with a different term that is more general or synonymous can be replaced with that different term at any position in the specification or the drawings. In addition, the structures and operations of the display driver, the electro-optical device, etc. are not limited to the contents described in the present embodiment, and various modifications can be implemented.

Claims

1. A display driver, characterized in that, the display driver includes: a row latch circuit for latching one row of display data; a first D / A conversion circuit for performing D / A conversion on the display data from the row latch circuit; a second D / A conversion circuit for performing D / A conversion on the display data from the row latch circuit; a first amplifier circuit having a first switched capacitor circuit and a first operational amplifier. During a first initialization period, the charge of the capacitor of the first switched capacitor circuit is initialized. During a first output period, the first operational amplifier amplifies the output voltage of the first D / A conversion circuit based on the charge of the capacitor of the first switched capacitor circuit and outputs a data voltage; a second amplifier circuit having a second switched capacitor circuit and a second operational amplifier. During a second initialization period, the charge of the capacitor of the second switched capacitor circuit is initialized. During a second output period, the second operational amplifier amplifies the output voltage of the second D / A conversion circuit based on the charge of the capacitor of the second switched capacitor circuit and outputs a data voltage; and a control circuit for controlling the row latch circuit, the first amplifier circuit, and the second amplifier circuit, the control circuit ends the second initialization period of the second amplifier circuit before the output of the first amplifier circuit changes when the display data is latched by the row latch circuit at a latch timing.

2. The display driver according to claim 1, characterized in that, the display driver includes a power supply circuit having a switching regulator and supplying a power supply voltage to the first amplifier circuit and the second amplifier circuit, the control circuit stops the operation of the switching regulator at least during the second initialization period.

3. The display driver according to claim 1 or 2, characterized in that, the first amplifier circuit is a positive-polarity amplifier circuit for outputting a positive-polarity voltage, the second amplifier circuit is a negative-polarity amplifier circuit for outputting a negative-polarity voltage.

4. The display driver according to claim 1 or 2, characterized in that, the control circuit alternately performs the initialization operation of the first amplifier circuit during the first initialization period and the initialization operation of the second amplifier circuit during the second initialization period for each horizontal scan period.

5. The display driver according to claim 1 or 2, characterized in that, the control circuit performs the following control: after the gate line selection period during the first horizontal scan period, perform the initialization operation of the second amplifier circuit during the second initialization period, before the output of the first amplifier circuit changes when the display data is latched by the row latch circuit at a latch timing, end the second initialization period of the second amplifier circuit, after the gate line selection period during the second horizontal scan period, perform the initialization operation of the first amplifier circuit during the first initialization period, Before the display data is latched by the row latching circuit at the latching timing and the output of the second amplifier circuit changes, end the first initialization period of the first amplifier circuit.

6. The display driver according to claim 1 or 2, wherein, the control circuit performs the following control: Before switching from the first horizontal scanning period to the second horizontal scanning period, end the second initialization period, and after switching from the first horizontal scanning period to the second horizontal scanning period, perform the latching operation of the row latching circuit during the second horizontal scanning period.

7. The display driver according to claim 1 or 2, wherein, the capacitors of the first switched capacitor circuit and the second switched capacitor circuit are capacitors that are initialized by being applied a reference voltage.

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