A device for reducing blind area of wireless communication based on FPGA

Abstract

The application discloses a kind of based on FPGA reduces the device of wireless communication blind area, it includes: external antenna, radio frequency front end module, demodulator module, baseband amplification filter module, ADC sampling module, FPGA sampling pre-processing module, parallel decoding module, decision selection module, CPU interface module.Compared with prior art, the application uses digital signal processing technology, without changing radio frequency hardware circuit, through the realization of multiple parallel bit synchronous decoding and criterion selection by FPGA gate array optimal channel, can effectively reduce the influence of blind area on system sensitivity, improve system sensitivity and communication efficiency.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of aviation computer control, and relates to a device for reducing a blind area of wireless communication based on an FPGA. BACKGROUND

[0002] In an RFID electronic license plate application, a reader and a passive tag communicate in a wireless manner. The reader first sends a carrier wave and a forward modulation signal to the passive tag. The passive tag rectifies the carrier energy to power the tag chip. The passive tag enters the reader antenna in a reflection mode by modulating the carrier wave sent by the reader. In this mode, electromagnetic wave reflection occurs and multipath effect is generated when the tag is far away from the reader or there are obstacles around the electromagnetic field. Especially during the movement of the tag with the vehicle, the blind area causes part of the data to fail to be successfully decoded, thereby reducing the system sensitivity and the overall communication efficiency.

[0003] To solve the above problems, the forward signal power can be increased to increase the reflection signal strength, or multiple antennas can be used to receive signals from different angles to reduce the influence of the blind area. However, the above methods undoubtedly increase the hardware cost or engineering construction cost.

[0004] Chinese invention patent 202010481632.X discloses a portable miniaturized short wave blind area free antenna, which relates to the technical field of short wave antenna communication equipment. It comprises a radiation ring, a coupling ring, a foldable retractable support rod and an impedance matching unit box. The radiation ring and the coupling ring are fixed at the upper end of the impedance matching unit box, and the upper ends of the radiation ring and the coupling ring are connected and fixed by the foldable retractable support rod. The impedance matching unit box is fixed on the foldable retractable support rod. The foldable retractable support rod is composed of an upper end support rod and a lower end support rod which can be folded in half. The radiation ring is composed of four antenna rods, two of which are connected in the upper end support rod as the upper end antenna rods of the radiation ring, and the other two are connected in the lower end support rod as the lower end antenna rods of the radiation ring. The coupling ring is composed of two coupling ring antenna rods connected in the lower end support rod. The patent has the advantages of high efficiency, low loss, simple installation, portability, miniaturization, blind area free, anti-interference and easy to carry, and has wide application prospect. The patent realizes the reduction of the blind area through the circuit and structure. The antenna is a transmitting device, while the present application is a receiving device which reduces the influence of the blind area on communication through a specific method.

[0005] Chinese invention patent 202010980273.2 relates to a method, equipment, device and medium for communicating in an area containing a communication blind area. The method comprises: transmitting monitoring information collected by a monitoring device to a server, the monitoring information at least including position information of the monitoring device; determining whether the monitoring device is in the communication blind area based on the monitoring information; in response to determining that the monitoring device is in the communication blind area, storing the collected monitoring information in the monitoring device, making the communication module of the monitoring device enter an inactive state and stop transmitting the monitoring information to the server; and in response to determining that the monitoring device leaves the communication blind area, making the communication module of the monitoring device transition from the inactive state to the active state and transmitting the monitoring information stored in the monitoring device to the server after successfully connecting with the communication network. This patent reduces the impact of the blind area on communication by storing information locally in the blind area and reporting data in the non-blind area, which is different from the present invention which reduces the impact of the blind area on communication by multi-channel acquisition and multi-channel decoding. SUMMARY

[0006] (I) Invention purpose

[0007] The purpose of the present invention is to provide a device for reducing wireless communication blind area based on FPGA, which can effectively reduce the impact of blind area on system sensitivity by processing the signal through FPGA algorithm, parallel decoding multiple data and selecting the optimal data among them without increasing additional hardware overhead.

[0008] (II) Technical solution

[0009] In order to solve the above technical problems, the application provides a device for reducing wireless communication blind area based on FPGA, which comprises an external antenna, a radio frequency front-end module, a demodulator module, a baseband amplification and filtering module, an ADC sampling module, an FPGA sampling preprocessing module, a parallel decoding module, a decision selection module and a CPU interface module; the external antenna is used to complete the transmission and reception of wireless signals; the radio frequency front-end module is connected with the external antenna and the demodulator module, and receives reverse wireless signals; the demodulator module is connected with the baseband amplification and filtering module, and realizes signal demodulation by mixing the local carrier with the modulated signal; the baseband amplification and filtering module amplifies the demodulated signal and filters out the out-of-band interference, and increases the anti-aliasing filter; the ADC sampling module is connected with the baseband amplification and filtering module and the FPGA sampling preprocessing module, simultaneously samples the IQ two-way signals, and converts the analog signals into digital signals; the FPGA sampling preprocessing module realizes the timing of the ADC chip interface with the ADC sampling module, and performs digital filtering on the collected signals; the parallel decoding module is connected with the FPGA sampling preprocessing module and the decision selection module, adopts bit synchronization decoding algorithm to separate the 0 / 1 signal from the sampling signal, and performs parallel demodulation on the I signal, the Q signal, the I+Q signal and the I-Q signal through the four decoding modules; the decision selection module selects an optimal channel from the four channels as effective data and stores it into the FIFO according to the decoding length and the return signal energy size; and the CPU interface module is connected with the decision selection module, and is used to report the decoding data to the CPU for data analysis.

[0010] (Three) beneficial effects

[0011] Compared with the prior art, the device for reducing wireless communication blind area based on FPGA provided by the above technical solution adopts digital signal processing technology, does not need to change the radio frequency hardware circuit, realizes multi-channel parallel bit synchronization decoding through the FPGA gate array, selects the optimal channel through the criterion, can effectively reduce the influence of the blind area on the system sensitivity, and improves the system sensitivity and communication efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0012] Figure 1 It is a system principle block diagram of the application.

[0013] Figure 2 It is an FPGA internal signal processing block diagram of the application. DETAILED DESCRIPTION

[0014] In order to make the purpose, content and advantages of the application more clear, the specific embodiments of the application are further described in detail below in combination with the drawings and examples.

[0015] As Figure 1 and Figure 2As shown, the device for reducing blind area of wireless communication based on FPGA in the embodiment comprises an external antenna, a radio frequency front-end module, a demodulator module, a baseband amplification and filtering module, an ADC sampling module, an FPGA sampling preprocessing module, a parallel decoding module, a decision selection module, and a CPU interface module. The external antenna is used to complete transmission and reception of wireless signals. The radio frequency front-end module is connected with the external antenna and the demodulator module to receive reverse wireless signals. The demodulator module is connected with the baseband amplification and filtering module to realize signal demodulation through mixing of a local carrier and a modulated signal. The baseband amplification and filtering module amplifies the demodulated signal and filters out out-of-band interference to increase anti-aliasing filtering. The ADC sampling module is connected with the baseband amplification and filtering module and the FPGA sampling preprocessing module to simultaneously sample IQ two-way signals and convert analog signals into digital signals. The FPGA sampling preprocessing module realizes timing of an ADC chip interface with the ADC sampling module and performs digital filtering on the collected signals. The parallel decoding module is connected with the FPGA sampling preprocessing module and the decision selection module, adopts bit synchronization decoding algorithm to separate 0 / 1 signals from the sampling signals, and performs parallel demodulation on I-way signals, Q-way signals, I+Q signals, and I-Q signals through four decoding modules. The decision selection module selects an optimal channel from the four channels as effective data according to decoding length and return signal energy size and stores the effective data into a FIFO. The CPU interface module is connected with the decision selection module to report decoding data to a CPU for data analysis.

[0016] The ADC sampling module has two ways, namely an ADC sampling I-way module and an ADC sampling Q-way module. The I-way module and the Q-way module are respectively processed by the parallel decoding module after band-pass filtering.

[0017] After the reader is powered on, a carrier is transmitted according to a protocol to activate passive tags in an electromagnetic field. The passive tags do not have the ability to actively send modulated signals, but rely on modulated reflected carriers for communication, so the sender and the receiver share a frequency band in this sense. Transmission and reception of wireless signals are completed through an external antenna. According to application needs, a circularly polarized antenna with a gain of 6dBi or 9dBi is generally selected.

[0018] The radio frequency front-end module completes reception and filtering processing of reverse small signals. The module is composed of a circulator, a band-pass filter, and a low-noise amplifier. The circulator is a three-terminal device with one-way transmission characteristics. It can control electromagnetic waves to transmit in a ring shape, thereby ensuring energy of a forward link transmission carrier and ensuring reverse reception of small signal modulation information. The band-pass filter completes filtering of out-of-band signals in a radio frequency band. The low-noise amplifier is mainly used to amplify weak signals and is used for high-frequency or intermediate-frequency front-stage signal amplification of a wireless receiver.

[0019] The demodulator module completes signal demodulation, mixes frequency spectrum from radio frequency into zero intermediate frequency. The demodulator mixes the local carrier with the modulated signal to realize signal demodulation, wherein the local carrier is realized by a high-precision crystal oscillator and a phase-locked loop circuit, and the frequency point of the phase-locked loop can be configured by FPGA.

[0020] The baseband amplification filter module realizes amplification of the demodulated small signal and filtering of out-of-band interference, and increases anti-aliasing filtering. The present application mainly aims at baseband signals, so a differential operational amplifier with a small noise figure is used to amplify the I Q two-way signal. In order to reduce the interference of low-frequency signals and direct-current signals on effective signals, a band-pass filter is added.

[0021] The ADC sampling module completes the conversion of analog signals to digital signals. In order to enhance the anti-interference performance and filter out the influence of common-mode signals, the analog input signals I and Q are designed as differential circuits respectively, so that the ADC is used in the subsequent design to sample the I and Q signals. In order to increase the signal sensitivity, the present application uses high-speed ADC to realize oversampling of baseband signals, so as to ensure that the sampling frequency is more than 20 times of the baseband signal. The ADC uses high-speed ADC of ADI company, and the sampling accuracy is 12 bits.

[0022] The FPGA sampling preprocessing module completes the ADC interface timing, realizes a digital band-pass filter, and pre-processes the filtered 2-way signals. The ADC interface timing is realized by FPGA extension, FPGA outputs sampling clock, and samples parallel sampling data according to the rising edge of the clock. Since the default output sampling data of ADC is in straight code form, the sign bit needs to be processed and converted into the complement code required by the computer. After the ADC sampling data is converted into the complement code, it enters the band-pass digital filter. The present application uses FIR filter to filter out out-of-band interference, in order to enhance the signal sensitivity, the out-of-band attenuation of the filter is more than 40dB, and the in-band flatness is 1dB. After the 2-way sampling signals are filtered, they enter the preprocessing link, the signals pass through the adder to realize I+Q, and pass through the subtractor to realize I-Q, so as to realize signal phase shift. In addition to the above phase shift processing, the preprocessing module calculates the energy of the IQ signal, and takes the logarithm of the calculated I^2+Q^2 signal, which is convenient for subsequent processing (the present application uses lookup table method to calculate the logarithm, which can also use IP core calculation).

[0023] The parallel decoding module uses a bit synchronization decoding algorithm to recover 0 / 1 signals from the sampling data. Since the scheme is pre-processed into 4 signals, 4 independent decoding modules are used to decode the 4 signals simultaneously, that is, I, Q, I+Q and I-Q signals are demodulated simultaneously. Since the phase difference between I and Q signals is 90 degrees, after phase shifting, it is moved forward and backward by 45 degrees. In this way, when the electromagnetic wave appears blind area due to multipath effect, the multi-channel signal processing method of the scheme can weaken the influence of the blind area on the signal to a certain extent. The decoded 0 / 1 signal is decoded by subsequent FM0 (including MILLER decoding) to identify the preamble and frame header information, so that the effective data can be stored in the DPRAM. According to the foregoing description, there are at most 4 effective data after decoding.

[0024] The decision selection module is responsible for selecting the optimal channel from the 4 decoded data and reporting the final data to the processor. The optimal algorithm of the scheme is judged in two dimensions. First, according to the protocol, whether the length of the decoded signal is consistent with the expected value is judged. If it is not consistent, the data of this channel is discarded. Under the premise that the signal length meets the expected value, the next step is to compare the signal strength, and the channel with the largest signal strength is selected as the optimal channel. After the optimal decision, the final data is stored in the cache FIFO realized by the IP core.

[0025] The CPU interface module is responsible for reporting the decoded data to the CPU for data analysis. The FPGA and the CPU communicate through the LocalBus, and the FPGA realizes the decoding of the local bus address, data, chip selection and read-write signals, realizes the general register read-write operation and FIFO read operation.

[0026] The FPGA gate array of the present application converts the input 2-channel signal into 4-channel signal, then enters the parallel decoding module, and selects the optimal channel through the optimal decision link to solve the problem of low communication efficiency caused by the decrease of sensitivity in the blind area of wireless communication. In addition, the present application does not need to change the radio frequency link, and solves the problem of communication sensitivity caused by blind area through digital gate array method, which can effectively improve the sensitivity of wireless communication.

[0027] As can be seen from the above technical scheme, the present application uses IQ two-channel signals and phase-shifted signals as decoding signals, uses FPGA gate array to realize bit synchronization decoding and instantiates a multi-channel decoder to realize parallel decoding, and increases the decision link by combining decoding length and signal strength to select the optimal channel from the multi-channel decoding data.

[0028] The above merely describes the preferred embodiments of the present application, and it should be pointed out that, for those skilled in the art, several improvements and modifications can be made without departing from the technical principles of the present application, and these improvements and modifications should also be considered as the protection scope of the present application.

Claims

1. An apparatus for reducing blind spots in wireless communication based on FPGA, the apparatus comprising: Comprise: External antenna, radio frequency front-end module, demodulator module, baseband amplification filter module, ADC sampling module, FPGA sampling preprocessing module, parallel decoding module, decision selection module, CPU interface module; external antenna is used to complete the transmission and reception of wireless signal; radio frequency front-end module is connected with external antenna and demodulator module, and receives reverse wireless signal; demodulator module is connected with baseband amplification filter module, and signal demodulation is realized through local carrier and modulation signal mixing; baseband amplification filter module amplifies demodulation signal and filters out out-of-band interference, and increases anti-aliasing filter; ADC sampling module is connected with baseband amplification filter module and FPGA sampling preprocessing module, and simultaneously samples IQ two-way signal, and converts analog signal into digital signal; FPGA sampling preprocessing module realizes the interface timing of ADC chip in ADC sampling module, and carries out digital filtering to the collected signal; parallel decoding module is connected with FPGA sampling preprocessing module and decision selection module, adopts bit synchronization decoding algorithm to separate 0 / 1 signal from sampling signal, and through 4-way decoding module, I-way signal, Q-way signal, I+Q signal and I-Q signal are parallel demodulated; decision selection module selects one optimal channel from four channels as effective data and stores in FIFO through decoding length and return signal energy size; CPU interface module is connected with decision selection module, and is used for reporting decoding data to CPU and data analysis; The ADC sampling module has two ways, which are ADC sampling I-way module and ADC sampling Q-way module, and the I-way module and the Q-way module are parallel processed by parallel decoding module after band-pass filtering processing; The external antenna selects gain 6dBi or 9dBi circularly polarized antenna; The radio frequency front-end module comprises circulator, band-pass filter and low-noise amplifier; the circulator is a three-terminal device with one-way transmission characteristic, and controls electromagnetic wave to be transmitted along the ring direction; the band-pass filter filters out-of-band signal in the radio frequency band, and the low-noise amplifier amplifies weak signal and is used for high-frequency or intermediate-frequency front-stage signal amplification of wireless receiver; The demodulator module completes signal demodulation, and mixes frequency spectrum from radio frequency into zero intermediate frequency; The baseband amplification filter module adopts differential operational amplifier with small noise coefficient to amplify I Q two-way signal for baseband signal; In the ADC sampling module, the I-way module and the Q-way module are set as differential circuits, and the ADC adopts high-speed ADC of ADI company, and sampling precision is 12 bits; The FPGA output sampling clock samples parallel sampling data according to clock rising edge, and sampling signal is filtered out-of-band interference by FIR filter, the filter out-of-band attenuation is above 40 dB, and the in-band flatness is 1 dB; After 2-way sampling signal is filtered, it enters preprocessing link, and signal realizes I+Q through adder and realizes I-Q through subtractor, so that signal phase shift is realized; The decision selection module selects the optimal channel from the 4-way decoded data in two dimensions, first, according to the protocol, whether the length of the returned decoded signal is consistent with the expected value, if not, the data is discarded; under the premise that the signal length meets the expected value, the next step is to compare the signal strength, and the channel with the larger signal strength is selected as the optimal channel, and after the optimal decision, the final data is stored in the cache FIFO realized by the IP core; The CPU and the FPGA communicate through the LocalBus, the FPGA realizes the decoding of the LocalBus address, data, chip selection and read-write signals, realizes the general register read-write operation and FIFO read operation.

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