Method performed by an electronic device and a decoder in the electronic device

Abstract

A method performed by an electronic device and a decoder in the electronic device are disclosed. The method performed by an electronic device configured to decode data received from an encoder includes: receiving a transmission bit by a decoder of the electronic device, the transmission bit including a sequence of conversion-encoded data bits and conversion-encoded key protection data; decoding the conversion-encoded key protection data by the decoder to generate key protection data; determining that the key is accurate based on the key protection data; and decoding the sequence of conversion-encoded data bits by the decoder based on the accurate key to generate a sequence of decoded data bits, wherein the key protection data is a check bit, and the encoded key protection data is represented as a key bit with the key protection data added.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of U.S. Provisional Patent Application No. 63 / 227,278, filed on July 29, 2021, which is incorporated herein by reference in its entirety. Technical Field

[0003] The present application relates generally to transcoding and, more particularly, to systems and methods for transcoding using protected keys. Background Art

[0004] Electronic devices that use serial data transmission rely on error-free information provided from the transmitter to the receiver. In addition, some serial data transmission technologies rely on keys to encode the serial data and then decode it. Since the encoding and decoding process relies on keys, if an incorrect or wrong key is received by the receiver, the error from the key propagates to the data and the serial data cannot be correctly decoded. Therefore, it is desirable to use technology to ensure the reliability and integrity of the key. Summary of the invention

[0005] According to some embodiments, a method for encoding is described. The method may include: receiving a sequence of data bits at an encoder; performing a first conversion encoding on the data bits at the encoder to generate a sequence of encoded data bits based on a key; performing protection encoding on the key at the encoder to generate key protection data; performing a second conversion encoding on the key protection data at the encoder to generate encoded key protection data; and transmitting a sequence of encoded transmission bits to a receiver, the sequence of encoded transmission bits including the sequence of encoded data bits and the encoded key protection data.

[0006] The key protection data may include a check digit.

[0007] Generating the encoded key protection data may include inverting a check bit.

[0008] The method may further include: selecting the key at the encoder to be a value in which the most significant bit (MSB) is a constant; and removing the MSB from the key to generate a modified key, wherein the sequence of encoded transmitted bits comprises the modified key.

[0009] The constant can be zero.

[0010] The key protection data may include multiple check bits.

[0011] Multiple check bits can be calculated based on the Hamming code.

[0012] Generating the encoded key protection data may include inverting at least one of the plurality of check bits.

[0013] The method may further include: selecting the key at the encoder to be a value in which the MSB is a constant; and removing the MSB from the key to generate a modified key, wherein the sequence of encoded transmitted bits comprises the modified key.

[0014] Generating the encoded key protection data may further include inserting one or more of the inverted check bits to the front of the modified key, and inserting one or more of the inverted check bits to the end of the modified key.

[0015] According to some embodiments, an encoder is described. The encoder may include: an input end configured to receive a sequence of data bits; a processor configured to perform operations, which may include: performing a first conversion encoding on the data bits to generate a sequence of encoded data bits based on a key; performing protection encoding on the key to generate key protection data; and performing a second conversion encoding on the key protection data to generate encoded key protection data; and an output end configured to send a sequence of encoded transmission bits to a receiver, the sequence of encoded transmission bits including the sequence of encoded data bits and the encoded key protection data.

[0016] The key protection data may include a check digit.

[0017] Generating the encoded key protection data may include inverting a check bit.

[0018] The operations may further include: selecting, at the encoder, a key as a value in which a most significant bit (MSB) is a constant; and removing the MSB from the key to generate a modified key, wherein the sequence of encoded transmitted bits comprises the modified key.

[0019] The constant can be zero.

[0020] The key protection data may include multiple check bits.

[0021] Multiple check bits can be calculated based on the Hamming code.

[0022] Generating the encoded key protection data may include inverting at least one of the plurality of check bits.

[0023] The operations may further include: selecting, at the encoder, the key as a value in which the MSB is a constant; and removing the MSB from the key to generate a modified key, wherein the sequence of encoded transmitted bits comprises the modified key.

[0024] Generating the encoded key protection data further includes inserting one or more of the inverted check bits to the front of the modified key and inserting one or more of the inverted check bits to the end of the modified key.

[0025] The scope of the present invention is defined by the claims, which are incorporated herein by reference. By considering the following detailed description of one or more embodiments, those skilled in the art will gain a more complete understanding of embodiments of the present invention and a recognition of their additional advantages. Reference will be made to the attached drawings, which will first be briefly described. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is an example of a sequence of data bits illustrating conversions within data according to various embodiments of the present disclosure.

[0027] Figure 2 is a table showing example codewords according to various embodiments of the present disclosure.

[0028] Figure 3 is a flow chart illustrating steps for encoding a sequence of data bits according to various embodiments of the present disclosure.

[0029] Figure 4 is a flow chart illustrating steps for encoding key protection data according to various embodiments of the present disclosure.

[0030] Figure 5 is a block diagram of an electronic system according to various embodiments of the present disclosure.

[0031] Embodiments of the present disclosure and their advantages are best understood by referring to the detailed description below. Unless otherwise specified, the same reference numerals represent the same elements throughout the drawings and written description, and therefore, their description will not be repeated. In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. DETAILED DESCRIPTION

[0032] By referring to the detailed description and the accompanying drawings of the embodiments, it is easier to understand the aspects of some embodiments of the present disclosure and the methods for realizing them. Hereinafter, the embodiments will be described in more detail with reference to the accompanying drawings. However, the described embodiments can be implemented in various forms and should not be construed as being limited to the embodiments shown herein. On the contrary, these embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements and techniques that are not necessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure may not be described.

[0033] In digital communications, an encoder encodes data bits (e.g., a data packet) and sends the encoded data bits to a decoder. The decoder then decodes the encoded data bits so that the data bits can be used by a system such as a television, a display device, a computer, etc. According to one technique, the encoded data bits can be serialized and sent from the encoder to the decoder via a serial digital data link. Such serial digital data can be sent together with a separate clock signal accompanying the serial digital data, or the serial digital data can be sent together with a clock signal embedded in the serial digital data signal (i.e., without a separate clock signal).

[0034] Transition coding is a method for sending serial digital data signals without a separate clock signal. Transition coding relies on the presence of data transitions (where a data bit transitions or changes from zero to one, or from one to zero) in a sequence of data bits. In other words, in order for a decoder to properly utilize the received data, a certain amount of transitions must occur within the sequence of data bits. However, if the run length in the sequence of data bits exceeds a certain limit, the decoder may not be able to decode the data correctly, and the system will not end up with the data it should have received. Run length refers to the number of consecutive ones or zeros in a sequence of data bits. For example, in Figure 1 In the sequence of example data bits 10100111001 shown in , the run length between each transition is indicated as 1, 2, or 3. For example, the run length for a scenario where there are three consecutive ones is 3.

[0035] Some conversion coding techniques include keys (e.g., scrambling keys) that can be used when encoding data bits to maintain the integrity of the sequence of encoded data bits when data is sent across a serial data link. In such a case, the encoder generates a key, and applies conversion coding to the data bits based on the key, and adds the key to the sequence of encoded data bits to generate a sequence of transmission bits for sending to a receiver. When the encoded transmission bits are received by a decoder, the decoder decodes the received transmission bits using the key. If the key becomes damaged during transmission, the decoder will not be able to decode the transmission bits, and may cause error propagation. That is, the error in the key continues to the error in the sequence of the entire data bit, thereby making the sequence of the entire data bit unavailable. Accordingly, embodiments of the present disclosure describe a technology for improving the reliability of the transmission of a key. Moreover, it can be expected that the key is protected without changing the conversion properties of the encoded sequence (e.g., without exceeding the run length limit of the encoding).

[0036] Example conversion coding techniques include encoding 31 groups of 6-bit words of data and a 6-bit key. Therefore, according to an embodiment, the sequence of transmitted bits includes 192 bits, of which 186 bits are data and 6 bits are keys. The 6-bit key can be represented as D, and D can be a word different from all 31 words of the original data word, and can also be a word different from the complement of the 31 original data words. Accordingly, the value of D can be selected, and an exclusive or ("XOR") operation can be applied to each of the 31 words and D. Therefore, for example, each word of 186 data bits can be represented as x1, x2, ... x31, and an XOR operation can be applied to each of the words (x1, x2, ... x31) and a key (D) to generate x1^D, x2^D, ... x31^D. Thus, by performing transform coding on a sequence of data words {x1, x2, ... x31}, the encoded data words become {D, x1^D, x2^D, ... x31^D}, where the first data word is the key (D), followed by each of the 31 data words XORed with the key (D). Accordingly, the sequence of the transmitted data stream becomes 32 word lengths, where 192 bits are serialized and transmitted over a serial data link. According to this example transform coding technique, the run length can be limited to 10. The details for determining the run length of this transform coding technique are not relevant to the present disclosure and therefore will not be described herein.

[0037] When the transmit data sequence is received by the decoder, the decoder takes the key (D) and applies the XOR operation to each encoded word (i.e., each of the 31 words). Thus, by XORing D with the first encoded word (x1^D), D is eliminated, thereby leaving only x1 as the first word. The same XOR operation is performed on all 31 encoded words to decode the 31 words. Therefore, if an error is introduced into the key (D), the error will propagate to each of the 31 words because the decoder will perform the XOR operation using the wrong (i.e., incorrect) key (D).

[0038] According to various embodiments of the present disclosure, the technology for protecting the integrity of the key (D) will be described. In other words, the methods and techniques for error detection and / or error correction can be implemented by the encoder and applied to the key (D), so that if an error (e.g., during transmission) occurs in the key (D), the decoder will be able to detect the error in the key (D), and therefore the wrong key (D) is not applied to decode the data stream. On the contrary, the decoder can, for example, wait for another key (D) that does not contain an error to arrive. In other embodiments, the decoder can not only detect the existence of an error, but also correct the error, so that the decoder does not have to discard the key (D) and wait for the next key, but corrects the wrong key so that the decoder can now use the corrected key immediately. It is noted that the technology for protecting the integrity of the key described in the present disclosure is applicable to various encoding and / or decoding techniques known to those skilled in the art. Such encoding and / or decoding techniques can include utilizing different logical operations, different word lengths, different word counts, etc.

[0039] In general, a check bit can be included in the encoded data to help detect the presence of errors. One example is to generate an even check bit and include the even check bit in the encoded data. For example, if there are n bits (d1 to dn) in a given word (e.g., a 6-bit key) or block, an even check bit (p) can be generated or calculated by performing an XOR operation on the bits (d1 to dn). Therefore, the even check bits (p) of d1 to dn can be shown as: p = d1 ⊕ d2 ⊕ d3 ⊕ ... ⊕ dn, and the encoded block including the even check bit (p) can be expressed as: {d1, d2, d3, ... dn, p}. Therefore, the correlation between the data bit and the check bit can be written as d1 ⊕ d2 ⊕ d3 ⊕ ... ⊕ dn ⊕ p = 0. In other words, if the correlation is equal to 0 in the case of an even check bit, the data bit (d1 to dn) is likely to contain no errors. On the other hand, if the correlation indicates that it is equal to 1, there is a possibility that one of the data bits (d1 to dn) contains an error.

[0040] More complex block codes can be constructed by including multiple check bits. For example, a Hamming code such as the (7,4) Hamming code can be used. In the (7,4) Hamming code, three check bits can be implemented in the block of data bits being encoded. In such a case, the check bits (p1, p2, p3) can be generated as:

[0041] p1=d1⊕d2⊕d4,

[0042] p2=d1⊕d3⊕d4,

[0043] p3=d2⊕d3⊕d4,

[0044] And the correlation between the check bit and the data bit can be expressed as:

[0045] d1⊕d2⊕d4⊕p1=0,

[0046]

[0047]

[0048] Another example of a parity bit is an odd parity bit. For an odd parity bit (pb), applying an XOR operation to the data bit and the odd parity bit produces 1, which can be expressed as Therefore, the odd parity bit (pb) can be generated as: That is, the odd parity bit is the inverse of the result of the XOR operation of all the data bits.

[0049] In transition coding, odd parity includes some useful features. For example, if the block consists of an odd number of bits, that is, n is an odd number, then there is a guaranteed transition in the block of data bits. That is, if d1=0, d2=0, d3=0, d4=0, and d5=0, then Therefore, if an odd parity bit is inserted at the end of the code, the block code is 000001, which includes one transition. Similarly, if d1=1, d2=1, d3=1, d4=1, and d5=1, then Thus, the block code is 111110, which also includes one transition. Accordingly, in the worst case scenario where bits (d1 to dn) (where n is an odd number) are all ones or all zeros, the run length is limited to n, and the inclusion of an odd parity bit guarantees a transition.

[0050] Now returning to the example conversion coding technique using 31 groups of 6-bit words and a 6-bit key (D), the concept of using an odd check bit can be applied to the key (D) to detect errors, and in some embodiments, detect and correct errors. According to this example, the key (D) includes 6 bits and the most significant bit ("MSB") (i.e., the 6th bit) of the value of the key (D) is always zero. Therefore, according to an embodiment of the present disclosure, the 6th bit of the key (D) can be removed and replaced with an odd check bit instead of zero. For example, what the decoder knows is that the MSB of the value of the key (D) is always zero. Therefore, when the decoder receives the encoded key (D), even if the actual value of the MSB (i.e., 0) is replaced with an odd check bit, the decoder can remove the odd check bit from the MSB during the decoding process and replace it with zero.

[0051] Accordingly, by removing 0 from the MSB of the value of the key (D) and replacing it with an odd parity bit, the encoded key (D) now includes five bits corresponding to the key data, and 1 bit (i.e., the 6th bit) for the odd parity bit. For example, the key (D) can be represented as D=d1, d2, d3, d4, d5, pb, where pb corresponds to the odd parity bit, where Accordingly, the relationship between the odd parity bit and the five data bits is: Therefore, if there is an error in any of the data bits of the key (D), the odd parity correlation will no longer apply and will therefore reveal that there is an error in one of the data bits d1, d2, d3, d4 and d5.

[0052] In addition, the run length is limited to 5, because as explained above, in the worst case scenario where all data positions d1 to d5 are one, the odd check bit is zero, or if all data positions d1 to d5 are zero, the odd check bit is one. Therefore, the run length is not more than 5, and it falls within the run length limit of 10 as previously indicated for this example conversion coding technology. However, although an odd check bit is realized that can detect the existence of an error, the specific location of the error in this example is undeterminable. It should be noted that the above-described embodiment is only an example for explaining the aspect of the embodiment, and is not intended to limit. Therefore, the same or similar technology can be suitable for other schemes in which words have different places, different run limits, etc. For example, in other embodiments, words can have 8 bits, and the run length limit can be 9.

[0053] According to another embodiment of the present disclosure, the key (D) may include multiple check bits to further improve the integrity of the key. For example, similar to the above example key (D) including 6 bits (where the MSB is always zero), the 6th bit may be discarded and four additional odd check bits may be included. Accordingly, the new key (D) is 9 bits, of which 5 bits are data bits and 4 bits are check bits. In some embodiments, four odd check bits may be generated and inserted into the block. For example, the four odd check bits may be generated as follows:

[0054] pb1=inv(d1⊕d2⊕d3),

[0055] pb2=inv(d1⊕d3⊕d4),

[0056] pb3=inv(d2⊕d3⊕d5),

[0057] pb4=inv(d3⊕d4⊕d5).

[0058] Accordingly, by generating and including four check bits, if there is an error in one of the data bits, the correlation of the check bits will no longer apply, and therefore what will be revealed is that there is an error. In addition, because there are four check bits, depending on which correlation equations are no longer applicable, the system can determine which of the five data bits is wrong, and then correct the error bit. For example, if the error is in d1, the correlation equation including pb1 and pb2 will be invalid. If the error is in d2, the correlation equation including pb1 and pb3 will be invalid. If the error is in d3, the correlation equation including pb1, pb2, pb3 and pb4 will be invalid. If the error is in d4, the correlation equation including pb2 and pb4 will be invalid. If the error is in d5, the correlation equation including pb3 and pb4 will be invalid. Accordingly, the system can accurately pinpoint the error bit, and then correct the error bit, because these bits are binary, and if the error bit is zero, it becomes one, and if it is one, it becomes zero. In some embodiments, if there are two errors in a data bit, the system can detect the error but will not be able to accurately determine the error bit to correct the error. Instead, the error will only be detected.

[0059] In some embodiments, the 9-bit key is arranged so that the first two bits and the last two bits are check bits and the middle five bits are data bits. Thus, a key including an odd check bit can be represented as pb1, pb2, d1, d2, d3, d4, d5, pb3, pb4. By arranging the data bits and check bits in this way, the run length can be limited to 5 and the transition can be guaranteed in the key (D). Figure 2 is a diagram showing each combination of data bits of the key (D). Because there are 5 data bits, there are 32 possible combinations. As indicated by the shaded boxes, when all data bits are zero and when all data bits are one, the run length limit is 5. Accordingly, the run length limit satisfies the run length limit of 10 of the example conversion coding technique described in this disclosure, and accordingly, the possibility of errors and error propagation in the serial data link can be reduced.

[0060] Figure 3300 is a flowchart illustrating steps for encoding a sequence of data bits according to various embodiments of the present disclosure. According to an embodiment, an encoder is configured to receive a sequence of data bits to be encoded and transmitted to a receiver (302). In some embodiments, the data may be a packet of data, while in other embodiments, the data may be any serial data with an embedded clock signal. The sequence of data bits received at the encoder may be encoded by performing a first conversion encoding on the data bits, the first conversion encoding generating a sequence of encoded data bits based on a key (304). In some embodiments, the value of the key may be used to perform an XOR operation with the data bits to generate a sequence of encoded data bits. Therefore, when the data bits are to be decoded, the decoder relies on the key to perform the decoding operation. Accordingly, the key is important and the integrity of the key should be protected so that errors are not introduced into the key, for example, during transmission. Moreover, if the key generates an error, it is desirable to detect the presence of the error and correct the error in some cases. Accordingly, the encoder may be configured to perform protection encoding on the key to generate key protection data (306).

[0061] In some embodiments, the key protection data is a check bit. For example, an odd check bit can be generated by performing an XOR operation on each bit of the key and taking the inverse of the result. Therefore, if the key includes bits (d1, d2...dn), the odd check bit (pb) can be expressed as: pb = inv (d1⊕d2⊕...⊕dn).

[0062] Once the odd parity bit is generated, the encoder can perform a second conversion encoding on the key protection data (e.g., the odd parity bit) to generate the encoded key protection data (308). In some embodiments, the encoded key protection data can be represented as a key bit with the key protection data added. In other words, if the key protection data is an odd parity bit (pb) and the key includes an odd number of bits (d1, d2, ... dn) (where n is an odd number), the encoded key protection data can be represented as d1, d2, ... dn, pb. In other embodiments in which the parity bit is calculated according to the Hamming code, the encoded key protection data can be represented as, for example, d1, d2, ... dn, p1, p2, p3. Once the encoded key protection data is generated, the sequence of encoded data bits and the encoded key protection data can be combined into a sequence of encoded transmission bits and sent to the receiver (310). The transmitter and the receiver can be coupled to a serial data link, and the sequence of encoded transmission bits can be sent from the transmitter to the receiver via the serial data link. In some embodiments, the receiver may include a decoder that receives the sequence of encoded transmitted bits and decodes them using the key. To reduce error propagation, the integrity of the key may be verified by using included key protection data (e.g., odd check bits) to ensure that the value of the key corresponds to the odd check bit.

[0063] Figure 4 400 is a flowchart illustrating steps for encoding key protection data according to various embodiments of the present disclosure. According to an embodiment, a key can be selected so that the key protection data can be encoded with it. For example, the key can be selected by the encoder so that the most significant bit (MSB) of the value of the key is a constant (e.g., always one or always zero) (402). Therefore, by selecting a key in which the MSB is always the same value, the MSB does not necessarily have to be sent to the receiver, because the receiver can be configured to know that the MSB of the value of the key is always the same value. For example, if the selected key is a 6-bit value and the MSB of the 6th bit (i.e., the 6th bit) is always zero, the 6th bit can be removed. In contrast, the MSB can be replaced by key protection data (e.g., an odd check bit), thereby better utilizing the bandwidth occupied by the bit. Accordingly, a modified key can be generated, and the modified key can be included in the sequence of encoded transmission bits (404).

[0064] In some embodiments, the key protection data may include multiple check bits, which improves the integrity of the key by enabling detection of multiple errors in the key and correction of errors. For example, in some embodiments, the key protection data may include a Hamming code. Accordingly, catastrophic error propagation at the receiver may be reduced by optimizing serial data transmission while meeting run length requirements.

[0065] Figure 5 5 is an example block diagram of an electronic system 500. By way of example and not limitation, the electronic system 500 may be a television or a display device, and may include at least a transmitter 502 and a receiver 504, which may be configured to communicate with each other, for example, via a high-speed digital serial link 506. In some embodiments, the transmitter 502 may include an encoder 508, which takes data (e.g., digital data) that may be generated within the system 500 or received from another source (e.g., an external source), and encodes the data and then transmits the encoded data to the receiver 504. The receiver 504 may communicate with a display driver that controls, for example, pixels in a display device that emit light according to the received data. The receiver 504 may include a decoder 510, which receives the encoded data from the transmitter 502 via the high-speed digital serial link 506 and decodes the encoded data so that the data can be utilized by the electronic system 500. In some embodiments, the encoder 508 may be a transcoding encoder to perform transcoding such as the techniques described in accordance with various embodiments of the present disclosure. In yet another embodiment, encoder 508 may be configured to perform other digital encoding techniques known to those skilled in the art. It should be noted that the illustrated electronic system 500 is merely one example of an electronic system utilizing high speed serial data transmission that relies on the accuracy of the transmitted data, but one of ordinary skill in the art will appreciate that other systems are contemplated.

[0066] Unless otherwise specified, throughout the drawings and written description, the same reference numerals, characters, or combinations thereof denote the same elements, and thus description thereof will not be repeated. In addition, for clarity of description, parts that are not relevant or unrelated to the description of the embodiment may not be shown.

[0067] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. As such, unless specified, neither the presence nor the absence of cross-hatching or shading conveys or indicates any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristic, idiosyncrasy, property, etc. of an element.

[0068] In the detailed description, for the purpose of explanation, many specific details are set forth to provide a thorough understanding of the various embodiments. However, it is apparent that the various embodiments can be practiced without these specific details or with one or more equivalent arrangements. In other instances, well-known structures and devices are shown in block diagram form to avoid unnecessarily obscuring the various embodiments.

[0069] It will be understood that when an element, layer, region, or component is referred to as being "formed on," "on" another element, layer, region, or component, "connected to," or "coupled to" another element, layer, region, or component, it may be directly formed on, on, directly connected to, or coupled to, or indirectly formed on, on, indirectly connected to, or coupled to, such that there may be one or more intervening elements, layers, regions, or components. Furthermore, this may collectively mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or coupled to, or there may be intervening layers, regions, or components. However, "direct connection / direct coupling" refers to one component being directly connected or coupled to another component without an intermediate component. Meanwhile, other expressions describing the relationship between components, such as “between,” “directly between,” or “adjacent to” and “directly adjacent to,” may be similarly interpreted. In addition, it will also be understood that when an element or layer is referred to as being “between” two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers may also be present.

[0070] For the purposes of this disclosure, when a statement such as "at least one of..." follows a list of elements, it modifies the entire list of elements and does not modify the individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as only X, only Y, only Z, or any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ, or any variation thereof. Similarly, a statement such as "at least one of A and B" can include A, B, or A and B. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, a statement such as "A and / or B" can include A, B, or A and B.

[0071] It will be understood that, although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are used to distinguish an element, component, region, layer or part from another element, component, region, layer or part. Therefore, the first element, component, region, layer or part described herein can be referred to as the second element, component, region, layer or part, without departing from the spirit and scope of the present disclosure. Describing an element as a "first" element may not require or imply the presence of a second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different categories or groups of elements. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0072] The terms used herein are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure. As used herein, the singular form "a" is also intended to include the plural form, unless the context clearly indicates otherwise. It will be further understood that when the terms "comprise", "have", "include" and variations thereof are used in this specification, the existence of the features, wholes, steps, operations, elements and / or parts of the statements is specified, but the existence or addition of one or more other features, wholes, steps, operations, elements, parts and / or combinations thereof is not excluded.

[0073] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as terms of approximation rather than terms of degree, and are intended to account for the inherent deviations in measured or calculated values ​​that one of ordinary skill in the art would recognize. Taking into account problematic measurements and errors associated with the measurement of a particular quantity (i.e., limitations of the measurement system), "approximately" or "approximately" as used herein include stated values ​​and averages within an acceptable range of deviation of a particular value as determined by one of ordinary skill in the art. For example, "approximately" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of a stated value. Further, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure."

[0074] When one or more embodiments can be implemented differently, the specific process order can be performed in an order different from the described order. For example, two processes described in succession can be performed substantially simultaneously or in an order opposite to the described order.

[0075] The electronic device or electrical device according to the embodiment of the present disclosure described herein and / or any other related device or component can be implemented using any suitable hardware, firmware (e.g., an application specific integrated circuit), software, or a combination of software, firmware, and hardware to process data or digital signals. For example, the various components of these devices can be formed on an integrated circuit (IC) chip or on a separate IC chip. Further, the various components of these devices can be implemented on a flexible printed circuit film, a carrier package (TCP), a printed circuit board (PCB), or formed on a substrate. Circuit hardware may include, for example, an application specific integrated circuit (ASIC), a general or dedicated central processing unit (CPU) configured to execute instructions stored in a non-temporary storage medium, a digital signal processor (DSP), a graphics processing unit (GPU), and a programmable logic device such as a field programmable gate array (FPGA).

[0076] In addition, the various components of these devices can be processes or threads running on one or more processors in one or more computing devices, executing computer program instructions and interacting with other system components to perform the various functions described herein. The computer program instructions are stored in a memory, which can be implemented in a computing device using a standard memory device such as a random access memory (RAM) as an example. The computer program instructions can also be stored in other non-transitory computer-readable media such as a CD-ROM or flash drive as an example. In addition, it should be recognized by those skilled in the art that the functions of various computing devices can be combined or integrated into a single computing device, or the functions of a particular computing device can be distributed throughout one or more other computing devices without departing from the spirit and scope of the embodiments of the present disclosure.

[0077] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as those commonly understood by those of ordinary skill in the art to which the present disclosure belongs. It will be further understood that terms (such as those defined in general dictionaries) should be interpreted as having a meaning consistent with their meaning in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense, unless explicitly defined as such in this article.

[0078] The embodiments described herein are merely examples. Those skilled in the art may recognize various alternative embodiments from the specifically disclosed embodiments. Those alternative embodiments are also intended to be within the scope of the present disclosure. Thus, the embodiments are limited only by the appended claims and their equivalents.

Claims

1. A method performed by an electronic device, the electronic device being configured to decode data received from an encoder, the method include: receiving, by a decoder of the electronic device, a transmission bit, the transmission bit comprising a sequence of conversion-encoded data bits and conversion-encoded key protection data; Decoding the converted encoded key protection data by the decoder to generate key protection data; determining that the key is accurate based on the key protection data; as well as decoding the sequence of the converted encoded data bits by the decoder based on the accurate key to generate a sequence of decoded data bits, The key protection data is a check bit, and the converted encoded key protection data is represented by a key bit to which the key protection data is added.

2. The method according to claim 1, in, The converted encoded key protection data includes an inverted check bit.

3. The method according to claim 2, in, The generating key protection data includes inverting the inverted check bit.

4. The method according to claim 3, in, The converting the most significant bit (MSB) of the encoded key protection data comprises the key protection data, the method further comprising replacing the MSB with a constant to generate the key.

5. The method according to claim 4, in, The constant is zero.

6. The method according to claim 1, in, The key protection data includes a plurality of check bits.

7. The method according to claim 6, in, The plurality of check bits are based on a Hamming code.

8. The method according to claim 6, in, The generating key protection data includes inverting at least one of the plurality of inverted check bits.

9. The method according to claim 8, in, The converting the MSB of the encoded key protection data includes the key protection data, and the method further includes replacing the MSB with a constant to generate the key.

10. The method according to claim 9, in, The decoding of the conversion encoded key protection data further includes removing one or more of the inverted check bits from the front of the key and removing one or more of the inverted check bits from the end of the key.

11. A decoder in an electronic device, the decoder being configured to decode data received from an encoder, include: An input terminal configured to receive a sequence of transmitted bits, the sequence of transmitted bits comprising a sequence of conversion-encoded data bits and conversion-encoded key protection data; as well as A processor is configured to perform operations, the operations comprising: Decoding the converted encoded key protection data to generate key protection data; determining that the key is accurate based on the key protection data; and decoding the sequence of data bits encoded by the conversion based on the exact key to generate a sequence of decoded data bits, The key protection data is a check bit, and the converted encoded key protection data is represented by a key bit to which the key protection data is added.

12. The decoder according to claim 11, in, The converted encoded key protection data includes an inverted check bit.

13. The decoder according to claim 12, in, The generating key protection data includes inverting the inverted check bit.

14. The decoder according to claim 13, in, The converting of the most significant bit (MSB) of the encoded key protection data comprises the key protection data, and the operation further comprises replacing the MSB with a constant to generate the key.

15. The decoder according to claim 14, in, The constant is zero.

16. The decoder according to claim 11, in, The key protection data includes a plurality of check bits.

17. The decoder according to claim 16, in, The plurality of check bits are based on a Hamming code.

18. The decoder according to claim 16, in, The generating key protection data includes inverting at least one of the plurality of inverted check bits.

19. The decoder according to claim 18, in, The converting the MSB of the encoded key protection data includes the key protection data, and the operation further includes replacing the MSB with a constant to generate the key.

20. The decoder according to claim 19, in, The decoding of the conversion encoded key protection data further includes removing one or more of the inverted check bits from the front of the key and removing one or more of the inverted check bits from the end of the key.

Images