Information processing system and control method of information processing system

Abstract

The system enables performance power control of algorithms suitable for computational applications, preventing performance power delays. The information processing system includes an execution block computation intensity data area, a roofline model data storage unit, a computation intensity data acquisition unit, and a performance power control unit. The execution block computation intensity data area stores the computation intensity data of each execution block of the computational application operating in the environment of a computer system equipped with a power-saving processor and main memory. The roofline model data storage unit stores a roofline model corresponding to the processor's operating frequency and number of cores, as well as the main memory's operating frequency. The computation intensity data acquisition unit acquires the computation intensity data of each execution block. The performance power control unit controls the processor's operating frequency and number of cores, as well as the main memory's operating frequency, based on the roofline model and the computation intensity data of each execution block.

Description

Technical Field

[0001] This disclosure relates to information processing systems and methods for controlling such systems. Background Technology

[0002] In recent years, with the increasing demand for more complex and faster applications, processors installed in embedded systems have sought to improve performance by increasing the operating frequency of each core, multi-core architecture, graphics processing units (GPUs), and incorporating multiple arithmetic units, such as dedicated accelerators.

[0003] In addition, processors with Dynamic Voltage and Frequency Scaling (DVFS) functionality have been developed as one of the structures for reducing power consumption. The DVFS function is achieved by a power-saving mechanism that allows the processor to have several operating frequencies and operating voltages and changes the processor's operating frequency and operating voltage according to the processor's load conditions.

[0004] With the evolution of processors installed in embedded systems, throughput has increased. On the other hand, embedded systems require both thermal management and device miniaturization as essential conditions. Therefore, it is necessary to control the processor's power consumption while meeting the performance requirements of the application.

[0005] Previously, power-saving controls for processors have included methods that monitor the processor's load status and, when the load is high, operate the processor at a high frequency, and when the load is low, operate it at a low frequency. Patent Document 1 proposes a method for controlling reduced computing power based on statistical information related to memory performance, where memory bandwidth dominates performance. Patent Document 2 proposes a method for comparing the computational load of the Central Processing Unit (CPU) with the amount of access to cache memory, and making the processor's power-saving mechanism effective when the latter dominates.

[0006] Existing technical documents

[0007] Patent documents

[0008] Patent Document 1: International Publication No. 2008 / 120274

[0009] Patent Document 2: Japanese Patent Application Publication No. 2008-40734 Summary of the Invention

[0010] The method proposed in Patent Document 1 utilizes only statistical information related to memory access within the processor, thus failing to achieve high-precision power performance control suitable for computational applications. Furthermore, this method does not utilize the computational intensity of the applications, resulting in delays in power-saving control, particularly when high computational performance is required, leading to a low processor frequency. Additionally, this method focuses on controlling the processor's operating frequency and command issuance width, neglecting multi-core ON / OFF control and main memory operating frequency control, thus failing to achieve sufficient power-saving control.

[0011] In the method proposed in Patent Document 2, performance power control is not performed on the executable code executed by the computer in areas where the CPU execution rate is high, so there is a problem that more power than necessary is consumed in the main storage device.

[0012] This disclosure was made in view of these problems. The purpose of this disclosure is to enable performance power control of algorithms suitable for computational applications. Furthermore, the purpose of this disclosure is to prevent delays in performance power control.

[0013] This disclosure relates to information processing systems.

[0014] The information processing system includes an execution block computation intensity data area, a roof line model data storage unit, a computation intensity data acquisition unit, and a performance power control unit.

[0015] The execution block computation intensity data area maintains the computation intensity data of each execution block of the computational application that operates in the operating environment of a computer system equipped with a processor and main memory with power-saving mechanisms.

[0016] The roofline model data storage unit maintains a roofline model that corresponds to the processor's operating frequency and number of cores, as well as the operating frequency of the main storage device.

[0017] The computation intensity data acquisition unit obtains the computation intensity data of each execution block from the execution block computation intensity data area.

[0018] The performance power control unit controls the processor's operating frequency and number of cores, as well as the main memory's operating frequency, based on the roofline model and the computational intensity data of each execution block.

[0019] This disclosure also relates to control methods for information processing systems.

[0020] According to this disclosure, performance power control is performed based on computational intensity data of each execution block constituting the computing application. This enables performance power control tailored to the algorithm of the computing application. Furthermore, performance power control is performed feedforward based on predefined computational intensity data. This prevents delays in performance power control.

[0021] The purpose, features, solutions, and advantages of this disclosure will become more apparent from the following detailed description and accompanying drawings. Attached Figure Description

[0022] Figure 1 This is a block diagram schematically illustrating the hardware structure of the information processing system of Embodiment 1.

[0023] Figure 2 This is a schematic block diagram illustrating the functional structure of the information processing system of Embodiment 1.

[0024] Figure 3 This is a flowchart illustrating the operation of the basic system software installed in the information processing system of Embodiment 1.

[0025] Figure 4 This is a diagram illustrating an example of a roofline model stored in the roofline model data storage unit of the information processing system provided in Embodiment 1.

[0026] Figure 5 This is a diagram illustrating the relationship between the selectable operating frequency of the processor, the combination of cores, and the upper limit of the performance of floating decimal point operations for the roofline model stored in the roofline model data storage unit of the information processing system provided in Embodiment 1.

[0027] Figure 6 This is a diagram illustrating the relationship between the selectable operating frequency and bandwidth of the main storage device for the roofline model stored in the roofline model data storage unit of the information processing system provided in Embodiment 1.

[0028] Figure 7 This is a diagram illustrating an example of information stored in the execution block computation intensity data area of ​​the information processing system provided in Embodiment 1.

[0029] Figure 8 This is a flowchart illustrating the operation of the performance power judgment unit of the information processing system installed in Embodiment 1.

[0030] Figure 9 This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 1, where the execution block is storage-enhanced.

[0031] Figure 10This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 1, where the execution block is computationally enhanced.

[0032] Figure 11 This is a diagram illustrating an example of the overhead time spent performing various controls in the information processing system of Embodiment 1.

[0033] Figure 12 This diagram illustrates the operation of the power control delay data unit and the performance power command unit in the information processing system of Embodiment 1.

[0034] Figure 13 This is a flowchart illustrating the operation of the performance power judgment unit of the information processing system installed in Embodiment 2.

[0035] Figure 14 This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 2, where the execution block is storage-enhanced.

[0036] Figure 15 This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 2, where the execution block is storage-enhanced.

[0037] Figure 16 This diagram illustrates an example of a power-saving control policy implemented through the information processing system of Embodiment 2, where the execution block is computationally enhanced.

[0038] Figure 17 This diagram illustrates an example of a power-saving control policy implemented through the information processing system of Embodiment 2, where the execution block is computationally enhanced.

[0039] (Explanation of reference numerals in the attached diagram)

[0040] 10: Computer system; 11: Processor; 12: Main storage device; 13: Auxiliary storage device; 1000: Information processing system; 1100: System basic software; 1200: Computational application; 1110: Roofline model data storage unit; 1120: Action environment acquisition unit; 1130: Computational intensity data acquisition unit; 1140: Performance power control unit; 1141: Performance power judgment unit; 1142: Execution time measurement unit; 1143: Power control delay data unit; 1144: Performance power instruction unit; 1210: Program area; 1220: Data area; 1230: Execution block computational intensity data area. Detailed Implementation

[0041] <Implementation Method 1>

[0042] Figure 1This is a block diagram schematically illustrating the hardware structure of the information processing system of Embodiment 1.

[0043] like Figure 1 As shown in the figure, the information processing system 1000 of Embodiment 1 includes a computer system 10.

[0044] like Figure 1 As shown in the figure, the computer system 10 includes a processor 11, a main storage device 12, and an auxiliary storage device 13.

[0045] The processor 11 includes a central processing unit (CPU), a graphics processing unit (GPU), and a digital signal processor (DSP). The processor 11 has a power-saving mechanism. This mechanism dynamically changes the operating frequency and / or number of cores of the processor 11.

[0046] The main storage device 12 is a random access memory (RAM) or the like.

[0047] Auxiliary storage device 13 is a hard disk drive, solid-state drive, RAM disk, etc.

[0048] Figure 2 This is a schematic block diagram illustrating the functional structure of the information processing system of Embodiment 1.

[0049] like Figure 2 The diagram shows that the information processing system 1000 includes basic system software 1100 and computing applications 1200.

[0050] The system basic software 1100 and the computing application 1200 operate within the operating environment of the computer system 10. The system basic software 1100 may also be an operating system. There are no restrictions on the algorithm of the computing application 1200. This algorithm is a vehicle control algorithm for an autonomous vehicle that executes at a constant period.

[0051] like Figure 2 As shown in the diagram, the information processing system 1000 includes a roofline model data storage unit 1110, an operating environment acquisition unit 1120, a computational intensity data acquisition unit 1130, and a performance power control unit 1140. These elements are configured by the processor 1 executing system basic software 1100 loaded from auxiliary storage device 13 to main storage device 12.

[0052] The roofline model data storage unit 1110 maintains performance information related to the computer system 10.

[0053] The motion environment acquisition unit 1120 acquires the current motion environment of the computer system 10.

[0054] The computation intensity data acquisition unit 1130 acquires the computation intensity data of each execution block constituting the computation application 1200 from the execution block computation intensity data area 1230 described below.

[0055] The performance power control unit 1140 performs performance power control based on the maintained performance information and the acquired computational intensity data of each execution block.

[0056] In Implementation 1, the performance information maintained related to the computer system 10 includes a roofline model corresponding to the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12. Additionally, the current operating environment of the computer system 10 includes the current operating frequency and number of cores of the processor 11 and the current operating frequency of the main memory device 12. Furthermore, performance power control based on the performance information and the computational intensity data of each execution block includes controlling the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12 based on the roofline model included in the performance information and the computational intensity data of each execution block. Using the current operating environment of the computer system 10 includes using the current operating frequency and number of cores of the processor 11 and the current operating frequency of the main memory device 12 included in the current operating environment of the computer system 10.

[0057] The performance power control unit 1140 includes a performance power judgment unit 1141, an execution time measurement unit 1142, a power control latency data unit 1143, and a performance power command unit 1144.

[0058] The performance power judgment unit 1141 determines the policy for performance power control based on the maintained roof line model and the computational intensity data of each execution block.

[0059] The execution time measurement unit 1142 measures the execution time of each execution block.

[0060] The power control delay data unit 1143 determines whether to enable the performance power command unit 1144 to perform performance power control based on the overhead time spent when the performance power command unit 1144 performs performance power control.

[0061] The performance power command unit 1144 outputs control commands according to the determined performance power control policy. The performance power command unit 1144 also outputs control commands when the power control delay data unit 1143 determines that the performance power command unit 1144 should perform performance power control.

[0062] In Implementation 1, the determined performance power control policy includes the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12. Furthermore, the determined performance power control policy includes the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12 as included in the determined performance power control policy. Additionally, output control commands are executed for controlling the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12.

[0063] like Figure 2 As shown in the figure, the information processing system 1000 includes a program area 1210, a data area 1220, and an execution block computation intensity data area 1230. These elements are stored in at least one of the main storage device 12 and the auxiliary storage device 13.

[0064] Program area 1210 holds the program that constitutes the operation application 1200.

[0065] Data area 1220 holds the variables, arrangements, etc. that constitute the operational application 1200.

[0066] The execution block computation intensity data area 1230 stores the computation intensity data of each execution block constituting the computation application 1200, as well as the deadline of each execution block. The deadline of each execution block indicates the time at which the processing of each execution block must be completed.

[0067] In the information processing system 1000, performance power control is performed based on the computational intensity data of each execution block constituting the computing application 1200. This enables performance power control tailored to the algorithms of the computing application 1200.

[0068] Furthermore, in the information processing system 1000, performance power control is performed feedforward based on predefined computational intensity data. This prevents delays in performance power control.

[0069] Furthermore, the operating frequency of the main storage device 12 is controlled within the information processing system 1000. This prevents the main storage device 12 from consuming excessive power.

[0070] Figure 3 This is a flowchart illustrating the operation of the basic system software installed in the information processing system of Embodiment 1.

[0071] System basic software 1100 execution Figure 3 The illustrated steps are S100 to S105.

[0072] In step S100, the operating environment acquisition unit 1120 acquires the current operating environment of the computer system 10. At this time, the operating environment acquisition unit 1120 acquires the current operating frequency and number of cores of the processor 11 and the current operating frequency of the main storage device 12.

[0073] In the next step S101, the motion environment acquisition unit 1120 selects a roofline model corresponding to the current motion environment of the acquired computer system 10.

[0074] According to steps S100 and S101, a roofline model corresponding to the current operating environment of the computer system 10 can be referenced.

[0075] In the next step S102, the computation intensity data acquisition unit 1130 acquires the computation intensity data of the execution block to be executed next.

[0076] In the next step S103, the performance power control unit 1140 compares the selected roofline model with the obtained computational intensity data of the execution block. Additionally, the performance power control unit 1140 selects the operating environment of the computer system 10. At this time, the performance power control unit 1140 selects the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12.

[0077] In the next step S104, the performance power control unit 1140 determines whether the execution time of the execution block exceeds the deadline due to control delay when the operating environment of the computer system 10 is changed from the current operating environment to the operating environment selected in step S103. This control delay is due to the overhead time that occurs when the operating environment of the computer system 10 is changed from the current operating environment to the selected operating environment.

[0078] If the performance power control unit 1140 determines that the execution time of the execution block exceeds the deadline, it terminates the operation without executing step S105. On the other hand, if the performance power control unit 1140 determines that the execution time of the execution block does not exceed the deadline, it terminates the operation after executing step S105.

[0079] In step S105, the performance power control unit 1140 performs performance power control. At this time, the performance power control unit 1140 sets the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12 to their selected values.

[0080] Figure 4 This is a diagram illustrating an example of a roofline model stored in the roofline model data storage unit of the information processing system provided in Embodiment 1. In this diagram, computational intensity is shown on the horizontal axis. Additionally, the performance of floating decimal point operations is shown on the vertical axis.

[0081] A roofline model exists for a computer system 10, containing content corresponding to the processor 11 and main memory 12 installed in the computer system 10. Regarding the selectable computing performance of the processor 11 and the selectable memory performance of the main memory 12, the roofline model specifies upper limits for floating-point arithmetic performance relative to computing intensity. The roofline model can also specify upper limits for performance other than floating-point arithmetic performance. The computing performance of the processor 11 is a combination of the processor 11's operating frequency and the number of cores, etc. The memory performance of the main memory 12 is a combination of the main memory 12's operating frequency, etc. When the computing performance of the processor 11 is a combination of the processor 11's operating frequency and the number of cores, and the memory performance of the main memory 12 is the main memory 12's operating frequency, roofline data corresponding to the combination of the processor 11's operating frequency and the number of cores, and the main memory 12's operating frequency, can be referenced. Figure 4 In the illustrated example, the roofline model specifies upper limits for floating-point arithmetic performance for computational intensity, corresponding to the selectable operating frequencies of processor 11 ("2.6GHz", "2.4GHz", "1.8GHz", and "1.0GHz") and the bandwidths of main storage device 12 ("25.4GB / s", "16.4GB / s", and "10.6GB / s") for the selectable operating frequencies. According to the roofline model, it is possible to visually determine, based on the computational intensity of the execution block constituting the computational application 1200, whether the computational performance of processor 11 or the memory performance of main storage device 12 is dominant in the floating-point arithmetic performance when executing that execution block. Details of the roofline model are described in Samuel Williams, Andrew Waterman, and David Patterson, "Roofline: An Insightful Visual Performance Model for Floating-Point Programs and Multicore, (2009)".

[0082] Figure 5 This is a diagram illustrating the relationship between the selectable operating frequency of the processor, the combination of cores, and the upper limit of the performance of floating decimal point operations for the roofline model stored in the roofline model data storage unit of the information processing system provided in Embodiment 1.

[0083] As described above, regarding each of the selectable computing performance parameters of processor 11, the roofline model specifies an upper limit for the performance of floating decimal point operations relative to computing intensity. However, among the upper limits for the performance of floating decimal point operations relative to computing intensity specified for each of the selectable computing performance parameters of processor 11, the upper limit for the performance of floating decimal point operations is independent of computing intensity. Therefore, by specifying an upper limit for the performance of floating decimal point operations for each of the selectable computing performance parameters of processor 11, it is possible to specify an upper limit for the performance of floating decimal point operations relative to computing intensity for each of the selectable computing performance parameters of processor 11. For example, by... Figure 5 The diagram illustrates the relationship between the selectable operating frequency and core number combination of processor 11 and the upper limit of floating decimal point arithmetic performance, which allows for the determination of the upper limit of floating decimal point arithmetic performance for computational intensity for each combination of the selectable operating frequency and core number combination of processor 11.

[0084] Figure 6 This is a diagram illustrating the relationship between the selectable operating frequency and bandwidth of the main storage device for the roofline model stored in the roofline model data storage unit of the information processing system provided in Embodiment 1.

[0085] As described above, regarding each of the selectable memory performance parameters of the main memory device 12, the roofline model specifies an upper limit for the performance of floating decimal point operations relative to the computational intensity. However, the bandwidth of the main memory device 12 has a one-to-one relationship with its operating frequency. Therefore, regarding each of the selectable bandwidth parameters, an upper limit for the performance of floating decimal point operations relative to the computational intensity is specified, preparing... Figure 6 The diagram illustrates the relationship between the selectable operating frequency and bandwidth of the main storage device, thereby allowing the determination of an upper limit for the performance of floating decimal point operations for computational intensity for each of the selectable operating frequencies of the main storage device 12.

[0086] Figure 7 This is a diagram illustrating an example of information held in the execution block computation intensity data area of ​​the information processing system provided in Embodiment 1.

[0087] like Figure 7 As shown in the diagram, the execution block computation intensity data area 1230 stores the execution address of each execution block, the computation intensity data of each execution block, and the deadline of each execution block.

[0088] according to Figure 7The information shown in the diagram enables performance-power control that takes into account both performance and power consumption at a finer granularity. Furthermore, users can obtain the computational intensity data of the desired execution blocks without having to process the source code files of the computational application 1200.

[0089] In the making Figure 7 When displaying the information, a file is pre-created that includes: information that identifies the execution block, computational intensity data, and paired data including deadlines. This file is created separately from the source code file of the computation application 1200. The information that identifies the execution block includes the name of the function corresponding to the execution block, etc.

[0090] Next, compilation is performed to create an executable file for the computation application 1200 based on its source code and the generated files. If the executable file uses an executable and linkable format (ELF), dedicated sections for the computation intensity data of each execution block can be newly defined as execution block computation intensity data areas 1230 within the executable file. In this case, the information for the newly defined sections is appended to the ELF header and the section header.

[0091] During compilation, based on the information that can determine the execution block, the corresponding machine language portion within program region 1210 is determined. Within this determined machine language portion, a command that triggers a software interrupt is inserted. This interrupt-trigger command, in the case of an x86-based processor, is an INT3 command, etc. The interrupt-trigger command replaces the first byte of the original command as a breakpoint. Furthermore, the execution address of the determined machine language portion is obtained and appended to the execution block's computational data region 1230.

[0092] Independently, before executing the computational application 1200, the interrupt processor that performs a series of processes contained in the performance power control unit 1140 is registered in the interrupt descriptor table with the corresponding interrupt number.

[0093] Therefore, when the computing application 1200 is loaded into the main memory device 12 by the system base software 1100 and executed by the processor 11, a software interrupt occurs each time a block is reached. In a UNIX environment, the loading and execution of the computing application 1200 begins via the exec memory. For example, if the command that causes the software interrupt is the INT3 command, the SIGTRAP signal is sent to the system base software 1100. In the system base software 1100, in conjunction with the occurrence of the software interrupt, the interrupt handler pre-registered in the interrupt descriptor table is started, and a series of processes included in the performance power control unit 1140 are executed. At this time, the computing intensity data acquisition unit 1130 acquires the computing intensity data and the deadline of each execution block according to the execution address of each execution block. At this time, the computing intensity data acquisition unit 1130 determines the execution block loaded into the main memory device 12 corresponding to the currently executing address, and acquires the computing intensity data and the deadline of the determined execution block. In addition, the computation intensity data acquisition unit 1130 sends the acquired computation intensity data of each execution block and the deadline of each execution block to the performance power judgment unit 1141.

[0094] Figure 8 This is a flowchart illustrating the operation of the performance power judgment unit of the information processing system installed in Embodiment 1.

[0095] The performance power control unit 1140 receives the roofline model corresponding to the current operating environment from the roofline model data storage unit 1110, and receives the calculation intensity data and deadline of the next execution block from the calculation intensity data acquisition unit 1130, and then executes the operation. Figure 8 The illustrated steps are S200 to S207.

[0096] In step S200, the performance power determination unit 1141 plots the computational intensity data of the accepted execution block on the accepted roofline model. Additionally, the performance power determination unit 1141 compares the roofline model with the computational intensity data of the execution block.

[0097] In the next step S201, the performance power determination unit 1141 determines whether the execution block is memory-intensive. The performance power determination unit 1141 determines whether the memory performance of the main storage device 12 or the computing performance of the processor 11 is the performance limiting factor of the computing application 1200. If it is determined that the memory performance of the main storage device 12 is the performance limiting factor, the execution block is determined to be memory-intensive. If it is determined that the computing performance of the processor 11 is the performance limiting factor, the execution block is determined not to be memory-intensive, that is, it is determined to be computing-intensive.

[0098] If the execution block is determined to be memory-enhanced, steps S202 to S204 are executed. If the execution block is determined not to be memory-enhanced, steps S205 to S207 are executed.

[0099] In step S202, the performance power determination unit 1141 increases the operating frequency of the main storage device 12. At this time, the performance power determination unit 1141 selects an operating frequency that is higher than the current operating frequency of the main storage device 12 from the selectable operating frequencies of the main storage device 12 stored in the roof line model data storage unit 1110.

[0100] In the next step S203, the performance power determination unit 1141 updates the roofline model. At this time, the performance power determination unit 1141 updates the roofline model according to the operating frequency of the selected main storage device 12.

[0101] In the next step S204, the performance power determination unit 1141 reduces the operating frequency and / or number of cores of the processor 11 in such a way that the discontinuity between the gradient portion and the flat portion of the roofline model is located in the computational intensity. At this time, the performance power determination unit 1141 selects an operating frequency and / or number of cores that is smaller than the current operating frequency and / or number of cores of the processor 11 from the selectable operating frequencies and / or number of cores of the processor 11 stored in the roofline model data storage unit 1110.

[0102] The gradient portion of the roofline model exists within the range of computational intensity where the memory performance of the main storage device 12 becomes a speed-limiting factor. The flat portion of the roofline model exists within the range of computational intensity where the computational performance of the processor 11 becomes a speed-limiting factor.

[0103] In step S205, the performance power determination unit 1141 increases the operating frequency and / or number of cores of the processor 11. At this time, the performance power determination unit 1141 selects an operating frequency and / or number of cores that is greater than the current operating frequency and / or number of cores of the processor 11 from the selectable operating frequencies and / or number of cores of the processor 11 stored in the rooftop model data storage unit 1110.

[0104] In the next step S206, the performance power determination unit 1141 updates the roofline model. At this time, the performance power determination unit 1141 updates the roofline model according to the operating frequency and / or number of cores of the selected processor 11.

[0105] In the next step S207, the performance power determination unit 1141 reduces the operating frequency of the main storage device 12 in such a way that the discontinuity between the gradient portion and the flat portion of the roofline model is located at the computational intensity. At this time, the performance power determination unit 1141 selects an operating frequency lower than the current operating frequency of the main storage device 12 from the selectable operating frequencies of the main storage device 12 stored in the roofline model data storage unit 1110.

[0106] Figure 9 This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 1, where the execution block is storage-enhanced.

[0107] exist Figure 9 In the example of the power-saving control policy illustrated, considering the current memory performance of the main memory device 12 (shown by dashed lines) and the computing performance of the processor 11, it is decided to increase the memory performance of the main memory device 12, which would be an obstacle to the performance of the execution block, to the level shown by the gradient portion (shown by solid lines), to meet performance requirements. Furthermore, it is decided to reduce the computing performance of the processor 11 to the level shown by the flat portion (shown by solid lines) by placing the discontinuity between the gradient portion and the flat portion at the computing intensity, thereby achieving power saving. Thus, the memory performance of the main memory device 12 and the computing performance of the processor 11 are selected in a manner that transfers the memory performance of the main memory device 12 and the computing performance of the processor 11 to the level shown by solid lines.

[0108] Figure 10 This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 1, where the execution block is computationally enhanced.

[0109] exist Figure 10 In the example of the power-saving control policy illustrated, considering the current memory performance of the main memory device 12 (shown by dashed lines) and the computing performance of the processor 11, it is decided to increase the computing performance of the processor 11, which would be an obstacle to the performance of the execution block, to the computing performance of the processor 11 (shown by solid lines representing the flat portion), to meet performance requirements. Furthermore, it is decided to reduce the memory performance of the main memory device 12 to the memory performance of the main memory device 12 (shown by solid lines representing the gradient portion) by placing the discontinuity between the gradient portion and the flat portion on the computing intensity, thereby achieving power saving. Thus, by transferring the memory performance of the main memory device 12 and the computing performance of the processor 11 to the memory performance of the main memory device 12 and the computing performance of the processor 11 (shown by solid lines), the memory performance of the main memory device 12 and the computing performance of the processor 11 are selected.

[0110] according to Figure 9 as well as Figure 10 The power-saving control strategy illustrated can save power while meeting the necessary performance requirements.

[0111] Figure 11 This is a diagram illustrating an example of the overhead time spent performing various controls in the information processing system of Embodiment 1.

[0112] Predefined Figure 11 The diagram illustrates the overhead time spent performing each control. The overhead time spent performing each control includes the overhead time spent controlling the operating frequency of processor 11, the on / off state of the processor 11 core, and the operating frequency of main memory device 12.

[0113] Figure 12 This diagram illustrates the operation of the power control delay data unit and the performance power command unit in the information processing system of Embodiment 1.

[0114] like Figure 12 As shown in the diagram, the processing related to performance power control implemented through the system base software 1100 is performed via software interrupts before the execution blocks constituting the computational application are executed.

[0115] After performing the processing related to performance power control implemented through the system base software 1100, the execution time measurement unit 1142 can measure the execution time of each execution block by obtaining the current time before and after the processing. The power control delay data unit 1143 holds the measured execution time of each execution block. In addition, the power control delay data unit 1143 calculates the execution time of each execution block based on the measured execution time of each execution block and... Figure 11 The diagram illustrates the overhead time spent performing each control action, and determines whether to perform performance power control. In Embodiment 1, if the total execution time and overhead time of the execution block in the previous cycle does not exceed the deadline of the execution block obtained by the computational intensity data acquisition unit 1130, the power control delay data unit 1143 outputs a command to perform performance power control for that execution block to the performance power instruction unit 1144. On the other hand, if this is not the case, the power control delay data unit 1143 outputs a command not to perform performance power control for that execution block to the performance power instruction unit 1144.

[0116] Therefore, it is possible to perform performance and power control on each execution block while adhering to the deadline of each execution block.

[0117] <Implementation Method 2>

[0118] The differences between Embodiment 2 and Embodiment 1 will be explained below. For any points not explained, the structure used in Embodiment 1 is also adopted in Embodiment 2.

[0119] In Implementation 1, performance power control is performed based solely on the computational intensity data of each execution block constituting the computing application 1200, according to a roofline model corresponding to the current operating environment of the computer system 10. This operating environment includes the operating frequency and number of cores of the processor 11 and the operating frequency of the main memory device 12. However, the actual performance of the computing application 1200 may not match the limit performance of the computer system 10 represented by the roofline model.

[0120] Therefore, in Implementation 2, in addition to the computational intensity data of each execution block constituting the computational application 1200, the actual computational performance when executing the computational application 1200 is also utilized, thereby achieving higher precision performance power control. Hereinafter, the computational performance utilized will be referred to as "actual computational performance".

[0121] The actual computational performance of each execution block can be determined by dividing the total number of floating decimal point operations determined based on the computational intensity data of each execution block obtained by the computational intensity data acquisition unit 1130 by the execution time of each execution block held by the power control delay data unit 1143.

[0122] Figure 13 This is a flowchart illustrating the operation of the performance power judgment unit of the information processing system installed in Embodiment 2.

[0123] Performance Power Control Unit 1140 Execution Figure 13 The illustrated steps are S300 to S309.

[0124] In step S300, the performance power determination unit 1141 plots the computational intensity data of the accepted execution block on the accepted roofline model. Additionally, the performance power determination unit 1141 compares the roofline model with the computational intensity data of the execution block.

[0125] In the next step S301, the performance power determination unit 1141 determines whether the execution block is a storage-enhanced type.

[0126] If the execution block is determined to be memory-enhanced, steps S302 to S305 are executed. If the execution block is determined not to be memory-enhanced, steps S306 to S309 are executed.

[0127] In step S302, the performance power determination unit 1141 determines whether the actual computing performance of the execution block reaches the peak performance of the memory performance of the main storage device 12 in the current operating environment.

[0128] If it is determined that the actual computational performance of the execution block reaches the peak performance of the main storage device 12, steps S303 to S305 are executed. If it is determined that the actual computational performance of the execution block does not reach the peak performance of the memory, step S305 is executed.

[0129] In step S303, the performance power determination unit 1141 increases the operating frequency of the main storage device 12. At this time, the performance power determination unit 1141 selects an operating frequency that is higher than the current operating frequency of the main storage device 12 from the selectable operating frequencies of the main storage device 12 stored in the roof line model data storage unit 1110.

[0130] In the next step S304, the performance power determination unit 1141 updates the roofline model. At this time, the performance power determination unit 1141 updates the roofline model according to the operating frequency of the selected main storage device 12.

[0131] In the next step S305, the performance power determination unit 1141 reduces the operating frequency and / or number of cores of the processor 11 in such a way that the discontinuity between the gradient portion and the flat portion of the roofline model is located at the computational intensity. At this time, the performance power determination unit 1141 selects an operating frequency and / or number of cores that is smaller than the current operating frequency and / or number of cores of the processor 11 from the selectable operating frequencies and / or number of cores of the processor 11 stored in the roofline model data storage unit 1110.

[0132] In steps S302 to S305, if the actual computational performance of the execution block does not reach the peak performance of the memory performance of the main storage device 12, the operating frequency of the main storage device 12 is determined to meet the necessary conditions for the memory performance of the main storage device 12, and no selection is made.

[0133] In step S306, the performance power determination unit 1141 determines whether the actual computing performance of the execution block reaches the peak performance of the processor 11 in the current operating environment.

[0134] If it is determined that the actual computational performance of the execution block reaches the peak performance of the processor 11, steps S307 to S309 are executed. If it is determined that the actual computational performance of the execution block does not reach the peak performance of the processor 11, step S309 is executed.

[0135] In step S307, the performance power determination unit 1141 increases the operating frequency and / or number of cores of the processor 11. At this time, the performance power determination unit 1141 selects an operating frequency and / or number of cores that is greater than the current operating frequency and / or number of cores of the processor 11 from the selectable operating frequencies and / or number of cores of the processor 11 stored in the roof line model data storage unit 1110.

[0136] In the next step S308, the performance power determination unit 1141 updates the roofline model. At this time, the performance power determination unit 1141 updates the roofline model according to the operating frequency and / or number of cores of the selected processor 11.

[0137] In the next step S309, the performance power determination unit 1141 reduces the operating frequency of the main storage device 12 in such a way that the discontinuity between the gradient portion and the flat portion of the roofline model is located at the computational intensity. At this time, the performance power determination unit 1141 selects an operating frequency lower than the current operating frequency of the main storage device 12 from the selectable operating frequencies of the main storage device 12 stored in the roofline model data storage unit 1110.

[0138] In steps S306 to S309, if the actual computing performance of the execution block does not reach the peak computing performance of the processor 11, the operating frequency and number of cores of the processor 11 are determined to meet the necessary conditions for the computing performance of the processor 11 in the current operating environment, and no selection is made.

[0139] Figure 14 as well as Figure 15 This is a diagram illustrating an example of a power-saving control policy implemented through the information processing system of Embodiment 2, where the execution block is storage-enhanced.

[0140] exist Figure 14 In the example of the power-saving control policy illustrated, the actual computational performance of the execution block reaches the peak performance of the main memory device 12 in the current operating environment. Therefore, the memory performance of the main memory device 12, which would be an obstacle to the performance when executing this execution block, is improved to the memory performance shown by the solid-line gradient portion to meet the performance requirements. Furthermore, by placing the discontinuity between the gradient portion and the flat portion at the computational intensity, the computational performance of the processor 11 is reduced to the computational performance shown by the solid-line flat portion, thereby achieving power saving. Thus, the memory performance of the main memory device 12 and the computational performance of the processor 11 are transferred to the respective performances shown by the solid lines.

[0141] exist Figure 15In the example of the power-saving control policy illustrated, the actual computational performance of the execution block does not reach the peak performance of the main memory device 12 in the current operating environment. Therefore, the memory performance of the main memory device 12 is maintained so as not to become an obstacle to the performance when executing the execution block. In addition, by placing the discontinuity between the gradient portion and the flat portion on the computational intensity, the computational performance of the processor 11 is reduced to the computational performance of the processor 11 illustrated by the solid line flat portion, thereby achieving power saving. As a result, the memory performance of the main memory device 12 and the computational performance of the processor 11 are transferred to the respective performances illustrated by the solid lines.

[0142] Figure 16 as well as Figure 17 This diagram illustrates an example of a power-saving control policy implemented through the information processing system of Embodiment 2, where the execution block is computationally enhanced.

[0143] exist Figure 16 In the example of the power-saving control policy illustrated, the actual computational performance of the execution block reaches the peak performance of the processor 11 in the current operating environment. Therefore, the computational performance of the processor 11, which would otherwise hinder the performance of this execution block, is improved to the performance level of the processor 11 shown in the solid-line flat portion illustration, to meet performance requirements. Furthermore, by placing the discontinuity between the gradient portion and the flat portion at the computational intensity, the memory performance of the main memory device 12 is reduced to the memory performance of the main memory device 12 shown in the solid-line gradient portion, thus achieving power saving. Consequently, the memory performance of the main memory device 12 and the computational performance of the processor 11 are transferred to the respective performance levels shown in the solid-line illustration.

[0144] exist Figure 17 In the example of the power-saving control policy illustrated, the actual computational performance of the execution block does not reach the peak performance of the processor 11 in the current operating environment. Therefore, the computational performance of the processor 11 is maintained at a level that does not hinder the performance when executing the execution block. Furthermore, by placing the discontinuity between the gradient portion and the flat portion at the computational intensity, the memory performance of the main memory device 12 is reduced to the memory performance of the main memory device 12 illustrated by the solid line gradient portion, thereby achieving power saving. Thus, the memory performance of the main memory device 12 and the computational performance of the processor 11 are transferred to the respective performance levels illustrated by the solid lines.

[0145] Furthermore, it is possible to freely combine the various implementation methods, or to appropriately modify or omit the various implementation methods.

[0146] While the implementation methods have been described in detail, the above description is merely illustrative of all embodiments, and the implementation is not limited thereto. It should be understood that numerous variations not illustrated are conceivable.

Claims

1. An information processing system, comprising: The execution block computation intensity data area holds the computation intensity data of each execution block that constitutes the computational application operating in the operating environment of the computer system. The computer system has a processor with a power-saving mechanism and a main memory device. The roofline model data storage unit maintains roofline models that correspond to the selectable operating frequency and number of cores of the processor and the selectable operating frequency of the main storage device. The computation intensity data acquisition unit acquires the computation intensity data of each execution block from the execution block computation intensity data region; and The performance power control unit controls the operating frequency and number of cores of the processor and the operating frequency of the main memory device based on the roofline model and the computational intensity data of each execution block. Regarding the selectable computing performance of the processor and the selectable memory performance of the main storage device, the roofline model specifies an upper limit for the computing performance for computing intensity.

2. The information processing system according to claim 1, wherein, It includes an operating environment acquisition unit that acquires the current operating frequency and number of cores of the processor and the current operating frequency of the main storage device.

3. The information processing system according to claim 1, wherein, The execution block computation intensity data area stores the execution address of each execution block, the computation intensity data of each execution block, and the deadline of each execution block, which indicates the time when the processing of each execution block must be completed.

4. The information processing system according to claim 2, wherein, The execution block computation intensity data area stores the execution address of each execution block, the computation intensity data of each execution block, and the deadline of each execution block, which indicates the time when the processing of each execution block must be completed.

5. The information processing system according to claim 3 or 4, wherein, The computation intensity data acquisition unit obtains the computation intensity data of each execution block and the deadline of each execution block based on the execution address of each execution block.

6. The information processing system according to any one of claims 1 to 4, wherein, The roofline model specifies upper limits for performance for computational intensity, relating to each combination of selectable operating frequencies and core counts of the processor and each selectable operating frequency of the main storage device.

7. The information processing system according to any one of claims 1 to 4, wherein, The performance power control unit includes: The performance power judgment unit determines the operating frequency and number of cores of the processor and the operating frequency of the main memory device based on the roof line model and the computational intensity data of each execution block. The execution time measurement unit measures the execution time of each execution block; The performance power instruction unit performs the control according to the operating frequency and number of cores of the processor and the operating frequency of the main memory device determined by the performance power determination unit; as well as The power control delay data unit determines whether to enable the performance power command unit to perform the control based on the overhead time spent when the performance power command unit performs the control.

8. The information processing system according to claim 7, wherein, The performance power judgment unit: By comparing the roofline model with the computational intensity data of each execution block, Determine which of the following factors—the memory performance of the main storage device and the computing performance of the processor—is the performance limiting factor for the computing application. If the memory performance is determined to be the speed limiting factor, an operating frequency higher than the current operating frequency of the main storage device is selected from the selectable operating frequencies of the main storage device held in the roofline model data storage unit. If the computing performance is determined to be the speed limiting factor, an operating frequency and / or number of cores greater than the current operating frequency and / or number of cores is selected from the selectable operating frequency and / or number of cores of the processor stored in the roofline model data storage unit.

9. The information processing system according to claim 7, wherein, The power control delay data unit determines whether to perform the control based on the execution time of each execution block measured by the execution time measurement unit and the predefined overhead time spent to perform each control.

10. The information processing system according to claim 7, wherein, When the power control delay data unit determines that the control should be performed, the performance power instruction unit sets the operating frequency and number of cores of the processor and the operating frequency of the main memory device, as determined by the performance power determination unit, to the operating frequency and number of cores of the processor and the operating frequency of the main memory device.

11. A control method for an information processing system, comprising: a) A process for maintaining computational intensity data of each execution block of a computational application that operates in the operating environment of a computer system, the computer system having a processor with a power-saving mechanism and a main memory device. b) The process of obtaining the computational intensity data of each execution block; c) The process of storing roofline models corresponding to the selectable operating frequency and number of cores of the processor and the selectable operating frequency of the main storage device; and d) The process of controlling the operating frequency and number of cores of the processor and the operating frequency of the main memory device based on the roofline model and the computational intensity data of each execution block. Regarding the selectable computing performance of the processor and the selectable memory performance of the main storage device, the roofline model specifies an upper limit for the computing performance for computing intensity.

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