A method and apparatus for processing a graph instruction

Abstract

The application discloses a kind of graph instruction processing method and device, it is related to computer technical field, for reducing the demand for bus resource and instruction space resource in graph instruction processing process.Method comprising: detecting whether there is conditional instruction element in first graph instruction;When there is conditional instruction element in first graph instruction, determine that first graph instruction is conditional execution instruction, and when the data flow information and control flow information of first graph instruction are both in preparation completion state, process first graph instruction;When there is no conditional instruction element in first graph instruction, determine that first graph instruction is non-conditional execution instruction, and when the data flow information of first graph instruction is in preparation completion state, process first graph instruction.

Description

Technical Field

[0001] The present application relates to the field of computer technology, and in particular to a method and device for processing graphic instructions. Background Art

[0002] A directed graph flow architecture transforms data and control flows into a directed graph consisting of N nodes. Each node's connection represents a data flow or a control flow. In a directed graph flow architecture, data flow parallelism is triggered by checking whether the inputs of each node in the architecture are ready.

[0003] In a directed graph flow computing architecture, for graph instructions with conditional inputs (e.g., if-else branch operations), it is necessary to convert the control flow dependencies into data flow dependencies. In the prior art, switch instructions and gate instructions are usually used to convert the control flow dependencies into data flow dependencies. For example, Figure 1 As shown in (a) in FIG, for an instruction that needs to determine whether the conditional input p is true (true, T), a gate instruction with a result of T can be set at the conditional input end of the instruction, so that when the conditional input of the instruction is T and the left input and the right input are ready (ready), the operation can be performed by the arithmetic logic unit (ALU); Figure 1 As shown in (b), for an instruction that needs to determine whether the conditional input p is false (false, F), a gate instruction with a result of F can be set at the conditional input end of the instruction, so that when the conditional input of the instruction is F and the left input and the right input are ready (ready), the operation can be performed through the ALU.

[0004] However, when switch and gate instructions are used to convert control flow dependencies into data flow dependencies, these instructions consume a clock cycle of computing resources and a certain amount of bus resources. Furthermore, when a directed graph flow computing architecture includes a large number of switch and gate instructions, it consumes a large amount of instruction space resources in the processor. In addition, the use of switch and gate instructions also limits the parallelism between instructions, thereby affecting the processor's operating performance. Summary of the Invention

[0005] The present application provides a method and apparatus for processing a graph instruction, which are used to reduce the demand for bus resources and instruction space resources during the processing of a graph instruction.

[0006] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0007] In a first aspect, a method for processing a graph instruction is provided. The method includes detecting whether a first graph instruction includes a conditional instruction element. When the first graph instruction includes the conditional instruction element, the first graph instruction is determined to be a conditional execution instruction, and the first graph instruction is processed when both data flow information and control flow information of the first graph instruction are in a ready-to-complete state. The data flow information can include left input and right input. The control flow information can include a conditional input. When the first graph instruction does not include the conditional instruction element, the first graph instruction is determined to be a non-conditional execution instruction, and the first graph instruction is processed when the data flow information of the first graph instruction is in the ready-to-complete state. The data flow information can include left input and right input.

[0008] In the above technical solution, whether the first graph instruction includes the conditional instruction element is detected. When the first graph instruction includes the conditional instruction element, the first graph instruction is determined to be the conditional execution instruction. When the first graph instruction does not include the conditional instruction element, the first graph instruction is determined to be the non-conditional execution instruction. Subsequently, the first graph instruction can be processed according to whether the first graph instruction is the conditional execution instruction or the non-conditional execution instruction, thereby reducing the demand for bus resources and instruction space resources in the process of processing the graph instruction. The technical solution does not need to convert the dependency relationship of the control flow into the dependency relationship of the data flow, thereby not needing to use a large number of switch instructions and gate instructions, and thereby ensuring the running performance of the processor.

[0009] In a possible implementation manner of the first aspect, the conditional instruction element is 1 bit. For example, when the value of the 1 bit is 1, it indicates that the first graph instruction includes the conditional instruction element. When the value of the 1 bit is 0, it indicates that the first graph instruction does not include the conditional instruction element. In addition or alternatively, the control flow information is 1 bit. For example, the control flow information is a 1-bit conditional signal. In the above possible implementation manner, when the conditional instruction element is 1 bit or the control flow information is 1 bit, the demand for bus resources of the conditional instruction element or the control flow information can be reduced as much as possible.

[0010] In a possible implementation manner of the first aspect, the conditional instruction element and the control flow information are transmitted through a control bus, and the data flow information is transmitted through a data bus. In the above possible implementation manner, the conditional instruction element and the control flow information can interfere with the data flow information.

[0011] In a possible implementation of the first aspect, the method further includes: receiving a first broadcast message, the first broadcast message is used to indicate a first broadcast channel; when the broadcast channel registered by the first graph instruction is the first broadcast channel, determining that the control flow information of the first graph instruction is in a ready state; optionally, the first broadcast channel is registered with at least one graph instruction, at least one graph instruction is related to the first processing result of the second graph instruction, and the at least one graph instruction here includes the first graph instruction, and the method further includes: when the processing result of the second graph instruction is the first processing result, sending the first broadcast message. In the above possible implementation, when the second graph instruction has a large number of output addresses, the processing result of the second graph instruction can be transmitted to the graph instructions corresponding to multiple output addresses at the same time by broadcasting, thereby improving the processing rate of the graph instruction.

[0012] In one possible implementation of the first aspect, the method further includes: when the processing result of the second graph instruction is the second processing result, sending second broadcast information, the second broadcast information being used to indicate a second broadcast channel, and the broadcast channel registered for at least one graph instruction related to the second processing result being the second broadcast channel. In the above possible implementation, when the second graph instruction has multiple output addresses, the processing result of the second graph instruction can be simultaneously transmitted to the graph instructions corresponding to the multiple output addresses via broadcast, thereby increasing the processing rate of the graph instructions.

[0013] In one possible implementation of the first aspect, the method further includes: during the compilation of the first graph instruction, registering the first graph instruction in a first broadcast channel. In this possible implementation, multiple graph instructions registered on the same broadcast channel can simultaneously obtain corresponding control flow information, thereby improving the processing rate of the graph instructions.

[0014] In a possible implementation of the first aspect, when the control flow information of the first graph instruction includes a logical operation, the logical operation is used to generate at least one conditional signal; optionally, the control flow information of the first graph instruction includes an OR operation, then the left input and right input corresponding to the OR operation can be used to generate a conditional signal respectively, and the arrival of at least one of the two generated conditional signals can determine that the conditional input of the first graph instruction is ready; or, the control flow information of the first graph instruction includes an AND operation, then the left input and right input corresponding to the AND operation can be used to generate a conditional signal respectively, and the arrival of both generated conditional signals can determine that the conditional input of the first graph instruction is ready. In the above possible implementations, the control flow information includes a logical operation that is only used to generate a conditional signal with a smaller data bit width, and does not need to occupy a larger data bit width like the data flow information of the graph instruction, thereby reducing the demand for bus resources during the processing of the graph instruction.

[0015] In one possible implementation of the first aspect, when the first graph instruction is a read instruction or a write instruction, the method further includes: determining, based on a preset read and write order, a graph instruction that transmits control flow information for the first graph instruction. For example, the preset read and write order may be the read and write order in the original program corresponding to the first graph instruction. In the above possible implementation, by determining, based on the preset read and write order, the graph instruction that transmits control flow information for the first graph instruction, read instructions and write instructions that may have a dependency relationship can be associated via conditional signals, thereby implementing the read and write order of memory in the original program.

[0016] In a second aspect, a graph instruction processing device is provided, which includes: a status buffer unit, an arbitration unit and an operation unit; wherein the status buffer unit is used to detect whether a conditional instruction element exists in the first graph instruction; the status buffer unit and the arbitration unit are also used to determine that the first graph instruction is a conditional execution instruction when a conditional instruction element exists in the first graph instruction, and the operation unit is used to process the first graph instruction when the data flow information and the control flow information of the first graph instruction are both in a ready state; the status buffer unit and the arbitration unit are also used to determine that the first graph instruction is a non-conditional execution instruction when there is no conditional instruction element in the first graph instruction, and the operation unit is also used to process the first graph instruction when the data flow information of the first graph instruction is in a ready state.

[0017] In a possible implementation of the second aspect, the conditional instruction element is 1 bit, for example, when the value of this 1 bit is 1, it indicates that the conditional instruction element exists in the first graph instruction, and when the value of this 1 bit is 0, it indicates that the conditional instruction element does not exist in the first graph instruction; and / or, the control flow information is 1 bit, for example, the control flow information is a 1-bit conditional signal.

[0018] In a possible implementation manner of the second aspect, the apparatus further includes a control bus and a data bus, the conditional instruction element and the control flow information are transmitted via the control bus, and the data flow information is transmitted via the data bus.

[0019] In a possible implementation of the second aspect, the device also includes: a listening register; a listening register for receiving first broadcast information, the first broadcast information being used to indicate a first broadcast channel; a status buffer unit, further for marking the control flow information of the first graph instruction as ready when the broadcast channel registered for the first graph instruction is the first broadcast channel.

[0020] In a possible implementation of the second aspect, at least one graph instruction is registered with the first broadcast channel, and the at least one graph instruction is related to the first processing result of the second graph instruction. The at least one graph instruction here includes the first graph instruction. The device also includes: an output unit, which is used to send the first broadcast information when the processing result of the second graph instruction is the first processing result.

[0021] In a possible implementation of the second aspect, the output unit is also used to: when the processing result of the second graph instruction is the second processing result, send a second broadcast message, the second broadcast message is used to indicate a second broadcast channel, and the broadcast channel registered for at least one graph instruction related to the second processing result is the second broadcast channel.

[0022] In a possible implementation manner of the second aspect, the apparatus further includes: a compiler, configured to register the first graph instruction in the first broadcast channel during a process of compiling the first graph instruction.

[0023] In a possible implementation of the second aspect, when the control flow information of the first diagram instruction includes a logical operation, the logical operation is used to generate at least one conditional signal; optionally, the control flow information of the first diagram instruction includes an OR operation, then the left input and right input corresponding to the OR operation can be used to generate a conditional signal respectively, and the arrival of at least one of the two generated conditional signals can determine that the conditional input preparation of the first diagram instruction is completed; or, the control flow information of the first diagram instruction includes an AND operation, then the left input and right input corresponding to the AND operation can be used to generate a conditional signal respectively, and the arrival of both generated conditional signals can determine that the conditional input preparation of the first diagram instruction is completed.

[0024] In a possible implementation of the second aspect, when the first graph instruction is a read instruction or a write instruction, the device also includes: a compiler, used to determine the graph instruction that emits the control flow information of the first graph instruction based on a preset read and write order. For example, the preset read and write order can be the read and write order in the original program corresponding to the first graph instruction.

[0025] In another aspect of the present application, a graph instruction processing device is provided, which includes a processor and a memory, in which instructions are stored. When the processor runs the instructions, the instruction processing device executes the graph instruction processing method provided by the first aspect or any possible implementation of the first aspect.

[0026] In another aspect of the present application, a readable storage medium is provided, in which instructions are stored. When the readable storage medium is run on a device, the device executes the graph instruction processing method provided by the first aspect or any possible implementation of the first aspect.

[0027] In another aspect of the present application, a computer program product is provided. When the computer program product is run on a computer, the computer is caused to execute the graph instruction processing method provided by the first aspect or any possible implementation of the first aspect.

[0028] It can be understood that the device, electronic device, computer storage medium or computer program product of any of the above-mentioned graph instruction processing methods is used to execute the corresponding method provided above. Therefore, the beneficial effects that can be achieved can refer to the beneficial effects in the corresponding method provided above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 A schematic diagram of the operation of a graph instruction with conditional input;

[0030] Figure 2 A schematic diagram of a directed graph flow computing architecture provided in an embodiment of the present application;

[0031] Figure 3 A schematic diagram of the structure of a processor provided in an embodiment of the present application;

[0032] Figure 4 A schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0033] Figure 5 A flowchart of a method for processing a graph instruction provided in an embodiment of the present application;

[0034] Figure 6 A schematic diagram of the operation of a graph instruction provided in an embodiment of the present application;

[0035] Figure 7 A schematic diagram of monitoring broadcast information provided in an embodiment of the present application;

[0036] Figure 8 A schematic diagram of another directed graph flow computing architecture provided in an embodiment of the present application;

[0037] Figure 9 A schematic diagram of another directed graph flow computing architecture provided in an embodiment of the present application;

[0038] Figure 10 A schematic diagram of another directed graph flow computing architecture provided in an embodiment of the present application;

[0039] Figure 11 A schematic diagram of another directed graph flow computing architecture provided in an embodiment of the present application;

[0040] Figure 12 A schematic diagram of a flow chart of a graph instruction processing device provided in an embodiment of the present application;

[0041] Figure 13 A schematic diagram of a flow chart of another image instruction processing device provided in an embodiment of the present application;

[0042] Figure 14A schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0043] Figure 15 A schematic diagram of the structure of another processor provided in an embodiment of the present application;

[0044] Figure 16 A schematic diagram of a source code synthesis compilation and execution process provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In the present application, "at least one" means one or more, and "more" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a, b or c can mean: a, b, c, ab, ac, bc, or abc, where a, b, c can be single or multiple. In addition, in the embodiments of the present application, words such as "first" and "second" do not limit the quantity and execution order.

[0046] It should be noted that, in this application, words such as "exemplary" or "for example" are used to indicate examples, illustrations, or descriptions. Any embodiment or design described in this application as "exemplary" or "for example" should not be construed as being preferred or advantageous over other embodiments or designs. Rather, the use of words such as "exemplary" or "for example" is intended to present the relevant concepts in a concrete manner.

[0047] As used in this description, the terms "component," "module," "system" and the like are intended to refer to a computer-related entity, either hardware, software, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to being, a process running on a processor, a processor, an object, an executable, a thread of execution, a program, and / or a computer. By way of illustration, both an application running on a computing device and the computing device can be a component. One or more components can reside within a process and / or thread of execution and a component can be localized, partially localized, and / or distributed across two or more computers. Also, these components can execute from various computer readable media having various data structures stored thereon. The components can communicate by way of local and / or remote processes such as in accordance with a signal having one or more data packets (e.g., data from one component interacting with another component in a local system, distributed system, and / or across a network such as the Internet with other systems via the signal).

[0048] To facilitate understanding of the technical solutions of the embodiments of the present application, first, the directed graph flow computing architecture involved in the embodiments of the present application is introduced and described.

[0049] The directed graph flow computing architecture converts data flow and control flow into a directed graph composed of N nodes, and the connection between nodes represents a data flow or a control flow, and each node is a graph instruction. For the graph instruction in the directed graph flow computing architecture, once the input required by the graph instruction is prepared, the graph instruction can perform operation and transmit the result to the corresponding input of the lower-level graph instruction. Wherein, the input required by a graph instruction can include left input (l) and right input (r), which can be referred to as data flow; further, the input required by a graph instruction can also include conditional input (p), which can be referred to as control flow. In the directed graph flow computing architecture, only the address of the output needs to be provided without providing the input information of the instruction, and each graph instruction only needs to ensure that the input of the graph instruction has the operation result of a single or multiple graph instructions. Therefore, the directed graph flow computing architecture has the advantage of simple coding.

[0050] For example, Figure 2The directed graph flow computing architecture shown includes 6 graph instructions, and the corresponding IDs are represented as 0 to 5. Among them, graph instruction 0 is connected to the right input (r) of the next-level graph instruction 3, graph instructions 1 and 2 are respectively connected to the left input (l) and right input (r) of the next-level graph instruction 4, and graph instructions 3 and 4 are respectively connected to the left input (l) and right input (r) of the next-level graph instruction 5. Taking the add operation a+b in graph instruction 1 as an example, in the graph architecture instruction set, graph instruction 1 can be represented as "1 add 4l", which means: once a and b of graph instruction 1 are ready, the result of the a+b operation of graph instruction 1 is passed to the left input (l) of graph instruction 4. Figure 2 sll, add, mul and st in the expression represent different operators respectively, i, a, c and A in the left input (l), and 2, b and d in the right input (l) represent different input operands respectively.

[0051] In the directed graph flow computing architecture, multiple graph instructions without dependencies can be executed concurrently to increase the computing speed. Figure 2 In the directed graph flow computing architecture shown, graph instruction 0, graph instruction 1 and graph instruction 2 can be executed in the first beat, graph instruction 3 and graph instruction 4 can be executed in the second beat, and graph instruction 5 can be executed in the third beat.

[0052] In a directed graph flow computing architecture, for graph instructions with conditional input (for example, branch operations such as if-else), it is necessary to convert the control flow dependencies into data flow dependencies. Switch instructions and gate instructions can usually be used to convert the control flow dependencies into data flow dependencies. However, when switch instructions and gate instructions are used to convert the control flow dependencies into data flow dependencies, these switch instructions or gate instructions will occupy one beat of computing resources and certain bus resources. Furthermore, when the instruction set corresponding to the directed graph flow computing architecture includes a large number of switch instructions and gate instructions, a large amount of space resources in the processor will be consumed. In addition, the use of switch instructions and gate instructions will also limit the parallelism between instructions, which will affect the operating performance of the processor.

[0053] Based on this, the embodiments of the present application provide a graph instruction processing method and apparatus for solving a series of problems caused by converting the dependencies of control flow into dependencies of data flow in a directed graph flow computing architecture. The technical solution provided by the embodiments of the present application can be applied to electronic devices including a processor, for example, the electronic device can be a computer, a mobile phone, a tablet, a personal digital assistant, a smart wearable device, a smart car, a smart home appliance, and other types of devices. Among them, the specific description of the architecture of the processor in the electronic device can be as described below.

[0054] Figure 3 and Figure 4 An architectural diagram of a processor provided for an embodiment of the present application, the processor architecture can be used to execute the above-mentioned directed graph flow computing architecture. The processor architecture may include one or more processing engines (PEs), each PE may include a state buffer, an arbitration logic unit, one or more arithmetic logic units (ALUs), and a write-back unit, etc.; optionally, each PE may also include an output unit (OU). Among them, the state buffer can be used to cache graph instructions, ready fields and valid fields related to graph instructions, and the output address (destination, dest) of the graph instructions in the directed graph flow computing architecture, where the valid field is used to indicate whether the graph instruction requires input parameters, and the ready field is used to indicate whether each input parameter of the graph instruction is ready; the arbitration logic unit can be used to select a graph instruction through the information that the input of each graph instruction is ready, and send it to the ALU; the ALU can be used to execute graph instruction operations; the write-back unit can be used to write data in the state buffer, for example, to mark the ready field and valid field of each graph instruction in the state buffer, etc. Optionally, the processor architecture may further include a compiler for compiling the program or code to be compiled into an instruction set of the directed graph flow computing architecture. Figure 3 and Figure 4 The compiler, arbitration logic unit and write-back unit are not shown.

[0055] In one embodiment, the processor architecture may further include one or more clusters, each cluster may include multiple PEs, and the multiple clusters and the multiple PEs included in each cluster may communicate with each other through a switch or a router.

[0056] Figure 3 In the description, an example is given in which the processor architecture includes a cluster, the cluster includes four PEs, and the four PEs communicate through a switch. The four PEs are respectively represented as PE0, PE1, PE2, and PE3. Figure 4 (a) in the figure is explained by taking the processor architecture including two clusters and each cluster including four PEs and a switch as an example. The PEs in the two clusters can communicate between clusters and between multiple PEs in the same cluster through the two switches. Figure 4 (b) is explained by taking the example that the processor architecture includes 4 clusters and each cluster includes 4 PEs and a switch. The PEs in the four clusters can communicate between clusters and between multiple PEs in the same cluster through the four switches.

[0057] It should be noted that Figure 3 In the figure, multiple (for example, 8) graph instructions in each PE share one ALU as an example. Of course, multiple (for example, P) graph instructions in each PE can also share multiple (for example, X) ALUs. For example, P = 8 and X = 3, that is, 8 graph instructions in each PE can share 3 ALUs, that is, each PE can execute 3 graph instructions simultaneously in one beat.

[0058] in addition, Figure 3 In the figure, id represents the identifier of the graph instruction, opc represents the operator symbol of the graph instruction, op0 represents the left input operand, op1 represents the right input operand, p represents the conditional input, R represents the ready field, V represents the valid field, add, mul and cmp.ge represent different operators respectively, and dest0 and dest1 represent the output addresses of the graph instruction respectively.

[0059] Specifically, in Figure 3 In the example, PE0 can be used to execute graph instructions with ids of 0 to 7, PE1 can be used to execute graph instructions with ids of 8 to 15, PE2 can be used to execute graph instructions with ids of 16 to 23, and PE4 can be used to execute graph instructions with ids of 24 to 31. In PE0, the output addresses of the graph instruction with id 1 are 2l and 4r, that is, the operation result of the graph instruction with id 1 is passed to the left input of the graph instruction with id 2 and the right input of the graph instruction with id 4; the output address of the graph instruction with id 2 is 3l, that is, the operation result of the graph instruction with id 2 is passed to the left input of the graph instruction with id 3; the output address of the graph instruction with id 3 is 4r, that is, the operation result of the graph instruction with id 3 is passed to the right input of the graph instruction with id 4; the output addresses of the graph instruction with id 4 are 2p and 12p, that is, the operation result of the graph instruction with id 4 is passed to the conditional input of the graph instruction with id 2 and the conditional input of the graph instruction with id 12. The graph instruction with id 4 is in PE0, and the graph instruction with id 12 is in PE1, that is, these two graph instructions are not in the same PE. Then, when the operation of the graph instruction with id 4 is completed, the OU in PE0 can pass the operation result of the graph instruction with id 4 to the OU in PE1 through the switch, and the OU in PE1 will pass it to the conditional input of the graph instruction with id 12.

[0060] Figure 5 A flowchart of a method for processing a graph instruction provided in an embodiment of the present application is provided. The method can be applied to the processor provided above, and the method includes the following steps.

[0061] S301: Detect whether a conditional instruction element exists in the first diagram instruction. If so, determine that the first diagram instruction is a conditional execution instruction. If not, determine that the first diagram instruction is an unconditional execution instruction.

[0062] Among them, a graph instruction may refer to a graph instruction in a directed graph computing architecture instruction set, which may include multiple graph instructions, and each graph instruction may correspond to one or more ready fields and one or more valid fields. The valid field of a graph instruction is used to indicate whether the graph instruction requires input data flow information and control flow information, the data flow information may include left input and right input, and the control flow information may include conditional input; the ready field of a graph instruction is used to indicate whether the data flow information and control flow information of the graph instruction are ready, for example, whether the left input and right input in the data flow information are ready, and whether the conditional input in the control flow is ready. For example, taking a graph instruction with an unconditional input and operation "a+b" as an example, the valid field of the graph instruction can be used to indicate that the data flow information required by the graph instruction includes left input a and right input b, and the ready field of the graph instruction can be used to indicate whether a and b are ready.

[0063] In addition, the first graph instruction may be any graph instruction in the instruction set. For example, the first graph instruction may refer to a graph instruction having a left input, a right input, and a conditional input, or may refer to a graph instruction having only a left input and a right input. Whether the first graph instruction has a conditional instruction element may also refer to whether the processing of the first graph instruction needs to wait for the control flow information of the first graph instruction. When the first graph instruction has a conditional instruction element, the first graph instruction is a conditional execution instruction, that is, the processing of the first graph instruction needs to wait for the control flow information; when the first graph instruction does not have a conditional instruction element, the first graph instruction is an unconditional execution instruction, that is, the processing of the first graph instruction does not need to wait for the control flow information.

[0064] Optionally, the conditional instruction element can be 1 bit, and the value of this 1 bit can be 0 or 1. For example, when the value of this 1 bit is 1, it indicates that the conditional instruction element exists in the first diagram instruction, so that the processing of the first diagram instruction needs to wait for the condition input; when the value of this 1 bit is 0, it indicates that the conditional instruction element does not exist in the first diagram instruction, so that the processing of the first diagram instruction does not need to wait for the condition input. Of course, in actual applications, when the value of this 1 bit is 0, it may also correspond to the presence of the conditional instruction element in the first diagram instruction, and when the value of this 1 bit is 1, it may also correspond to the absence of the conditional instruction element in the first diagram instruction. The embodiment of the present application does not impose specific restrictions on this.

[0065] Specifically, whether the first graph instruction has a conditional instruction element can be configured for the first graph instruction during the compilation process. For example, the compiler in the processor can configure the conditional instruction element (for example, setting the value of the above 1 bit to 1) or not configure the conditional instruction element (for example, setting the value of the above 1 bit to 0) for the first graph instruction during the compilation process, and store the configured related information, so that the PE in the subsequent processor can read the stored related information when processing the first graph instruction.

[0066] For example, Figure 6 As shown in the figure, the add operation of graph instruction 2 can be compiled as "2padd" during compilation; the sub operation of graph instruction 3 can be compiled as "3p sub" during compilation. Here, 2 and 3 represent the IDs of graph instructions 2 and 3, respectively. The "p" before "add" and "sub" here indicates a conditional instruction element, meaning that the processing of graph instructions 2 and 3 requires waiting for conditional input.

[0067] S302a: When the first diagram instruction is a conditional execution instruction, the first diagram instruction is processed when both the data flow information and the control flow information of the first diagram instruction are in a prepared state.

[0068] Among them, the data flow information and control flow information in the embodiment of the present application are both in the ready state, which can mean that the data flow information and the control flow information are both ready (also called arrived). For example, the ready field of the first diagram instruction indicates that the left input, right input and conditional input of the first diagram instruction have all arrived, that is, the data flow information and control flow information of the first diagram instruction are both in the ready state.

[0069] Specifically, when the processor detects that there is a conditional instruction element in the first-graph instruction, that is, the first-graph instruction is a conditional execution instruction or the processing of the first-graph instruction needs to wait for control flow information, the processor can detect whether the data flow information of the first-graph instruction and the control flow information of the first-graph instruction are ready (also referred to as whether they have arrived), and when the data flow information and the control flow information are both ready (for example, the ready field of the first-graph instruction indicates that the left input, right input and conditional input of the first-graph instruction have all arrived), the processor can execute the first-graph instruction according to the data flow information and the control flow information.

[0070] In one embodiment, the control flow information (e.g., conditional input) of the first graph instruction can be generated by other graph instructions that have a dependency on the first graph instruction and are processed before the first graph instruction. Optionally, the control flow information of the first graph instruction can include a 1-bit conditional signal. In another embodiment, the data flow information (e.g., left input and right input) of the first graph instruction can also be generated by other graph instructions that have a dependency on the first graph instruction and are processed before the first graph instruction.

[0071] For example, Figure 6 As shown, assuming that the first graph instruction is graph instruction 2, and the valid field of graph instruction 2 is 111 (indicating that graph instruction 2 requires input of left input l, right input r, and conditional input p), the conditional input of graph instruction 2 is generated by the processing result of graph instruction 1 "cmp.ge2p (greater than or equal to), 3p (less than)", where cmp.ge is a comparison instruction. The p after cmp.ge indicates that the graph instruction needs to send a conditional signal (i.e., control flow information), and if the processing result of cmp.ge is greater than, a 1-bit conditional signal is sent to graph instruction 2. If the processing result of cmp.ge is less than, a 1-bit conditional signal is sent to graph instruction 3. When the ready field of graph instruction 2 is 111, it means that the left input l, right input r, and conditional input p of graph instruction 2 are all ready, and the processor can execute graph instruction 2. Figure 6 In the following, the left input l, right input r, and conditional input p of instruction 2 are all 1 as an example.

[0072] S302b: When the first diagram instruction is a non-conditional execution instruction, the first diagram instruction is processed when the data flow information of the first diagram instruction is in a ready state.

[0073] Specifically, when the processor detects that there is no conditional instruction element in the first graph instruction, that is, the first graph instruction is a non-conditional execution instruction or the processing of the first graph instruction does not need to wait for control flow information, the processor can detect whether the data flow information of the first graph instruction is ready (also known as whether it has arrived), and when the data flow information is ready (for example, the ready field of the first graph instruction indicates that both the left input and the right input of the first graph instruction have arrived), the processor can execute the first graph instruction according to the data flow information.

[0074] Optionally, the conditional instruction element and the control flow information (e.g., conditional input or conditional signal) are transmitted via a control bus, and the data flow information (e.g., left input and right input) is transmitted via a data bus. For example, the transmission of conditional instruction elements or conditional signals across PEs can be transmitted through one switch, and the transmission of left inputs and right inputs across PEs can be transmitted through another switch. This can reduce the interference of conditional instruction elements and control flow information on data flow information, and at the same time, can enable the conditional instruction element to be transmitted to any graph instruction in any PE in the processor within one beat.

[0075] In the embodiment of the present application, whether the first graph instruction has a conditional instruction element is detected. If the first graph instruction has a conditional instruction element, it is determined that the first graph instruction is a conditional execution instruction. If the first graph instruction does not have a conditional instruction element, it is determined that the first graph instruction is a non-conditional execution instruction. Subsequently, the first graph instruction can be processed according to whether the first graph instruction is a conditional execution instruction or a non-conditional execution instruction, thereby reducing the demand for bus resources and instruction space resources in the process of processing graph instructions. For example, as shown in Figure 6 For example, by adding p in front of the operators of the graph instruction 2 and the graph instruction 3, it is indicated that the processing of the graph instruction 2 and the graph instruction 3 needs to wait for the control flow information, thereby the processing of the graph instruction 2 and the graph instruction 3 needs to wait for the operation result of the graph instruction 1. If the graph instruction 2 or the graph instruction 3 does not receive the conditional signal sent by the graph instruction 1, it will wait forever. In the prior art, the processing result of the graph instruction 1 needs to be sent to the graph instruction 2 and the graph instruction 3, regardless of whether the processing result is greater than or less than. However, the embodiment of the present application only needs to send a conditional signal to the other graph instruction, that is, the two output addresses of the graph instruction 1 correspond to true and false. If the calculation result is true, the conditional signal only needs to be sent to the first output address. If the calculation result is false, the conditional signal only needs to be sent to the second output address, thereby greatly reducing the demand for bus resources.

[0076] Further, in the above S301a, determining that the control flow information of the first graph instruction is in a ready completion state can include: receiving first broadcast information, the first broadcast information being used for indicating a first broadcast channel; and determining that the control flow information of the first graph instruction is in a ready completion state when the broadcast channel registered by the first graph instruction is the first broadcast channel. The first broadcast information can be sent when the second graph instruction is processed to obtain a first processing result. The second graph instruction can be a graph instruction with more output addresses.

[0077] Specifically, when the second graph instruction has more output addresses, the processing result of the second graph instruction can be transmitted to the graph instructions corresponding to the multiple output addresses as a conditional signal in a broadcast manner, that is, simultaneously transmitted to multiple graph instructions. The multiple graph instructions can register corresponding broadcast channels in the compilation process. Subsequently, when the second graph instruction is processed to obtain a processing result, the corresponding broadcast information can be broadcast. The multiple graph instructions registered with the broadcast channel can be assigned with a listening register. When the listening register of a certain graph instruction listens to the broadcast channel registered by the graph instruction, it is determined that the control flow information of the graph instruction is in a ready completion state, that is, the conditional input in the ready field is in a ready state.

[0078] For example, as shown in Figure 7As shown, assuming that the second graph instruction is "1cmp.ge 2p 3p 4p 5p, 6p", that is, the id of the second graph instruction is 1, the second graph instruction is a comparison instruction (cmp.ge), if the processing result of the second graph instruction is greater than or equal to, then a conditional signal is sent to the graph instructions with ids of 2, 3, 4 and 5; if the processing result of the second graph instruction is less than, then a conditional signal is sent to the graph instruction with id of 6. At this time, during the compilation process, the graph instructions with ids of 2, 3, 4, and 5 can be registered in the 0th broadcast channel b0. When the processing result obtained by processing the second graph instruction is greater than, a broadcast information indicating the 0th broadcast channel b0 can be sent. For example, the broadcast information is a channel identifier. In this way, the monitoring registers corresponding to the graph instructions with ids of 2, 3, 4, and 5 (the above-mentioned first graph instruction can be any of the graph instructions with ids of 2, 3, 4, and 5) can monitor the broadcast channel identifier, and when it is determined that the monitored channel identifier is consistent with the channel identifier registered by itself, the conditional input in each ready field is marked as ready (for example, the conditional input p is marked as 1). Compared with the prior art of adding a copy instruction through a tree algorithm to gradually transmit the conditional signal generated by the second graph instruction, the processing speed of the graph instruction can be greatly improved. Among them, the specific process of adding a copy instruction through a tree algorithm to gradually transmit the conditional signal generated by the graph instruction with id 1 in the prior art is as follows:

[0079] 1 cmp.ge 7p, 6p;

[0080] 7 copy 8p 9p;

[0081] 8 copy 2p 3p;

[0082] 9 copy 4p 5p.

[0083] Optionally, when the second graph instruction includes two possible processing results, and each possible processing result corresponds to multiple graph instructions, the multiple graph instructions related to each possible processing result can be registered on one broadcast channel, and different possible processing results can be registered on different broadcast channels. For example, if the second graph instruction is "1cmp.ge 2p 3p4p 5p, 6p 7p 8p 9p", then the graph instructions with ids 2, 3, 4, and 5 can be registered on the first broadcast channel, and the graph instructions with ids 6, 7, 8, and 9 can be registered on the second broadcast channel.

[0084] In an embodiment of the present application, when the control flow information of the first diagram instruction includes a logic operation, the logic operation can be used to generate at least one conditional signal. For example, Figure 8As shown in (a), for the graph instruction "if((i>=j)||(m<n))a=c+d”,该图指令的条件输入(i> =j)||(m<n)包括逻辑运算,则逻辑运算(i> =j) can be converted into a comparison instruction to generate the first condition signal, logical operation (m <n)也可转换为比较指令用于产生第二个条件信号,这两个条件信号都指向“c+d(即图中的add运算)”的p,且在这两个条件信号中至少一个条件信号到达“c+d”的p时,即可执行“c+d”。又比如,如 Figure 8 As shown in (b), for the graph instruction "if((i>=j)&&(m<n))a=c+d”,该图指令的条件输入(i> =j)&&(m<n)包括逻辑运算,则逻辑运算(i> =j) can be converted into a comparison instruction to generate the first condition signal, logical operation (m <n)也可转换为比较指令用于产生第二个条件信号,这两个条件信号可指向&&运算(图中表示为tfand2)的左输入和右输入,该&&运算产生的条件信号指向“c+d(即图中的add运算)”的p,这样当上述第一个条件信号和第二个条件信号均到达时即可执行“c+d”。 Figure 8 Here, l represents the left input, r represents the right input, p represents the conditional input, T represents true, F represents false, and cmp.ge, cmp.It, tfand2, and add represent different operators respectively.

[0085] Furthermore, in a directed graph flow computing architecture, during the compilation process, the direction (or output address) of the conditional signal of the graph instruction included in the subgraph in the directed graph flow computing architecture can be adjusted to provide the freedom of scheduling in the two dimensions of performance tendency and energy efficiency tendency during the processing of the directed graph flow computing architecture. The subgraph here can be an instruction chain composed of multiple graph instructions with dependencies in the directed graph flow computing architecture.

[0086] For example, for the subgraph corresponding to "if(i<=j)A[i]=(a+b)*(c+d)", if low energy consumption is required (the performance is low at this time), the if condition can be executed before executing the subgraph, i.e. Figure 9 As shown in (a), at this time, the result of comparing i and j (i.e., cmp.ge) points to the input of the subgraph. In this way, the subgraph below if will be executed only when the result of cmp.ge is T, so it takes four steps to complete the entire operation. Similarly, for the subgraph corresponding to "if(i<=j)A[i]=(a+b)*(c+d)", if high performance is required (the energy consumption is higher at this time), the conditional execution of if can be placed at the end of the subgraph, as shown in Figure 9As shown in (b) in the example, the result of comparing i and j (i.e., cmp.ge) points to the subgraph output (i.e., the graph instruction corresponding to st). This allows the graph instructions preceding the graph instruction corresponding to st to execute concurrently, independent of cmp.ge. When the result of cmp.ge is T, the graph instruction corresponding to st can be executed in the next tick, completing the entire operation in three ticks. While the first approach offers lower performance, it also consumes less energy. While the second approach offers higher performance, if the result of cmp.ge is F, the previous operation is invalidated, resulting in a waste of bus and computing resources.

[0087] Therefore, in order to ensure the scheduling freedom in terms of performance tendency and energy efficiency tendency during the processing of the directed graph flow computing architecture, the compiler can determine the prediction and direction of the conditional signal of the subgraph, so that the compiler can predict the control branch by controlling the target of the conditional signal. Figure 10 As shown, for "if (i <= j) A[i] = (a + b) * (c + d); else B[i] = (e + f) * (g + h)", if the compiler analyzes and finds that the T branch under the if statement is frequently executed, it can redirect the conditional branch of T after cmp.ge to the output of the subgraph under the if statement. If the F branch under the if statement is not frequently executed, it can redirect the conditional branch of F after cmp.ge to the input of its corresponding subgraph. This improves the processing performance of the directed graph flow computing architecture and reduces the waste of bus and computing resources.

[0088] Furthermore, for a directed graph flow computing architecture, any graph instruction can send a conditional signal to another graph instruction, so that the compiler can use this to manage or maintain the reading and writing order of data in the directed graph flow computing architecture.

[0089] Specifically, because in a directed graph flow computing architecture, the order of memory reads and writes is determined based on the order in which the inputs of the graph instructions are ready, the read and write operations on the memory by read instructions and write instructions will disrupt the preset read and write order in the original program. In an embodiment of the present application, the compiler can associate read instructions and write instructions that may have dependencies through conditional signals to force the memory read and write order in the original program to be reflected. That is, the compiler can determine the graph instruction that emits the conditional signal for a certain graph instruction based on the preset read and write order.

[0090] For example, for an original program such as "A[i+k]=xy=A[i]", if the directed graph flow computing architecture corresponding to the original program is as follows Figure 11As shown, there is no order between the read instruction with id 3 and the write instruction with id 5. However, in the original program, only after the corresponding data is written to the memory by the write instruction with id 5 can the data be read by the read instruction with id 3. Therefore, according to the read and write order in the original program, the write instruction with id 5 can transmit a conditional signal to the read instruction with id 3, that is, after the write instruction with id 5 is processed, a conditional signal is transmitted to the p of the read instruction with id 3, so that the read instruction with id 3 can read the data. This ensures that the processing of the directed graph flow computing architecture follows the read and write order preset in the original program.

[0091] It should be noted that in Figures 9 to 11 In the table, l represents the left input, r represents the right input, p represents the conditional input, T represents true, F represents false, sll, add, mul, st, shli and ld represent different operators respectively.

[0092] The embodiment of the present application can divide the functional modules of the graph instruction processing device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one processing module. The above-mentioned integrated module can be implemented in the form of hardware or in the form of software functional modules. It should be noted that the division of modules in the embodiment of the present application is schematic and is only a logical function division. There may be other division methods in actual implementation.

[0093] In the case of dividing each functional module into corresponding functional modules, Figure 12 A possible structural diagram of a graph instruction processing device involved in the above-mentioned embodiment is shown. The device can be a processor or an electronic device including a processor. The device includes: a status buffer unit 401, an arbitration unit 402, and an operation unit 403. Furthermore, the device can also include: a monitoring register 404 and an output unit 405. In actual applications, the status buffer unit 401, the arbitration unit 402, the operation unit 403, the monitoring register 404, and the output unit 405 can be integrated together to form a processing engine PE.

[0094] Among them, the status buffer unit 401 and the arbitration unit 402 are used to execute S301 in the above method embodiment, as well as the step of determining that the data flow information and / or control flow information of the first image instruction is in a ready state; the operation unit 403 is used to execute the step of processing the first image instruction in the above method embodiment; the monitoring register 404 is used to monitor the first broadcast information or the second broadcast information; the output unit 405 is used to execute the step of sending the first broadcast information or the second broadcast information in the above method embodiment, etc.

[0095] The above describes the graph instruction processing apparatus in the embodiment of the present application from the perspective of the modular functional entity. The following describes the graph instruction processing apparatus in the embodiment of the present application from the perspective of hardware processing.

[0096] Figure 13 The following is a structural schematic diagram of a graph instruction processing apparatus (which can be a processor 10) provided in the embodiment of the present application. The processor 10 can be located in any electronic device, such as a computer, a mobile phone, a tablet, a personal digital assistant, a smart wearable device, a smart vehicle, or a smart home appliance. The processor 10 can be a chip or a chip set or a circuit board carrying a chip or a chip set. The chip or the chip set or the circuit board carrying the chip or the chip set can work under necessary software drivers.

[0097] Specifically, the processor 10 can include at least one processor core 101, and the processor core 101 can include an instruction scheduling unit 1011, a graph computing flow unit 1012 connected to the instruction scheduling unit 1011, and at least one general-purpose operation unit 1013. The instruction scheduling unit 1011 operates in the transmit pipeline stage of the processor core 101 to complete the scheduling and distribution of the to-be-executed instructions. The graph computing flow unit 1012 and the at least one general-purpose operation unit 1013 both operate in the execute pipeline stage (execute stage) as execution units (EUs, which can also be referred to as functional units FU) of the processor 10 to complete various types of computing tasks. Specifically, the processor 10 can directly assign the graph computing task in the to-be-executed instruction to the graph computing flow unit 1012 for execution through the instruction scheduling unit 1011 to achieve the function of accelerating the general-purpose processor through the graph computing mode. The general-purpose computing task in the to-be-executed instruction is scheduled to the at least one general-purpose operation unit 1013 for execution to achieve the general-purpose computing function. Optionally, the processor 10 can call only the graph computing flow unit 1012 to execute a task, or call only the at least one general-purpose operation unit 1013 to execute a task, or call both the graph computing flow unit 1012 and the at least one general-purpose operation unit 1013 to execute a task in parallel according to different computing tasks. It can be understood that the instruction scheduling unit 1011, the graph computing flow unit 1012, and the at least one general-purpose operation unit 1013 can be connected through a bus or other means to directly communicate with each other. Figure 13 The connection relationship shown in the above structural schematic diagram does not limit the connection relationship between them.

[0098] In a possible implementation manner, Figure 14 The following is a structural schematic diagram of another processor provided in the embodiment of the present application. The processor 10 can include a plurality of processor cores 101, Figure 14Take F as an example, where F is an integer greater than 1), such as processor core 101, processor core 102, processor core 103, ..., processor core 10F. The processor cores can be isomorphic or heterogeneous, that is, the structure between the processor cores (102, 103, ..., 10F) and the processor core 101 can be the same or different, and the embodiments of the present application do not specifically limit this. Optionally, the processor core 101 can be used as the main processing core, and the processor cores (102, 103, ..., 10F) can be used as slave processing cores, and the main processing core and the (F-1) slave processing cores can be located in one or more chips (ICs). It can be understood that the main processing core 101 and the (F-1) slave processing cores can be coupled and communicated via a bus or other means, which is not specifically limited here. It should be noted that the pipeline structure may be different depending on the structure of each processor core. Therefore, the pipeline structure referred to in this application refers to the pipeline structure of processor core 101, and does not specifically limit the pipeline structure of other processor cores.

[0099] In one possible implementation, Figure 15 This is a structural diagram of another processor 10 provided in an embodiment of the present application. The processor core 101 may further include an instruction acquisition unit 1015 and an instruction decoding unit 1016, which respectively operate in the instruction fetch pipeline stage and the decoding pipeline stage and complete the corresponding instruction fetch and instruction decoding functions. Figure 15As shown, the at least one general-purpose operation unit 1013 may specifically include one or more of a memory read / write unit (load store unit, LSU) 1013A, a floating point operation unit (floating point unit, FPU) 1013B, a vector operation unit (single instruction multiple data, SIMD) 1013C, and an arithmetic and logic unit (arithmetic and logic unit, ALU) 1013D. The above-mentioned multiple general-purpose operation units (including 1013A, 1013B, 1013C, 1013D) and the graph calculation flow unit 1012 are all connected to the instruction scheduling unit 1011 and run as the execution unit (EU) of the processor core in the execution pipeline stage. The above-mentioned execution units respectively receive different types of instructions scheduled by the instruction scheduling unit 1011, and then perform the type of operation tasks they are good at based on their own different hardware structures. Further optionally, the processor core 101 of the processor 10 also includes a memory unit 1017 outside the core, and the above-mentioned memory read and write unit (LSU) reads and writes data from the memory unit 1017 and runs in the memory access pipeline stage; further optionally, the processor core 101 also includes a result write back unit 1014, which runs in the write back pipeline stage and is responsible for writing the calculation result of the instruction back to the destination register. Optionally, the memory unit 1017 is usually a power-off volatile memory, and the content stored therein will be lost when the power is off. It can also be called memory (memory) or main memory. The memory unit 1017 can be used as a storage medium for temporary data of the operating system or other running programs in the processor 10. For example, the operating system running on the processor 10 transfers the data to be calculated from the memory unit 1017 to the processor core 101 for calculation, and when the calculation is completed, the processor core 101 transmits the result. The memory unit 1017 may include one or more of dynamic random access memory (DRAM), static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), first level cache (L1cache), second level cache (L2cache), third level cache (L3cache), etc.

[0100] Based on the architecture of the above-mentioned processor provided in this application, an embodiment of this application also provides a pipeline structure suitable for the above-mentioned processor architecture. The life cycle of an instruction in this pipeline structure may include instruction fetch pipeline → decoding pipeline → scheduling (issuance) pipeline → execution pipeline → memory access pipeline → write-back pipeline, that is, the pipeline structure divides the execution process of an instruction into at least the following six stages.

[0101] Instruction fetch pipeline: Instruction fetch refers to the process of reading instructions from memory.

[0102] Decoding pipeline: Instruction decoding refers to the process of translating instructions taken out of the memory.

[0103] Scheduling (Issuance) Pipeline: Instruction dispatch and issue reads registers to obtain operands, and sends instructions to the corresponding execution unit (EU) for execution based on the instruction type.

[0104] Execution Pipeline: After instruction decoding, the required computation type is known, and the required operands have been read from the general registers. Next, instruction execution is performed based on the instruction type to complete the computation. Instruction execution refers to the actual operation performed on the instruction. For example, if the instruction is an addition, the operands are added; if it is a subtraction instruction, the operands are subtracted; if it is a graph operation, the graph operation is performed.

[0105] Memory access pipeline: Memory access refers to the process of reading data from the memory or writing data into the memory by memory access instructions, mainly executing read / write (load / store) instructions.

[0106] Write-back pipeline: Write-back refers to the process of writing the results of instruction execution back to the general register bank. For ordinary arithmetic instructions, this result value comes from the result calculated in the "execute" phase; for memory read instructions, this result comes from the data read from memory in the "access" phase.

[0107] In the above-mentioned pipeline structure, each instruction in the processor must go through the above-mentioned operation steps, but different operation steps of multiple instructions can be executed simultaneously, thereby speeding up the instruction flow speed as a whole and shortening the program execution time. It is understood that the above-mentioned processor architecture and processor pipeline structure are only some exemplary implementation methods provided in the embodiments of this application. The processor architecture and processor pipeline structure in the embodiments of this application include but are not limited to the above implementation methods.

[0108] It should be noted that Figure 15 The various functional modules within the processor can communicate through buses or other connection methods. Figure 15 The connection relationship shown in the figure does not limit the connection relationship between them. Each functional module will be further described in the subsequent embodiments and will not be described in detail here.

[0109] It is understandable that Figures 13 to 15 The structure of the processor is only some exemplary embodiments provided by the embodiments of the present application, and the structure of the processor in the embodiments of the present application includes but is not limited to the above implementation.

[0110] Based on the above Figures 13 to 15 The micro-architecture of the processor provided by the embodiments of the present application can include the following functions:

[0111] The instruction acquisition unit 1015 acquires a target program to be executed from the memory unit 1017; the instruction decoding unit 1016 decodes the target program according to a predetermined instruction format to obtain the decoded to-be-executed instruction. The instruction scheduling unit 1011 receives the decoded to-be-executed instruction, the to-be-executed instruction includes a general computing instruction and a graph computing control instruction, the general computing instruction is used to instruct to execute a general computing task, and the graph computing control instruction is used to instruct to execute a graph computing task; the general computing instruction is sent to the at least one general operation unit, and the graph computing control instruction is sent to the graph computing flow unit; the at least one general operation unit 1013 receives and executes the general computing instruction to obtain an execution result of the general computing task; the graph computing flow unit 1012 receives and executes the graph computing control instruction to obtain an execution result of the graph computing task. The at least one general operation unit 1013 also sends the first execution result of the general computing task to the result write-back unit 1014; the graph computing flow unit 1012 also sends the second execution result of the graph computing task to the result write-back unit 1014; and the result write-back unit 1014 stores the first execution result and the second execution result, and writes part or all of the first execution result and the second execution result back to the instruction scheduling unit 1011.

[0112] First, the target program involved in the present application is described from the compilation to the execution process in combination with the structure and function of the processor 10. Figure 16 A flowchart of source code comprehensive compilation and execution provided by the embodiments of the present application is provided.

[0113] 1. Provide program source code written by a high-level language, for example, source code written by a developer in various programming languages (such as C language, JAVA, etc.).

[0114] 2. Based on the cost estimation model, determine which parts of the source code are suitable for general operation mode compilation and which parts are suitable for graph computation flow mode compilation, and then compile them into general operation object files or graph computation flow object files (both are binary) according to different compilation modes. For example, an application (APP) may have millions of instructions, and multiple instructions actually have input and output relationships. For example, if the input condition for the execution of one instruction is the output result of another instruction, then the two instructions can constitute the basic elements of graph computation (vertices and edges). Therefore, during the source program compilation stage, based on the cost estimation model, complex instruction sequences (such as instruction sequences with complex relationships, indirect jumps or interrupts) or instruction sequences that are only used once can be compiled using the general operation mode; while instruction sequences suitable for repeated repetition, such as loops or repeatedly called functions (their relationships can be complex or simple, but they usually need to be executed repeatedly), are compiled using the graph computation flow mode. Graph flow compilation abstracts the logic involved in code into a graph architecture. This transforms processor-generated operations, such as checks, jumps, and predictions, into binary machine instructions for the graph architecture during program compilation (i.e., through the graph flow compiler). Because these graph instructions contain the relationships between their inputs and outputs, the GFU in the processor significantly reduces the amount of logical reasoning required to execute instructions during actual computations, significantly reducing CPU core overhead and delivering high performance and low power consumption.

[0115] 3. The compiled general operation object files and graph calculation flow object files are linked (linked) into a comprehensive program (executable file) through a linker. For example, the object file is a .o file, etc., and when the program is to be executed, it needs to be linked. In the linking process, the above object files (such as .o files) are mainly linked with the library to create an executable file. It is understandable that the compilation stages corresponding to the above 1, 2, and 3 can be completed on a device other than the device where the processor 10 is located (such as a server, compiler, etc.), can be pre-compiled on the device where the processor 10 is located, or can be executed or compiled on the device where the processor 10 is located, and no specific limitation is made here.

[0116] 4. After the above executable file is executed on the processor 10, the processor 10 will load the target program to be executed in the executable file (such as code segment, data segment, BSS segment or stack, etc.) into the memory unit 1017 through a series of instruction loading, instruction prefetching, instruction predecoding and division prediction operations.

[0117] 5、The instruction fetch unit 1015 can fetch the target program from the memory unit 1017 in a plurality of times and one instruction each time, and then each instruction enters the instruction decode unit 1016 from the instruction fetch unit 1015 for decoding.

[0118] 6、The instruction decode unit 1016 splits and interprets the to-be-executed instruction according to a predetermined instruction format, further obtains a micro-operation instruction, that is, a to-be-executed instruction after decoding in the present application, and sends the to-be-executed instruction to the instruction scheduling unit 1011.

[0119] 7、After receiving the decoded to-be-executed instruction, the instruction scheduling unit 1011 distributes the to-be-executed instruction to each execution unit according to the type of each instruction for calculation, for example, to the general operation unit 1013 or the graph computing flow unit 1012 for operation. Since the graph computing flow unit 1012 is arranged in the processor core 101 of the processor 10, the instruction scheduling unit 1011 can be directly connected to and communicate with the graph computing flow unit 1012, so as to directly schedule the identified graph computing control instruction to the graph computing flow unit 1012 without the need of communication through other message channels or memory reading and writing, thereby greatly reducing the communication delay. In a possible implementation manner, the general computing instruction and the graph computing control instruction in the present application can be identified through different identification bits (the identification bits can be added in the above-mentioned compiling stage), that is, different types of instructions can correspond to different instruction IDs, so that the instruction scheduling unit 1011 can identify according to the instruction ID.

[0120] 8、The graph computing flow unit 1012 receives and executes the graph computing control instruction to obtain the execution result of the graph computing task; and one or more general operation units 1013 receive and execute the general computing instruction to obtain the execution result of the general computing task. Optionally, the graph computing flow unit 1012 and the general operation unit 1013 can execute instructions in parallel or in series, which depends on the logical relationship between the instructions executed between the execution units in the target program, and the present application embodiment does not make a specific limitation.

[0121] 9、Finally, the graph computation flow unit 1012 and the general operation unit 1013 can send the computation results to the result write-back unit 1014, and the result write-back unit 1014 can feed back part or all of the computation results to the instruction scheduling unit 1011, for example, as parameters in the instructions scheduled by the instruction scheduling unit 1011. Alternatively, the first execution result or the second execution result can be directly written into the memory unit 1017 or written into the memory unit 1017 through the memory read-write unit 1013A, so that the relevant execution unit (such as the graph computation flow unit 1012 or the memory read-write unit 1013A) can obtain the required parameters from the corresponding storage location. Since the graph computation flow unit 1012 is arranged in the processor core 101 of the processor 10, the processor core 101 has the right and condition to obtain the relevant computation states (such as the first execution result and the second execution result) of the graph computation flow unit 1012 and other general computation units 1013, and thus can control the synchronous or asynchronous running between the graph computation flow unit 1012 and other computation units, thereby improving the running efficiency of the processor.

[0122] In summary, the graph computation flow unit 1012, like other general computation units, receives the live-in data on the registers sent from the instruction scheduling unit 1011 (such as including instruction launch and reservation stations), and transmits the input to the corresponding computation nodes of the graph computation flow unit 1012. Similarly, the graph computation flow unit 1012 also writes the live-out output data back to the result write-back unit 1014 (such as including registers and reorder buffers), so as to write the output of the graph into the corresponding registers and instruction reservation stations depending on the graph output.

[0123] Next, the computation model of the graph computation flow unit involved in the above execution phase when performing graph computation is further described. The theoretical computation model of the graph flow in the present application can be abstracted into N fully connected computation nodes (corresponding to the vertices of the graph). An instruction can be placed in each node to perform an operation, and the result can be transmitted to itself or other nodes. The theoretical computation model of the graph flow can be divided into two stages of repeated switching:

[0124] 1. Graph Build: N instructions are read from the instruction memory. Each node in the graph is configured with an operation instruction and up to two target nodes. Assuming N is 16, 1-b has 16 compute nodes, from 0 to 15. Once the graph is built, the operations and connections of each node are solidified (read-only). For example, the operation instruction in compute node 0 is the add instruction, which performs an addition operation; the operation instruction in compute node 2 is the sll instruction, which performs a shift operation; and the operation instruction in compute node 3 is the xor instruction, which performs an exclusive-or operation. For compute node 5, the ld operation (instruction fetch) is performed by using the operation results of compute node 1 and compute node 1 as the input of the compute node; for compute node 6, the add operation (addition operation) is performed by using the operation results of compute node 2 and compute node 3 as the input of the compute node, and so on. The operation process of other compute nodes will not be described one by one.

[0125] 2. Execution phase (graph execute): The external module passes in input (liveIn) to start the data flow. All computing nodes run in parallel. For each node, as long as its input arrives, it can perform calculations and pass the results to the next computing node; if the input does not arrive, it is in the waiting Idle state. The operation continues until the data flow reaches the end node (tm). Because the input parameters of some computing nodes (such as computing nodes 0, 1, 2, and 3) are input externally, that is, the startup data needs to be input from the external memory unit 1017; and the other computing nodes (such as computing nodes 5, 6, 8, 9, 10, 11, 12, 13, 14, and 15) need to obtain the calculation results output by the computing nodes with which they are connected from the inside, then they can perform calculations and input the results of the calculations to the computing nodes associated with them.

[0126] It should be noted that the above Figures 13 to 15 The processor provided in any of the diagrams can be used to execute the graph instruction processing method provided in the above method embodiment. Since each step has been described in detail in the above graph instruction processing method embodiment, it will not be repeated here.

[0127] The present application also provides a computer-readable storage medium storing instructions that, when executed on a device (e.g., a single-chip microcomputer, a chip, a computer, etc.), cause the device to perform one or more steps of the above-described method embodiments. If the various components of the above-described instruction processing device are implemented as software functional units and sold or used as independent products, they may be stored in the computer-readable storage medium.

[0128] Based on this understanding, the embodiments of the present application also provide a computer program product containing instructions. The technical solution of the present application, or the part that contributes to the prior art, or all or part of the technical solution can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes a number of instructions for enabling a computer device (which can be a personal computer, a server, or a network device, etc.) or the processor therein to execute all or part of the steps of the method described in each embodiment of the present application.

[0129] Finally, it should be noted that the above description is merely a specific embodiment of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A method for processing a graph instruction, characterized in that: The method comprises: detecting whether a conditional instruction element exists in a first graph instruction, where the first graph instruction is a graph instruction in a directed graph flow computing architecture; When the conditional instruction element exists in the first graph instruction, determining that the first graph instruction is a conditional execution instruction, and processing the first graph instruction when both data flow information and control flow information of the first graph instruction are in a prepared state; When the conditional instruction element does not exist in the first graph instruction, the first graph instruction is determined to be a non-conditional execution instruction, and when the data flow information of the first graph instruction is in a prepared state, the first graph instruction is processed.

2. The method according to claim 1, characterized in that The conditional instruction element is 1 bit, and / or the control flow information is 1 bit.

3. The method according to claim 1, characterized in that The conditional instruction element and the control flow information are transmitted via a control bus, and the data flow information is transmitted via a data bus.

4. The method according to claim 1, wherein The method further comprises: receiving first broadcast information, where the first broadcast information is used to indicate a first broadcast channel; When the broadcast channel registered by the first graph instruction is the first broadcast channel, it is determined that the control flow information of the first graph instruction is in a preparation completion state.

5. The method according to claim 4, characterized in that At least one graph instruction is registered with the first broadcast channel, the at least one graph instruction is related to a first processing result of the second graph instruction, the at least one graph instruction includes the first graph instruction, and the method further includes: When the processing result of the second image instruction is the first processing result, the first broadcast information is sent.

6. The method according to claim 5, characterized in that The method further comprises: When the processing result of the second graph instruction is the second processing result, second broadcast information is sent, where the second broadcast information is used to indicate a second broadcast channel, and the broadcast channel registered for at least one graph instruction related to the second processing result is the second broadcast channel.

7. The method according to claim 5, characterized in that The method further comprises: During the process of compiling the first graph instruction, the first graph instruction is registered in the first broadcast channel.

8. The method according to claim 1, characterized in that When the control flow information of the first diagram instruction includes a logic operation, the logic operation is used to generate at least one condition signal.

9. The method according to any one of claims 1 to 8, characterized in that When the first image instruction is a read instruction or a write instruction, the method further includes: According to a preset reading and writing order, a graph instruction for emitting the control flow information of the first graph instruction is determined.

10. A graph instruction processing device, characterized in that: The device comprises: a status buffer unit, an arbitration unit and an operation unit; The state buffer unit is configured to detect whether a conditional instruction element exists in a first graph instruction, where the first graph instruction is a graph instruction in a directed graph flow computing architecture; The state buffer unit and the arbitration unit are further configured to determine that the first graph instruction is a conditional execution instruction when the conditional instruction element exists in the first graph instruction, and the operation unit is configured to process the first graph instruction when both the data flow information and the control flow information of the first graph instruction are in a prepared state; The status buffer unit and the arbitration unit are further used to determine that the first graph instruction is a non-conditional execution instruction when the conditional instruction element does not exist in the first graph instruction, and the operation unit is further used to process the first graph instruction when the data flow information of the first graph instruction is in a ready state.

11. The device according to claim 10, characterized in that The conditional instruction element is 1 bit, and / or the control flow information is 1 bit.

12. The device according to claim 10, characterized in that The device further includes a control bus and a data bus, the conditional instruction element and the control flow information are transmitted via the control bus, and the data flow information is transmitted via the data bus.

13. The device according to claim 10, characterized in that The apparatus further comprises: a monitoring register; The monitoring register is used to receive first broadcast information, where the first broadcast information is used to indicate a first broadcast channel; The status buffer unit is further configured to mark the control flow information of the first graph instruction as being in a ready state when the broadcast channel registered by the first graph instruction is the first broadcast channel.

14. The device according to claim 13, characterized in that At least one graph instruction is registered with the first broadcast channel, the at least one graph instruction is related to a first processing result of the second graph instruction, the at least one graph instruction includes the first graph instruction, and the apparatus further includes: An output unit is configured to send the first broadcast information when the processing result of the second image instruction is the first processing result.

15. The device according to claim 14, characterized in that The output unit is further configured to: When the processing result of the second graph instruction is the second processing result, second broadcast information is sent, where the second broadcast information is used to indicate a second broadcast channel, and the broadcast channel registered for at least one graph instruction related to the second processing result is the second broadcast channel.

16. The device according to claim 14, characterized in that The device further comprises: The compiler is configured to register the first graph instruction in the first broadcast channel during a process of compiling the first graph instruction.

17. The device according to claim 10, characterized in that When the control flow information of the first diagram instruction includes a logic operation, the logic operation is used to generate at least one condition signal.

18. The device according to any one of claims 10 to 17, characterized in that When the first image instruction is a read instruction or a write instruction, the apparatus further includes: The compiler is configured to determine, according to a preset reading and writing order, a graph instruction for emitting the control flow information of the first graph instruction.

19. A graphics instruction processing device, characterized in that: The graph instruction processing device includes a processor and a memory, wherein instructions are stored in the memory. When the processor runs the instructions in the memory, the graph instruction processing device executes the graph instruction processing method according to any one of claims 1 to 9.

20. A readable storage medium, characterized in that The readable storage medium stores instructions, and when the readable storage medium is run on a device, the device executes the graph instruction processing method according to any one of claims 1 to 9.

21. A computer program product, characterized in that When the computer program product is run on a computer, the computer is enabled to execute the graph instruction processing method according to any one of claims 1 to 9.

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