Touch panel and manufacturing method thereof, and display device

Abstract

A touch panel and a manufacturing method thereof, and a display device. The touch panel includes a touch area and a binding area located on one side of the touch area in a first direction; the touch area includes: a chip area including a first side, a second side, a third side, and a fourth side, the first side and the second side extending along a second direction, and the first direction and the second direction intersecting; a plurality of pins located in the chip area, the plurality of pins including a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines; a plurality of touch electrodes located in the touch area; a plurality of touch signal lines located in the touch area and the binding area, the plurality of touch signal lines being correspondingly connected to the plurality of touch electrodes and the plurality of touch pins.

Description

Technical Field

[0001] The present disclosure relates to but is not limited to the field of display technology, and in particular to a touch panel and a manufacturing method thereof, and a display device. Background Art

[0002] With the rapid development of display technology, touch screens have gradually become common in people's lives. According to the composition structure, touch screens can be divided into add-on mode, on-cell, and in-cell types. According to the working principle, touch screens can be divided into capacitive, resistive, infrared, and surface acoustic wave types. The capacitive on-cell type forms a touch structure on the light-emitting side of the display screen. Due to its simple structure, thin thickness, and high transmittance, it has gradually replaced the add-on type and become the mainstream technology. Summary of the invention

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] In one aspect, an exemplary embodiment of the present disclosure provides a touch panel, comprising a touch area and a binding area located on one side of a first direction of the touch area, wherein the binding area comprises:

[0005] a chip area, the chip area comprising a first side, a second side, a third side and a fourth side, the first side and the second side extending along a second direction, the second side being located at a side of the first side away from the touch control area, the third side and the fourth side extending along the first direction, and the first direction intersecting the second direction;

[0006] a plurality of pins, located in the chip area, the plurality of pins comprising a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines;

[0007] A plurality of touch electrodes, located in the touch area;

[0008] A plurality of touch signal lines are located in the touch area and the binding area, and the plurality of touch signal lines are correspondingly connected to the plurality of touch electrodes and the plurality of touch pins.

[0009] In an exemplary embodiment, the chip area includes a first pin area, a second pin area, a third pin area, a fourth pin area, a fifth pin area and a sixth pin area; the first pin area is arranged along a first side of the chip area, the second pin area is arranged along a second side of the chip area, the third pin area and the fifth pin area are arranged in sequence along a third side of the chip area, and the fourth pin area and the sixth pin area are arranged in sequence along a fourth side of the chip area.

[0010] In an exemplary embodiment, the plurality of display pins include a plurality of display signal output pins and a plurality of display signal input pins, the plurality of display signal output pins are arranged in the first pin area, and the plurality of display signal input pins are arranged in the second pin area; the plurality of display signal output pins are configured to be connected to data signal lines, and the display signal input pins are configured to be connected to an external circuit board through display connection lines and a binding pin area of ​​the binding area, so that the external circuit board provides a display signal through the binding pin area, the display connection lines and the display signal input pins.

[0011] In an exemplary embodiment, the plurality of touch pins include a plurality of touch signal output pins and a plurality of touch signal input pins, the plurality of touch signal output pins are arranged in the third pin area and the fourth pin area, and the plurality of touch signal input pins are arranged in the fifth pin area and the sixth pin area; the touch signal output pins are configured to be connected to touch signal lines, and the touch signal input pins are configured to be connected to touch input lines, and touch signals are output to the touch signal output pins through the touch input lines and the touch signal input pins.

[0012] In an exemplary embodiment, the chip area has a center line, and the plurality of touch pins and the plurality of touch signal lines in the chip area are symmetrically arranged relative to the center line, and the center line is a straight line extending along the first direction and equally dividing the chip area;

[0013] The plurality of touch signal lines include a first touch signal line group and a second touch signal line group symmetrically arranged relative to the center line, the first touch signal line group includes a first output line group and a second output line group, the first output line group includes a plurality of first touch signal lines, the second output line group includes a plurality of second touch signal lines, the first output line group is arranged on a side of the second output line group away from the center line, and the plurality of first touch signal lines and the plurality of second touch signal lines are correspondingly connected to a plurality of touch signal output pins in the third pin area;

[0014] The second touch signal line group includes a third output line group and a fourth output line group, the third output line group includes multiple third touch signal lines, the fourth output line group includes multiple fourth touch signal lines, the third output line group is arranged on a side of the fourth output line group away from the center line, and the multiple third touch signal lines and the multiple fourth touch signal lines are correspondingly connected to multiple touch signal output pins in the fourth pin area.

[0015] In an exemplary embodiment, the first touch signal line includes a first output line segment, a second output line segment, a third output line segment and a fourth output line segment connected in sequence, the first output line segment extends along the first direction, the second output line segment and the fourth output line segment extend along the second direction, the third output line segment has a first angle with the second direction, and the first angle is 20° to 80°.

[0016] In an exemplary embodiment, the second touch signal line includes a first output line segment, a second output line segment, a third output line segment and a fourth output line segment connected in sequence, the second output line segment and the fourth output line segment extend along the second direction, the third output line segment has a second angle with the second direction, and the second angle is 20° to 80°.

[0017] In an exemplary embodiment, the plurality of first output line segments include a first output line segment group and a second output line segment group, the first output line segment group includes a plurality of first fold lines bent toward a direction close to the center line, the second output line segment group includes a plurality of second fold lines bent toward a direction away from the center line, the plurality of first fold lines and the plurality of second fold lines enclose at least one polygonal area, and at least one virtual pin is arranged in the polygonal area.

[0018] In an exemplary embodiment, the chip area also includes at least one virtual pin, and the virtual pin is arranged at any one or more of the following positions: between the first output line group and the second output line group, between the third output line group and the fourth output line group, on a side of the second output line group away from the first output line group, on a side of the fourth output line group away from the third output line group, and on the center line.

[0019] In an exemplary embodiment, the chip area further includes at least one first connection line, the first connection line is configured to connect a portion of the touch signal input pins, and the first connection line is disposed on a side of the touch signal input pins close to the center line.

[0020] In an exemplary embodiment, the chip area further includes at least one second connection line, the second connection line is configured to connect a portion of the display signal input pins, and the second connection line is disposed on a side of the display signal input pins close to the touch control area.

[0021] In an exemplary embodiment, the plurality of pins in at least one of the first pin area, the second pin area, the third pin area, the fourth pin area, the fifth pin area, and the sixth pin area are arranged in a multi-row staggered structure.

[0022] In an exemplary embodiment, the pins in the first pin area and / or the second pin area are aligned in a single row horizontally, and a plurality of pins are arranged in sequence along the second direction and aligned in the first direction; or, the pins in the first pin area and / or the second pin area are arranged in a two-row horizontal staggered arrangement structure, and the two-row horizontal staggered arrangement structure includes a first pin row and a second pin row arranged along the first direction, and a plurality of pins in the first pin row and the second pin row are arranged in sequence along the second direction, and a plurality of pins in the first pin row and a plurality of pins in the second pin row are staggered in the second direction.

[0023] In an exemplary embodiment, at least one of the third pin area, the fourth pin area, the fifth pin area and the sixth pin area adopts a single-row longitudinal alignment, and a plurality of pins are arranged in sequence along the first direction and aligned in the second direction; or, at least one of the third pin area, the fourth pin area, the fifth pin area and the sixth pin area adopts a two-row longitudinal staggered arrangement structure, and the two-row longitudinal staggered arrangement structure includes a first pin column and a second pin column arranged along the second direction, and a plurality of pins in the first pin column and the second pin column are arranged in sequence along the first direction, and a plurality of pins in the first pin column and a plurality of pins in the second pin column are staggered in the first direction.

[0024] In an exemplary embodiment, the third pin area and the fourth pin area include a plurality of touch signal output pins and at least one idle pin, and the touch signal line is connected to the touch signal output pins but not to the idle pin.

[0025] In an exemplary embodiment, the third pin area and the fourth pin area further include at least one first ground pin and at least one second ground pin, the first ground pin is connected to the first ground wire, and the second ground pin is connected to the second ground wire; the idle pin is arranged between the first ground pin and the touch signal output pin, and / or the idle pin is arranged between the touch signal output pins.

[0026] In an exemplary embodiment, the fifth pin area and the sixth pin area further include a plurality of touch signal input pins and at least one idle pin, and the touch input line is connected to the touch signal input pins but not to the idle pin.

[0027] In an exemplary embodiment, the idle pin is disposed between the touch signal output pin and the touch signal input pin.

[0028] On the other hand, an exemplary embodiment of the present disclosure further provides a display device including the aforementioned touch panel.

[0029] In another aspect, the exemplary embodiments of the present disclosure further provide a method for preparing a touch panel, comprising:

[0030] A touch area and a binding area located on one side of the touch area in a first direction are formed, wherein the touch area includes:

[0031] a chip area, the chip area comprising a first side, a second side, a third side and a fourth side, the first side and the second side extending along a second direction, the second side being located at a side of the first side away from the touch control area, the third side and the fourth side extending along the first direction, and the first direction intersecting the second direction;

[0032] a plurality of pins, located in the chip area, the plurality of pins comprising a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines;

[0033] A plurality of touch electrodes, located in the touch area;

[0034] A plurality of touch signal lines are located in the touch area and the binding area, and the plurality of touch signal lines are correspondingly connected to the plurality of touch electrodes and the plurality of touch pins.

[0035] Other aspects will become apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The accompanying drawings are used to provide a further understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure. The shapes and sizes of the components in the accompanying drawings do not reflect the actual proportions and are only intended to illustrate the contents of the present disclosure.

[0037] Figure 1 is a structural schematic diagram of an OLED display device;

[0038] Figure 2 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0039] Figure 3 is a working timing diagram of a pixel driving circuit;

[0040] Figure 4 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0041] Figure 5 A schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure;

[0042] Figure 6 A schematic diagram of the structure of a touch panel according to an exemplary embodiment of the present disclosure;

[0043] Figure 7 A schematic diagram of a touch electrode arrangement according to an exemplary embodiment of the present disclosure;

[0044] Figure 8-1 to Figure 8-5 The schematic diagrams of the structures of several metal grids are shown below;

[0045] Fig. 9 A schematic diagram of the structure of a metal grid touch electrode;

[0046] Fig.10 A schematic diagram of touch wiring in a touch panel;

[0047] Fig.11 A schematic diagram of a signal lead in a touch panel according to an exemplary embodiment of the present disclosure;

[0048] Fig.12 is a schematic diagram of a first group of leads according to an exemplary embodiment of the present disclosure;

[0049] Fig.13 is a schematic diagram of a second group of leads according to an exemplary embodiment of the present disclosure;

[0050] Fig.14 is a schematic diagram of a third group of leads according to an exemplary embodiment of the present disclosure;

[0051] Fig.15 is a schematic diagram of a fourth group of leads according to an exemplary embodiment of the present disclosure;

[0052] Fig.16 A schematic diagram of a lead collection area in a border region of an exemplary embodiment of the present disclosure;

[0053] Fig.17 A schematic diagram of a binding area of ​​an exemplary embodiment of the present disclosure;

[0054] Fig.18A schematic diagram of a chip area pin arrangement according to an exemplary embodiment of the present disclosure;

[0055] Fig.19 A schematic diagram of a chip area wiring arrangement according to an exemplary embodiment of the present disclosure;

[0056] Fig. 20 for Fig.19 Schematic diagram on the left side of the middle chip area;

[0057] Fig.21 for Fig. 20 Enlarged view of the middle C1 region;

[0058] Fig. 22 for Fig. 20 Enlarged view of the middle C2 region;

[0059] Fig.23 A schematic diagram of two rows of pins of an exemplary embodiment of the present disclosure;

[0060] Fig.24 FIG. 1 is a schematic diagram of another chip area pin arrangement according to an exemplary embodiment of the present disclosure.

[0061] Description of reference numerals:

[0062] 10-substrate; 11A-transistor; 11B-storage capacitor;

[0063] 12-driving circuit layer; 13-light emitting structure layer; 14-packaging layer;

[0064] 15-touch electrode layer; 31-anode; 32-pixel definition layer;

[0065] 33-organic light emitting layer; 34-cathode; 41-first encapsulation layer;

[0066] 42-second packaging layer; 43-third packaging layer; 100-touch area;

[0067] 101-first electrode region; 102-second electrode region; 103-third electrode region;

[0068] 104- fourth electrode area; 105- fifth electrode area; 200- frame area;

[0069] 210-signal lead; 220-ground wire; 230-virtual line segment;

[0070] 300-binding area; 310-bending area; 320-routing area;

[0071] 330-chip area; 340-binding pin area; 400-touch electrode;

[0072] 410-touch line; 500-cutout; 610-data signal line;

[0073] 620-touch signal line; 630-first power line; 640-second power line;

[0074] 710 - first pin area; 720 - second pin area; 730 - third pin area;

[0075] 740- fourth pin area; 750- fifth pin area; 760- sixth pin area;

[0076] 810-first pin; 810-1-data pin; 810-2-control pin;

[0077] 820- second pin; 830- third pin; 840- fourth pin;

[0078] 900 - virtual pin; 910 - first touch signal line; 920 - second touch signal line;

[0079] 930 - third touch signal line; 940 - fourth touch signal line; 950 - first connection line;

[0080] 960-Second connecting line. DETAILED DESCRIPTION

[0081] The embodiments of the present disclosure will be described in detail below in conjunction with the accompanying drawings. Note that the embodiments can be implemented in a number of different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other. In order to keep the following description of the embodiments of the present disclosure clear and concise, the present disclosure omits detailed descriptions of some known functions and known components. The drawings of the embodiments of the present disclosure only involve structures related to the embodiments of the present disclosure, and other structures can refer to the general design.

[0082] In the drawings, the size of each component, the thickness of a layer, or the area is sometimes exaggerated for the sake of clarity. Therefore, one embodiment of the present disclosure is not necessarily limited to this size, and the shape and size of each component in the drawings do not reflect the true proportion. In addition, the drawings schematically show ideal examples, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0083] In the present specification, ordinal numbers such as “first”, “second”, “third”, 1st, 2nd, 3rd, etc. are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0084] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0085] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the meanings of the above terms in this disclosure can be understood according to the circumstances.

[0086] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0087] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the direction of current changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged.

[0088] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0089] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0090] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0091] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0092] Capacitive On Cell touch panels are mainly divided into mutual capacitance and self capacitance. The mutual capacitance structure is composed of the overlapping driving electrodes and sensing electrodes to form mutual capacitance, and the change of mutual capacitance is used for position detection. The self capacitance structure is composed of the touch electrodes and the human body to form self capacitance, and the change of self capacitance is used for position detection. The self capacitance touch panel is a single-layer structure with the characteristics of low power consumption and simple structure, while the mutual capacitance touch panel is a multi-layer structure with the characteristics of multi-touch.

[0093] The display device of the exemplary embodiment of the present disclosure may include a display substrate or a display backplane arranged on a substrate and a touch panel arranged on the display substrate. The display substrate or the display backplane may be a liquid crystal display (LCD) substrate, or may be an organic light emitting diode (OLED) display substrate, or may be a plasma display device (PDP) display substrate, or may be an electrophoretic display (EPD) display substrate. In an exemplary embodiment, the display substrate is an organic light emitting diode (OLED) display substrate, which is an active light emitting display device having the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, and extremely high response speed. With the continuous development of display technology, a flexible display device (Flexible Display) using OLED as a light emitting device and signal controlled by a thin film transistor (TFT) has become a mainstream product in the current display field.

[0094] The OLED display substrate may include a substrate, a driving circuit layer disposed on the substrate, a light emitting structure layer disposed on the driving circuit layer, and an encapsulation layer disposed on the light emitting structure layer. The touch panel is disposed on the encapsulation layer of the display substrate to form a touch structure on thin film encapsulation (Touch on Thin Film Encapsulation, referred to as Touch on TFE). The display structure and the touch structure are integrated together, which has the advantages of being light, thin, and foldable, and can meet product requirements such as flexible folding and narrow bezels.

[0095] At present, the Touch on TFE structure mainly includes the Flexible Multi Layer On Cell (FMLOC) structure and the Flexible Single Layer On Cell (FSLOC) structure. The FMLOC structure is based on the working principle of mutual capacitance detection. Generally, two layers of metal are used to form the driving (Tx) electrode and the sensing (Rx) electrode. The integrated circuit (IC) realizes the touch action by detecting the mutual capacitance between the driving electrode and the sensing electrode. The FSLOC structure is based on the working principle of self-capacitance (or voltage) detection. Generally, a single layer of metal is used to form the touch electrode. The integrated circuit realizes the touch action by detecting the self-capacitance (or voltage) of the touch electrode.

[0096] Figure 1 Schematic diagram of the structure of an OLED display device. Figure 1As shown, the OLED display device may include a timing controller, a data signal driver, a scan signal driver, a light emitting signal driver, and a pixel array, and the pixel array may include a plurality of scan signal lines (S1 to Sm), a plurality of data signal lines (D1 to Dn), a plurality of light emitting signal lines (E1 to Eo), and a plurality of sub-pixels Pxij. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data signal driver to the data signal driver, a clock signal suitable for the specification of the scan signal driver, a scan start signal, etc. to the scan signal driver, and a clock signal suitable for the specification of the light emitting signal driver, an emission stop signal, etc. to the light emitting signal driver. The data signal driver may generate a data voltage to be provided to the data signal lines D1, D2, D3, ... and Dn using the grayscale value and the control signal received from the timing controller. For example, the data signal driver may sample the grayscale value using the clock signal, and apply the data voltage corresponding to the grayscale value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan signal driver may generate a scan signal to be provided to the scan signal lines S1, S2, S3, ... and Sm by receiving a clock signal, a scan start signal, etc. from a timing controller. For example, the scan signal driver may sequentially provide a scan signal having an on-level pulse to the scan signal lines S1 to Sm. For example, the scan signal driver may be constructed in the form of a shift register, and may generate a scan signal in a manner that sequentially transmits a scan start signal provided in the form of an on-level pulse to a next-level circuit under the control of a clock signal, and m may be a natural number. The luminous signal driver may generate an emission signal to be provided to the luminous signal lines E1, E2, E3, ... and Eo by receiving a clock signal, an emission stop signal, etc. from a timing controller. For example, the luminous signal driver may sequentially provide an emission signal having an off-level pulse to the luminous signal lines E1 to Eo. For example, the luminous signal driver may be constructed in the form of a shift register, and may sequentially transmit a luminous stop signal provided in the form of an off-level pulse to a next-level circuit under the control of a clock signal, and o may be a natural number. The pixel array may include a plurality of sub-pixels Pxij, at least one sub-pixel Pxij may include a pixel driving circuit and a light-emitting device, the pixel driving circuit may be connected to a corresponding data signal line, a corresponding scanning signal line and a corresponding light-emitting signal line, the pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting device, the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel, i and j may be natural numbers. The sub-pixel Pxij may refer to a sub-pixel in which the pixel driving circuit is connected to the i-th scanning signal line and to the j-th data signal line.

[0097] In exemplary embodiments, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, or 7T1C structure. Figure 2 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 2 As shown, the pixel driving circuit may include 7 transistors (first transistor T1 to seventh transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS).

[0098] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power line VDD, and a second end of the storage capacitor C is connected to the second node N2 , ie, the second end of the storage capacitor C is connected to the control electrode of the third transistor T3 .

[0099] The control electrode of the first transistor T1 is connected to the second scan signal line S2, the first electrode of the first transistor T1 is connected to the initial signal line INIT, and the second electrode of the first transistor is connected to the second node N2. When the on-level scan signal is applied to the second scan signal line S2, the first transistor T1 transmits the initialization voltage to the control electrode of the third transistor T3, so that the charge amount of the control electrode of the third transistor T3 is initialized.

[0100] The control electrode of the second transistor T2 is connected to the first scan signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When the on-level scan signal is applied to the first scan signal line S1, the second transistor T2 connects the control electrode of the third transistor T3 to the second electrode.

[0101] The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 can be called a driving transistor, and the third transistor T3 determines the amount of driving current flowing between the first power line VDD and the second power line VSS according to the potential difference between its control electrode and the first electrode.

[0102] The control electrode of the fourth transistor T4 is connected to the first scan signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 can be called a switching transistor, a scan transistor, etc. When the on-level scan signal is applied to the first scan signal line S1, the fourth transistor T4 enables the data voltage of the data signal line D to be input to the pixel driving circuit.

[0103] The control electrode of the fifth transistor T5 is connected to the light emitting signal line E, the first electrode of the fifth transistor T5 is connected to the first power line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emitting signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 can be called light emitting transistors. When the on-level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power line VDD and the second power line VSS to make the light emitting device emit light.

[0104] The control electrode of the seventh transistor T7 is connected to the first scan signal line S1, the first electrode of the seventh transistor T7 is connected to the initial signal line INIT, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When the on-level scan signal is applied to the first scan signal line S1, the seventh transistor T7 transmits the initialization voltage to the first electrode of the light emitting device to initialize or release the charge accumulated in the first electrode of the light emitting device.

[0105] In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power line VSS, the signal of the second power line VSS is a low level signal, and the signal of the first power line VDD is a continuously provided high level signal. The first scanning signal line S1 is a scanning signal line in the pixel driving circuit of the current display row, and the second scanning signal line S2 is a scanning signal line in the pixel driving circuit of the previous display row, that is, for the nth display row, the first scanning signal line S1 is S(n), and the second scanning signal line S2 is S(n-1), and the second scanning signal line S2 of the current display row is the same as the first scanning signal line S1 in the pixel driving circuit of the previous display row, which can reduce the signal lines of the display panel and realize the narrow frame of the display panel.

[0106] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0107] In an exemplary embodiment, the first scan signal line S1, the second scan signal line S2, the emission signal line E, and the initial signal line INIT extend in a horizontal direction, and the second power line VSS, the first power line VDD, and the data signal line D extend in a vertical direction.

[0108] In an exemplary embodiment, the light emitting device may be an organic light emitting diode (OLED) including a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) stacked.

[0109] Figure 3 This is a working timing diagram of a pixel driving circuit. Figure 2 The operation process of the pixel driving circuit of the example is described in detail. Figure 2 The pixel driving circuit includes 7 transistors (first transistor T1 to sixth transistor T7), 1 storage capacitor C and 7 signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emitting signal line E, initial signal line INIT, first power line VDD and second power line VSS), and all 7 transistors are P-type transistors.

[0110] In an exemplary embodiment, the operation process of the pixel driving circuit may include:

[0111] The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, which turns on the first transistor T1. The signal of the initial signal line INIT is provided to the second node N2 to initialize the storage capacitor C and clear the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, which turns off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7. In this stage, the OLED does not emit light.

[0112] The second stage A2 is called the data writing stage or the threshold compensation stage. The signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emitting signal line E are high level signals, and the data signal line D outputs the data voltage. In this stage, since the second end of the storage capacitor C is at a low level, the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. The second transistor T2 and the fourth transistor T4 are turned on so that the data voltage output by the data signal line D is provided to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2, and the difference between the data voltage output by the data signal line D and the threshold voltage of the third transistor T3 is charged into the storage capacitor C. The voltage of the second end (the second node N2) of the storage capacitor C is Vd-|Vth|, Vd is the data voltage output by the data signal line D, and Vth is the threshold voltage of the third transistor T3. The seventh transistor T7 is turned on so that the initial voltage of the initial signal line INIT is provided to the first electrode of the OLED, the first electrode of the OLED is initialized (reset), the pre-stored voltage inside it is cleared, the initialization is completed, and the OLED is ensured not to emit light. The signal of the second scanning signal line S2 is a high-level signal, which turns off the first transistor T1. The signal of the light-emitting signal line E is a high-level signal, which turns off the fifth transistor T5 and the sixth transistor T6.

[0113] The third stage A3 is called the light-emitting stage, the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output by the first power supply line VDD provides a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, driving the OLED to emit light.

[0114] During the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vdata-|Vth|, the driving current of the third transistor T3 is:

[0115] I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[(Vdd-Vd] 2

[0116] Among them, I is the driving current flowing through the third transistor T3, that is, the driving current driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output by the data signal line D, and Vdd is the power supply voltage output by the first power supply line VDD.

[0117] Figure 4 FIG. 1 is a schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure. Figure 4 As shown, the display substrate may include a plurality of pixel units P arranged in a matrix manner, at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light, the first sub-pixel P1, the second sub-pixel P2, and the third sub-pixel P3 each include a pixel driving circuit and a light-emitting device, the pixel driving circuits in the sub-pixels are respectively connected to the scanning signal lines, the data signal lines, and the light-emitting signal lines, the light-emitting devices in the sub-pixels are respectively connected to the pixel driving circuits of the sub-pixels, the pixel driving circuits are configured to receive the data voltage transmitted by the data signal lines under the control of the scanning signal lines and the light-emitting signal lines, and output a corresponding current to the light-emitting device, and the light-emitting device is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0118] In an exemplary embodiment, the first subpixel P1 may be a red (R) subpixel, the second subpixel P2 may be a green (G) subpixel, and the third subpixel P3 may be a blue (B) subpixel. The three subpixels are arranged in a herringbone shape. The rectangular R subpixel and the rectangular G subpixel are located on one side of the pixel unit, and the rectangular B subpixel is located on the other side of the pixel unit. The area of ​​the B subpixel may be approximately the sum of the areas of the R subpixel and the G subpixel. In an exemplary embodiment, the shape of the subpixel may be any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a parallelogram, a pentagon, a hexagon, and other polygons. The plurality of subpixels may be arranged horizontally, vertically, in an X shape, a cross shape, or a herringbone shape, etc., which is not limited in the present disclosure.

[0119] In an exemplary embodiment, the pixel unit P may include four sub-pixels, such as a red sub-pixel, a green sub-pixel, a blue sub-pixel and a white sub-pixel. The four sub-pixels may be arranged in horizontal parallel, vertical parallel or square manner, which is not limited in the present disclosure.

[0120] Figure 5 FIG. 1 is a schematic cross-sectional structure diagram of a display substrate according to an exemplary embodiment of the present disclosure, illustrating the structure of three sub-pixels of an OLED display substrate. Figure 5As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 12 disposed on a substrate 10, a light emitting structure layer 13 disposed on a side of the driving circuit layer 12 away from the substrate 10, and an encapsulation layer 14 disposed on a side of the light emitting structure layer 13 away from the substrate 10. In some possible implementations, the display substrate may include other film layers, such as spacers, etc., which are not limited in the present disclosure.

[0121] In an exemplary embodiment, the substrate 10 may be a flexible substrate, or may be a rigid substrate. The driving circuit layer 12 of each sub-pixel may include a plurality of transistors and storage capacitors constituting a pixel driving circuit. Figure 5 Only one transistor 11A and one storage capacitor 11B are taken as examples. The light emitting structure layer 13 may include an anode 31, a pixel definition layer 32, an organic light emitting layer 33 and a cathode 34. The anode 31 is connected to the drain electrode of the transistor 11A through a via. The pixel definition layer 32 covers the anode 31 and is provided with a pixel opening exposing the anode 31. The organic light emitting layer 33 is connected to the anode 31 through the pixel opening. The cathode 34 is connected to the organic light emitting layer 33. The organic light emitting layer 33 emits light of corresponding colors under the drive of the anode 31 and the cathode 34. The encapsulation layer 14 may include a first encapsulation layer 41, a second encapsulation layer 42 and a third encapsulation layer 43 stacked. The first encapsulation layer 41 and the third encapsulation layer 43 may be made of inorganic materials, and the second encapsulation layer 42 may be made of organic materials. The second encapsulation layer 42 is arranged between the first encapsulation layer 41 and the third encapsulation layer 43, which can ensure that external water vapor cannot enter the light emitting structure layer 13. In an exemplary embodiment, the touch panel is arranged on the side of the third encapsulation layer 43 away from the substrate.

[0122] In an exemplary embodiment, the driving circuit layer of each sub-pixel may include: a first insulating layer disposed on a flexible substrate, an active layer disposed on the first insulating layer, a second insulating layer covering the active layer, a gate electrode and a first capacitor electrode disposed on the second insulating layer, a third insulating layer covering the gate electrode and the first capacitor electrode, a second capacitor electrode disposed on the third insulating layer, a fourth insulating layer covering the second capacitor electrode, a via hole being provided on the fourth insulating layer, the via hole exposing the active layer, a source electrode and a drain electrode disposed on the fourth insulating layer, the source electrode and the drain electrode being connected to the active layer through the via hole, respectively, and a flat layer covering the aforementioned structure. The active layer, the gate electrode, the source electrode and the drain electrode constitute a transistor, and the first capacitor electrode and the second capacitor electrode constitute a storage capacitor. In an exemplary embodiment, the active layer may be made of amorphous indium gallium zinc oxide material (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), sexithiophene or polythiophene, and the like, that is, the present disclosure is applicable to transistors manufactured based on oxide technology, silicon technology or organic technology.

[0123] In an exemplary embodiment, the organic light emitting layer may include a light emitting layer (EML), and any one or more of the following layers: a hole injection layer (HIL), a hole transport layer (HTL for short), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, the hole injection layers of all sub-pixels may be a common layer connected together, the electron injection layers of all sub-pixels may be a common layer connected together, the hole transport layers of all sub-pixels may be a common layer connected together, the electron transport layers of all sub-pixels may be a common layer connected together, the hole blocking layers of all sub-pixels may be a common layer connected together, the light emitting layers of adjacent sub-pixels may have a small overlap, or may be isolated, and the electron blocking layers of adjacent sub-pixels may have a small overlap, or may be isolated.

[0124] In an exemplary embodiment, each sub-pixel in the display substrate may include a light-emitting region and a non-light-emitting region. Since the organic light-emitting layer emits light in the pixel opening region defined by the pixel definition layer, the pixel opening region is the light-emitting region FA of the sub-pixel, and the region outside the pixel opening is the non-light-emitting region BF of the sub-pixel, and the non-light-emitting region BF is located between the light-emitting regions FA of adjacent sub-pixels.

[0125] The exemplary embodiment of the present disclosure provides a touch panel. In an exemplary embodiment, the touch panel may include a touch area and a binding area located on one side of the touch area in a first direction; the binding area may include:

[0126] a chip area, the chip area comprising a first side, a second side, a third side and a fourth side, the first side and the second side extending along a second direction, the second side being located at a side of the first side away from the touch control area, the third side and the fourth side extending along the first direction, and the first direction intersecting the second direction;

[0127] a plurality of pins, located in the chip area, the plurality of pins comprising a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines;

[0128] A plurality of touch electrodes, located in the touch area;

[0129] A plurality of touch signal lines are located in the touch area and the binding area, and the plurality of touch signal lines are correspondingly connected to the plurality of touch electrodes and the plurality of touch pins.

[0130] In an exemplary embodiment, the chip area includes a first pin area, a second pin area, a third pin area, a fourth pin area, a fifth pin area and a sixth pin area; the first pin area is arranged along a first side of the chip area, the second pin area is arranged along a second side of the chip area, the third pin area and the fifth pin area are arranged in sequence along a third side of the chip area, and the fourth pin area and the sixth pin area are arranged in sequence along a fourth side of the chip area.

[0131] In an exemplary embodiment, the plurality of display pins include a plurality of display signal output pins and a plurality of display signal input pins, the plurality of display signal output pins are arranged in the first pin area, and the plurality of display signal input pins are arranged in the second pin area; the plurality of display signal output pins are configured to be connected to data signal lines, and the display signal input pins are configured to be connected to an external circuit board through display connection lines and a binding pin area of ​​the binding area, so that the external circuit board provides a display signal through the binding pin area, the display connection lines and the display signal input pins.

[0132] In an exemplary embodiment, the plurality of touch pins include a plurality of touch signal output pins and a plurality of touch signal input pins, the plurality of touch signal output pins are arranged in the third pin area and the fourth pin area, and the plurality of touch signal input pins are arranged in the fifth pin area and the sixth pin area; the touch signal output pins are configured to be connected to touch signal lines, and the touch signal input pins are configured to be connected to touch input lines, and touch signals are output to the touch signal output pins through the touch input lines and the touch signal input pins.

[0133] In an exemplary embodiment, the plurality of pins in at least one of the first pin area, the second pin area, the third pin area, the fourth pin area, the fifth pin area, and the sixth pin area are arranged in a multi-row staggered structure.

[0134] Figure 6 FIG. 1 is a schematic diagram of a touch panel according to an exemplary embodiment of the present disclosure. Figure 6As shown, in a plane parallel to the touch panel, the touch panel includes a touch area 100, a binding area 300 located on one side of the touch area 100 in the first direction D1, and a frame area 200 located on the other side of the touch area 100. In an exemplary embodiment, the shape of the touch area 100 may be circular, the circular touch area 100 is configured to be provided with a plurality of touch electrodes, the shape of the frame area 200 may be a ring surrounding the touch area 100, the ring-shaped frame area 200 is configured to be provided with a plurality of signal leads, a first end of at least one signal lead is connected to at least one touch electrode in the touch area 100, a second end of the signal lead extends along the frame shape to the binding area 300, the shape of the binding area 300 may be rectangular, and the binding area 300 is configured to connect the plurality of signal leads to an external control device.

[0135] like Figure 6 As shown, the circular touch control area 100 may be divided into a plurality of electrode areas. In an exemplary embodiment, the plurality of electrode areas may include: a first electrode area 101 located in the middle of the touch control area 100, a second electrode area 102 located on one side (lower side) of the first electrode area 101 in the first direction D1, a third electrode area 103 located on one side (upper side) of the first electrode area 101 in the opposite direction of the first direction D1, a fourth electrode area 104 located on one side (right side) of the first electrode area 101 in the second direction D2, and a fifth electrode area 105 located on one side (left side) of the first electrode area 101 in the opposite direction of the second direction D2. In an exemplary embodiment, the shape of the first electrode area 101 may be a rectangle, which may be inscribed in the circle defining the touch control area, and the rectangular first electrode area 101 is configured to arrange a plurality of touch control electrodes in a matrix arrangement. In an exemplary embodiment, the second electrode region 102 , the third electrode region 103 , the fourth electrode region 104 and the fifth electrode region 105 may be in the shape of a dome, and the dome-shaped electrode region is configured to sequentially arrange a plurality of touch electrodes in the first direction D1 or in the second direction D2 .

[0136] Figure 7 FIG. 1 is a schematic diagram of an arrangement of touch electrodes according to an exemplary embodiment of the present disclosure, taking the touch area including 24 self-capacitive touch electrodes as an example. Figure 7As shown, in a plane parallel to the touch panel, the touch area 100 may include 24 regularly arranged touch electrodes 400. In an exemplary embodiment, the rectangular first electrode area 101 may include 4 rows*4 columns of touch electrodes 400 arranged in a matrix, each touch electrode 400 may be rectangular in shape, the 16 touch electrodes 400 may have the same area, and the area of ​​each touch electrode 400 is S. The crown-shaped second electrode area 102 and the third electrode area 103 may each include 2 touch electrodes 400, the 2 touch electrodes 400 are sequentially arranged along the second direction D2, the areas of the 2 touch electrodes 400 in each electrode area may be the same, and the area of ​​the touch electrode 400 in the second electrode area 102 and the area of ​​the touch electrode 400 in the third electrode area 103 may be the same. The fourth electrode region 104 and the fifth electrode region 105 in a crown shape may each include two touch electrodes 400, and the two touch electrodes 400 are arranged sequentially along the first direction D1. The areas of the two touch electrodes 400 in each electrode region may be the same, and the area of ​​the touch electrode 400 in the fourth electrode region 104 and the area of ​​the touch electrode 400 in the fifth electrode region 105 may be the same.

[0137] In an exemplary embodiment, the area of ​​at least one touch electrode 400 in the second electrode region 102 and the third electrode region 103 may be approximately 1.5S to 1.6S. For example, the area of ​​each touch electrode 400 in the second electrode region 102 and the third electrode region 103 may be approximately 1.55S.

[0138] In an exemplary embodiment, the area of ​​at least one touch electrode 400 in the fourth electrode region 104 and the fifth electrode region 105 may be approximately 1.47S to 1.57S. For example, the area of ​​each touch electrode 400 in the fourth electrode region 104 and the fifth electrode region 105 may be approximately 1.52S.

[0139] In an exemplary embodiment, the plurality of touch electrodes 400 in the touch area 100 may be symmetrically arranged with respect to a center line O, and the center line O may be a center line extending along the first direction D1 and equally dividing the touch area.

[0140] In an exemplary embodiment, the plurality of touch electrodes 400 in the first electrode region 101 may be in a rectangular pattern of approximately 4 mm*4 mm or 5 mm*5 mm. In some possible exemplary embodiments, the plurality of touch electrodes 400 in the first electrode region 101 may be in a rhombus, a triangle, a polygon, etc. During operation, the touch of a human finger may cause the self-capacitance of the corresponding touch electrode to change, and the external control device may determine the position of the finger according to the change in the capacitance of the touch electrode.

[0141] In an exemplary embodiment, the touch electrode in the touch panel can be in the form of a metal grid, the metal grid is formed by interweaving a plurality of metal wires, the metal grid includes a plurality of grid patterns, the grid pattern is a polygon surrounded by a plurality of metal wires, and the touch electrode in the form of a metal grid has the advantages of low resistance, small thickness, and fast response speed. In an exemplary embodiment, the area surrounded by the metal wires in a grid pattern includes the light-emitting area of ​​the sub-pixel, and the metal wires are located in the non-light-emitting area between adjacent light-emitting areas. For example, when the display substrate is an OLED display substrate, the light-emitting area is the area of ​​the pixel opening in the pixel defining layer, the non-light-emitting area is the area outside the pixel opening, the orthographic projection of the light-emitting area on the display substrate is located within the range of the orthographic projection of the area surrounded by the metal wires on the display substrate, and the orthographic projection of the metal wires on the display substrate is located within the range of the orthographic projection of the non-light-emitting area on the display substrate.

[0142] Figure 8-1 to Figure 8-5 Schematic diagrams of the structures of several metal grids. The metal grid includes multiple grid patterns, the grid pattern is a polygon formed by metal wires, and the metal grid is formed by repeatedly and continuously arranging multiple grid patterns. In an exemplary embodiment, the shape of the grid pattern surrounded by metal wires can be a rhombus, such as Figure 8-1 Alternatively, the shape of the grid pattern formed by the metal wires can be a triangle, such as Figure 8-2 Alternatively, the shape of the grid pattern surrounded by metal wires can be a rectangle, such as Figure 8-3 Alternatively, the shape of the grid pattern formed by the metal wires can be a hexagon, such as Figure 8-4 Alternatively, the shape of the grid pattern formed by the metal wires can be a combination of multiple shapes, such as a combination of pentagons and hexagons, such as Figure 8-5 As shown. Alternatively, the shape of the grid pattern formed by the metal wires may include any one or more of a triangle, a square, a rectangle, a rhombus, a trapezoid, a pentagon, and a hexagon. In some possible implementations, the grid pattern formed by the metal wires may be a regular shape or an irregular shape, which is not limited in the present disclosure. In some possible implementations, the line width of the metal wire is ≤5μm.

[0143] Fig. 9 FIG. 1 is a schematic diagram of the structure of a metal grid touch electrode, taking a rectangular grid pattern as an example. Fig. 9 As shown, in order to form a plurality of touch electrodes insulated from each other in the touch area, a plurality of cutouts 500 are provided on the metal grid, and the plurality of cutouts 500 disconnect the metal lines of the grid pattern to achieve isolation of the grid patterns of adjacent touch electrodes 400 . Fig. 9In the figure, a black block is used to represent the cutout 500, and the cutout 500 can be understood as an imaginary line for cutting the metal wire. In an exemplary embodiment, a plurality of cutouts 500 can form a touch area and a boundary area in the metal grid, and a cutout 500 is provided in each grid pattern located in the boundary area, and the cutout 500 cuts off the metal wire of the grid pattern, so that each grid pattern is divided into two parts, one part belongs to the touch electrode 400 on one side, and the other part belongs to the touch electrode 400 on the other side.

[0144] In an exemplary embodiment, the touch area may be provided with a plurality of cutouts (not shown), and the plurality of cutouts respectively form one or more dummy areas in the touch area.

[0145] Fig.10 This is a schematic diagram of a touch line in a touch panel, illustrating the structure of the touch line in the junction area of ​​the touch area 100 and the frame area 200, taking a rectangular grid pattern as an example. In an exemplary embodiment, in order to form a plurality of touch lines that are insulated from each other in the touch area 100, this can be achieved by providing cuts on the metal grid. In an exemplary embodiment, a plurality of cuts are provided on the grid pattern, and the plurality of cuts disconnect the metal wires of the grid pattern to isolate the grid pattern of one touch line from the grid pattern of another adjacent touch line. The cuts can be understood as imaginary lines that cut the metal wires, and the plurality of cuts on the plurality of grid patterns can form a signal transmission channel. Fig.10 As shown, the black blocks represent cutouts, and the dark and light fillings represent the touch traces 410 defined by the multiple cutouts. In an exemplary embodiment, the signal leads 210 of the frame area 200 may be in the form of metal wires, and the multiple signal leads 210 of the frame area 200 are correspondingly connected to the multiple touch traces 410 of the touch area 100.

[0146] Fig.11 FIG. 1 is a schematic diagram of a signal lead in a touch panel according to an exemplary embodiment of the present disclosure, taking the touch area including 24 self-capacitive touch electrodes as an example. Fig.11 As shown, the touch panel may include a touch area 100, a frame area 200, and a binding area 300. The touch area 100 may include a plurality of touch electrodes 400 and a plurality of touch traces 410. The frame area 200 may include a plurality of signal leads 210, a ground line 220, and a virtual line segment 230. In an exemplary embodiment, the plurality of touch electrodes 400 and the plurality of touch traces 410 of the touch area 100 are in the form of a metal grid pattern, and the plurality of signal leads 210 and the ground line 220 of the frame area 200 are in the form of metal lines.

[0147] In an exemplary embodiment, the 24 touch electrodes 400 of the touch area 100 are arranged in 6 rows and 6 columns, and the 24 touch electrodes 400 may be symmetrically arranged with respect to the center line O. The positions of the touch electrodes are described below by taking the 12 touch electrodes on the left side of the center line O as an example.

[0148] In an exemplary embodiment, no touch electrodes are provided in the area where the 1st row and the 1st column are located and the area where the 6th row and the 1st column are located, the area where the 2nd and 3rd columns of the 1st row are located forms a 1st row of strip touch electrodes extending along the second direction D2, the area where the 2nd and 3rd columns of the 6th row are located forms a 6th row of strip touch electrodes extending along the second direction D2, the area where the 2nd and 3rd rows of the 1st column are located forms a 2nd-3rd row of strip touch electrodes extending along the first direction D1, the area where the 4th and 5th rows of the 1st column are located forms a 4th-5th row of strip touch electrodes extending along the first direction D1, and the area where the 2nd to 3rd columns of the 2nd row, the area where the 2nd to 3rd columns of the 3rd row, the area where the 2nd to 3rd columns of the 4th row, and the area where the 2nd to 3rd columns of the 5th row form 8 block touch electrodes.

[0149] In an exemplary embodiment, the 24 touch traces 410 of the touch area 100 may be arranged between the touch electrodes 400, and the 24 touch traces 410 may be symmetrically arranged relative to the center line O. A first end of a touch trace 410 is connected to a touch electrode 400, and a second end of the touch trace 410 extends to the frame area 200 and is connected to a first end of a signal lead 210 in the frame area 200. The positions of the touch traces are described below by taking the 12 touch traces on the left side of the center line O as an example.

[0150] In an exemplary embodiment, the plurality of touch lines 410 may include a first group of lines, a second group of lines, a third group of lines, and a fourth group of lines sequentially arranged along the first direction D1. The first group of lines may include 4 touch lines, the first ends of which are respectively connected to the strip touch electrodes in the first row, the block touch electrodes in the second row and the second column, the block touch electrodes in the second row and the third column, and the block touch electrodes in the third row and the third column, and the second ends extend to the frame area 200. The second group of lines may include 3 touch lines, the first ends of which are respectively connected to the strip touch electrodes in the second and third rows, the block touch electrodes in the third row and the second column, and the block touch electrodes in the fourth row and the second column, and the second ends extend to the frame area 200. The third group of traces may include 4 touch traces, the first ends of which are respectively connected to the strip touch electrodes in the 4th and 5th rows, the block touch electrodes in the 4th row and the 3rd column, the block touch electrodes in the 5th row and the 2nd column, and the block touch electrodes in the 5th row and the 3rd column, and the second ends extend to the frame area 200. The fourth group of traces may include 1 touch trace, the first end of which is connected to the strip touch electrode in the 6th row, and the second end directly extends to the binding area 300.

[0151] In an exemplary embodiment, a first end of a signal lead 210 in the frame area 200 is connected to a second end of a touch trace 410 in the touch area 100, and a second end of the signal lead 210 extends along the frame shape to the binding area 300. A first end of a ground wire 220 in the frame area 200 is disposed on a side of the frame area 200 away from the binding area 300, a second end of the ground wire 220 extends along the frame shape to the binding area 300, and the ground wire 220 is disposed on a side of the signal lead 210 away from the touch area 100, and the ground wire 220 is configured to conduct static electricity generated by the touch panel through a conductive loop.

[0152] In an exemplary embodiment, the signal lead 210 and the ground line 220 in the frame region 200 may be symmetrically arranged with respect to the center line O. The positions of the lead are described below by taking the lead on the left side of the center line O as an example.

[0153] In an exemplary embodiment, the plurality of signal leads 210 may include a first group of leads 211, a second group of leads 212, a third group of leads 213, and a fourth group of leads 214 sequentially arranged along the first direction D1. The first group of leads 211 may include 4 signal leads, the first ends of the 4 signal leads are respectively connected to the second ends of the 4 touch lines in the first group of lines, and the second ends of the 4 signal leads are respectively extended along the frame shape to the binding area 300. The second group of leads 212 may include 3 signal leads, the first ends of the 3 signal leads are respectively connected to the second ends of the 3 touch lines in the second group of lines, and the second ends of the 3 signal leads are respectively extended along the frame shape to the binding area 300. The third group of leads 213 may include 4 signal leads, the first ends of the 4 signal leads are respectively connected to the second ends of the 4 touch lines in the third group of lines, and the second ends of the 4 signal leads are respectively extended along the frame shape to the binding area 300. The fourth group of leads 214 may include one signal lead, a first end of the signal lead is connected to a second end of a touch line in the fourth group of leads, and a second end of the signal lead extends to the binding area 300 .

[0154] Fig.12 is a schematic diagram of a first group of leads according to an exemplary embodiment of the present disclosure, Fig.11 A magnified view of area A. Fig.12 As shown, the first group of leads 211 may include a first signal lead 210-1, a second signal lead 210-2, a third signal lead 210-3, and a fourth signal lead 210-4, and the four signal leads are respectively connected to the four touch lines of the first group of lines in the touch area. In an exemplary embodiment, each signal lead includes a lead-out section and an extension section, the first end of the lead-out section is connected to the touch line connected to the touch electrode, the second end of the lead-out section is extended in the opposite direction of the second direction D2 and then connected to the first end of the extension section, and the second end of the extension section extends toward the binding area along the frame shape.

[0155] In an exemplary embodiment, the first signal lead 210-1, the second signal lead 210-2, the third signal lead 210-3 and the fourth signal lead 210-4 form a nested lead structure, the fourth signal lead 210-4 is embedded in the third signal lead 210-3, the third signal lead 210-3 is embedded in the second signal lead 210-2, and the second signal lead 210-2 is embedded in the first signal lead 210-1.

[0156] In an exemplary embodiment, the first end of the grounding wire 220 is disposed on a side of the frame area away from the binding area, and the second end of the grounding wire 220 extends toward the binding area along the frame shape. In an exemplary embodiment, the grounding wire 220 is disposed on a side of the first signal lead 210-1 away from the touch control area.

[0157] In an exemplary embodiment, a plurality of virtual line segments 230 may be provided in the border area. The plurality of virtual line segments 230 may be provided between the extension section of the first signal lead 210-1 and the ground line 220. The plurality of virtual line segments 230 are provided sequentially in a direction away from the touch area, and each virtual line segment 230 extends along the shape of the border.

[0158] Fig.13 is a schematic diagram of a second group of leads according to an exemplary embodiment of the present disclosure, Fig.11 A magnified view of area B in the figure. Fig.13 As shown, the second group of leads 212 may include a fifth signal lead 210-5, a sixth signal lead 210-6, and a seventh signal lead 210-7, and the three signal leads are respectively connected to the three touch lines of the second group of lines in the touch area. In an exemplary embodiment, each signal lead includes a lead-out section and an extension section, the first end of the lead-out section is connected to the touch line connected to the touch electrode, the second end of the lead-out section is extended in the opposite direction of the second direction D2 and then connected to the first end of the extension section, and the second end of the extension section extends toward the binding area along the frame shape.

[0159] In an exemplary embodiment, the fifth signal lead 210-5, the sixth signal lead 210-6, and the seventh signal lead 210-7 form a nested lead structure, the seventh signal lead 210-7 is embedded within the sixth signal lead 210-6, and the sixth signal lead 210-6 is embedded within the fifth signal lead 210-5.

[0160] In an exemplary embodiment, an extension section of the fifth signal lead 210-5 is arranged on a side of an extension section of the fourth signal lead 210-4 close to the touch area, that is, the four signal leads of the first group of leads 211 are arranged on a side of the fifth signal lead 210-5 away from the touch area, and the ground line 220 is arranged on a side of the first signal lead 210-1 away from the touch area.

[0161] In an exemplary embodiment, a plurality of virtual line segments 230 may be disposed between the first signal lead 210 - 1 and the ground line 220 , and the plurality of virtual line segments 230 are sequentially disposed in a direction away from the touch area, and each virtual line segment 230 extends along a frame shape.

[0162] Fig.14 is a schematic diagram of a third group of leads of an exemplary embodiment of the present disclosure, Fig.11 A magnified view of the C area. Fig.14As shown, the third group of leads 213 may include an eighth signal lead 210-8, a ninth signal lead 210-9, a tenth signal lead 210-10, and an eleventh signal lead 210-11, and the four signal leads are respectively connected to the four touch lines of the third group of lines in the touch area. In an exemplary embodiment, each signal lead includes a lead-out section and an extension section, the first end of the lead-out section is connected to the touch line connected to the touch electrode, the second end of the lead-out section is extended in the opposite direction of the second direction D2 and then connected to the first end of the extension section, and the second end of the extension section extends toward the binding area along the frame shape.

[0163] The eighth signal lead 210-8, the ninth signal lead 210-9, the tenth signal lead 210-10 and the eleventh signal lead 210-11 form a nested lead structure, the eleventh signal lead 210-11 is embedded in the tenth signal lead 210-10, the tenth signal lead 210-10 is embedded in the ninth signal lead 210-9, and the ninth signal lead 210-9 is embedded in the eighth signal lead 210-8.

[0164] In an exemplary embodiment, an extension section of the eighth signal lead 210-8 is arranged on a side of an extension section of the seventh signal lead 210-7 close to the touch area, that is, the seven signal leads of the first group of leads 211 and the second group of leads 212 are arranged on a side of the eighth signal lead 210-8 away from the touch area, and the ground line 220 is arranged on a side of the first signal lead 210-1 away from the touch area.

[0165] In an exemplary embodiment, a plurality of virtual line segments 230 may be disposed between the first signal lead 210 - 1 and the ground line 220 , and the plurality of virtual line segments 230 are sequentially disposed in a direction away from the touch area, and each virtual line segment 230 extends along a frame shape.

[0166] Fig.15 is a schematic diagram of a fourth group of leads according to an exemplary embodiment of the present disclosure, Fig.11 A magnified view of the D area. Fig.14 As shown, the fourth group of leads 214 may include a twelfth signal lead 210-12, which is connected to the touch trace of the fourth group of traces in the touch area. In an exemplary embodiment, the twelfth signal lead 210-12 includes a lead section and an extension section, the first end of the lead section is connected to the touch trace connected to the touch electrode, the second end of the lead section is extended along the second direction D2 and then connected to the first end of the extension section, and the second end of the extension section extends along the first direction D1 toward the binding area.

[0167] In an exemplary embodiment, 11 signal leads of the first group of leads 211, the second group of leads 212 and the third group of leads 213 are arranged on one side of the first direction D1 of the twelfth signal lead 210-12, a grounding line 220 is arranged on the side of the first signal lead 210-1 away from the touch area, and extends along the second direction D2 and then turns to extend toward the binding area, and another grounding line 220 is arranged on one side of the second direction D2 of the extension section of the twelfth signal lead 210-12 and extends along the first direction D1 toward the binding area.

[0168] Fig.16 FIG. 1 is a schematic diagram of a lead collection area in a border region of an exemplary embodiment of the present disclosure. Fig.16 As shown, after the plurality of signal leads 210 are gathered together in the lead collection area of ​​the frame area, they extend toward the binding area along the first direction D1. On both sides of the center line O, the plurality of signal leads 210 are arranged between two grounding wires 220, and the grounding wires 220 can shield the signal leads so that static electricity and interference signals will not affect the signal leads.

[0169] Fig.17 FIG. 1 is a schematic diagram of a binding area of ​​an exemplary embodiment of the present disclosure. Fig.17 As shown, the binding area 300 is arranged on one side of the first direction D1 of the touch area 100, and the binding area 300 may include a bending area 310, a routing area 320, a chip area 330 and a pin binding area 340 arranged in sequence along the first direction D1 (i.e., the direction away from the touch area 100). In an exemplary embodiment, the bending area 310 is configured to bend the binding area to the back of the touch panel, the routing area 320 is configured to lead the data signal line, the power signal line and the touch signal line to a set position, the chip area 330 is configured to bind the integrated circuit chip, and the pin binding area 340 is configured to set a plurality of binding pins, and the plurality of binding pins can be bound to a flexible printed circuit (Flexible Printed Circuit, referred to as FPC), so that the data signal line, the power signal line and the touch signal line are connected to an external control device through the binding pins and the binding flexible circuit board, and the external control device provides the display panel or the display backplane with a data signal, a power signal and a touch signal to realize image display and touch functions.

[0170] In an exemplary embodiment, an array test unit (not shown) is further provided on one side of the binding area 300 away from the touch area 100. The array test unit includes a plurality of test terminals (ET Pad), which are correspondingly connected to a plurality of binding pins of the binding pin area through interface lines, and are configured to test the display substrate and the touch panel to check whether there are problems such as short circuit and open circuit. In an exemplary embodiment, a cutting line is provided between the binding area 300 and the array test unit. After the test is completed, the cutting device cuts along the cutting line to remove the array test unit.

[0171] In an exemplary embodiment, the data signal lines and power signal lines in the display substrate and the touch signal lines (signal leads) in the touch panel are first gathered in the lead collection area of ​​the frame area, and then extend from the lead collection area to the binding area. In the binding area, these signal lines first cross the bending area 310 through a plurality of connecting lines, and then are led out to the corresponding positions in the routing area 320. Among them, the data signal line 610 and the touch signal line 620 are led to the chip area 330 and connected to the pins of the chip area. The power signal line includes at least a first power line (VDD) 630 and a second power line (VSS) 640. The first power line 630 and the second power line 640 are led to the pin binding area 340 and connected to the corresponding binding pins. The first power line 630 and the second power line 640 are configured to respectively connect the high voltage power line and the low voltage power line of the display substrate or the display backplane.

[0172] In an exemplary embodiment, the first power line and the second power line can be arranged in the same layer, the first power line and the second power line and the data signal line can be arranged in different layers, the touch signal line and the data signal line can be arranged in different layers, the orthographic projection of the data signal line on the binding area plane overlaps with the orthographic projection of the first power line and the second power line on the binding area plane, the orthographic projection of the touch signal line on the binding area plane overlaps with the orthographic projection of the first power line and the second power line on the binding area plane, the first power line and the second power line can provide shielding function for the data signal line and the touch signal line, avoid signal interference, and improve the reliability of signal transmission. In an exemplary embodiment, the binding area can include an anti-static area, and the signal line in the binding area can include a scanning signal line transmitted to the gate drive circuit and a ground line transmitted to the touch panel, etc., which is not limited in the present disclosure.

[0173] In an exemplary embodiment, the data signal line 610 may be disposed on both sides of the touch signal line 620, and the orthographic projection of the data signal line 610 on the binding area plane does not overlap with the orthographic projection of the touch signal line 620 on the binding area plane. The present disclosure avoids the problem of signal crosstalk caused by the crossing of the touch signal line and the data signal line by making the orthographic projection of the data signal line on the binding area plane and the orthographic projection of the touch signal line on the binding area plane not overlap, thereby improving the touch performance.

[0174] In a display device, a display driver integrated circuit is usually arranged in the chip area, and a touch integrated circuit (Touch IC) is arranged on the flexible circuit board FPC connected to the pin binding area. The display driver integrated circuit is configured to drive the display of the display substrate, and the touch integrated circuit is configured to drive the touch of the touch panel. Use shows that setting up independent display driver integrated circuits and touch integrated circuits not only has the problems of a large number of components and high overall cost, but also leads to problems such as low touch sensitivity, high display noise and large device thickness.

[0175] In the exemplary embodiment of the present disclosure, the integrated circuit in the chip area adopts a touch and display driver integrated circuit (Touchand Display Driver Integration, referred to as TDDI). The present disclosure effectively improves the touch sensitivity and effectively reduces the display noise by setting the touch and display driver integrated circuit in the chip area, and can provide first-class capacitive touch performance. Since the display driver and the touch driver are integrated in one chip, not only can the number of touch structure layers be reduced, the light transmittance of the touch panel is improved, which is beneficial to improving the brightness of the display device, but also the thickness of the display device can be reduced, which is beneficial to meet the design requirements of the thin display device. In addition, the use of touch and display driver integrated circuits effectively reduces the number of components, reduces the supply chain of equipment manufacturers, simplifies the preparation process, improves the output, and reduces the overall cost.

[0176] Fig.18 Schematic diagram of a chip area pin arrangement of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the chip area 330 in the binding area may be rectangular, provided with a plurality of pins, and the plurality of pins are configured to bind and connect a plurality of terminals of a driver IC (touch and display driver integrated circuit), and the edge of the driver IC may coincide with the boundary of the chip area 330. In an exemplary embodiment, the chip area 330 may include a first side, a second side, a third side, and a fourth side constituting a rectangle, the first side and the second side extending along the second direction D2, the third side and the fourth side extending along the first direction D1, the first side close to the touch area, and the second side away from the touch area.

[0177] like Fig.18As shown, the chip area 330 may include a first side 330-1 extending along the second direction D2 and close to the touch area, a second side 330-2 extending along the second direction D2 and away from the touch area, a third side 330-3 and a fourth side 330-4 extending along the first direction D1 and connecting the first side and the second side respectively.

[0178] In an exemplary embodiment, the chip region 330 may include a first pin region 710 , a second pin region 720 , a third pin region 730 , a fourth pin region 740 , a fifth pin region 750 , and a sixth pin region 760 .

[0179] In an exemplary embodiment, the first pin region 710 may be disposed at the first side 330 - 1 of the chip region 330 , and the second pin region 720 may be disposed at the second side 330 - 2 of the chip region 330 , and the first pin region 710 and the second pin region 720 are disposed opposite to each other in the first direction D1 .

[0180] In an exemplary embodiment, the third pin area 730 and the fifth pin area 750 may be disposed at the third side 330-3 of the chip area 330, and the third pin area 730 and the fifth pin area 750 may be sequentially disposed along the first direction D1. The fourth pin area 740 and the sixth pin area 760 may be disposed at the fourth side 330-4 of the chip area 330, and the fourth pin area 740 and the sixth pin area 760 may be sequentially disposed along the first direction D1, the third pin area 730 and the fourth pin area 740 may be disposed opposite to each other in the second direction D2, and the fifth pin area 750 and the sixth pin area 760 may be disposed opposite to each other in the second direction D2.

[0181] In an exemplary embodiment, the pins can be divided into display pins and touch pins, the display pins are configured to be connected to the display signal lines, and the touch pins are configured to be connected to the touch signal lines. The display pins can be divided into display signal output pins and display signal input pins, the display signal output pins are configured to be connected to the data signal lines, and the display signals are output through the display signal output pins and the data signal lines; the display signal input pins are configured to be connected to the external circuit board through the display connection lines and the binding pin area of ​​the binding area, so that the external circuit board inputs the display signal through the binding pin area, the display connection lines and the display signal input pins. The touch pins can be divided into touch signal output pins and touch signal input pins; the touch signal output pins are configured to be connected to the touch signal lines, and the touch signals are output to the touch electrodes through the touch signal output pins and the touch signal lines; the touch signal input pins are configured to be connected to the touch input lines, and the touch signals are output to the touch signal output pins through the touch input lines and the touch signal input pins.

[0182] In an exemplary embodiment, the first pin area 710 may include a plurality of first pins 810, and the plurality of first pins 810 are configured to be connected to a plurality of data signal lines correspondingly, and display signals such as data signals are output to a display substrate or a display backplane through the first pins 810 and the data signal lines. In an exemplary embodiment, the first pin area 710 may be referred to as a display signal output pin area, and the first pins 810 may be referred to as display signal output pins.

[0183] In an exemplary embodiment, the second pin area 720 may include a plurality of second pins 820, and the plurality of second pins 820 are configured to be connected to one end of a plurality of display connection lines, and the other ends of the plurality of display connection lines are connected to a plurality of binding pins of the pin binding area 340, so that the external control device inputs a display signal to the display substrate or the display backplane through the binding pins, the display connection lines, and the second pins 820. In an exemplary embodiment, the second pin area 720 may be referred to as a display signal input pin area, and the second pins 820 may be referred to as a display signal input pin.

[0184] In an exemplary embodiment, the third pin area 730 and the fourth pin area 740 may include a plurality of third pins 830, and the plurality of third pins 830 are configured to be connected to a plurality of touch signal lines correspondingly, and the touch signals are output to the touch panel through the third pins 830 and the touch signal lines. In an exemplary embodiment, the third pin area 730 and the fourth pin area 740 may be referred to as a touch signal output pin area, and the third pin 830 may be referred to as a touch signal output pin.

[0185] In an exemplary embodiment, the fifth pin area 750 and the sixth pin area 760 may include a plurality of fourth pins 840, the plurality of fourth pins 840 are correspondingly connected to one end of the touch input line, and the other end of the plurality of touch input lines is correspondingly connected to a plurality of binding pins of the binding area, so that the external control device provides a touch signal to the touch signal output pin through the binding pin, the touch input line and the fourth pin. In an exemplary embodiment, the fifth pin area 750 and the sixth pin area 760 may be referred to as a touch signal input pin area, and the fourth pin 840 may be referred to as a touch signal input pin.

[0186] In an exemplary embodiment, the pins of at least one of the first to sixth pin regions 710 to 760 may adopt a single-row alignment structure, or may adopt a two-row or more-row staggered structure.

[0187] In an exemplary embodiment, the pins in the first pin area 710 and the second pin area 720 may be arranged in a single row in a horizontal alignment manner, and the plurality of pins are sequentially arranged along the second direction D2 and aligned in the first direction D1 to form a single row structure. The third pin area 730 to the sixth pin area 760 may be arranged in a two-row longitudinal alignment manner, and the pins in each pin area are in a two-row structure, and the plurality of pins in each row are sequentially arranged along the first direction D1 and aligned in the second direction D2, and the plurality of pins in the first row are staggered with the plurality of pins in the second row.

[0188] Fig.19 This is a schematic diagram of a chip area wiring arrangement of an exemplary embodiment of the present disclosure, wherein the pins and touch signal lines are only an exemplary description, and the number of pins and touch signal lines does not represent the actual number. Fig.19 As shown, the chip area 330 may be symmetrically arranged with respect to a center line O, and the center line O may be a straight line extending along the first direction D1 and equally dividing the binding area (or chip area). In an exemplary embodiment, the chip area 330 may be provided with a plurality of pins and a plurality of touch signal lines, and the plurality of pins and the plurality of touch signal lines may be arranged in a mirror-symmetrical manner with respect to the center line O.

[0189] In an exemplary embodiment, a plurality of data signal lines extend from the routing area 320 to the chip area 330, and are connected to a plurality of first pins 810 in the first pin area, and display signals are output to the display substrate or the display backplane through the first pins and the data signal lines. A plurality of second pins 820 in the second pin area are connected to a plurality of first ends of display connection lines, and the second ends of the plurality of display connection lines are connected to a plurality of binding pins in the binding pin area after extending in a direction away from the touch control area, so that the external control device provides display signals to the display substrate or the display backplane through the binding pins, the display connection lines, and the second pins.

[0190] In an exemplary embodiment, after a plurality of touch signal lines extend from the lead gathering area of ​​the frame area to the binding area, they first cross the bending area through a plurality of connecting lines, and then extend along the routing area 320 into the chip area 330. After extending in the chip area 330, they are correspondingly connected to a plurality of third pins 830, and touch signals are output to the touch panel through the third pins and the touch signal lines.

[0191] In an exemplary embodiment, the plurality of touch signal lines may include a first touch signal line group and a second touch signal line group, and the two touch signal line groups are respectively disposed on both sides of the center line O, and may be symmetrically disposed with respect to the center line O. For example, the first touch signal line group is disposed on the left side of the center line O, and the second touch signal line group is disposed on the right side of the center line O, and the plurality of touch signal lines in the first touch signal line group are configured to transmit touch signals to the plurality of touch electrodes on the left side of the touch area, and the plurality of touch signal lines in the second touch signal line group are configured to output touch signals to the plurality of touch electrodes on the right side of the touch area.

[0192] In an exemplary embodiment, on the left side of the center line O, the first touch signal line group may include a first output line group and a second output line group, the first output line group may include a plurality of first touch signal lines 910, the second output line group may include a plurality of second touch signal lines 920, the distance between the first output line group and the center line O is greater than the distance between the second output line group and the center line O, that is, the plurality of first touch signal lines 910 are arranged on a side of the plurality of second touch signal lines 920 away from the center line O. The plurality of first touch signal lines 910 and the plurality of second touch signal lines 920 extend to the chip area 330, and after extending inside the chip area 330 toward the third pin area (left side), they are correspondingly connected to the plurality of third pins 830 in the third pin area.

[0193] In an exemplary embodiment, on the right side of the center line O, the second touch signal line group may include a third output line group and a fourth output line group, the third output line group may include a plurality of third touch signal lines 930, the fourth output line group may include a plurality of fourth touch signal lines 940, the distance between the third output line group and the center line O is greater than the distance between the fourth output line group and the center line O, that is, the plurality of third touch signal lines 930 are arranged on a side of the plurality of fourth touch signal lines 940 away from the center line O. The plurality of third touch signal lines 930 and the plurality of fourth touch signal lines 940 extend to the chip area 330, and after extending inside the chip area 330 toward the fourth pin area (right side), they are connected to the plurality of third pins 830 in the fourth pin area.

[0194] In an exemplary embodiment, a plurality of first connection lines 950 may be provided on the side of the fifth pin area and the sixth pin area close to the center line O, and the plurality of first connection lines 950 are configured to connect part of the fourth pin 840 and the second pin 820, so as to provide the same signal to the corresponding pins. A plurality of second connection lines 960 may be provided on the side of the second pin area away from the binding pin area 340, and the second connection lines 960 are configured to connect part of the second pin 820, so as to provide the same signal to the corresponding pins. Generally, a common signal is required for display signals and touch signals, such as a high-level signal provided by the first power line (VDD), a low-level signal provided by the second power line (VSS), etc. By parallel processing of the first connection line and the second connection line, the resistance can be effectively reduced and the signal uniformity can be improved.

[0195] In an exemplary embodiment, the chip area 330 may be provided with at least one dummy pin 900, which is a pin into which no electrical signal is introduced. In an exemplary embodiment, the dummy pin 900 may be provided at any one or more of the following positions: between the plurality of first touch signal lines 910, on one side or both sides of the plurality of first touch signal lines 910, between the plurality of second touch signal lines 920, on one side or both sides of the plurality of second touch signal lines 920, between the plurality of second touch signal lines 930, on one side or both sides of the plurality of second touch signal lines 930, between the plurality of fourth touch signal lines 940, on one side or both sides of the plurality of fourth touch signal lines 940.

[0196] The present disclosure introduces multiple touch signal lines into the chip area, and then extends them inside the chip area and connects them with corresponding pins, which not only effectively saves space outside the chip area, helps reduce the area of ​​the binding area, and reduces the design difficulty, but also effectively avoids static electricity and noise interference, and maximizes the touch performance. In addition, the present disclosure sets multiple virtual pins, which can support the driver IC, so that the driver IC can be flatly bound to the chip area, and the touch signal lines will not be crushed during the binding process, thereby improving the process quality.

[0197] Fig. 20 for Fig.19 The schematic diagram on the left side of the chip area. Fig. 20As shown, in an exemplary embodiment, the first pin area may include a control pin sub-area and a data pin sub-area, and the data pin sub-area is arranged on a side of the data pin sub-area away from the center line O. The data pin sub-area may include a plurality of data pins 810-1, and the control pin sub-area may include a plurality of control pins 810-2. The plurality of data pins 810-1 are configured to be connected to a plurality of data signal lines, and data signals are output to the display substrate or the display backplane through the data pins 810-1 and the data signal lines. The plurality of control pins 810-2 are configured to be connected to a plurality of control signal lines, and control signals, such as GOA signals, are output to the display substrate or the display backplane through the control pins 810-2 and the control signal lines.

[0198] In an exemplary embodiment, the plurality of second pins 820 in the second pin area are connected to the first ends of the plurality of display connection lines, and the second ends of the plurality of display connection lines are connected to the plurality of binding pins in the binding pin area 340 after extending in a direction away from the touch control area, so that the external control device inputs the display signal through the binding pins, the display connection lines and the second pins. A plurality of second connection lines 960 may be provided on one side of the second pin area away from the binding pin area 340, and the second connection lines 960 are configured to connect part of the second pins 820.

[0199] In an exemplary embodiment, at least one first touch signal line 910 may include a first output line segment 911, a second output line segment 912, a third output line segment 913, and a fourth output line segment 914 connected in sequence. The first output line segment 911 may be parallel to the first direction D1, the second output line segment 912 and the fourth output line segment 914 may be parallel to the second direction D2, the third output line segment 913 may be an oblique line, and a first angle θ1 is formed between the third output line segment 913 and the second direction D2. In an exemplary embodiment, the first end of the first output line segment 911 is located at the edge of the chip area 330 and is connected to the touch signal line extending from the touch area to the chip area. The second end of the first output line segment 911 is connected to the first end of the second output line segment 912 after extending along the first direction D1. The second end of the second output line segment 912 is connected to the first end of the third output line segment 913 after extending in the opposite direction of the second direction D2. The second end of the third output line segment 913 extends toward the third pin 830 and is connected to the first end of the fourth output line segment 914. The second end of the fourth output line segment 914 extends in the opposite direction of the second direction D2 and is connected to the corresponding third pin 830.

[0200] In an exemplary embodiment, at least one second touch signal line 920 may include a first output line segment 921, a second output line segment 922, a third output line segment 923, and a fourth output line segment 924 connected in sequence. The second output line segment 922 and the fourth output line segment 924 may be parallel to the second direction D2, the third output line segment 923 may be an oblique line, and the third output line segment 923 has a second angle θ2 with the second direction D2. In an exemplary embodiment, the first end of the first output line segment 921 is located at the edge of the chip area 330 and is connected to the touch signal line extending from the touch area to the chip area. The second end of the first output line segment 921 extends in a direction away from the display area and is connected to the first end of the second output line segment 922. The second end of the second output line segment 922 extends in the opposite direction of the second direction D2 and is connected to the first end of the third output line segment 923. The second end of the third output line segment 923 extends toward the fourth pin 840 and is connected to the first end of the fourth output line segment 924. The second end of the fourth output line segment 924 extends in the opposite direction of the second direction D2 and is connected to the corresponding fourth pin 840 .

[0201] In an exemplary embodiment, a plurality of first connection lines 950 may be disposed on one side of the fourth pin 840 close to the center line O, and one end of the plurality of first connection lines 950 is connected to some of the fourth pins 840 , and the other end is connected to some of the second pins 820 .

[0202] In an exemplary embodiment, the first angle θ1 and the second angle θ2 may be the same or different. The first angle θ1 of the plurality of third output line segments 913 may be the same or different. The second angle θ2 of the plurality of third output line segments 923 may be the same or different. The first angle θ1 and the second angle θ2 may be approximately 20° to 80°. For example, the first angle θ1 and the second angle θ2 may be approximately 45° or so.

[0203] In an exemplary embodiment, the plurality of first output line segments 921 may include a first output line segment group and a second output line segment group. The first output line segment group may include a plurality of first fold lines bent toward a direction close to the center line O, and the second output line segment group may include a plurality of second fold lines bent toward a direction away from the center line O. The plurality of first fold lines and the plurality of second fold lines enclose at least one polygonal area, and at least one virtual pin 900 is provided in the polygonal area.

[0204] In an exemplary embodiment, at least one dummy pin 900 may be disposed between the plurality of first output line segments 911 and the plurality of first output line segments 921 , and at least one dummy pin 900 may be disposed between the plurality of first output line segments 921 and the center line O.

[0205] In an exemplary embodiment, a plurality of dummy pins 900 may be disposed between the plurality of second output line segments 912 and the plurality of second output line segments 922 , and the plurality of dummy pins 900 may be sequentially disposed along the second direction D2 .

[0206] In an exemplary embodiment, a plurality of dummy pins 900 may be disposed between the plurality of second output line segments 922 and the plurality of second pins 820 of the second pin region, and the plurality of dummy pins 900 may be sequentially disposed along the second direction D2.

[0207] In an exemplary embodiment, at least one dummy pin 900 may be disposed on the center line O.

[0208] In an exemplary embodiment, the shapes and sizes of the plurality of virtual pins 900 in the chip area 330 may be the same or different, and may be set according to actual needs, which is not limited in the present disclosure.

[0209] The exemplary embodiment of the present disclosure sets virtual pins in the chip area. The virtual pins can be set between the touch signal lines, which not only allows the driver IC to be flatly bound to the chip area, but also does not crush the touch signal lines during the binding process, thereby improving the process quality, and can reduce the interference between the touch signal lines, thereby improving the touch performance. In addition, the regular arrangement of the virtual pins is conducive to improving the process quality.

[0210] In an exemplary embodiment, the structure on the right side of the chip region and the structure on the left side of the chip region may be symmetrical with respect to the center line O.

[0211] Fig.21 for Fig. 20 A magnified view of the C1 region. Fig. 20 and Fig.21 As shown, the chip area 330 can be symmetrically arranged relative to the center line O. On the left side of the center line O, the first side of the chip area 330 can be divided into a pin sub-area 330-5 and a routing sub-area 330-6. The routing sub-area 330-6 is located on the left side of the center line O, and the pin sub-area 330-5 is located on the left side of the routing sub-area 330-6, that is, the pin sub-area 330-5 is located on the side of the routing sub-area 330-6 away from the center line O. The pin sub-area 330-5 is configured to sequentially arrange a plurality of first pins 810 along the second direction D2, and the routing sub-area 330-6 is configured to sequentially arrange a plurality of touch signal lines along the second direction D2.

[0212] In an exemplary embodiment, the multiple touch signal lines extending from the routing area 320 into the chip area 330 may include a first output line group and a second output line group, the first output line group may include a plurality of first touch signal lines 910, the second output line group may include a plurality of second touch signal lines 920, and the distance between the first output line group and the center line O is greater than the distance between the second output line group and the center line O, that is, the plurality of first touch signal lines 910 are arranged on a side of the plurality of second touch signal lines 920 away from the center line O.

[0213] In an exemplary embodiment, in the region of the chip area 330 close to the first side, at least one dummy pin 900 may be disposed between the first output line group and the second output line group, and at least one dummy pin 900 may be disposed between the second output line group and the center line O. In an exemplary embodiment, the dummy pin 900 may be in the shape of a strip extending along the first direction D1. For example, the dummy pin 900 may be a rectangle, and the long side of the rectangle extends along the first direction D1.

[0214] In an exemplary embodiment, the shape of the first pin 810 may be a rectangle whose long side extends along the first direction D1. In an exemplary embodiment, the first length L1 of the first pin 810 may be approximately 100 μm to 120 μm, the first width M1 of the first pin 810 may be approximately 20 μm to 30 μm, and the width-to-length ratio (M1 / L1) may be approximately 0.2 to 0.3. Among them, the first length L1 is the dimension in the first direction D1, and the first width M1 is the dimension in the second direction D2. In an exemplary embodiment, the period (Pitch) of the first pin may be approximately 40 μm to 60 μm.

[0215] In an exemplary embodiment, the structures of the plurality of touch signal lines on the right side of the center line O may be the same as those on the left side of the center line O, and are symmetrically arranged relative to the center line O, which will not be described in detail herein.

[0216] Fig. 22 for Fig. 20 A magnified view of the C2 region. Fig. 20 and Fig. 22 As shown, a third pin area 730 and a fifth pin area 750 arranged in sequence along the first direction D1 are arranged at the third side on the left side of the chip area. The third pin area 730 may include a plurality of third pins 830 arranged in two rows of longitudinal staggered arrangement, and the fifth pin area 750 may include a plurality of fourth pins 840 arranged in two rows of longitudinal staggered arrangement.

[0217] In an exemplary embodiment, the third pin area 730 may include 20 third pins 830 (pin 1 to pin 20), and the fifth pin area 750 may include 13 fourth pins 840 (pin 21 to pin 33).

[0218] In an exemplary embodiment, pin 1 in the third pin area 730 is connected to the first ground line GND1, pins 2 to 4 are first idle pins, pins 5 to 10 are respectively connected to five first touch signal lines 910, pins 11 to 13 are second idle pins, pins 14 to 19 are respectively connected to five second touch signal lines 920, and pin 20 is connected to the second ground line GND2. In this way, the first idle pin is arranged between the first ground pin and the touch signal output pin, and the second idle pin is arranged between the touch signal output pins.

[0219] In an exemplary embodiment, the first ground line GND1 and the five first touch signal lines 910 may include a first output line segment, a second output line segment, a third output line segment, and a fourth output line segment connected in sequence, the second output line segment and the fourth output line segment are parallel to the second direction D2, and the third output line segment of the first touch signal line 910 has a first angle θ1 with the second direction D2. In an exemplary embodiment, the first angle of the third output line segment in the first ground line GND1 may be smaller than the first angle of the third output line segment in the first touch signal line 910.

[0220] In an exemplary embodiment, the second ground line GND2 and the five second touch signal lines 920 may include a first output line segment, a second output line segment, a third output line segment, and a fourth output line segment connected in sequence, the second output line segment and the fourth output line segment are parallel to the second direction D2, and the third output line segment of the second touch signal line 920 has a second included angle θ2 with the second direction D2. In an exemplary embodiment, the second included angle of the third output line segment in the second ground line GND2 may be greater than the second included angle of the third output line segment in the second touch signal line 920.

[0221] In an exemplary embodiment, pin 21 in the fifth pin area 750 is a third idle pin, pins 22 , 23 , 28 , and 29 are connected to a first connection line 950 , and the first connection line 950 is connected to one second pin 820 .

[0222] In an exemplary embodiment, an idle pin is a pin that is not connected to any signal line and can be understood as a virtual pin that not only plays a supporting role but also plays an isolation role to improve the quality of the binding process.

[0223] The aforementioned pins are connected to the touch signal line and the ground line, which means that the right side of the pin (the side close to the center line) is connected to the touch signal line and the ground line. In an exemplary embodiment, the left side of the pin (the side away from the center line) can be connected to the corresponding connection line. For example, the left side of pins 1 and 20 in the third pin area 730 can be connected to one end of the ground connection line, and the other end of the ground connection line is connected to the binding pin of the binding pin area, so that the external control device transmits the ground signal to the first ground line and the second ground line. For another example, the left side of pins 5 to 19 in the third pin area 730 can be connected to one end of the touch connection line, and the other end of the touch connection line is correspondingly connected to a plurality of binding pins in the binding pin area, so that the array test unit inputs / outputs test signals through the binding pins, the touch connection line and the third pin. For another example, the left side of pins 22 to 33 in the fifth pin area 750 can be connected to one end of the touch input line, and the other end of the touch input line is correspondingly connected to a plurality of binding pins in the binding pin area.

[0224] In an exemplary embodiment, the first output line segments in the first touch signal line 910 and the second touch signal line 920 may be designed with non-equal widths, and the width of the first output line segment close to the second output line segment may be greater than the width of the first output line segment away from the second output line segment. In an exemplary embodiment, the width is the dimension in the first direction D1.

[0225] In an exemplary embodiment, the widths of the plurality of second output line segments in the first touch signal line 910 and the second touch signal line 920 may be the same, and the intervals between adjacent second output line segments may be the same.

[0226] In an exemplary embodiment, the virtual pins 900 may be disposed between the second output segments of the first touch signal line 910 and the second touch signal line 920 , and between the second output segments of the second touch signal line 920 and the second pins 820 .

[0227] In an exemplary embodiment, at least one of the third pin region 730 and the fifth pin region 750 may be arranged in a single row and aligned longitudinally, or may be arranged in multiple rows and staggered longitudinally, which is not limited in the present disclosure.

[0228] In an exemplary embodiment, the pin structure of the fourth side on the right side of the chip area may be the same as that of the third side and may be symmetrically arranged relative to the center line O, which will not be described in detail here.

[0229] Fig.23 FIG. 1 is a schematic diagram of two rows of pins of an exemplary embodiment of the present disclosure, taking a plurality of third pins in the third pin area as an example. Fig.23As shown, multiple third pins 830 are arranged into a first pin column and a second pin column, the multiple third pins 830 in the first pin column and the second pin column are arranged in sequence along the first direction D1, the first pin column and the second pin column are arranged in sequence along the second direction D2, and the multiple third pins 830 in the first pin column and the multiple third pins 830 in the second pin column are staggered in the first direction D1.

[0230] In an exemplary embodiment, the staggered setting means that the second direction center line of a third pin in the first pin column is located between the second direction center lines of two adjacent third pins in the second pin column, or, the second direction center line of a third pin in the second pin column is located between the second direction center lines of two adjacent third pins in the first pin column, and the second direction center line is a straight line extending along the second direction D2 and equally dividing the third pins.

[0231] In an exemplary embodiment, distances between center lines of adjacent third pins in the second direction may be equal.

[0232] In an exemplary embodiment, the shapes and geometric parameters of the third pins in the first pin column and the third pins in the second pin column may be the same or different. In the same pin column, the shapes and geometric parameters of the third pins may be the same or different.

[0233] In an exemplary embodiment, the shape of the third pin may be rectangular, the third length L3 of the third pin may be approximately 60 μm to 90 μm, the third width M3 of the third pin may be approximately 40 μm to 60 μm, and the width-to-length ratio (M3 / L3) may be approximately 0.5 to 1.0. The third length L3 is the dimension in the second direction D2, and the third width M3 is the dimension in the first direction D1. In an exemplary embodiment, the spacing between the two pin columns may be approximately 15 μm to 20 μm, and in an exemplary embodiment, the period (Pitch) of the third pin may be approximately 70 μm to 90 μm.

[0234] In a display device, since the display driver integrated circuit and the touch control integrated circuit are independently arranged, the pins in the chip area are usually arranged in a single row horizontally aligned or a single row vertically aligned. Due to the integrated characteristics of the driver IC, the number of pins in the integrated circuit increases, resulting in problems such as insufficient space for the pin arrangement in the chip area. If the single row horizontal alignment or single row vertical alignment is used, the pin area and the spacing between the pins will be reduced due to the limitation of the horizontal or vertical space. The reduction in the pin area will increase the contact resistance, which is prone to local heating and increased power consumption. The reduction in pin spacing will cause insufficient margin in the bonding process, which is prone to misalignment, resulting in binding failure.

[0235] The exemplary embodiment of the present disclosure adopts two rows of longitudinal staggered arrangement in the chip area, multiple pins are arranged in two columns, and the two columns of pins are staggered, and the pins are rectangular with a relatively large width and length. This can not only increase the area of ​​each pin, reduce contact resistance, and eliminate local heating, but also increase the spacing between adjacent pins, ensure the margin of the binding process, improve the stability of the binding process, improve product quality, and improve the yield rate. In addition, the exemplary embodiment of the present disclosure reasonably utilizes the space in the chip area, and even when the binding area space is limited, the width, area and spacing between each pin can be guaranteed, and the space on both sides of the pin for laying signal lines can be guaranteed, avoiding possible short circuits of signal lines.

[0236] Fig.24 FIG. 1 is a schematic diagram of another chip area pin arrangement of an exemplary embodiment of the present disclosure. In this exemplary embodiment, the pin structure of the second side 330-2, the third side 330-3 and the fourth side 330-4 is similar to Fig.18 The structure shown is similar, except that the first pin area 710 disposed on the first side 330-1 adopts a two-row horizontal staggered arrangement structure. Fig.24 As shown, multiple first pins 810 are arranged into a first pin row and a second pin row, and the multiple first pins 810 in the first pin row and the second pin row are arranged in sequence along the second direction D2. The first pin row and the second pin row are arranged in sequence along the first direction D1, and the multiple first pins 810 in the first pin row and the multiple first pins 810 in the second pin row are staggered in the second direction D2.

[0237] The exemplary embodiment of the present disclosure adopts a two-row horizontal staggered arrangement in the first pin area. Multiple pins are arranged in two rows, and the two rows of pins are staggered. This not only increases the area of ​​each pin, reduces contact resistance, and eliminates local heating, but also increases the spacing between adjacent pins, ensures the margin of the binding process, improves the stability of the binding process, improves product quality, and improves the yield rate.

[0238] The present disclosure also provides a method for preparing a touch panel. In an exemplary embodiment, the preparation method may include:

[0239] A touch area and a binding area located on one side of the touch area in a first direction are formed, wherein the touch area includes:

[0240] a chip area, the chip area comprising a first side, a second side, a third side and a fourth side, the first side and the second side extending along a second direction, the second side being located at a side of the first side away from the touch control area, the third side and the fourth side extending along the first direction, and the first direction intersecting the second direction;

[0241] a plurality of pins, located in the chip area, the plurality of pins comprising a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines;

[0242] A plurality of touch electrodes, located in the touch area;

[0243] A plurality of touch signal lines are located in the touch area and the binding area, and the plurality of touch signal lines are correspondingly connected to the plurality of touch electrodes and the plurality of touch pins.

[0244] The exemplary embodiments of the present disclosure further provide a display device, including the display substrate of the aforementioned embodiment. The display device may be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, an advertising panel, a watch phone, an e-book portable multimedia player, or a display screen of various Internet of Things products. In an exemplary embodiment, the display device may be a wearable display device that can be worn on a human body in some way, such as a smart watch, a smart bracelet, etc.

[0245] The drawings in this application only relate to the structures involved in this disclosure, and other structures can refer to the general design. In the absence of conflict, the embodiments of this disclosure, that is, the features in the embodiments, can be combined with each other to obtain new embodiments.

[0246] Those skilled in the art should understand that the technical solutions of the present disclosure may be modified or replaced by equivalents without departing from the spirit and scope of the technical solutions of the present disclosure, and all should be included in the scope of the claims of this application.

Claims

1. A touch panel, comprising a touch area and a binding area located on one side of the touch area in a first direction, wherein the binding area comprises: a chip area, the chip area comprising a first side, a second side, a third side and a fourth side, the first side and the second side extending along a second direction, the second side being located at a side of the first side away from the touch control area, the third side and the fourth side extending along the first direction, and the first direction intersecting the second direction; a plurality of pins, located in the chip area, the plurality of pins comprising a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines; A plurality of touch electrodes, located in the touch area; A plurality of touch signal lines are located in the touch area and the binding area, and the plurality of touch signal lines are correspondingly connected to the plurality of touch electrodes and the plurality of touch pins; The chip area includes a first pin area, a second pin area, a third pin area, a fourth pin area, a fifth pin area and a sixth pin area; the first pin area is arranged along a first side of the chip area, the second pin area is arranged along a second side of the chip area, the third pin area and the fifth pin area are arranged in sequence along a third side of the chip area, and the fourth pin area and the sixth pin area are arranged in sequence along a fourth side of the chip area; The multiple touch pins include multiple touch signal output pins and multiple touch signal input pins, the multiple touch signal output pins are arranged in the third pin area and the fourth pin area, and the multiple touch signal input pins are arranged in the fifth pin area and the sixth pin area; the touch signal output pins are configured to be connected to the touch signal lines, and the touch signal input pins are configured to be connected to the touch input lines, and the touch signals are output to the touch signal output pins through the touch input lines and the touch signal input pins.

2. The touch panel according to claim 1, wherein: The multiple display pins include multiple display signal output pins and multiple display signal input pins, the multiple display signal output pins are arranged in the first pin area, and the multiple display signal input pins are arranged in the second pin area; the multiple display signal output pins are configured to be connected to the data signal line, and the display signal input pins are configured to be connected to the external circuit board through the display connection line and the binding pin area of ​​the binding area, so that the external circuit board provides a display signal through the binding pin area, the display connection line and the display signal input pins.

3. The touch panel according to claim 1, wherein: The chip area has a center line, and a plurality of touch pins and a plurality of touch signal lines in the chip area are symmetrically arranged relative to the center line, and the center line is a straight line extending along the first direction and equally dividing the chip area; The plurality of touch signal lines include a first touch signal line group and a second touch signal line group symmetrically arranged relative to the center line, the first touch signal line group includes a first output line group and a second output line group, the first output line group includes a plurality of first touch signal lines, the second output line group includes a plurality of second touch signal lines, the first output line group is arranged on a side of the second output line group away from the center line, and the plurality of first touch signal lines and the plurality of second touch signal lines are correspondingly connected to a plurality of touch signal output pins in the third pin area; The second touch signal line group includes a third output line group and a fourth output line group, the third output line group includes multiple third touch signal lines, the fourth output line group includes multiple fourth touch signal lines, the third output line group is arranged on a side of the fourth output line group away from the center line, and the multiple third touch signal lines and the multiple fourth touch signal lines are correspondingly connected to multiple touch signal output pins in the fourth pin area.

4. The touch panel according to claim 3, wherein: The first touch signal line includes a first output line segment, a second output line segment, a third output line segment and a fourth output line segment connected in sequence, the first output line segment extends along the first direction, the second output line segment and the fourth output line segment extend along the second direction, and a first angle is formed between the third output line segment and the second direction, and the first angle is 20° to 80°.

5. The touch panel according to claim 3, wherein: The second touch signal line includes a first output line segment, a second output line segment, a third output line segment and a fourth output line segment connected in sequence, the second output line segment and the fourth output line segment extend along the second direction, and a second angle is formed between the third output line segment and the second direction, and the second angle is 20° to 80°.

6. The touch panel according to claim 5, wherein: The multiple first output line segments include a first output line segment group and a second output line segment group, the first output line segment group includes a plurality of first fold lines bent toward a direction close to the center line, the second output line segment group includes a plurality of second fold lines bent toward a direction away from the center line, the plurality of first fold lines and the plurality of second fold lines enclose at least one polygonal area, and at least one virtual pin is arranged in the polygonal area.

7. The touch panel according to claim 3, wherein: The chip area also includes at least one virtual pin, which is arranged at any one or more of the following positions: between the first output line group and the second output line group, between the third output line group and the fourth output line group, on a side of the second output line group away from the first output line group, on a side of the fourth output line group away from the third output line group, and on the center line.

8. The touch panel according to claim 3, wherein: The chip area further includes at least one first connection line, the first connection line is configured to connect a portion of the touch signal input pins, and the first connection line is arranged on a side of the touch signal input pins close to the center line.

9. The touch panel according to claim 2, wherein: The chip area further includes at least one second connection line, the second connection line is configured to connect a portion of the display signal input pins, and the second connection line is arranged on a side of the display signal input pins close to the touch area.

10. The touch panel according to any one of claims 1 to 9, wherein: The plurality of pins in at least one of the first pin area, the second pin area, the third pin area, the fourth pin area, the fifth pin area and the sixth pin area are arranged in a multi-row staggered structure.

11. The touch panel according to claim 10, wherein: The pins in the first pin area and / or the second pin area are aligned in a single row horizontally, and multiple pins are arranged in sequence along the second direction and aligned in the first direction; or, the pins in the first pin area and / or the second pin area are arranged in a two-row horizontal staggered arrangement structure, and the two-row horizontal staggered arrangement structure includes a first pin row and a second pin row arranged along the first direction, and multiple pins in the first pin row and the second pin row are arranged in sequence along the second direction, and multiple pins in the first pin row and multiple pins in the second pin row are staggered in the second direction.

12. The touch panel according to claim 10, wherein: At least one of the third pin area, the fourth pin area, the fifth pin area and the sixth pin area adopts a single-row longitudinal alignment, and multiple pins are arranged in sequence along the first direction and aligned in the second direction; or, at least one of the third pin area, the fourth pin area, the fifth pin area and the sixth pin area adopts a two-row longitudinal staggered arrangement structure, and the two-row longitudinal staggered arrangement structure includes a first pin column and a second pin column arranged along the second direction, and multiple pins in the first pin column and the second pin column are arranged in sequence along the first direction, and multiple pins in the first pin column and multiple pins in the second pin column are staggered in the first direction.

13. The touch panel according to claim 10, wherein: The third pin area and the fourth pin area include a plurality of touch signal output pins and at least one idle pin, and the touch signal line is connected to the touch signal output pins but not to the idle pin.

14. The touch panel according to claim 13, wherein: The third pin area and the fourth pin area also include at least one first ground pin and at least one second ground pin, the first ground pin is connected to the first ground wire, and the second ground pin is connected to the second ground wire; the idle pin is arranged between the first ground pin and the touch signal output pin, and / or the idle pin is arranged between the touch signal output pins.

15. The touch panel according to claim 10, wherein: The fifth pin area and the sixth pin area further include a plurality of touch signal input pins and at least one idle pin, and the touch input line is connected to the touch signal input pins but not to the idle pin.

16. The touch panel according to claim 15, wherein: The idle pin is arranged between the touch signal output pin and the touch signal input pin.

17. A display device, comprising the touch panel according to any one of claims 1 to 16.

18. A method for preparing a touch panel, comprising: A touch area and a binding area located on one side of the touch area in a first direction are formed, wherein the touch area includes: a chip area, the chip area comprising a first side, a second side, a third side and a fourth side, the first side and the second side extending along a second direction, the second side being located at a side of the first side away from the touch control area, the third side and the fourth side extending along the first direction, and the first direction intersecting the second direction; a plurality of pins, located in the chip area, the plurality of pins comprising a plurality of display pins and a plurality of touch pins, the plurality of display pins being arranged along the first side and the second side, the plurality of touch pins being arranged along the third side and the fourth side, and the plurality of display pins being configured to be connected to display signal lines; A plurality of touch electrodes, located in the touch area; A plurality of touch signal lines are located in the touch area and the binding area, and the plurality of touch signal lines are correspondingly connected to the plurality of touch electrodes and the plurality of touch pins; The chip area includes a first pin area, a second pin area, a third pin area, a fourth pin area, a fifth pin area and a sixth pin area; the first pin area is arranged along a first side of the chip area, the second pin area is arranged along a second side of the chip area, the third pin area and the fifth pin area are arranged in sequence along a third side of the chip area, and the fourth pin area and the sixth pin area are arranged in sequence along a fourth side of the chip area; The multiple touch pins include multiple touch signal output pins and multiple touch signal input pins, the multiple touch signal output pins are arranged in the third pin area and the fourth pin area, and the multiple touch signal input pins are arranged in the fifth pin area and the sixth pin area; the touch signal output pins are configured to be connected to the touch signal lines, and the touch signal input pins are configured to be connected to the touch input lines, and the touch signals are output to the touch signal output pins through the touch input lines and the touch signal input pins.

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